1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2005 Bruno Ducrot
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 /*
28 * This driver is based upon information found by examining speedstep-0.5
29 * from Marc Lehman, which includes all the reverse engineering effort of
30 * Malik Martin (function 1 and 2 of the GSI).
31 *
32 * The correct way for the OS to take ownership from the BIOS was found by
33 * Hiroshi Miura (function 0 of the GSI).
34 *
35 * Finally, the int 15h call interface was (partially) documented by Intel.
36 *
37 * Many thanks to Jon Noack for testing and debugging this driver.
38 */
39
40 #include <sys/param.h>
41 #include <sys/bus.h>
42 #include <sys/cpu.h>
43 #include <sys/kernel.h>
44 #include <sys/module.h>
45 #include <sys/mutex.h>
46 #include <sys/systm.h>
47
48 #include <machine/bus.h>
49 #include <machine/cputypes.h>
50 #include <machine/md_var.h>
51 #include <machine/vm86.h>
52
53 #include <dev/pci/pcivar.h>
54 #include <dev/pci/pcireg.h>
55
56 #include <vm/vm.h>
57 #include <vm/pmap.h>
58
59 #include "cpufreq_if.h"
60
61 #if 0
62 #define DPRINT(dev, x...) device_printf(dev, x)
63 #else
64 #define DPRINT(dev, x...)
65 #endif
66
67 struct smist_softc {
68 device_t dev;
69 int smi_cmd;
70 int smi_data;
71 int command;
72 int flags;
73 struct cf_setting sets[2]; /* Only two settings. */
74 };
75
76 static char smist_magic[] = "Copyright (c) 1999 Intel Corporation";
77
78 static void smist_identify(driver_t *driver, device_t parent);
79 static int smist_probe(device_t dev);
80 static int smist_attach(device_t dev);
81 static int smist_detach(device_t dev);
82 static int smist_settings(device_t dev, struct cf_setting *sets,
83 int *count);
84 static int smist_set(device_t dev, const struct cf_setting *set);
85 static int smist_get(device_t dev, struct cf_setting *set);
86 static int smist_type(device_t dev, int *type);
87
88 static device_method_t smist_methods[] = {
89 /* Device interface */
90 DEVMETHOD(device_identify, smist_identify),
91 DEVMETHOD(device_probe, smist_probe),
92 DEVMETHOD(device_attach, smist_attach),
93 DEVMETHOD(device_detach, smist_detach),
94
95 /* cpufreq interface */
96 DEVMETHOD(cpufreq_drv_set, smist_set),
97 DEVMETHOD(cpufreq_drv_get, smist_get),
98 DEVMETHOD(cpufreq_drv_type, smist_type),
99 DEVMETHOD(cpufreq_drv_settings, smist_settings),
100 {0, 0}
101 };
102
103 static driver_t smist_driver = {
104 "smist", smist_methods, sizeof(struct smist_softc)
105 };
106
107 DRIVER_MODULE(smist, cpu, smist_driver, 0, 0);
108
109 struct piix4_pci_device {
110 uint16_t vendor;
111 uint16_t device;
112 char *desc;
113 };
114
115 static struct piix4_pci_device piix4_pci_devices[] = {
116 {0x8086, 0x7113, "Intel PIIX4 ISA bridge"},
117 {0x8086, 0x719b, "Intel PIIX4 ISA bridge (embedded in MX440 chipset)"},
118
119 {0, 0, NULL},
120 };
121
122 #define SET_OWNERSHIP 0
123 #define GET_STATE 1
124 #define SET_STATE 2
125
126 static int
int15_gsic_call(int * sig,int * smi_cmd,int * command,int * smi_data,int * flags)127 int15_gsic_call(int *sig, int *smi_cmd, int *command, int *smi_data, int *flags)
128 {
129 struct vm86frame vmf;
130
131 bzero(&vmf, sizeof(vmf));
132 vmf.vmf_eax = 0x0000E980; /* IST support */
133 vmf.vmf_edx = 0x47534943; /* 'GSIC' in ASCII */
134 vm86_intcall(0x15, &vmf);
135
136 if (vmf.vmf_eax == 0x47534943) {
137 *sig = vmf.vmf_eax;
138 *smi_cmd = vmf.vmf_ebx & 0xff;
139 *command = (vmf.vmf_ebx >> 16) & 0xff;
140 *smi_data = vmf.vmf_ecx;
141 *flags = vmf.vmf_edx;
142 } else {
143 *sig = -1;
144 *smi_cmd = -1;
145 *command = -1;
146 *smi_data = -1;
147 *flags = -1;
148 }
149
150 return (0);
151 }
152
153 /* Temporary structure to hold mapped page and status. */
154 struct set_ownership_data {
155 int smi_cmd;
156 int command;
157 int result;
158 void *buf;
159 };
160
161 /* Perform actual SMI call to enable SpeedStep. */
162 static void
set_ownership_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int error)163 set_ownership_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
164 {
165 struct set_ownership_data *data;
166
167 data = arg;
168 if (error) {
169 data->result = error;
170 return;
171 }
172
173 /* Copy in the magic string and send it by writing to the SMI port. */
174 strlcpy(data->buf, smist_magic, PAGE_SIZE);
175 __asm __volatile(
176 "movl $-1, %%edi\n\t"
177 "out %%al, (%%dx)\n"
178 : "=D" (data->result)
179 : "a" (data->command),
180 "b" (0),
181 "c" (0),
182 "d" (data->smi_cmd),
183 "S" ((uint32_t)segs[0].ds_addr)
184 );
185 }
186
187 static int
set_ownership(device_t dev)188 set_ownership(device_t dev)
189 {
190 struct smist_softc *sc;
191 struct set_ownership_data cb_data;
192 bus_dma_tag_t tag;
193 bus_dmamap_t map;
194
195 /*
196 * Specify the region to store the magic string. Since its address is
197 * passed to the BIOS in a 32-bit register, we have to make sure it is
198 * located in a physical page below 4 GB (i.e., for PAE.)
199 */
200 sc = device_get_softc(dev);
201 if (bus_dma_tag_create(/*parent*/ NULL,
202 /*alignment*/ PAGE_SIZE, /*no boundary*/ 0,
203 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, /*highaddr*/ BUS_SPACE_MAXADDR,
204 NULL, NULL, /*maxsize*/ PAGE_SIZE, /*segments*/ 1,
205 /*maxsegsize*/ PAGE_SIZE, 0, NULL, NULL, &tag) != 0) {
206 device_printf(dev, "can't create mem tag\n");
207 return (ENXIO);
208 }
209 if (bus_dmamem_alloc(tag, &cb_data.buf, BUS_DMA_NOWAIT, &map) != 0) {
210 bus_dma_tag_destroy(tag);
211 device_printf(dev, "can't alloc mapped mem\n");
212 return (ENXIO);
213 }
214
215 /* Load the physical page map and take ownership in the callback. */
216 cb_data.smi_cmd = sc->smi_cmd;
217 cb_data.command = sc->command;
218 if (bus_dmamap_load(tag, map, cb_data.buf, PAGE_SIZE, set_ownership_cb,
219 &cb_data, BUS_DMA_NOWAIT) != 0) {
220 bus_dmamem_free(tag, cb_data.buf, map);
221 bus_dma_tag_destroy(tag);
222 device_printf(dev, "can't load mem\n");
223 return (ENXIO);
224 }
225 DPRINT(dev, "taking ownership over BIOS return %d\n", cb_data.result);
226 bus_dmamap_unload(tag, map);
227 bus_dmamem_free(tag, cb_data.buf, map);
228 bus_dma_tag_destroy(tag);
229 return (cb_data.result ? ENXIO : 0);
230 }
231
232 static int
getset_state(struct smist_softc * sc,int * state,int function)233 getset_state(struct smist_softc *sc, int *state, int function)
234 {
235 int new_state;
236 int result;
237 int eax;
238
239 if (!sc)
240 return (ENXIO);
241
242 if (function != GET_STATE && function != SET_STATE)
243 return (EINVAL);
244
245 DPRINT(sc->dev, "calling GSI\n");
246
247 __asm __volatile(
248 "movl $-1, %%edi\n\t"
249 "out %%al, (%%dx)\n"
250 : "=a" (eax),
251 "=b" (new_state),
252 "=D" (result)
253 : "a" (sc->command),
254 "b" (function),
255 "c" (*state),
256 "d" (sc->smi_cmd)
257 );
258
259 DPRINT(sc->dev, "GSI returned: eax %.8x ebx %.8x edi %.8x\n",
260 eax, new_state, result);
261
262 *state = new_state & 1;
263
264 switch (function) {
265 case GET_STATE:
266 if (eax)
267 return (ENXIO);
268 break;
269 case SET_STATE:
270 if (result)
271 return (ENXIO);
272 break;
273 }
274 return (0);
275 }
276
277 static void
smist_identify(driver_t * driver,device_t parent)278 smist_identify(driver_t *driver, device_t parent)
279 {
280 struct piix4_pci_device *id;
281 device_t piix4 = NULL;
282
283 if (resource_disabled("ichst", 0))
284 return;
285
286 /* Check for a supported processor */
287 if (cpu_vendor_id != CPU_VENDOR_INTEL)
288 return;
289 switch (cpu_id & 0xff0) {
290 case 0x680: /* Pentium III [coppermine] */
291 case 0x6a0: /* Pentium III [Tualatin] */
292 break;
293 default:
294 return;
295 }
296
297 /* Check for a supported PCI-ISA bridge */
298 for (id = piix4_pci_devices; id->desc != NULL; ++id) {
299 if ((piix4 = pci_find_device(id->vendor, id->device)) != NULL)
300 break;
301 }
302 if (!piix4)
303 return;
304
305 if (bootverbose)
306 printf("smist: found supported isa bridge %s\n", id->desc);
307
308 if (device_find_child(parent, "smist", -1) != NULL)
309 return;
310 if (BUS_ADD_CHILD(parent, 30, "smist", device_get_unit(parent))
311 == NULL)
312 device_printf(parent, "smist: add child failed\n");
313 }
314
315 static int
smist_probe(device_t dev)316 smist_probe(device_t dev)
317 {
318 struct smist_softc *sc;
319 device_t ichss_dev, perf_dev;
320 int sig, smi_cmd, command, smi_data, flags;
321 int type;
322 int rv;
323
324 if (resource_disabled("smist", 0))
325 return (ENXIO);
326
327 sc = device_get_softc(dev);
328
329 /*
330 * If the ACPI perf or ICH SpeedStep drivers have attached and not
331 * just offering info, let them manage things.
332 */
333 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
334 if (perf_dev && device_is_attached(perf_dev)) {
335 rv = CPUFREQ_DRV_TYPE(perf_dev, &type);
336 if (rv == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0)
337 return (ENXIO);
338 }
339 ichss_dev = device_find_child(device_get_parent(dev), "ichss", -1);
340 if (ichss_dev && device_is_attached(ichss_dev))
341 return (ENXIO);
342
343 int15_gsic_call(&sig, &smi_cmd, &command, &smi_data, &flags);
344 if (bootverbose)
345 device_printf(dev, "sig %.8x smi_cmd %.4x command %.2x "
346 "smi_data %.4x flags %.8x\n",
347 sig, smi_cmd, command, smi_data, flags);
348
349 if (sig != -1) {
350 sc->smi_cmd = smi_cmd;
351 sc->smi_data = smi_data;
352
353 /*
354 * Sometimes int 15h 'GSIC' returns 0x80 for command, when
355 * it is actually 0x82. The Windows driver will overwrite
356 * this value given by the registry.
357 */
358 if (command == 0x80) {
359 device_printf(dev,
360 "GSIC returned cmd 0x80, should be 0x82\n");
361 command = 0x82;
362 }
363 sc->command = (sig & 0xffffff00) | (command & 0xff);
364 sc->flags = flags;
365 } else {
366 /* Give some default values */
367 sc->smi_cmd = 0xb2;
368 sc->smi_data = 0xb3;
369 sc->command = 0x47534982;
370 sc->flags = 0;
371 }
372
373 device_set_desc(dev, "SpeedStep SMI");
374
375 return (-1500);
376 }
377
378 static int
smist_attach(device_t dev)379 smist_attach(device_t dev)
380 {
381 struct smist_softc *sc;
382
383 sc = device_get_softc(dev);
384 sc->dev = dev;
385
386 /* If we can't take ownership over BIOS, then bail out */
387 if (set_ownership(dev) != 0)
388 return (ENXIO);
389
390 /* Setup some defaults for our exported settings. */
391 sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN;
392 sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN;
393 sc->sets[0].power = CPUFREQ_VAL_UNKNOWN;
394 sc->sets[0].lat = 1000;
395 sc->sets[0].dev = dev;
396 sc->sets[1] = sc->sets[0];
397
398 cpufreq_register(dev);
399
400 return (0);
401 }
402
403 static int
smist_detach(device_t dev)404 smist_detach(device_t dev)
405 {
406
407 return (cpufreq_unregister(dev));
408 }
409
410 static int
smist_settings(device_t dev,struct cf_setting * sets,int * count)411 smist_settings(device_t dev, struct cf_setting *sets, int *count)
412 {
413 struct smist_softc *sc;
414 struct cf_setting set;
415 int first, i;
416
417 if (sets == NULL || count == NULL)
418 return (EINVAL);
419 if (*count < 2) {
420 *count = 2;
421 return (E2BIG);
422 }
423 sc = device_get_softc(dev);
424
425 /*
426 * Estimate frequencies for both levels, temporarily switching to
427 * the other one if we haven't calibrated it yet.
428 */
429 for (i = 0; i < 2; i++) {
430 if (sc->sets[i].freq == CPUFREQ_VAL_UNKNOWN) {
431 first = (i == 0) ? 1 : 0;
432 smist_set(dev, &sc->sets[i]);
433 smist_get(dev, &set);
434 smist_set(dev, &sc->sets[first]);
435 }
436 }
437
438 bcopy(sc->sets, sets, sizeof(sc->sets));
439 *count = 2;
440
441 return (0);
442 }
443
444 static int
smist_set(device_t dev,const struct cf_setting * set)445 smist_set(device_t dev, const struct cf_setting *set)
446 {
447 struct smist_softc *sc;
448 int rv, state, req_state, try;
449
450 /* Look up appropriate bit value based on frequency. */
451 sc = device_get_softc(dev);
452 if (CPUFREQ_CMP(set->freq, sc->sets[0].freq))
453 req_state = 0;
454 else if (CPUFREQ_CMP(set->freq, sc->sets[1].freq))
455 req_state = 1;
456 else
457 return (EINVAL);
458
459 DPRINT(dev, "requested setting %d\n", req_state);
460
461 rv = getset_state(sc, &state, GET_STATE);
462 if (state == req_state)
463 return (0);
464
465 try = 3;
466 do {
467 rv = getset_state(sc, &req_state, SET_STATE);
468
469 /* Sleep for 200 microseconds. This value is just a guess. */
470 if (rv)
471 DELAY(200);
472 } while (rv && --try);
473 DPRINT(dev, "set_state return %d, tried %d times\n",
474 rv, 4 - try);
475
476 return (rv);
477 }
478
479 static int
smist_get(device_t dev,struct cf_setting * set)480 smist_get(device_t dev, struct cf_setting *set)
481 {
482 struct smist_softc *sc;
483 uint64_t rate;
484 int state;
485 int rv;
486
487 sc = device_get_softc(dev);
488 rv = getset_state(sc, &state, GET_STATE);
489 if (rv != 0)
490 return (rv);
491
492 /* If we haven't changed settings yet, estimate the current value. */
493 if (sc->sets[state].freq == CPUFREQ_VAL_UNKNOWN) {
494 cpu_est_clockrate(0, &rate);
495 sc->sets[state].freq = rate / 1000000;
496 DPRINT(dev, "get calibrated new rate of %d\n",
497 sc->sets[state].freq);
498 }
499 *set = sc->sets[state];
500
501 return (0);
502 }
503
504 static int
smist_type(device_t dev,int * type)505 smist_type(device_t dev, int *type)
506 {
507
508 if (type == NULL)
509 return (EINVAL);
510
511 *type = CPUFREQ_TYPE_ABSOLUTE;
512 return (0);
513 }
514