1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (C) 2008-2009 Semihalf, Piotr Ziecik 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 21 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 22 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 23 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 24 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef _SEC_H 29 #define _SEC_H 30 31 /* 32 * Each SEC channel can hold up to 24 descriptors. All 4 channels can be 33 * simultaneously active holding 96 descriptors. Each descriptor can use 0 or 34 * more link table entries depending of size and granulation of input/output 35 * data. One link table entry is needed for each 65535 bytes of data. 36 */ 37 38 /* Driver settings */ 39 #define SEC_TIMEOUT 100000 40 #define SEC_MAX_SESSIONS 256 41 #define SEC_DESCRIPTORS 256 /* Must be power of 2 */ 42 #define SEC_LT_ENTRIES 1024 /* Must be power of 2 */ 43 #define SEC_MAX_IV_LEN 16 44 #define SEC_MAX_KEY_LEN 64 45 46 /* SEC information */ 47 #define SEC_20_ID 0x0000000000000040ULL 48 #define SEC_30_ID 0x0030030000000000ULL 49 #define SEC_31_ID 0x0030030100000000ULL 50 #define SEC_CHANNELS 4 51 #define SEC_POINTERS 7 52 #define SEC_MAX_DMA_BLOCK_SIZE 0xFFFF 53 #define SEC_MAX_FIFO_LEVEL 24 54 #define SEC_DMA_ALIGNMENT 8 55 56 #define __packed__ __attribute__ ((__packed__)) 57 58 struct sec_softc; 59 struct sec_session; 60 61 /* SEC descriptor definition */ 62 struct sec_hw_desc_ptr { 63 u_int shdp_length : 16; 64 u_int shdp_j : 1; 65 u_int shdp_extent : 7; 66 u_int __padding0 : 4; 67 uint64_t shdp_ptr : 36; 68 } __packed__; 69 70 struct sec_hw_desc { 71 union __packed__ { 72 struct __packed__ { 73 u_int eu_sel0 : 4; 74 u_int mode0 : 8; 75 u_int eu_sel1 : 4; 76 u_int mode1 : 8; 77 u_int desc_type : 5; 78 u_int __padding0 : 1; 79 u_int dir : 1; 80 u_int dn : 1; 81 u_int __padding1 : 32; 82 } request; 83 struct __packed__ { 84 u_int done : 8; 85 u_int __padding0 : 27; 86 u_int iccr0 : 2; 87 u_int __padding1 : 6; 88 u_int iccr1 : 2; 89 u_int __padding2 : 19; 90 } feedback; 91 } shd_control; 92 93 struct sec_hw_desc_ptr shd_pointer[SEC_POINTERS]; 94 95 /* Data below is mapped to descriptor pointers */ 96 uint8_t shd_iv[SEC_MAX_IV_LEN]; 97 uint8_t shd_key[SEC_MAX_KEY_LEN]; 98 uint8_t shd_mkey[SEC_MAX_KEY_LEN]; 99 uint8_t shd_digest[HASH_MAX_LEN]; 100 } __packed__; 101 102 #define shd_eu_sel0 shd_control.request.eu_sel0 103 #define shd_mode0 shd_control.request.mode0 104 #define shd_eu_sel1 shd_control.request.eu_sel1 105 #define shd_mode1 shd_control.request.mode1 106 #define shd_desc_type shd_control.request.desc_type 107 #define shd_dir shd_control.request.dir 108 #define shd_dn shd_control.request.dn 109 #define shd_done shd_control.feedback.done 110 #define shd_iccr0 shd_control.feedback.iccr0 111 #define shd_iccr1 shd_control.feedback.iccr1 112 113 /* SEC link table entries definition */ 114 struct sec_hw_lt { 115 u_int shl_length : 16; 116 u_int __padding0 : 6; 117 u_int shl_r : 1; 118 u_int shl_n : 1; 119 u_int __padding1 : 4; 120 uint64_t shl_ptr : 36; 121 } __packed__; 122 123 struct sec_dma_mem { 124 void *dma_vaddr; 125 bus_addr_t dma_paddr; 126 bus_dma_tag_t dma_tag; 127 bus_dmamap_t dma_map; 128 u_int dma_is_map; 129 }; 130 131 struct sec_desc { 132 struct sec_hw_desc *sd_desc; 133 bus_addr_t sd_desc_paddr; 134 struct sec_dma_mem sd_ptr_dmem[SEC_POINTERS]; 135 struct cryptop *sd_crp; 136 u_int sd_lt_used; 137 u_int sd_error; 138 }; 139 140 struct sec_lt { 141 struct sec_hw_lt *sl_lt; 142 bus_addr_t sl_lt_paddr; 143 }; 144 145 struct sec_eu_methods { 146 bool (*sem_newsession)(const struct crypto_session_params *csp); 147 int (*sem_make_desc)(struct sec_softc *sc, 148 const struct crypto_session_params *csp, struct sec_desc *desc, 149 struct cryptop *crp); 150 }; 151 152 struct sec_session { 153 struct sec_eu_methods *ss_eu; 154 uint8_t ss_key[SEC_MAX_KEY_LEN]; 155 uint8_t ss_mkey[SEC_MAX_KEY_LEN]; 156 int ss_mlen; 157 }; 158 159 struct sec_desc_map_info { 160 struct sec_softc *sdmi_sc; 161 bus_size_t sdmi_size; 162 bus_size_t sdmi_offset; 163 struct sec_lt *sdmi_lt_first; 164 struct sec_lt *sdmi_lt_last; 165 u_int sdmi_lt_used; 166 }; 167 168 struct sec_softc { 169 device_t sc_dev; 170 int32_t sc_cid; 171 int sc_blocked; 172 int sc_shutdown; 173 u_int sc_version; 174 175 uint64_t sc_int_error_mask; 176 uint64_t sc_channel_idle_mask; 177 178 struct mtx sc_controller_lock; 179 struct mtx sc_descriptors_lock; 180 181 struct sec_desc sc_desc[SEC_DESCRIPTORS]; 182 u_int sc_free_desc_get_cnt; 183 u_int sc_free_desc_put_cnt; 184 u_int sc_ready_desc_get_cnt; 185 u_int sc_ready_desc_put_cnt; 186 u_int sc_queued_desc_get_cnt; 187 u_int sc_queued_desc_put_cnt; 188 189 struct sec_lt sc_lt[SEC_LT_ENTRIES + 1]; 190 u_int sc_lt_alloc_cnt; 191 u_int sc_lt_free_cnt; 192 193 struct sec_dma_mem sc_desc_dmem; /* descriptors DMA memory */ 194 struct sec_dma_mem sc_lt_dmem; /* link tables DMA memory */ 195 196 struct resource *sc_rres; /* register resource */ 197 int sc_rrid; /* register rid */ 198 struct { 199 bus_space_tag_t bst; 200 bus_space_handle_t bsh; 201 } sc_bas; 202 203 struct resource *sc_pri_ires; /* primary irq resource */ 204 void *sc_pri_ihand; /* primary irq handler */ 205 int sc_pri_irid; /* primary irq resource id */ 206 207 struct resource *sc_sec_ires; /* secondary irq resource */ 208 void *sc_sec_ihand; /* secondary irq handler */ 209 int sc_sec_irid; /* secondary irq resource id */ 210 }; 211 212 /* Locking macros */ 213 #define SEC_LOCK(sc, what) \ 214 mtx_lock(&(sc)->sc_ ## what ## _lock) 215 #define SEC_UNLOCK(sc, what) \ 216 mtx_unlock(&(sc)->sc_ ## what ## _lock) 217 #define SEC_LOCK_ASSERT(sc, what) \ 218 mtx_assert(&(sc)->sc_ ## what ## _lock, MA_OWNED) 219 220 /* Read/Write definitions */ 221 #define SEC_READ(sc, reg) \ 222 bus_space_read_8((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg)) 223 #define SEC_WRITE(sc, reg, val) \ 224 bus_space_write_8((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg), (val)) 225 226 /* Base allocation macros (warning: wrap must be 2^n) */ 227 #define SEC_CNT_INIT(sc, cnt, wrap) \ 228 (((sc)->cnt) = ((wrap) - 1)) 229 #define SEC_ADD(sc, cnt, wrap, val) \ 230 ((sc)->cnt = (((sc)->cnt) + (val)) & ((wrap) - 1)) 231 #define SEC_INC(sc, cnt, wrap) \ 232 SEC_ADD(sc, cnt, wrap, 1) 233 #define SEC_DEC(sc, cnt, wrap) \ 234 SEC_ADD(sc, cnt, wrap, -1) 235 #define SEC_GET_GENERIC(sc, tab, cnt, wrap) \ 236 ((sc)->tab[SEC_INC(sc, cnt, wrap)]) 237 #define SEC_PUT_GENERIC(sc, tab, cnt, wrap, val) \ 238 ((sc)->tab[SEC_INC(sc, cnt, wrap)] = val) 239 240 /* Interface for descriptors */ 241 #define SEC_GET_FREE_DESC(sc) \ 242 &SEC_GET_GENERIC(sc, sc_desc, sc_free_desc_get_cnt, SEC_DESCRIPTORS) 243 244 #define SEC_PUT_BACK_FREE_DESC(sc) \ 245 SEC_DEC(sc, sc_free_desc_get_cnt, SEC_DESCRIPTORS) 246 247 #define SEC_DESC_FREE2READY(sc) \ 248 SEC_INC(sc, sc_ready_desc_put_cnt, SEC_DESCRIPTORS) 249 250 #define SEC_GET_READY_DESC(sc) \ 251 &SEC_GET_GENERIC(sc, sc_desc, sc_ready_desc_get_cnt, SEC_DESCRIPTORS) 252 253 #define SEC_PUT_BACK_READY_DESC(sc) \ 254 SEC_DEC(sc, sc_ready_desc_get_cnt, SEC_DESCRIPTORS) 255 256 #define SEC_DESC_READY2QUEUED(sc) \ 257 SEC_INC(sc, sc_queued_desc_put_cnt, SEC_DESCRIPTORS) 258 259 #define SEC_GET_QUEUED_DESC(sc) \ 260 &SEC_GET_GENERIC(sc, sc_desc, sc_queued_desc_get_cnt, SEC_DESCRIPTORS) 261 262 #define SEC_PUT_BACK_QUEUED_DESC(sc) \ 263 SEC_DEC(sc, sc_queued_desc_get_cnt, SEC_DESCRIPTORS) 264 265 #define SEC_DESC_QUEUED2FREE(sc) \ 266 SEC_INC(sc, sc_free_desc_put_cnt, SEC_DESCRIPTORS) 267 268 #define SEC_FREE_DESC_CNT(sc) \ 269 (((sc)->sc_free_desc_put_cnt - (sc)->sc_free_desc_get_cnt - 1) \ 270 & (SEC_DESCRIPTORS - 1)) 271 272 #define SEC_READY_DESC_CNT(sc) \ 273 (((sc)->sc_ready_desc_put_cnt - (sc)->sc_ready_desc_get_cnt) & \ 274 (SEC_DESCRIPTORS - 1)) 275 276 #define SEC_QUEUED_DESC_CNT(sc) \ 277 (((sc)->sc_queued_desc_put_cnt - (sc)->sc_queued_desc_get_cnt) \ 278 & (SEC_DESCRIPTORS - 1)) 279 280 #define SEC_DESC_SYNC(sc, mode) do { \ 281 sec_sync_dma_mem(&((sc)->sc_desc_dmem), (mode)); \ 282 sec_sync_dma_mem(&((sc)->sc_lt_dmem), (mode)); \ 283 } while (0) 284 285 #define SEC_DESC_SYNC_POINTERS(desc, mode) do { \ 286 u_int i; \ 287 for (i = 0; i < SEC_POINTERS; i++) \ 288 sec_sync_dma_mem(&((desc)->sd_ptr_dmem[i]), (mode)); \ 289 } while (0) 290 291 #define SEC_DESC_FREE_POINTERS(desc) do { \ 292 u_int i; \ 293 for (i = 0; i < SEC_POINTERS; i++) \ 294 sec_free_dma_mem(&(desc)->sd_ptr_dmem[i]); \ 295 } while (0); 296 297 #define SEC_DESC_PUT_BACK_LT(sc, desc) \ 298 SEC_PUT_BACK_LT(sc, (desc)->sd_lt_used) 299 300 #define SEC_DESC_FREE_LT(sc, desc) \ 301 SEC_FREE_LT(sc, (desc)->sd_lt_used) 302 303 /* Interface for link tables */ 304 #define SEC_ALLOC_LT_ENTRY(sc) \ 305 &SEC_GET_GENERIC(sc, sc_lt, sc_lt_alloc_cnt, SEC_LT_ENTRIES) 306 307 #define SEC_PUT_BACK_LT(sc, num) \ 308 SEC_ADD(sc, sc_lt_alloc_cnt, SEC_LT_ENTRIES, -(num)) 309 310 #define SEC_FREE_LT(sc, num) \ 311 SEC_ADD(sc, sc_lt_free_cnt, SEC_LT_ENTRIES, num) 312 313 #define SEC_FREE_LT_CNT(sc) \ 314 (((sc)->sc_lt_free_cnt - (sc)->sc_lt_alloc_cnt - 1) \ 315 & (SEC_LT_ENTRIES - 1)) 316 317 /* Size of SEC registers area */ 318 #define SEC_IO_SIZE 0x10000 319 320 /* SEC Controller registers */ 321 #define SEC_IER 0x1008 322 #define SEC_INT_CH_DN(n) (1ULL << (((n) * 2) + 32)) 323 #define SEC_INT_CH_ERR(n) (1ULL << (((n) * 2) + 33)) 324 #define SEC_INT_ITO (1ULL << 55) 325 326 #define SEC_ISR 0x1010 327 #define SEC_ICR 0x1018 328 #define SEC_ID 0x1020 329 330 #define SEC_EUASR 0x1028 331 #define SEC_EUASR_RNGU(r) (((r) >> 0) & 0xF) 332 #define SEC_EUASR_PKEU(r) (((r) >> 8) & 0xF) 333 #define SEC_EUASR_KEU(r) (((r) >> 16) & 0xF) 334 #define SEC_EUASR_CRCU(r) (((r) >> 20) & 0xF) 335 #define SEC_EUASR_DEU(r) (((r) >> 32) & 0xF) 336 #define SEC_EUASR_AESU(r) (((r) >> 40) & 0xF) 337 #define SEC_EUASR_MDEU(r) (((r) >> 48) & 0xF) 338 #define SEC_EUASR_AFEU(r) (((r) >> 56) & 0xF) 339 340 #define SEC_MCR 0x1030 341 #define SEC_MCR_SWR (1ULL << 32) 342 343 /* SEC Channel registers */ 344 #define SEC_CHAN_CCR(n) (((n) * 0x100) + 0x1108) 345 #define SEC_CHAN_CCR_CDIE (1ULL << 1) 346 #define SEC_CHAN_CCR_NT (1ULL << 2) 347 #define SEC_CHAN_CCR_AWSE (1ULL << 3) 348 #define SEC_CHAN_CCR_CDWE (1ULL << 4) 349 #define SEC_CHAN_CCR_BS (1ULL << 8) 350 #define SEC_CHAN_CCR_WGN (1ULL << 13) 351 #define SEC_CHAN_CCR_R (1ULL << 32) 352 #define SEC_CHAN_CCR_CON (1ULL << 33) 353 354 #define SEC_CHAN_CSR(n) (((n) * 0x100) + 0x1110) 355 #define SEC_CHAN_CSR2_FFLVL_M 0x1FULL 356 #define SEC_CHAN_CSR2_FFLVL_S 56 357 #define SEC_CHAN_CSR2_GSTATE_M 0x0FULL 358 #define SEC_CHAN_CSR2_GSTATE_S 48 359 #define SEC_CHAN_CSR2_PSTATE_M 0x0FULL 360 #define SEC_CHAN_CSR2_PSTATE_S 40 361 #define SEC_CHAN_CSR2_MSTATE_M 0x3FULL 362 #define SEC_CHAN_CSR2_MSTATE_S 32 363 #define SEC_CHAN_CSR3_FFLVL_M 0x1FULL 364 #define SEC_CHAN_CSR3_FFLVL_S 24 365 #define SEC_CHAN_CSR3_MSTATE_M 0x1FFULL 366 #define SEC_CHAN_CSR3_MSTATE_S 32 367 #define SEC_CHAN_CSR3_PSTATE_M 0x7FULL 368 #define SEC_CHAN_CSR3_PSTATE_S 48 369 #define SEC_CHAN_CSR3_GSTATE_M 0x7FULL 370 #define SEC_CHAN_CSR3_GSTATE_S 56 371 372 #define SEC_CHAN_CDPR(n) (((n) * 0x100) + 0x1140) 373 #define SEC_CHAN_FF(n) (((n) * 0x100) + 0x1148) 374 375 /* SEC Execution Units numbers */ 376 #define SEC_EU_NONE 0x0 377 #define SEC_EU_AFEU 0x1 378 #define SEC_EU_DEU 0x2 379 #define SEC_EU_MDEU_A 0x3 380 #define SEC_EU_MDEU_B 0xB 381 #define SEC_EU_RNGU 0x4 382 #define SEC_EU_PKEU 0x5 383 #define SEC_EU_AESU 0x6 384 #define SEC_EU_KEU 0x7 385 #define SEC_EU_CRCU 0x8 386 387 /* SEC descriptor types */ 388 #define SEC_DT_COMMON_NONSNOOP 0x02 389 #define SEC_DT_HMAC_SNOOP 0x04 390 391 /* SEC AESU declarations and definitions */ 392 #define SEC_AESU_MODE_ED (1ULL << 0) 393 #define SEC_AESU_MODE_CBC (1ULL << 1) 394 395 /* SEC DEU declarations and definitions */ 396 #define SEC_DEU_MODE_ED (1ULL << 0) 397 #define SEC_DEU_MODE_TS (1ULL << 1) 398 #define SEC_DEU_MODE_CBC (1ULL << 2) 399 400 /* SEC MDEU declarations and definitions */ 401 #define SEC_HMAC_HASH_LEN 12 402 #define SEC_MDEU_MODE_SHA1 0x00 /* MDEU A */ 403 #define SEC_MDEU_MODE_SHA384 0x00 /* MDEU B */ 404 #define SEC_MDEU_MODE_SHA256 0x01 405 #define SEC_MDEU_MODE_MD5 0x02 /* MDEU A */ 406 #define SEC_MDEU_MODE_SHA512 0x02 /* MDEU B */ 407 #define SEC_MDEU_MODE_SHA224 0x03 408 #define SEC_MDEU_MODE_PD (1ULL << 2) 409 #define SEC_MDEU_MODE_HMAC (1ULL << 3) 410 #define SEC_MDEU_MODE_INIT (1ULL << 4) 411 #define SEC_MDEU_MODE_SMAC (1ULL << 5) 412 #define SEC_MDEU_MODE_CICV (1ULL << 6) 413 #define SEC_MDEU_MODE_CONT (1ULL << 7) 414 415 #endif 416