| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiSelectionDAGInfo.cpp | 21 SDValue LanaiSelectionDAGInfo::EmitTargetCodeForMemcpy( in EmitTargetCodeForMemcpy() argument
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 86 DenseMap<SDValue, Register> &VRBaseMap) { in EmitCopyFromReg()
190 DenseMap<SDValue, Register> &VRBaseMap) { in CreateVirtualRegisters()
269 DenseMap<SDValue, Register> &VRBaseMap) { in getVR()
321 DenseMap<SDValue, Register> &VRBaseMap, in AddRegisterOperand()
402 DenseMap<SDValue, Register> &VRBaseMap, in AddOperand()
503 DenseMap<SDValue, Register> &VRBaseMap, in EmitSubregNode()
637 DenseMap<SDValue, Register> &VRBaseMap) { in EmitCopyToRegClassNode()
657 DenseMap<SDValue, Register> &VRBaseMap, in EmitRegSequence()
706 DenseMap<SDValue, Register> &VRBaseMap) { in EmitDbgValue()
758 DenseMap<SDValue, Register> &VRBaseMap) { in AddDbgValueLocationOps()
[all …]
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| H A D | InstrEmitter.h | 143 DenseMap<SDValue, Register> &VRBaseMap) { in EmitNode()
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| H A D | ScheduleDAGSDNodes.cpp | 740 DenseMap<SDValue, Register> &VRBaseMap, unsigned Order) { in ProcessSDDbgValues()
785 DenseMap<SDValue, Register> &VRBaseMap, in ProcessSourceNode()
864 DenseMap<SDValue, Register> &VRBaseMap) -> MachineInstr * { in EmitSchedule()
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| H A D | SelectionDAGISel.cpp | 2814 const SmallVectorImpl<std::pair<SDValue, SDNode *>> &RecordedNodes) { in CheckSame()
2824 const SmallVectorImpl<std::pair<SDValue, SDNode *>> &RecordedNodes, in CheckChildSame()
2980 SmallVectorImpl<std::pair<SDValue, SDNode*>> &RecordedNodes) { in IsPredicateKnownToFail()
3153 SmallVectorImpl<std::pair<SDValue, SDNode *>> &RN, in MatchStateUpdater()
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| H A D | StatepointLowering.cpp | 524 DenseMap<SDValue, int> &LowerAsVReg, in lowerStatepointMetaArgs()
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| H A D | SelectionDAG.cpp | 7778 SmallVector<SDValue, 32> &OutChains, unsigned From, in chainLoadsAndStoresForMemcpy()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 3815 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/, in getPreIndexedAddressParts() argument
3826 SDValue &/*Base*/, in getPostIndexedAddressParts() argument
4362 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const { in IsDesirableToPromoteOp() argument
4488 virtual SDValue LowerFormalArguments( in LowerFormalArguments() argument
4491 SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const { in LowerFormalArguments()
4749 SmallVectorImpl<SDValue> &/*InVals*/) const { in LowerCall()
4771 virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, in LowerReturn() argument
4774 const SmallVectorImpl<SDValue> & /*OutVals*/, in LowerReturn()
4785 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const { in isUsedByReturnOnly() argument
4893 SmallVectorImpl<SDValue> &/*Results*/, in ReplaceNodeResults()
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| H A D | SelectionDAGISel.h | 30 class SDValue; variable
436 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) { in CheckComplexPattern()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 818 bool hasAndNotCompare(SDValue) const override { in hasAndNotCompare() argument
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| H A D | PPCISelLowering.cpp | 5701 buildCallOperands(SmallVectorImpl<SDValue> &Ops, in buildCallOperands() argument
5785 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue Glue, in FinishCall() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelDAGToDAG.cpp | 2237 static unsigned pickOpcodeForVectorStParam(SmallVector<SDValue, 8> &Ops, in pickOpcodeForVectorStParam()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 1455 bool shouldScalarizeBinop(SDValue) const override; in shouldScalarizeBinop() argument
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| H A D | X86ISelLowering.cpp | 22790 SDNode *N, SDValue, SDValue IntPow2) const { in optimizeFMulOrFDivAsShiftAddBitcast() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 10248 SmallVector<std::pair<SDValue, SDValue>, 16> &WorkList) { in isOrXorChain() argument
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