1 /*-
2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 /*
29 * SDHCI driver glue for NVIDIA Tegra family
30 *
31 */
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/types.h>
35 #include <sys/bus.h>
36 #include <sys/gpio.h>
37 #include <sys/kernel.h>
38 #include <sys/lock.h>
39 #include <sys/malloc.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/resource.h>
43 #include <sys/rman.h>
44 #include <sys/sysctl.h>
45 #include <sys/taskqueue.h>
46
47 #include <machine/bus.h>
48 #include <machine/resource.h>
49 #include <machine/intr.h>
50
51 #include <dev/clk/clk.h>
52 #include <dev/hwreset/hwreset.h>
53 #include <dev/gpio/gpiobusvar.h>
54 #include <dev/mmc/bridge.h>
55 #include <dev/mmc/mmcbrvar.h>
56 #include <dev/ofw/ofw_bus.h>
57 #include <dev/ofw/ofw_bus_subr.h>
58 #include <dev/sdhci/sdhci.h>
59 #include <dev/sdhci/sdhci_fdt_gpio.h>
60
61 #include "sdhci_if.h"
62
63 #include "opt_mmccam.h"
64
65 /* Tegra SDHOST controller vendor register definitions */
66 #define SDMMC_VENDOR_CLOCK_CNTRL 0x100
67 #define VENDOR_CLOCK_CNTRL_CLK_SHIFT 8
68 #define VENDOR_CLOCK_CNTRL_CLK_MASK 0xFF
69 #define SDMMC_VENDOR_SYS_SW_CNTRL 0x104
70 #define SDMMC_VENDOR_CAP_OVERRIDES 0x10C
71 #define SDMMC_VENDOR_BOOT_CNTRL 0x110
72 #define SDMMC_VENDOR_BOOT_ACK_TIMEOUT 0x114
73 #define SDMMC_VENDOR_BOOT_DAT_TIMEOUT 0x118
74 #define SDMMC_VENDOR_DEBOUNCE_COUNT 0x11C
75 #define SDMMC_VENDOR_MISC_CNTRL 0x120
76 #define VENDOR_MISC_CTRL_ENABLE_SDR104 0x8
77 #define VENDOR_MISC_CTRL_ENABLE_SDR50 0x10
78 #define VENDOR_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
79 #define VENDOR_MISC_CTRL_ENABLE_DDR50 0x200
80 #define SDMMC_MAX_CURRENT_OVERRIDE 0x124
81 #define SDMMC_MAX_CURRENT_OVERRIDE_HI 0x128
82 #define SDMMC_VENDOR_CLK_GATE_HYSTERESIS_COUNT 0x1D0
83 #define SDMMC_VENDOR_PHWRESET_VAL0 0x1D4
84 #define SDMMC_VENDOR_PHWRESET_VAL1 0x1D8
85 #define SDMMC_VENDOR_PHWRESET_VAL2 0x1DC
86 #define SDMMC_SDMEMCOMPPADCTRL_0 0x1E0
87 #define SDMMC_AUTO_CAL_CONFIG 0x1E4
88 #define SDMMC_AUTO_CAL_INTERVAL 0x1E8
89 #define SDMMC_AUTO_CAL_STATUS 0x1EC
90 #define SDMMC_SDMMC_MCCIF_FIFOCTRL 0x1F4
91 #define SDMMC_TIMEOUT_WCOAL_SDMMC 0x1F8
92
93 /* Compatible devices. */
94 static struct ofw_compat_data compat_data[] = {
95 {"nvidia,tegra124-sdhci", 1},
96 {"nvidia,tegra210-sdhci", 1},
97 {NULL, 0},
98 };
99
100 struct tegra_sdhci_softc {
101 device_t dev;
102 struct resource * mem_res;
103 struct resource * irq_res;
104 void * intr_cookie;
105 u_int quirks; /* Chip specific quirks */
106 u_int caps; /* If we override SDHCI_CAPABILITIES */
107 uint32_t max_clk; /* Max possible freq */
108 clk_t clk;
109 hwreset_t reset;
110 gpio_pin_t gpio_power;
111 struct sdhci_fdt_gpio *gpio;
112
113 int force_card_present;
114 struct sdhci_slot slot;
115
116 };
117
118 static inline uint32_t
RD4(struct tegra_sdhci_softc * sc,bus_size_t off)119 RD4(struct tegra_sdhci_softc *sc, bus_size_t off)
120 {
121
122 return (bus_read_4(sc->mem_res, off));
123 }
124
125 static uint8_t
tegra_sdhci_read_1(device_t dev,struct sdhci_slot * slot,bus_size_t off)126 tegra_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
127 {
128 struct tegra_sdhci_softc *sc;
129
130 sc = device_get_softc(dev);
131 return (bus_read_1(sc->mem_res, off));
132 }
133
134 static uint16_t
tegra_sdhci_read_2(device_t dev,struct sdhci_slot * slot,bus_size_t off)135 tegra_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
136 {
137 struct tegra_sdhci_softc *sc;
138
139 sc = device_get_softc(dev);
140 return (bus_read_2(sc->mem_res, off));
141 }
142
143 static uint32_t
tegra_sdhci_read_4(device_t dev,struct sdhci_slot * slot,bus_size_t off)144 tegra_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
145 {
146 struct tegra_sdhci_softc *sc;
147 uint32_t val32;
148
149 sc = device_get_softc(dev);
150 val32 = bus_read_4(sc->mem_res, off);
151 /* Force the card-present state if necessary. */
152 if (off == SDHCI_PRESENT_STATE && sc->force_card_present)
153 val32 |= SDHCI_CARD_PRESENT;
154 return (val32);
155 }
156
157 static void
tegra_sdhci_read_multi_4(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint32_t * data,bus_size_t count)158 tegra_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
159 uint32_t *data, bus_size_t count)
160 {
161 struct tegra_sdhci_softc *sc;
162
163 sc = device_get_softc(dev);
164 bus_read_multi_4(sc->mem_res, off, data, count);
165 }
166
167 static void
tegra_sdhci_write_1(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint8_t val)168 tegra_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
169 uint8_t val)
170 {
171 struct tegra_sdhci_softc *sc;
172
173 sc = device_get_softc(dev);
174 bus_write_1(sc->mem_res, off, val);
175 }
176
177 static void
tegra_sdhci_write_2(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint16_t val)178 tegra_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
179 uint16_t val)
180 {
181 struct tegra_sdhci_softc *sc;
182
183 sc = device_get_softc(dev);
184 bus_write_2(sc->mem_res, off, val);
185 }
186
187 static void
tegra_sdhci_write_4(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint32_t val)188 tegra_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
189 uint32_t val)
190 {
191 struct tegra_sdhci_softc *sc;
192
193 sc = device_get_softc(dev);
194 bus_write_4(sc->mem_res, off, val);
195 }
196
197 static void
tegra_sdhci_write_multi_4(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint32_t * data,bus_size_t count)198 tegra_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
199 uint32_t *data, bus_size_t count)
200 {
201 struct tegra_sdhci_softc *sc;
202
203 sc = device_get_softc(dev);
204 bus_write_multi_4(sc->mem_res, off, data, count);
205 }
206
207 static void
tegra_sdhci_intr(void * arg)208 tegra_sdhci_intr(void *arg)
209 {
210 struct tegra_sdhci_softc *sc = arg;
211
212 sdhci_generic_intr(&sc->slot);
213 RD4(sc, SDHCI_INT_STATUS);
214 }
215
216 static int
tegra_sdhci_get_ro(device_t brdev,device_t reqdev)217 tegra_sdhci_get_ro(device_t brdev, device_t reqdev)
218 {
219 struct tegra_sdhci_softc *sc = device_get_softc(brdev);
220
221 return (sdhci_fdt_gpio_get_readonly(sc->gpio));
222 }
223
224 static bool
tegra_sdhci_get_card_present(device_t dev,struct sdhci_slot * slot)225 tegra_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot)
226 {
227 struct tegra_sdhci_softc *sc = device_get_softc(dev);
228
229 return (sdhci_fdt_gpio_get_present(sc->gpio));
230 }
231
232 static int
tegra_sdhci_probe(device_t dev)233 tegra_sdhci_probe(device_t dev)
234 {
235 struct tegra_sdhci_softc *sc;
236 phandle_t node;
237 pcell_t cid;
238 const struct ofw_compat_data *cd;
239
240 sc = device_get_softc(dev);
241 if (!ofw_bus_status_okay(dev))
242 return (ENXIO);
243
244 cd = ofw_bus_search_compatible(dev, compat_data);
245 if (cd->ocd_data == 0)
246 return (ENXIO);
247
248 node = ofw_bus_get_node(dev);
249 device_set_desc(dev, "Tegra SDHCI controller");
250
251 /* Allow dts to patch quirks, slots, and max-frequency. */
252 if ((OF_getencprop(node, "quirks", &cid, sizeof(cid))) > 0)
253 sc->quirks = cid;
254 if ((OF_getencprop(node, "max-frequency", &cid, sizeof(cid))) > 0)
255 sc->max_clk = cid;
256
257 return (BUS_PROBE_DEFAULT);
258 }
259
260 static int
tegra_sdhci_attach(device_t dev)261 tegra_sdhci_attach(device_t dev)
262 {
263 struct tegra_sdhci_softc *sc;
264 int rid, rv;
265 uint64_t freq;
266 phandle_t node, prop;
267
268 sc = device_get_softc(dev);
269 sc->dev = dev;
270 node = ofw_bus_get_node(dev);
271
272 rid = 0;
273 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
274 RF_ACTIVE);
275 if (!sc->mem_res) {
276 device_printf(dev, "cannot allocate memory window\n");
277 rv = ENXIO;
278 goto fail;
279 }
280
281 rid = 0;
282 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
283 RF_ACTIVE);
284 if (!sc->irq_res) {
285 device_printf(dev, "cannot allocate interrupt\n");
286 rv = ENXIO;
287 goto fail;
288 }
289
290 rv = hwreset_get_by_ofw_name(sc->dev, 0, "sdhci", &sc->reset);
291 if (rv != 0) {
292 device_printf(sc->dev, "Cannot get 'sdhci' reset\n");
293 goto fail;
294 }
295 rv = hwreset_assert(sc->reset);
296 if (rv != 0) {
297 device_printf(dev, "Cannot reset 'sdhci' reset\n");
298 goto fail;
299 }
300
301 gpio_pin_get_by_ofw_property(sc->dev, node, "power-gpios",
302 &sc->gpio_power);
303
304 if (OF_hasprop(node, "assigned-clocks")) {
305 rv = clk_set_assigned(sc->dev, node);
306 if (rv != 0) {
307 device_printf(dev, "Cannot set assigned clocks\n");
308 goto fail;
309 }
310 }
311
312 rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk);
313 if (rv != 0) {
314 device_printf(dev, "Cannot get clock\n");
315 goto fail;
316 }
317 rv = clk_enable(sc->clk);
318 if (rv != 0) {
319 device_printf(dev, "Cannot enable clock\n");
320 goto fail;
321 }
322 rv = clk_set_freq(sc->clk, 48000000, CLK_SET_ROUND_DOWN);
323 if (rv != 0) {
324 device_printf(dev, "Cannot set clock\n");
325 }
326 rv = clk_get_freq(sc->clk, &freq);
327 if (rv != 0) {
328 device_printf(dev, "Cannot get clock frequency\n");
329 goto fail;
330 }
331 DELAY(4000);
332 rv = hwreset_deassert(sc->reset);
333 if (rv != 0) {
334 device_printf(dev, "Cannot unreset 'sdhci' reset\n");
335 goto fail;
336 }
337 if (bootverbose)
338 device_printf(dev, " Base MMC clock: %jd\n", (uintmax_t)freq);
339
340 /* Fill slot information. */
341 sc->max_clk = (int)freq;
342 sc->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
343 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
344 SDHCI_QUIRK_MISSING_CAPS;
345
346 /* Limit real slot capabilities. */
347 sc->caps = RD4(sc, SDHCI_CAPABILITIES);
348 if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) {
349 sc->caps &= ~(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA);
350 switch (prop) {
351 case 8:
352 sc->caps |= MMC_CAP_8_BIT_DATA;
353 /* FALLTHROUGH */
354 case 4:
355 sc->caps |= MMC_CAP_4_BIT_DATA;
356 break;
357 case 1:
358 break;
359 default:
360 device_printf(dev, "Bad bus-width value %u\n", prop);
361 break;
362 }
363 }
364 if (OF_hasprop(node, "non-removable"))
365 sc->force_card_present = 1;
366 /*
367 * Clear clock field, so SDHCI driver uses supplied frequency.
368 * in sc->slot.max_clk
369 */
370 sc->caps &= ~SDHCI_CLOCK_V3_BASE_MASK;
371
372 sc->slot.quirks = sc->quirks;
373 sc->slot.max_clk = sc->max_clk;
374 sc->slot.caps = sc->caps;
375
376 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
377 NULL, tegra_sdhci_intr, sc, &sc->intr_cookie)) {
378 device_printf(dev, "cannot setup interrupt handler\n");
379 rv = ENXIO;
380 goto fail;
381 }
382 rv = sdhci_init_slot(dev, &sc->slot, 0);
383 if (rv != 0) {
384 goto fail;
385 }
386
387 sc->gpio = sdhci_fdt_gpio_setup(sc->dev, &sc->slot);
388
389 bus_generic_probe(dev);
390 bus_generic_attach(dev);
391
392 sdhci_start_slot(&sc->slot);
393
394 return (0);
395
396 fail:
397 if (sc->gpio != NULL)
398 sdhci_fdt_gpio_teardown(sc->gpio);
399 if (sc->intr_cookie != NULL)
400 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
401 if (sc->gpio_power != NULL)
402 gpio_pin_release(sc->gpio_power);
403 if (sc->clk != NULL)
404 clk_release(sc->clk);
405 if (sc->reset != NULL)
406 hwreset_release(sc->reset);
407 if (sc->irq_res != NULL)
408 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
409 if (sc->mem_res != NULL)
410 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
411
412 return (rv);
413 }
414
415 static int
tegra_sdhci_detach(device_t dev)416 tegra_sdhci_detach(device_t dev)
417 {
418 struct tegra_sdhci_softc *sc = device_get_softc(dev);
419 struct sdhci_slot *slot = &sc->slot;
420
421 bus_generic_detach(dev);
422 sdhci_fdt_gpio_teardown(sc->gpio);
423 clk_release(sc->clk);
424 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
425 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res),
426 sc->irq_res);
427
428 sdhci_cleanup_slot(slot);
429 bus_release_resource(dev, SYS_RES_MEMORY,
430 rman_get_rid(sc->mem_res),
431 sc->mem_res);
432 return (0);
433 }
434
435 static device_method_t tegra_sdhci_methods[] = {
436 /* Device interface */
437 DEVMETHOD(device_probe, tegra_sdhci_probe),
438 DEVMETHOD(device_attach, tegra_sdhci_attach),
439 DEVMETHOD(device_detach, tegra_sdhci_detach),
440
441 /* Bus interface */
442 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
443 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
444
445 /* MMC bridge interface */
446 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
447 DEVMETHOD(mmcbr_request, sdhci_generic_request),
448 DEVMETHOD(mmcbr_get_ro, tegra_sdhci_get_ro),
449 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
450 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
451
452 /* SDHCI registers accessors */
453 DEVMETHOD(sdhci_read_1, tegra_sdhci_read_1),
454 DEVMETHOD(sdhci_read_2, tegra_sdhci_read_2),
455 DEVMETHOD(sdhci_read_4, tegra_sdhci_read_4),
456 DEVMETHOD(sdhci_read_multi_4, tegra_sdhci_read_multi_4),
457 DEVMETHOD(sdhci_write_1, tegra_sdhci_write_1),
458 DEVMETHOD(sdhci_write_2, tegra_sdhci_write_2),
459 DEVMETHOD(sdhci_write_4, tegra_sdhci_write_4),
460 DEVMETHOD(sdhci_write_multi_4, tegra_sdhci_write_multi_4),
461 DEVMETHOD(sdhci_get_card_present, tegra_sdhci_get_card_present),
462
463 DEVMETHOD_END
464 };
465
466 static DEFINE_CLASS_0(sdhci, tegra_sdhci_driver, tegra_sdhci_methods,
467 sizeof(struct tegra_sdhci_softc));
468 DRIVER_MODULE(sdhci_tegra, simplebus, tegra_sdhci_driver, NULL, NULL);
469 SDHCI_DEPEND(sdhci_tegra);
470 #ifndef MMCCAM
471 MMC_DECLARE_BRIDGE(sdhci);
472 #endif
473