1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include "opt_mmccam.h"
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/bus.h>
34 #include <sys/kernel.h>
35 #include <sys/lock.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/resource.h>
39 #include <sys/rman.h>
40 #include <sys/sysctl.h>
41 #include <sys/taskqueue.h>
42
43 #include <dev/pci/pcireg.h>
44 #include <dev/pci/pcivar.h>
45
46 #include <machine/bus.h>
47 #include <machine/resource.h>
48
49 #include <dev/mmc/bridge.h>
50
51 #include <dev/sdhci/sdhci.h>
52
53 #include "mmcbr_if.h"
54 #include "sdhci_if.h"
55
56 /*
57 * PCI registers
58 */
59 #define PCI_SDHCI_IFPIO 0x00
60 #define PCI_SDHCI_IFDMA 0x01
61 #define PCI_SDHCI_IFVENDOR 0x02
62
63 #define PCI_SLOT_INFO 0x40 /* 8 bits */
64 #define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1)
65 #define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7)
66
67 /*
68 * RICOH specific PCI registers
69 */
70 #define SDHC_PCI_MODE_KEY 0xf9
71 #define SDHC_PCI_MODE 0x150
72 #define SDHC_PCI_MODE_SD20 0x10
73 #define SDHC_PCI_BASE_FREQ_KEY 0xfc
74 #define SDHC_PCI_BASE_FREQ 0xe1
75
76 static const struct sdhci_device {
77 uint32_t model;
78 uint16_t subvendor;
79 const char *desc;
80 u_int quirks;
81 } sdhci_devices[] = {
82 { 0x08221180, 0xffff, "RICOH R5C822 SD",
83 SDHCI_QUIRK_FORCE_DMA },
84 { 0xe8221180, 0xffff, "RICOH R5CE822 SD",
85 SDHCI_QUIRK_FORCE_DMA |
86 SDHCI_QUIRK_LOWER_FREQUENCY },
87 { 0xe8231180, 0xffff, "RICOH R5CE823 SD",
88 SDHCI_QUIRK_LOWER_FREQUENCY },
89 { 0x8034104c, 0xffff, "TI XX21/XX11 SD",
90 SDHCI_QUIRK_FORCE_DMA },
91 { 0x803c104c, 0xffff, "TI XX12 SD",
92 SDHCI_QUIRK_FORCE_DMA |
93 SDHCI_QUIRK_WAITFOR_RESET_ASSERTED },
94 { 0x05501524, 0xffff, "ENE CB712 SD",
95 SDHCI_QUIRK_BROKEN_TIMINGS },
96 { 0x05511524, 0xffff, "ENE CB712 SD 2",
97 SDHCI_QUIRK_BROKEN_TIMINGS },
98 { 0x07501524, 0xffff, "ENE CB714 SD",
99 SDHCI_QUIRK_RESET_ON_IOS |
100 SDHCI_QUIRK_BROKEN_TIMINGS },
101 { 0x07511524, 0xffff, "ENE CB714 SD 2",
102 SDHCI_QUIRK_RESET_ON_IOS |
103 SDHCI_QUIRK_BROKEN_TIMINGS },
104 { 0x410111ab, 0xffff, "Marvell CaFe SD",
105 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL },
106 { 0x2381197B, 0xffff, "JMicron JMB38X SD",
107 SDHCI_QUIRK_32BIT_DMA_SIZE |
108 SDHCI_QUIRK_RESET_AFTER_REQUEST },
109 { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader",
110 SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC },
111 { 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller",
112 /* DDR52 is supported but affected by the VLI54 erratum */
113 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
114 SDHCI_QUIRK_WAIT_WHILE_BUSY |
115 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
116 SDHCI_QUIRK_PRESET_VALUE_BROKEN},
117 { 0x0f158086, 0xffff, "Intel Bay Trail SDXC Controller",
118 SDHCI_QUIRK_WAIT_WHILE_BUSY |
119 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
120 { 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller",
121 /* DDR52 is supported but affected by the VLI54 erratum */
122 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
123 SDHCI_QUIRK_WAIT_WHILE_BUSY |
124 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
125 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
126 { 0x19db8086, 0xffff, "Intel Denverton eMMC 5.0 Controller",
127 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
128 SDHCI_QUIRK_WAIT_WHILE_BUSY |
129 SDHCI_QUIRK_MMC_DDR52 |
130 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
131 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
132 { 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller",
133 SDHCI_QUIRK_DATA_TIMEOUT_1MHZ |
134 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
135 SDHCI_QUIRK_WAIT_WHILE_BUSY |
136 SDHCI_QUIRK_MMC_DDR52 |
137 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
138 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
139 { 0x22968086, 0xffff, "Intel Braswell SDXC Controller",
140 SDHCI_QUIRK_WAIT_WHILE_BUSY |
141 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
142 { 0x5aca8086, 0xffff, "Intel Apollo Lake SDXC Controller",
143 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */
144 SDHCI_QUIRK_WAIT_WHILE_BUSY |
145 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
146 { 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller",
147 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */
148 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
149 SDHCI_QUIRK_WAIT_WHILE_BUSY |
150 SDHCI_QUIRK_MMC_DDR52 |
151 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
152 SDHCI_QUIRK_PRESET_VALUE_BROKEN },
153 { 0, 0xffff, NULL,
154 0 }
155 };
156
157 struct sdhci_pci_softc {
158 u_int quirks; /* Chip specific quirks */
159 struct resource *irq_res; /* IRQ resource */
160 void *intrhand; /* Interrupt handle */
161
162 int num_slots; /* Number of slots on this controller */
163 struct sdhci_slot slots[6];
164 struct resource *mem_res[6]; /* Memory resource */
165 uint8_t cfg_freq; /* Saved frequency */
166 uint8_t cfg_mode; /* Saved mode */
167 };
168
169 static int sdhci_enable_msi = 1;
170 SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi,
171 0, "Enable MSI interrupts");
172
173 static uint8_t
sdhci_pci_read_1(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off)174 sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
175 {
176 struct sdhci_pci_softc *sc = device_get_softc(dev);
177
178 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
179 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
180 return bus_read_1(sc->mem_res[slot->num], off);
181 }
182
183 static void
sdhci_pci_write_1(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off,uint8_t val)184 sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot __unused,
185 bus_size_t off, uint8_t val)
186 {
187 struct sdhci_pci_softc *sc = device_get_softc(dev);
188
189 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
190 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
191 bus_write_1(sc->mem_res[slot->num], off, val);
192 }
193
194 static uint16_t
sdhci_pci_read_2(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off)195 sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
196 {
197 struct sdhci_pci_softc *sc = device_get_softc(dev);
198
199 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
200 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
201 return bus_read_2(sc->mem_res[slot->num], off);
202 }
203
204 static void
sdhci_pci_write_2(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off,uint16_t val)205 sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot __unused,
206 bus_size_t off, uint16_t val)
207 {
208 struct sdhci_pci_softc *sc = device_get_softc(dev);
209
210 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
211 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
212 bus_write_2(sc->mem_res[slot->num], off, val);
213 }
214
215 static uint32_t
sdhci_pci_read_4(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off)216 sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
217 {
218 struct sdhci_pci_softc *sc = device_get_softc(dev);
219
220 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
221 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
222 return bus_read_4(sc->mem_res[slot->num], off);
223 }
224
225 static void
sdhci_pci_write_4(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off,uint32_t val)226 sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot __unused,
227 bus_size_t off, uint32_t val)
228 {
229 struct sdhci_pci_softc *sc = device_get_softc(dev);
230
231 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
232 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
233 bus_write_4(sc->mem_res[slot->num], off, val);
234 }
235
236 static void
sdhci_pci_read_multi_4(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off,uint32_t * data,bus_size_t count)237 sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot __unused,
238 bus_size_t off, uint32_t *data, bus_size_t count)
239 {
240 struct sdhci_pci_softc *sc = device_get_softc(dev);
241
242 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count);
243 }
244
245 static void
sdhci_pci_write_multi_4(device_t dev,struct sdhci_slot * slot __unused,bus_size_t off,uint32_t * data,bus_size_t count)246 sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot __unused,
247 bus_size_t off, uint32_t *data, bus_size_t count)
248 {
249 struct sdhci_pci_softc *sc = device_get_softc(dev);
250
251 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count);
252 }
253
254 static void sdhci_pci_intr(void *arg);
255
256 static void
sdhci_lower_frequency(device_t dev)257 sdhci_lower_frequency(device_t dev)
258 {
259 struct sdhci_pci_softc *sc = device_get_softc(dev);
260
261 /*
262 * Enable SD2.0 mode.
263 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822.
264 */
265 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
266 sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1);
267 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1);
268 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
269
270 /*
271 * Some SD/MMC cards don't work with the default base
272 * clock frequency of 200 MHz. Lower it to 50 MHz.
273 */
274 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
275 sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1);
276 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1);
277 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
278 }
279
280 static void
sdhci_restore_frequency(device_t dev)281 sdhci_restore_frequency(device_t dev)
282 {
283 struct sdhci_pci_softc *sc = device_get_softc(dev);
284
285 /* Restore mode. */
286 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
287 pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1);
288 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
289
290 /* Restore frequency. */
291 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
292 pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1);
293 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
294 }
295
296 static int
sdhci_pci_probe(device_t dev)297 sdhci_pci_probe(device_t dev)
298 {
299 uint32_t model;
300 uint16_t subvendor;
301 uint8_t class, subclass;
302 int i, result;
303
304 model = (uint32_t)pci_get_device(dev) << 16;
305 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
306 subvendor = pci_get_subvendor(dev);
307 class = pci_get_class(dev);
308 subclass = pci_get_subclass(dev);
309
310 result = ENXIO;
311 for (i = 0; sdhci_devices[i].model != 0; i++) {
312 if (sdhci_devices[i].model == model &&
313 (sdhci_devices[i].subvendor == 0xffff ||
314 sdhci_devices[i].subvendor == subvendor)) {
315 device_set_desc(dev, sdhci_devices[i].desc);
316 result = BUS_PROBE_DEFAULT;
317 break;
318 }
319 }
320 if (result == ENXIO && class == PCIC_BASEPERIPH &&
321 subclass == PCIS_BASEPERIPH_SDHC) {
322 device_set_desc(dev, "Generic SD HCI");
323 result = BUS_PROBE_GENERIC;
324 }
325
326 return (result);
327 }
328
329 static int
sdhci_pci_attach(device_t dev)330 sdhci_pci_attach(device_t dev)
331 {
332 struct sdhci_pci_softc *sc = device_get_softc(dev);
333 struct sdhci_slot *slot;
334 uint32_t model;
335 uint16_t subvendor;
336 int bar, err, rid, slots, i;
337
338 model = (uint32_t)pci_get_device(dev) << 16;
339 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
340 subvendor = pci_get_subvendor(dev);
341 /* Apply chip specific quirks. */
342 for (i = 0; sdhci_devices[i].model != 0; i++) {
343 if (sdhci_devices[i].model == model &&
344 (sdhci_devices[i].subvendor == 0xffff ||
345 sdhci_devices[i].subvendor == subvendor)) {
346 sc->quirks = sdhci_devices[i].quirks;
347 break;
348 }
349 }
350 sc->quirks &= ~sdhci_quirk_clear;
351 sc->quirks |= sdhci_quirk_set;
352
353 /* Some controllers need to be bumped into the right mode. */
354 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
355 sdhci_lower_frequency(dev);
356 /* Read slots info from PCI registers. */
357 slots = pci_read_config(dev, PCI_SLOT_INFO, 1);
358 bar = PCI_SLOT_INFO_FIRST_BAR(slots);
359 slots = PCI_SLOT_INFO_SLOTS(slots);
360 if (slots > 6 || bar > 5) {
361 device_printf(dev, "Incorrect slots information (%d, %d).\n",
362 slots, bar);
363 return (EINVAL);
364 }
365 /* Allocate IRQ. */
366 i = 1;
367 rid = 0;
368 if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0)
369 rid = 1;
370 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
371 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
372 if (sc->irq_res == NULL) {
373 device_printf(dev, "Can't allocate IRQ\n");
374 pci_release_msi(dev);
375 return (ENOMEM);
376 }
377 /* Scan all slots. */
378 for (i = 0; i < slots; i++) {
379 slot = &sc->slots[sc->num_slots];
380
381 /* Allocate memory. */
382 rid = PCIR_BAR(bar + i);
383 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
384 &rid, RF_ACTIVE);
385 if (sc->mem_res[i] == NULL) {
386 device_printf(dev,
387 "Can't allocate memory for slot %d\n", i);
388 continue;
389 }
390
391 slot->quirks = sc->quirks;
392
393 if (sdhci_init_slot(dev, slot, i) != 0)
394 continue;
395
396 sc->num_slots++;
397 }
398 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
399 /* Activate the interrupt */
400 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
401 NULL, sdhci_pci_intr, sc, &sc->intrhand);
402 if (err)
403 device_printf(dev, "Can't setup IRQ\n");
404 pci_enable_busmaster(dev);
405 /* Process cards detection. */
406 for (i = 0; i < sc->num_slots; i++) {
407 sdhci_start_slot(&sc->slots[i]);
408 }
409
410 return (0);
411 }
412
413 static int
sdhci_pci_detach(device_t dev)414 sdhci_pci_detach(device_t dev)
415 {
416 struct sdhci_pci_softc *sc = device_get_softc(dev);
417 int i;
418
419 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
420 bus_release_resource(dev, SYS_RES_IRQ,
421 rman_get_rid(sc->irq_res), sc->irq_res);
422 pci_release_msi(dev);
423
424 for (i = 0; i < sc->num_slots; i++) {
425 sdhci_cleanup_slot(&sc->slots[i]);
426 bus_release_resource(dev, SYS_RES_MEMORY,
427 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]);
428 }
429 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
430 sdhci_restore_frequency(dev);
431 return (0);
432 }
433
434 static int
sdhci_pci_shutdown(device_t dev)435 sdhci_pci_shutdown(device_t dev)
436 {
437 struct sdhci_pci_softc *sc = device_get_softc(dev);
438
439 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
440 sdhci_restore_frequency(dev);
441 return (0);
442 }
443
444 static int
sdhci_pci_suspend(device_t dev)445 sdhci_pci_suspend(device_t dev)
446 {
447 struct sdhci_pci_softc *sc = device_get_softc(dev);
448 int i, err;
449
450 err = bus_generic_suspend(dev);
451 if (err)
452 return (err);
453 for (i = 0; i < sc->num_slots; i++)
454 sdhci_generic_suspend(&sc->slots[i]);
455 return (0);
456 }
457
458 static int
sdhci_pci_resume(device_t dev)459 sdhci_pci_resume(device_t dev)
460 {
461 struct sdhci_pci_softc *sc = device_get_softc(dev);
462 int i, err;
463
464 for (i = 0; i < sc->num_slots; i++)
465 sdhci_generic_resume(&sc->slots[i]);
466 err = bus_generic_resume(dev);
467 if (err)
468 return (err);
469 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
470 sdhci_lower_frequency(dev);
471 return (0);
472 }
473
474 static void
sdhci_pci_intr(void * arg)475 sdhci_pci_intr(void *arg)
476 {
477 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg;
478 int i;
479
480 for (i = 0; i < sc->num_slots; i++)
481 sdhci_generic_intr(&sc->slots[i]);
482 }
483
484 static device_method_t sdhci_methods[] = {
485 /* device_if */
486 DEVMETHOD(device_probe, sdhci_pci_probe),
487 DEVMETHOD(device_attach, sdhci_pci_attach),
488 DEVMETHOD(device_detach, sdhci_pci_detach),
489 DEVMETHOD(device_shutdown, sdhci_pci_shutdown),
490 DEVMETHOD(device_suspend, sdhci_pci_suspend),
491 DEVMETHOD(device_resume, sdhci_pci_resume),
492
493 /* Bus interface */
494 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
495 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
496
497 /* mmcbr_if */
498 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
499 DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq),
500 DEVMETHOD(mmcbr_tune, sdhci_generic_tune),
501 DEVMETHOD(mmcbr_retune, sdhci_generic_retune),
502 DEVMETHOD(mmcbr_request, sdhci_generic_request),
503 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro),
504 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
505 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
506
507 /* SDHCI accessors */
508 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1),
509 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2),
510 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4),
511 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4),
512 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1),
513 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2),
514 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4),
515 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4),
516 DEVMETHOD(sdhci_set_uhs_timing, sdhci_generic_set_uhs_timing),
517
518 DEVMETHOD_END
519 };
520
521 static driver_t sdhci_pci_driver = {
522 "sdhci_pci",
523 sdhci_methods,
524 sizeof(struct sdhci_pci_softc),
525 };
526
527 DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, NULL, NULL);
528 SDHCI_DEPEND(sdhci_pci);
529
530 #ifndef MMCCAM
531 MMC_DECLARE_BRIDGE(sdhci_pci);
532 #endif
533