1 /****************************************************************************** 2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3 * 4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided 5 *that the following conditions are met: 6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7 *following disclaimer. 8 *2. Redistributions in binary form must reproduce the above copyright notice, 9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided 10 *with the distribution. 11 * 12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20 * 21 * 22 ******************************************************************************/ 23 /*****************************************************************************/ 24 /*! \file sa_spec.h 25 * \brief The file defines the constants defined by sas spec 26 */ 27 28 /*****************************************************************************/ 29 30 #ifndef __SA_SPEC_H__ 31 #define __SA_SPEC_H__ 32 33 /**************************************************************** 34 * SAS Specification related defines * 35 ****************************************************************/ 36 #define SA_SAS_PROTOCOL_SMP 0x00 37 #define SA_SAS_PROTOCOL_SSP 0x01 38 #define SA_SAS_PROTOCOL_STP 0x02 39 40 #define SA_OPENFRM_SIZE (28) 41 #define SA_IDENTIFY_FRAME_SIZE (28) 42 //#define SAS_IDENTIFY_FRM_SIZE SA_IDENTIFY_FRAME_SIZE 43 44 #define SA_SAS_FRAME_TYPE_SSP_DATA 0x01 45 #define SA_SAS_FRAME_TYPE_SSP_XRDY 0x05 46 #define SA_SAS_FRAME_TYPE_SSP_CMD 0x06 47 #define SA_SAS_FRAME_TYPE_SSP_RSP 0x07 48 #define SA_SAS_FRAME_TYPE_SSP_TASK 0x16 49 #define SA_SAS_FRAME_TYPE_SMP_REQ 0x40 50 #define SA_SAS_FRAME_TYPE_SMP_RSP 0x41 51 52 #define SA_SAS_CONNECTION_RATE_1_5G 0x08 53 #define SA_SAS_CONNECTION_RATE_3_0G 0x09 54 #define SA_SAS_CONNECTION_RATE_6_0G 0x0A 55 #define SA_SAS_CONNECTION_RATE_12_0G 0x0B 56 57 #define SA_SAS_DEV_TYPE_NO_DEVICE 0x00 58 #define SA_SAS_DEV_TYPE_END_DEVICE 0x01 59 #define SA_SAS_DEV_TYPE_EDGE_EXPANDER 0x02 60 #define SA_SAS_DEV_TYPE_FANOUT_EXPANDER 0x03 61 62 #define AGSA_DEV_TYPE_END_DEVICE (SA_SAS_DEV_TYPE_END_DEVICE << 4) 63 #define AGSA_DEV_TYPE_EDGE_EXPANDER (SA_SAS_DEV_TYPE_EDGE_EXPANDER << 4) 64 #define AGSA_DEV_TYPE_FAN_EXPANDER (SA_SAS_DEV_TYPE_FANOUT_EXPANDER << 4) 65 66 #define SA_SAS_SMP_REPORT_GENERAL 0x00 67 #define SA_SAS_SMP_REPORT_MANUFACTURE_INFORMATION 0x01 68 #define SA_SAS_SMP_READ_GPIO_REGISTER 0x02 69 #define SA_SAS_SMP_DISCOVER 0x10 70 #define SA_SAS_SMP_REPORT_PHY_ERROR_LOG 0x11 71 #define SA_SAS_SMP_REPORT_PHY_SATA 0x12 72 #define SA_SAS_SMP_REPORT_ROUTING_INFORMATION 0x13 73 #define SA_SAS_SMP_WRITE_GPIO_REGISTER 0x82 74 #define SA_SAS_SMP_CONFIGURE_ROUTING_INFORMATION 0x90 75 #define SA_SAS_SMP_PHY_CONTROL 0x91 76 #define SA_SAS_SMP_PHY_TEST 0x92 77 78 #define SA_SAS_SMP_FUNCTION_ACCEPTED 0x00 79 #define SA_SAS_SMP_FUNCTION_UNKNOWN 0x01 80 #define SA_SAS_SMP_FUNCTION_FAILED 0x02 81 #define SA_SAS_SMP_INVALID_REQ_FRAME_LENGTH 0x03 82 #define SA_SAS_SMP_PHY_NOT_EXIST 0x10 83 84 #define SA_SAS_ROUTING_DIRECT 0x00 85 #define SA_SAS_ROUTING_SUBTRACTIVE 0x01 86 #define SA_SAS_ROUTING_TABLE 0x02 87 88 #define SA_SAS_PHYCTL_LINK_RESET 0x01 89 #define SA_SAS_PHYCTL_HARD_RESET 0x02 90 #define SA_SAS_PHYCTL_DISABLE 0x03 91 #define SA_SAS_PHYCTL_CLEAR_ERROR_LOG 0x05 92 #define SA_SAS_PHYCTL_CLEAR_AFFILIATION 0x06 93 #define SA_SAS_PHYCTL_TRANSMIT_PS_SIGNAL 0x07 94 95 #define SA_SSP_CMDIU_LEN_BYTES 28 96 #define SA_SSP_TMIU_LEN_BYTES 28 97 98 99 #define SASD_DEV_SATA_MASK 0xF0 100 #define SASD_DEV_SAS_MASK 0x0F 101 102 #define SASD_DEV_SAS_END_DEVICE 0x01 /* SAS end device type */ 103 #define SASD_DEV_SAS_EDGE_EXPANDER 0x02 /* SAS edge expander device type */ 104 #define SASD_DEV_SAS_FAN_EXPANDER 0x03 /* SAS fan out expander device type */ 105 106 #define SASD_DEV_SATA_ATA_DEVICE 0x10 /* SATA ATA device type */ 107 #define SASD_DEV_SATA_ATAPI_DEVICE 0x20 /* SATA ATAPI device type */ 108 #define SASD_DEV_SATA_PM_DEVICE 0x30 /* SATA PM device type */ 109 #define SASD_DEV_SATA_SEMB_DEVICE 0x40 /* SATA SEMB device type */ 110 #define SASD_DEV_SATA_SEMB_WO_SEP_DEVICE 0x50 /* SATA SEMB without SEP device type */ 111 112 #define SASD_DEV_SATA_UNKNOWN_DEVICE 0xFF /* SAS SATA unknown device type */ 113 114 115 #define SASD_TASK_ATTR_SIMPLE 0x0 116 #define SASD_TASK_ATTR_HEAD_OF_QUEUE 0x1 117 #define SASD_TASK_ATTR_ORDERED 0x2 118 #define SASD_TASK_ATTR_ACA 0x4 119 120 121 /***************************************************************************** 122 ** SAS TM Function definitions 123 *****************************************************************************/ 124 #define SASD_SAS_ABORT_TASK 0x01 125 #define SASD_SAS_ABORT_TASK_SET 0x02 126 #define SASD_SAS_CLEAR_TASK_SET 0x04 127 #define SASD_SAS_LOGICAL_UNIT_RESET 0x08 128 #define SASD_SAS_CLEAR_ACA 0x40 129 #define SASD_SAS_QUARY_TASK 0x80 130 131 /**************************************************************** 132 * SATA Specification related defines * 133 ****************************************************************/ 134 #define SA_SATA_MAX_QUEUED_COMMANDS 32 135 #define SA_SATA_MAX_PM_PORTS 15 136 137 #define SA_SATA_FIS_TYPE_HOST_2_DEV 0x27 138 #define SA_SATA_FIS_TYPE_DEV_2_HOST 0x34 139 #define SA_SATA_FIS_TYPE_SET_DEVICE 0xA1 140 #define SA_SATA_FIS_TYPE_DMA_ACTIVE 0x39 141 #define SA_SATA_FIS_TYPE_FDMA_SETUP 0x41 142 #define SA_SATA_FIS_TYPE_BIST 0x58 143 144 #define SA_SATA_CMD_IDENTIFY_DEVICE 0xEC 145 #define SA_SATA_CMD_EXEC_DEV_DIAG 0x90 146 147 #define SA_SATA_CONTROL_SRST 0x04 148 149 #define SA_SATA_H2DREG_LEN_BYTES 20 150 #define SA_SATA_H2D_BIST_LEN_BYTES 12 151 /**************************************************************** 152 * SAS Specification related structures * 153 ****************************************************************/ 154 155 156 157 /** \brief Structure for SATA BIST FIS 158 * 159 * The agsaFisBIST_t data structure describes a SATA FIS (Frame Information Structures) 160 * for FIS type BIST (Built In Self Test) Activate Bidirectional. 161 * 162 * This data structure is one instance of the SATA request structure agsaSATAInitiatorRequest_t, 163 * which is one instance of the generic request, issued to saSATAStart(). 164 */ 165 166 167 #define SA_SATA_BIST_PATTERN_T_BIT 0x80 168 #define SA_SATA_BIST_PATTERN_A_BIT 0x40 169 #define SA_SATA_BIST_PATTERN_S_BIT 0x20 170 #define SA_SATA_BIST_PATTERN_L_BIT 0x10 171 #define SA_SATA_BIST_PATTERN_F_BIT 0x08 172 #define SA_SATA_BIST_PATTERN_P_BIT 0x04 173 #define SA_SATA_BIST_PATTERN_R_BIT 0x02 174 #define SA_SATA_BIST_PATTERN_V_BIT 0x01 175 176 /* 177 * The first SATA DWORD types. 178 */ 179 typedef struct agsaFisBISTHeader_s 180 { 181 bit8 fisType; /* fisType, set to 58h for BIST */ 182 bit8 pmPort; 183 /* b7-b4 reserved */ 184 /* b3-b0 PM Port. device port address that the PM should deliver the FIS to */ 185 bit8 patternDefinition; 186 /* b7 : T Far end transmit only mode */ 187 /* b6 : A ALIGN Bypass (Do not Transmit Align Primitives) (valid only in combination with T Bit) (optional behavior) */ 188 /* b5 : S Bypass Scrambling (valid only in combination with T Bit) (optional behavior) */ 189 /* b4 : L Far End Retimed Loopback. Transmitter shall insert additional ALIGNS) */ 190 /* b3 : F Far End Analog (AFE) Loopback (Optional) */ 191 /* b2 : P Primitive bit. (valid only in combination with the T Bit) (optional behavior) */ 192 /* b1 : R Reserved */ 193 /* b0 : V Vendor Specific Test Mode. Causes all other bits to be ignored */ 194 bit8 reserved5; /* Reserved */ 195 } agsaFisBISTHeader_t; 196 197 198 typedef struct agsaFisRegD2HHeader_s 199 { 200 bit8 fisType; /* fisType, set to 34h for DeviceToHostReg */ 201 bit8 i_pmPort; 202 /* b7 : reserved */ 203 /* b6 : I Interrupt bit */ 204 /* b5-b4 : reserved */ 205 /* b3-b0 : PM Port */ 206 bit8 status; /* Contains the contents to be placed in the Status(and Alternate status) 207 Register of the Shadow Command Block */ 208 bit8 error; /* Contains the contents to be placed in the Error register of the Shadow Command Block */ 209 } agsaFisRegD2HHeader_t; 210 211 typedef struct agsaFisSetDevBitsHeader_s 212 { 213 bit8 fisType; /* fisType, set to A1h for SetDeviceBit */ 214 bit8 n_i_pmPort; 215 /* b7 : n Bit. Notification bit. If set device needs attention. */ 216 /* b6 : i Bit. Interrupt Bit */ 217 /* b5-b4: reserved2 */ 218 /* b3-b0: PM Port */ 219 bit8 statusHi_Lo; 220 /* b7 : reserved */ 221 /* b6-b4: Status Hi. Contains the contents to be placed in bits 6, 5, and 4 of 222 the Status register of the Shadow Command Block */ 223 /* b3 : Reserved */ 224 /* b2-b0: Status Lo Contains the contents to be placed in bits 2,1, and 0 of the 225 Status register of the Shadow Command Block */ 226 bit8 error; /* Contains the contents to be placed in the Error register of 227 the Shadow Command Block */ 228 } agsaFisSetDevBitsHeader_t; 229 230 typedef struct agsaFisRegH2DHeader_s 231 { 232 bit8 fisType; /* fisType, set to 27h for DeviceToHostReg */ 233 bit8 c_pmPort; 234 /* b7 : C_bit This bit is set to one when the register transfer is 235 due to an update of the Command register */ 236 /* b6-b4: reserved */ 237 /* b3-b0: PM Port */ 238 bit8 command; /* Contains the contents of the Command register of 239 the Shadow Command Block */ 240 bit8 features; /* Contains the contents of the Features register of 241 the Shadow Command Block */ 242 } agsaFisRegH2DHeader_t; 243 244 typedef struct agsaFisPioSetupHeader_s 245 { 246 bit8 fisType; /* set to 5F */ 247 bit8 i_d_pmPort; 248 /* b7 : reserved */ 249 /* b6 : i bit. Interrupt bit */ 250 /* b5 : d bit. data transfer direction. set to 1 for device to host xfer */ 251 /* b4 : reserved */ 252 /* b3-b0: PM Port */ 253 bit8 status; 254 bit8 error; 255 } agsaFisPioSetupHeader_t; 256 257 typedef union agsaFisHeader_s 258 { 259 agsaFisBISTHeader_t Bist; 260 agsaFisRegD2HHeader_t D2H; 261 agsaFisRegH2DHeader_t H2D; 262 agsaFisSetDevBitsHeader_t SetDevBits; 263 agsaFisPioSetupHeader_t PioSetup; 264 } agsaFisHeader_t; 265 266 267 typedef struct agsaFisBISTData_s 268 { 269 bit8 data[8]; /* BIST data */ 270 } agsaFisBISTData_t; 271 272 273 typedef struct agsaFisBIST_s 274 { 275 agsaFisBISTHeader_t h; 276 agsaFisBISTData_t d; 277 } agsaFisBIST_t; 278 279 /** \brief Structure for SATA Device to Host Register FIS 280 * 281 * The agsaFisRegDeviceToHost_t data structure describes a SATA FIS (Frame Information 282 * Structures) for FIS type Register Device to Host. 283 * 284 * This structure is used only as inbound data (device to host) to describe device to 285 * host response. 286 */ 287 288 #define SA_SATA_RD2H_I_BIT 0x40 289 290 typedef struct agsaFisRegD2HData_s 291 { 292 bit8 lbaLow; /* Contains the contents to be placed in the LBA Low register 293 of the Shadow Command Block */ 294 bit8 lbaMid; /* Contains the contents to be placed in the LBA Mid register 295 of the Shadow Command Block */ 296 297 bit8 lbaHigh; /* Contains the contents to be placed in the LBA High register 298 of the Shadow Command Block */ 299 bit8 device; /* Contains the contents to be placed in the Device register of the Shadow Command Block */ 300 301 bit8 lbaLowExp; /* Contains the contents of the expanded address field 302 of the Shadow Command Block */ 303 bit8 lbaMidExp; /* Contains the contents of the expanded address field 304 of the Shadow Command Block */ 305 bit8 lbaHighExp; /* Contains the contents of the expanded address field 306 of the Shadow Command Block */ 307 bit8 reserved4; /** reserved */ 308 309 bit8 sectorCount; /* Contains the contents to be placed in the Sector 310 Count register of the Shadow Command Block */ 311 bit8 sectorCountExp; /* Contains the contents of the expanded address 312 field of the Shadow Command Block */ 313 bit8 reserved6; /* Reserved */ 314 bit8 reserved5; /* Reserved */ 315 bit32 reserved7; /* Reserved */ 316 } agsaFisRegD2HData_t; 317 318 319 typedef struct agsaFisRegDeviceToHost_s 320 { 321 agsaFisRegD2HHeader_t h; 322 agsaFisRegD2HData_t d; 323 } agsaFisRegDeviceToHost_t; 324 325 326 327 /** \brief Structure for SATA Host to Device Register FIS 328 * 329 * The agsaFisRegHostToDevice_t data structure describes a SATA FIS 330 * (Frame Information Structures) for FIS type Register Host to Device. 331 332 * This data structure is one instance of the SATA request structure 333 * agsaSATAInitiatorRequest_t, which is one instance of the generic request, 334 * issued to saSATAStart(). 335 */ 336 typedef struct agsaFisRegH2DData_s 337 { 338 bit8 lbaLow; /* Contains the contents of the LBA Low register of the Shadow Command Block */ 339 bit8 lbaMid; /* Contains the contents of the LBA Mid register of the Shadow Command Block */ 340 bit8 lbaHigh; /* Contains the contents of the LBA High register of the Shadow Command Block */ 341 bit8 device; /* Contains the contents of the Device register of the Shadow Command Block */ 342 343 bit8 lbaLowExp; /* Contains the contents of the expanded address field of the 344 Shadow Command Block */ 345 bit8 lbaMidExp; /* Contains the contents of the expanded address field of the 346 Shadow Command Block */ 347 bit8 lbaHighExp; /* Contains the contents of the expanded address field of the 348 Shadow Command Block */ 349 bit8 featuresExp; /* Contains the contents of the expanded address field of the 350 Shadow Command Block */ 351 352 bit8 sectorCount; /* Contains the contents of the Sector Count register of the 353 Shadow Command Block */ 354 bit8 sectorCountExp; /* Contains the contents of the expanded address field of 355 the Shadow Command Block */ 356 bit8 reserved4; /* Reserved */ 357 bit8 control; /* Contains the contents of the Device Control register of the 358 Shadow Command Block */ 359 bit32 reserved5; /* Reserved */ 360 } agsaFisRegH2DData_t; 361 362 typedef struct agsaFisRegHostToDevice_s 363 { 364 agsaFisRegH2DHeader_t h; 365 agsaFisRegH2DData_t d; 366 } agsaFisRegHostToDevice_t; 367 368 369 /** \brief Structure for SATA SetDeviceBit FIS 370 * 371 * The agsaFisSetDevBits_t data structure describes a SATA FIS (Frame Information Structures) 372 * for FIS type Set Device Bits - Device to Host. 373 * 374 * This structure is used only as inbound data (device to host) to describe device to host 375 * response. 376 */ 377 typedef struct agsaFisSetDevBitsData_s 378 { 379 bit32 reserved6; /* Reserved */ 380 } agsaFisSetDevBitsData_t; 381 382 383 typedef struct agsaFisSetDevBits_s 384 { 385 agsaFisSetDevBitsHeader_t h; 386 agsaFisSetDevBitsData_t d; 387 } agsaFisSetDevBits_t; 388 389 390 /** \brief union data structure specifies a FIS from host software 391 * 392 * union data structure specifies a FIS from host software 393 */ 394 typedef union agsaSATAHostFis_u 395 { 396 agsaFisRegHostToDevice_t fisRegHostToDev; /* Structure containing the FIS request 397 for Register - Host to Device */ 398 agsaFisBIST_t fisBIST; /* Structure containing the FIS request for BIST */ 399 } agsaSATAHostFis_t; 400 401 /** \brief 402 * 403 * This structure is used 404 * 405 */ 406 typedef struct agsaFisPioSetupData_s 407 { 408 bit8 lbaLow; /* Contains the contents of the LBA Low register of the Shadow Command Block */ 409 bit8 lbaMid; /* Contains the contents of the LBA Mid register of the Shadow Command Block */ 410 bit8 lbaHigh; /* Contains the contents of the LBA High register of the Shadow Command Block */ 411 bit8 device; /* Contains the contents of the Device register of the Shadow Command Block */ 412 413 bit8 lbaLowExp; /* Contains the contents of the expanded address field of the 414 Shadow Command Block */ 415 bit8 lbaMidExp; /* Contains the contents of the expanded address field of the 416 Shadow Command Block */ 417 bit8 lbaHighExp; /* Contains the contents of the expanded address field of the 418 Shadow Command Block */ 419 bit8 reserved1; /* reserved */ 420 421 bit8 sectorCount; /* Contains the contents of the Sector Count register of the 422 Shadow Command Block */ 423 bit8 sectorCountExp; /* Contains the contents of the expanded address field of 424 the Shadow Command Block */ 425 bit8 reserved2; /* Reserved */ 426 bit8 e_status; /* Contains the new value of Status Reg of the Command block 427 at the conclusion of the subsequent Data FIS */ 428 bit8 reserved4[2]; /* Reserved */ 429 bit8 transferCount[2]; /* the number of bytes to be xfered in the subsequent Data FiS */ 430 } agsaFisPioSetupData_t; 431 432 433 typedef struct agsaFisPioSetup_s 434 { 435 agsaFisPioSetupHeader_t h; 436 agsaFisPioSetupData_t d; 437 } agsaFisPioSetup_t; 438 439 440 441 /** \brief describe SAS IDENTIFY address frame 442 * 443 * describe SAS IDENTIFY address frame, the CRC field is not included in the structure 444 * 445 */ 446 typedef struct agsaSASIdentify_s 447 { 448 bit8 deviceType_addressFrameType; 449 /* b7 : reserved */ 450 /* b6-4 : device type */ 451 /* b3-0 : address frame type */ 452 bit8 reason; /* reserved */ 453 /* b7-4 : reserved */ 454 /* b3-0 : reason SAS2 */ 455 bit8 initiator_ssp_stp_smp; 456 /* b8-4 : reserved */ 457 /* b3 : SSP initiator port */ 458 /* b2 : STP initiator port */ 459 /* b1 : SMP initiator port */ 460 /* b0 : reserved */ 461 bit8 target_ssp_stp_smp; 462 /* b8-4 : reserved */ 463 /* b3 : SSP target port */ 464 /* b2 : STP target port */ 465 /* b1 : SMP target port */ 466 /* b0 : reserved */ 467 bit8 deviceName[8]; /* reserved */ 468 469 bit8 sasAddressHi[4]; /* BE SAS address Lo */ 470 bit8 sasAddressLo[4]; /* BE SAS address Hi */ 471 472 bit8 phyIdentifier; /* phy identifier of the phy transmitting the IDENTIFY address frame */ 473 bit8 zpsds_breakReplyCap; 474 /* b7-3 : reserved */ 475 /* b2 : Inside ZPSDS Persistent */ 476 /* b1 : Requested Inside ZPSDS */ 477 /* b0 : Break Reply Capable */ 478 bit8 reserved3[6]; /* reserved */ 479 } agsaSASIdentify_t; 480 481 #define SA_IDFRM_GET_SAS_ADDRESSLO(identFrame) \ 482 DMA_BEBIT32_TO_BIT32(*(bit32 *)(identFrame)->sasAddressLo) 483 484 #define SA_IDFRM_GET_SAS_ADDRESSHI(identFrame) \ 485 DMA_BEBIT32_TO_BIT32(*(bit32 *)(identFrame)->sasAddressHi) 486 487 #define SA_IDFRM_GET_DEVICETTYPE(identFrame) \ 488 (((identFrame)->deviceType_addressFrameType & 0x70) >> 4) 489 490 #define SA_IDFRM_PUT_SAS_ADDRESSLO(identFrame, src32) \ 491 ((*(bit32 *)((identFrame)->sasAddressLo)) = BIT32_TO_DMA_BEBIT32(src32)) 492 493 #define SA_IDFRM_PUT_SAS_ADDRESSHI(identFrame, src32) \ 494 ((*(bit32 *)((identFrame)->sasAddressHi)) = BIT32_TO_DMA_BEBIT32(src32)) 495 496 #define SA_IDFRM_SSP_BIT 0x8 /* SSP Initiator port */ 497 #define SA_IDFRM_STP_BIT 0x4 /* STP Initiator port */ 498 #define SA_IDFRM_SMP_BIT 0x2 /* SMP Initiator port */ 499 #define SA_IDFRM_SATA_BIT 0x1 /* SATA device, valid in the discovery response only */ 500 501 502 #define SA_IDFRM_IS_SSP_INITIATOR(identFrame) \ 503 (((identFrame)->initiator_ssp_stp_smp & SA_IDFRM_SSP_BIT) == SA_IDFRM_SSP_BIT) 504 505 #define SA_IDFRM_IS_STP_INITIATOR(identFrame) \ 506 (((identFrame)->initiator_ssp_stp_smp & SA_IDFRM_STP_BIT) == SA_IDFRM_STP_BIT) 507 508 #define SA_IDFRM_IS_SMP_INITIATOR(identFrame) \ 509 (((identFrame)->initiator_ssp_stp_smp & SA_IDFRM_SMP_BIT) == SA_IDFRM_SMP_BIT) 510 511 #define SA_IDFRM_IS_SSP_TARGET(identFrame) \ 512 (((identFrame)->target_ssp_stp_smp & SA_IDFRM_SSP_BIT) == SA_IDFRM_SSP_BIT) 513 514 #define SA_IDFRM_IS_STP_TARGET(identFrame) \ 515 (((identFrame)->target_ssp_stp_smp & SA_IDFRM_STP_BIT) == SA_IDFRM_STP_BIT) 516 517 #define SA_IDFRM_IS_SMP_TARGET(identFrame) \ 518 (((identFrame)->target_ssp_stp_smp & SA_IDFRM_SMP_BIT) == SA_IDFRM_SMP_BIT) 519 520 #define SA_IDFRM_IS_SATA_DEVICE(identFrame) \ 521 (((identFrame)->target_ssp_stp_smp & SA_IDFRM_SATA_BIT) == SA_IDFRM_SATA_BIT) 522 523 /** \brief data structure provides the identify data of the SATA device 524 * 525 * data structure provides the identify data of the SATA device 526 * 527 */ 528 typedef struct agsaSATAIdentifyData_s 529 { 530 bit16 rm_ataDevice; 531 /* b15-b9 : */ 532 /* b8 : ataDevice */ 533 /* b7-b1 : */ 534 /* b0 : removableMedia */ 535 bit16 word1_9[9]; /**< word 1 to 9 of identify device information */ 536 bit8 serialNumber[20]; /**< word 10 to 19 of identify device information, 20 ASCII chars */ 537 bit16 word20_22[3]; /**< word 20 to 22 of identify device information */ 538 bit8 firmwareVersion[8]; /**< word 23 to 26 of identify device information, 4 ASCII chars */ 539 bit8 modelNumber[40]; /**< word 27 to 46 of identify device information, 40 ASCII chars */ 540 bit16 word47_48[2]; /**< word 47 to 48 of identify device information, 40 ASCII chars */ 541 bit16 dma_lba_iod_ios_stimer; 542 /* b15-b14:word49_bit14_15 */ 543 /* b13 : standbyTimerSupported */ 544 /* b12 : word49_bit12 */ 545 /* b11 : IORDYSupported */ 546 /* b10 : IORDYDisabled */ 547 /* b9 : lbaSupported */ 548 /* b8 : dmaSupported */ 549 /* b7-b0 : retired */ 550 bit16 word50_52[3]; /**< word 50 to 52 of identify device information, 40 ASCII chars */ 551 bit16 valid_w88_w70; 552 /* b15-3 : word53_bit3_15 */ 553 /* b2 : validWord88 */ 554 /* b1 : validWord70_64 */ 555 /* b0 : word53_bit0 */ 556 bit16 word54_59[6]; /**< word54-59 of identify device information */ 557 bit16 numOfUserAddressableSectorsLo; /**< word60 of identify device information */ 558 bit16 numOfUserAddressableSectorsHi; /**< word61 of identify device information */ 559 bit16 word62_74[13]; /**< word62-74 of identify device information */ 560 bit16 queueDepth; 561 /* b15-5 : word75_bit5_15 */ 562 /* b4-0 : queueDepth */ 563 bit16 sataCapabilities; 564 /* b15-b11: word76_bit11_15 */ 565 /* b10 : phyEventCountersSupport */ 566 /* b9 : hostInitPowerMangment */ 567 /* b8 : nativeCommandQueuing */ 568 /* b7-b3 : word76_bit4_7 */ 569 /* b2 : sataGen2Supported (3.0 Gbps) */ 570 /* b1 : sataGen1Supported (1.5 Gbps) */ 571 /* b0 :word76_bit0 */ 572 bit16 word77; /**< word77 of identify device information */ 573 /* b15-b6 : word77 bit6_15, Reserved */ 574 /* b5 : DMA Setup Auto-Activate support */ 575 /* b4 : NCQ streaming support */ 576 /* b3-b1 : coded value indicating current negotiated SATA signal speed */ 577 /* b0 : shall be zero */ 578 bit16 sataFeaturesSupported; 579 /* b15-b7 : word78_bit7_15 */ 580 /* b6 : softSettingPreserveSupported */ 581 /* b5 : word78_bit5 */ 582 /* b4 : inOrderDataDeliverySupported */ 583 /* b3 : devInitPowerManagementSupported */ 584 /* b2 : autoActiveDMASupported */ 585 /* b1 : nonZeroBufOffsetSupported */ 586 /* b0 : word78_bit0 */ 587 bit16 sataFeaturesEnabled; 588 /* b15-7 : word79_bit7_15 */ 589 /* b6 : softSettingPreserveEnabled */ 590 /* b5 : word79_bit5 */ 591 /* b4 : inOrderDataDeliveryEnabled */ 592 /* b3 : devInitPowerManagementEnabled */ 593 /* b2 : autoActiveDMAEnabled */ 594 /* b1 : nonZeroBufOffsetEnabled */ 595 /* b0 : word79_bit0 */ 596 bit16 majorVersionNumber; 597 /* b15 : word80_bit15 */ 598 /* b14 : supportATA_ATAPI14 */ 599 /* b13 : supportATA_ATAPI13 */ 600 /* b12 : supportATA_ATAPI12 */ 601 /* b11 : supportATA_ATAPI11 */ 602 /* b10 : supportATA_ATAPI10 */ 603 /* b9 : supportATA_ATAPI9 */ 604 /* b8 : supportATA_ATAPI8 */ 605 /* b7 : supportATA_ATAPI7 */ 606 /* b6 : supportATA_ATAPI6 */ 607 /* b5 : supportATA_ATAPI5 */ 608 /* b4 : supportATA_ATAPI4 */ 609 /* b3 : supportATA3 */ 610 /* b2-0 : word80_bit0_2 */ 611 bit16 minorVersionNumber; /**< word81 of identify device information */ 612 bit16 commandSetSupported; 613 /* b15 : word82_bit15 */ 614 /* b14 : NOPSupported */ 615 /* b13 : READ_BUFFERSupported */ 616 /* b12 : WRITE_BUFFERSupported */ 617 /* b11 : word82_bit11 */ 618 /* b10 : hostProtectedAreaSupported */ 619 /* b9 : DEVICE_RESETSupported */ 620 /* b8 : SERVICEInterruptSupported */ 621 /* b7 : releaseInterruptSupported */ 622 /* b6 : lookAheadSupported */ 623 /* b5 : writeCacheSupported */ 624 /* b4 : word82_bit4 */ 625 /* b3 : mandPowerManagmentSupported */ 626 /* b2 : removableMediaSupported */ 627 /* b1 : securityModeSupported */ 628 /* b0 : SMARTSupported */ 629 bit16 commandSetSupported1; 630 /* b15-b14: word83_bit14_15 */ 631 /* b13 : FLUSH_CACHE_EXTSupported */ 632 /* b12 : mandatoryFLUSH_CACHESupported */ 633 /* b11 : devConfOverlaySupported */ 634 /* b10 : address48BitsSupported */ 635 /* b9 : autoAcousticManageSupported */ 636 /* b8 : SET_MAX_SecurityExtSupported */ 637 /* b7 : word83_bit7 */ 638 /* b6 : SET_FEATUREReqSpinupSupported */ 639 /* b5 : powerUpInStandyBySupported */ 640 /* b4 : removableMediaStNotifSupported */ 641 /* b3 : advanPowerManagmentSupported */ 642 /* b2 : CFASupported */ 643 /* b1 : DMAQueuedSupported */ 644 /* b0 : DOWNLOAD_MICROCODESupported */ 645 bit16 commandSetFeatureSupportedExt; 646 /* b15-b13: word84_bit13_15 */ 647 /* b12 : timeLimitRWContSupported */ 648 /* b11 : timeLimitRWSupported */ 649 /* b10 : writeURGBitSupported */ 650 /* b9 : readURGBitSupported */ 651 /* b8 : wwwNameSupported */ 652 /* b7 : WRITE_DMAQ_FUA_EXTSupported */ 653 /* b6 : WRITE_FUA_EXTSupported */ 654 /* b5 : generalPurposeLogSupported */ 655 /* b4 : streamingSupported */ 656 /* b3 : mediaCardPassThroughSupported */ 657 /* b2 : mediaSerialNoSupported */ 658 /* b1 : SMARTSelfRestSupported */ 659 /* b0 : SMARTErrorLogSupported */ 660 bit16 commandSetFeatureEnabled; 661 /* b15 : word85_bit15 */ 662 /* b14 : NOPEnabled */ 663 /* b13 : READ_BUFFEREnabled */ 664 /* b12 : WRITE_BUFFEREnabled */ 665 /* b11 : word85_bit11 */ 666 /* b10 : hostProtectedAreaEnabled */ 667 /* b9 : DEVICE_RESETEnabled */ 668 /* b8 : SERVICEInterruptEnabled */ 669 /* b7 : releaseInterruptEnabled */ 670 /* b6 : lookAheadEnabled */ 671 /* b5 : writeCacheEnabled */ 672 /* b4 : word85_bit4 */ 673 /* b3 : mandPowerManagmentEnabled */ 674 /* b2 : removableMediaEnabled */ 675 /* b1 : securityModeEnabled */ 676 /* b0 : SMARTEnabled */ 677 bit16 commandSetFeatureEnabled1; 678 /* b15-b14: word86_bit14_15 */ 679 /* b13 : FLUSH_CACHE_EXTEnabled */ 680 /* b12 : mandatoryFLUSH_CACHEEnabled */ 681 /* b11 : devConfOverlayEnabled */ 682 /* b10 : address48BitsEnabled */ 683 /* b9 : autoAcousticManageEnabled */ 684 /* b8 : SET_MAX_SecurityExtEnabled */ 685 /* b7 : word86_bit7 */ 686 /* b6 : SET_FEATUREReqSpinupEnabled */ 687 /* b5 : powerUpInStandyByEnabled */ 688 /* b4 : removableMediaStNotifEnabled */ 689 /* b3 : advanPowerManagmentEnabled */ 690 /* b2 : CFAEnabled */ 691 /* b1 : DMAQueuedEnabled */ 692 /* b0 : DOWNLOAD_MICROCODEEnabled */ 693 bit16 commandSetFeatureDefault; 694 /* b15-b13: word87_bit13_15 */ 695 /* b12 : timeLimitRWContEnabled */ 696 /* b11 : timeLimitRWEnabled */ 697 /* b10 : writeURGBitEnabled */ 698 /* b9 : readURGBitEnabled */ 699 /* b8 : wwwNameEnabled */ 700 /* b7 : WRITE_DMAQ_FUA_EXTEnabled */ 701 /* b6 : WRITE_FUA_EXTEnabled */ 702 /* b5 : generalPurposeLogEnabled */ 703 /* b4 : streamingEnabled */ 704 /* b3 : mediaCardPassThroughEnabled */ 705 /* b2 : mediaSerialNoEnabled */ 706 /* b1 : SMARTSelfRestEnabled */ 707 /* b0 : SMARTErrorLogEnabled */ 708 bit16 ultraDMAModes; 709 /* b15 : word88_bit15 */ 710 /* b14 : ultraDMAMode6Selected */ 711 /* b13 : ultraDMAMode5Selected */ 712 /* b12 : ultraDMAMode4Selected */ 713 /* b11 : ultraDMAMode3Selected */ 714 /* b10 : ultraDMAMode2Selected */ 715 /* b9 : ultraDMAMode1Selected */ 716 /* b8 : ultraDMAMode0Selected */ 717 /* b7 : word88_bit7 */ 718 /* b6 : ultraDMAMode6Supported */ 719 /* b5 : ultraDMAMode5Supported */ 720 /* b4 : ultraDMAMode4Supported */ 721 /* b3 : ultraDMAMode3Supported */ 722 /* b2 : ultraDMAMode2Supported */ 723 /* b1 : ultraDMAMode1Supported */ 724 /* b0 : ultraDMAMode0Supported */ 725 bit16 timeToSecurityErase; 726 bit16 timeToEnhhancedSecurityErase; 727 bit16 currentAPMValue; 728 bit16 masterPasswordRevCode; 729 bit16 hardwareResetResult; 730 /* b15-b14: word93_bit15_14 */ 731 /* b13 : deviceDetectedCBLIBbelow Vil */ 732 /* b12-b8 : device1 HardwareResetResult */ 733 /* b7-b0 : device0 HardwareResetResult */ 734 bit16 currentAutoAccousticManagementValue; 735 /* b15-b8 : Vendor recommended value */ 736 /* b7-b0 : current value */ 737 bit16 word95_99[5]; /**< word85-99 of identify device information */ 738 bit16 maxLBA0_15; /**< word100 of identify device information */ 739 bit16 maxLBA16_31; /**< word101 of identify device information */ 740 bit16 maxLBA32_47; /**< word102 of identify device information */ 741 bit16 maxLBA48_63; /**< word103 of identify device information */ 742 bit16 word104_107[4]; /**< word104-107 of identify device information */ 743 bit16 namingAuthority; 744 /* b15-b12: NAA_bit0_3 */ 745 /* b11-b0 : IEEE_OUI_bit12_23*/ 746 bit16 namingAuthority1; 747 /* b15-b4 : IEEE_OUI_bit0_11 */ 748 /* b3-b0 : uniqueID_bit32_35 */ 749 bit16 uniqueID_bit16_31; /**< word110 of identify device information */ 750 bit16 uniqueID_bit0_15; /**< word111 of identify device information */ 751 bit16 word112_126[15]; 752 bit16 removableMediaStatusNotificationFeature; 753 /* b15-b2 : word127_b16_2 */ 754 /* b1-b0 : supported set see ATAPI6 spec */ 755 bit16 securityStatus; 756 /* b15-b9 : word128_b15_9 */ 757 /* b8 : securityLevel */ 758 /* b7-b6 : word128_b7_6 */ 759 /* b5 : enhancedSecurityEraseSupported */ 760 /* b4 : securityCountExpired */ 761 /* b3 : securityFrozen */ 762 /* b2 : securityLocked */ 763 /* b1 : securityEnabled */ 764 /* b0 : securitySupported */ 765 bit16 vendorSpecific[31]; 766 bit16 cfaPowerMode1; 767 /* b15 : word 160 supported */ 768 /* b14 : word160_b14 */ 769 /* b13 : cfaPowerRequired */ 770 /* b12 : cfaPowerModeDisabled */ 771 /* b11-b0 : maxCurrentInMa */ 772 bit16 word161_175[15]; 773 bit16 currentMediaSerialNumber[30]; 774 bit16 word206_254[49]; /**< word206-254 of identify device information */ 775 bit16 integrityWord; 776 /* b15-b8 : cheksum */ 777 /* b7-b0 : signature */ 778 } agsaSATAIdentifyData_t; 779 780 781 782 783 /** \brief data structure describes an SSP Command INFORMATION UNIT 784 * 785 * data structure describes an SSP Command INFORMATION UNIT used for SSP command and is part of 786 * the SSP frame. 787 * 788 * Currently, only CDB up to 16 bytes is supported. Additional CDB length is supported to 0 bytes.. 789 * 790 */ 791 typedef struct agsaSSPCmdInfoUnit_s 792 { 793 bit8 lun[8]; /* SCSI Logical Unit Number */ 794 bit8 reserved1; /* reserved */ 795 bit8 efb_tp_taskAttribute; 796 /* B7 : enabledFirstBurst */ 797 /* B6-3 : taskPriority */ 798 /* B2-0 : taskAttribute */ 799 bit8 reserved2; /* reserved */ 800 bit8 additionalCdbLen; 801 /* B7-2 : additionalCdbLen */ 802 /* B1-0 : reserved */ 803 bit8 cdb[16]; /* The SCSI CDB up to 16 bytes length */ 804 } agsaSSPCmdInfoUnit_t; 805 806 #define SA_SSPCMD_GET_TASKATTRIB(pCmd) ((pCmd)->efb_tp_taskAttribute & 0x7) 807 808 809 /** \brief structure describes an SSP Response INFORMATION UNIT 810 * 811 * data structure describes an SSP Response INFORMATION UNIT used for SSP response to Command IU 812 * or Task IU and is part of the SSP frame 813 * 814 */ 815 816 typedef struct agsaSSPResponseInfoUnit_s 817 { 818 bit8 reserved1[10]; /* reserved */ 819 820 bit8 dataPres; /* which data is present */ 821 /* B7-2 : reserved */ 822 /* B1-0 : data Present */ 823 bit8 status; /* SCSI status as define by SAM-3 */ 824 bit8 reserved4[4]; /* reserved */ 825 bit8 senseDataLen[4]; /* SCSI Sense Data length */ 826 bit8 responsedataLen[4]; /* Response data length */ 827 /* Follow by Response Data if any */ 828 /* Follow by Sense Data if any */ 829 } agsaSSPResponseInfoUnit_t; 830 831 832 typedef struct agsaSSPFrameFormat_s 833 { 834 bit8 frameType; /* frame type */ 835 bit8 hdsa[3]; /* Hashed destination SAS Address */ 836 bit8 reserved1; 837 bit8 hssa[3]; /* Hashed source SAS Address */ 838 bit8 reserved2; 839 bit8 reserved3; 840 bit8 tlr_rdf; 841 /* B7-5 : reserved */ 842 /* B4-3 : TLR control*/ 843 /* B2 : Retry Data Frames */ 844 /* B1 : Retransmit */ 845 /* B0 : Changing Data Pointer */ 846 bit8 fill_bytes; 847 /* B7-2 : reserved */ 848 /* B1-0 : Number of Fill bytes*/ 849 bit8 reserved5; 850 bit8 reserved6[3]; 851 bit8 tag[2]; /* CMD or TM tag */ 852 bit8 tptt[2]; /* target port transfer tag */ 853 bit8 dataOffset[4]; /* data offset */ 854 /* Follow by IU */ 855 } agsaSSPFrameFormat_t; 856 857 858 typedef struct agsaSSPOpenFrame_s 859 { 860 bit8 frameType; /* frame type */ 861 /* B7 : Initiator Port */ 862 /* B6-4 : Protocol */ 863 /* B3-0 : Address Frame Type */ 864 bit8 feat_connrate; 865 /* B7-4 : features */ 866 /* B3-0 : connection rate */ 867 bit8 initiatorConnTag[2]; /* Initiator connection tag */ 868 bit8 dstSasAddr[8]; /* Destination SAS Address */ 869 bit8 srcSasAddr[8]; /* Source SAS Address */ 870 bit8 zoneSrcGroup; /* Zone source group */ 871 bit8 pathwayBlockCount; /* pathway block count */ 872 bit8 arbWaitTime[2]; /* Arbitration Wait Time */ 873 bit8 moreCompatFeat[4]; /* More Compatibility Features */ 874 /* Follow by CRC */ 875 } agsaSSPOpenFrame_t; 876 877 #define SA_SSPRESP_GET_SENSEDATALEN(pSSPResp) \ 878 DMA_BEBIT32_TO_BIT32(*(bit32*)(pSSPResp)->senseDataLen) 879 880 #define SA_SSPRESP_GET_RESPONSEDATALEN(pSSPResp) \ 881 DMA_BEBIT32_TO_BIT32(*(bit32*)(pSSPResp)->responsedataLen) 882 883 #define SA_SSPRESP_GET_DATAPRES(pSSPResp) ((pSSPResp)->dataPres & 0x3) 884 885 /** \brief structure describes a SAS SSP Task Management command request 886 * 887 * The agsaSSPScsiTaskMgntReq_t data structure describes a SAS SSP Task Management command request sent by the 888 * initiator or received by the target. 889 * 890 * The response to Task Management is specified by agsaSSPResponseInfoUnit_t. 891 * 892 * This data structure is one instance of the generic request issued to saSSPStart() and is passed 893 * as an agsaSASRequestBody_t 894 * 895 */ 896 typedef struct agsaSSPScsiTaskMgntReq_s 897 { 898 bit8 lun[8]; /* SCSI Logical Unit Number */ 899 bit16 reserved1; /* reserved */ 900 bit8 taskMgntFunction; /* task management function code */ 901 bit8 reserved2; /* reserved */ 902 bit16 tagOfTaskToBeManaged; /* Tag/context of task to be managed */ 903 bit16 reserved3; /* reserved */ 904 bit32 reserved4[3]; /* reserved */ 905 bit32 tmOption; /* Not part of SSP TMF IU */ 906 /* B7-2 : reserved */ 907 /* B1 : DS_OPTION */ 908 /* B0 : ADS_OPTION */ 909 } agsaSSPScsiTaskMgntReq_t; 910 911 912 /** \brief data structure describes the first four bytes of the SMP frame. 913 * 914 * The agsaSMPFrameHeader_t data structure describes the first four bytes of the SMP frame. 915 * 916 * 917 */ 918 919 typedef struct agsaSMPFrameHeader_s 920 { 921 bit8 smpFrameType; /* The first byte of SMP frame represents the SMP FRAME TYPE */ 922 bit8 smpFunction; /* The second byte of the SMP frame represents the SMP FUNCTION */ 923 bit8 smpFunctionResult; /* The third byte of SMP frame represents FUNCTION RESULT of the SMP response. */ 924 bit8 smpReserved; /* reserved */ 925 } agsaSMPFrameHeader_t; 926 927 /**************************************************************** 928 * report general response 929 ****************************************************************/ 930 #define SA_REPORT_GENERAL_CONFIGURING_BIT 0x2 931 #define SA_REPORT_GENERAL_CONFIGURABLE_BIT 0x1 932 933 typedef struct agsaSmpRespReportGeneral_s 934 { 935 bit8 expanderChangeCount16[2]; 936 bit8 expanderRouteIndexes16[2]; 937 bit8 reserved1; 938 bit8 numOfPhys; 939 bit8 configuring_configurable; 940 /* B7-2 : reserved */ 941 /* B1 : configuring */ 942 /* B0 : configurable */ 943 bit8 reserved4[17]; 944 } agsaSmpRespReportGeneral_t; 945 946 #define SA_REPORT_GENERAL_IS_CONFIGURING(pResp) \ 947 (((pResp)->configuring_configurable & SA_REPORT_GENERAL_CONFIGURING_BIT) == \ 948 SA_REPORT_GENERAL_CONFIGURING_BIT) 949 950 #define SA_REPORT_GENERAL_IS_CONFIGURABLE(pResp) \ 951 (((pResp)->configuring_configurable & SA_REPORT_GENERAL_CONFIGURABLE_BIT) == \ 952 SA_REPORT_GENERAL_CONFIGURABLE_BIT) 953 954 #define SA_REPORT_GENERAL_GET_ROUTEINDEXES(pResp) \ 955 DMA_BEBIT16_TO_BIT16(*(bit16 *)((pResp)->expanderRouteIndexes16)) 956 957 /**************************************************************** 958 * report manufacturer info response 959 ****************************************************************/ 960 typedef struct agsaSmpRespReportManufactureInfo_s 961 { 962 bit8 reserved1[8]; 963 bit8 vendorIdentification[8]; 964 bit8 productIdentification[16]; 965 bit8 productRevisionLevel[4]; 966 bit8 vendorSpecific[20]; 967 } agsaSmpRespReportManufactureInfo_t; 968 969 /**************************************************************** 970 * discover request 971 ****************************************************************/ 972 typedef struct agsaSmpReqDiscover_s 973 { 974 bit32 reserved1; 975 bit8 reserved2; 976 bit8 phyIdentifier; 977 bit8 ignored; 978 bit8 reserved3; 979 } agsaSmpReqDiscover_t; 980 981 /**************************************************************** 982 * discover response 983 ****************************************************************/ 984 typedef struct agsaSmpRespDiscover_s 985 { 986 bit8 reserved1[4]; 987 bit8 reserved2; 988 bit8 phyIdentifier; 989 bit8 reserved3[2]; 990 bit8 attachedDeviceType; 991 /* B7 : reserved */ 992 /* B6-4 : attachedDeviceType */ 993 /* B3-0 : reserved */ 994 bit8 negotiatedPhyLinkRate; 995 /* B7-4 : reserved */ 996 /* B3-0 : negotiatedPhyLinkRate */ 997 bit8 attached_Ssp_Stp_Smp_Sata_Initiator; 998 /* B7-4 : reserved */ 999 /* B3 : attachedSspInitiator */ 1000 /* B2 : attachedStpInitiator */ 1001 /* B1 : attachedSmpInitiator */ 1002 /* B0 : attachedSataHost */ 1003 bit8 attached_SataPS_Ssp_Stp_Smp_Sata_Target; 1004 /* B7 : attachedSataPortSelector */ 1005 /* B6-4 : reserved */ 1006 /* B3 : attachedSspTarget */ 1007 /* B2 : attachedStpTarget */ 1008 /* B1 : attachedSmpTarget */ 1009 /* B0 : attachedSatadevice */ 1010 bit8 sasAddressHi[4]; 1011 bit8 sasAddressLo[4]; 1012 bit8 attachedSasAddressHi[4]; 1013 bit8 attachedSasAddressLo[4]; 1014 bit8 attachedPhyIdentifier; 1015 bit8 reserved9[7]; 1016 bit8 programmedAndHardware_MinPhyLinkRate; 1017 /* B7-4 : programmedMinPhyLinkRate */ 1018 /* B3-0 : hardwareMinPhyLinkRate */ 1019 bit8 programmedAndHardware_MaxPhyLinkRate; 1020 /* B7-4 : programmedMaxPhyLinkRate */ 1021 /* B3-0 : hardwareMaxPhyLinkRate */ 1022 bit8 phyChangeCount; 1023 bit8 virtualPhy_partialPathwayTimeout; 1024 /* B7 : virtualPhy*/ 1025 /* B6-4 : reserved */ 1026 /* B3-0 : partialPathwayTimeout */ 1027 bit8 routingAttribute; 1028 /* B7-4 : reserved */ 1029 /* B3-0 : routingAttribute */ 1030 bit8 reserved13[5]; 1031 bit8 vendorSpecific[2]; 1032 } agsaSmpRespDiscover_t; 1033 1034 #define SA_DISCRSP_SSP_BIT 0x08 1035 #define SA_DISCRSP_STP_BIT 0x04 1036 #define SA_DISCRSP_SMP_BIT 0x02 1037 #define SA_DISCRSP_SATA_BIT 0x01 1038 1039 #define SA_DISCRSP_SATA_PS_BIT 0x80 1040 1041 #define SA_DISCRSP_GET_ATTACHED_DEVTYPE(pResp) \ 1042 (((pResp)->attachedDeviceType & 0x70) >> 4) 1043 #define SA_DISCRSP_GET_LINKRATE(pResp) \ 1044 ((pResp)->negotiatedPhyLinkRate & 0x0F) 1045 1046 #define SA_DISCRSP_IS_SSP_INITIATOR(pResp) \ 1047 (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & SA_DISCRSP_SSP_BIT) == SA_DISCRSP_SSP_BIT) 1048 #define SA_DISCRSP_IS_STP_INITIATOR(pResp) \ 1049 (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & SA_DISCRSP_STP_BIT) == SA_DISCRSP_STP_BIT) 1050 #define SA_DISCRSP_IS_SMP_INITIATOR(pResp) \ 1051 (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & SA_DISCRSP_SMP_BIT) == SA_DISCRSP_SMP_BIT) 1052 #define SA_DISCRSP_IS_SATA_HOST(pResp) \ 1053 (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & SA_DISCRSP_SATA_BIT) == SA_DISCRSP_SATA_BIT) 1054 1055 #define SA_DISCRSP_IS_SSP_TARGET(pResp) \ 1056 (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & SA_DISCRSP_SSP_BIT) == SA_DISCRSP_SSP_BIT) 1057 #define SA_DISCRSP_IS_STP_TARGET(pResp) \ 1058 (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & SA_DISCRSP_STP_BIT) == SA_DISCRSP_STP_BIT) 1059 #define SA_DISCRSP_IS_SMP_TARGET(pResp) \ 1060 (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & SA_DISCRSP_SMP_BIT) == SA_DISCRSP_SMP_BIT) 1061 #define SA_DISCRSP_IS_SATA_DEVICE(pResp) \ 1062 (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & SA_DISCRSP_SATA_BIT) == SA_DISCRSP_SATA_BIT) 1063 #define SA_DISCRSP_IS_SATA_PORTSELECTOR(pResp) \ 1064 (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & SA_DISCRSP_SATA_PS_BIT) == SA_DISCRSP_SATA_PS_BIT) 1065 1066 #define SA_DISCRSP_GET_SAS_ADDRESSHI(pResp) \ 1067 DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->sasAddressHi) 1068 #define SA_DISCRSP_GET_SAS_ADDRESSLO(pResp) \ 1069 DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->sasAddressLo) 1070 1071 #define SA_DISCRSP_GET_ATTACHED_SAS_ADDRESSHI(pResp) \ 1072 DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->attachedSasAddressHi) 1073 #define SA_DISCRSP_GET_ATTACHED_SAS_ADDRESSLO(pResp) \ 1074 DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->attachedSasAddressLo) 1075 1076 #define SA_DISCRSP_VIRTUALPHY_BIT 0x80 1077 #define SA_DISCRSP_IS_VIRTUALPHY(pResp) \ 1078 (((pResp)->virtualPhy_partialPathwayTimeout & SA_DISCRSP_VIRTUALPHY_BIT) == SA_DISCRSP_VIRTUALPHY_BIT) 1079 1080 #define SA_DISCRSP_GET_ROUTINGATTRIB(pResp) \ 1081 ((pResp)->routingAttribute & 0x0F) 1082 1083 /**************************************************************** 1084 * report route table request 1085 ****************************************************************/ 1086 typedef struct agsaSmpReqReportRouteTable_s 1087 { 1088 bit8 reserved1[2]; 1089 bit8 expanderRouteIndex16[20]; 1090 bit8 reserved2; 1091 bit8 phyIdentifier; 1092 bit8 reserved3[2]; 1093 } agsaSmpReqReportRouteTable_t; 1094 1095 /**************************************************************** 1096 * report route response 1097 ****************************************************************/ 1098 typedef struct agsaSmpRespReportRouteTable_s 1099 { 1100 bit8 reserved1[2]; 1101 bit8 expanderRouteIndex16[2]; 1102 bit8 reserved2; 1103 bit8 phyIdentifier; 1104 bit8 reserved3[2]; 1105 bit8 disabled; 1106 /* B7 : expander route entry disabled */ 1107 /* B6-0 : reserved */ 1108 bit8 reserved5[3]; 1109 bit8 routedSasAddressHi32[4]; 1110 bit8 routedSasAddressLo32[4]; 1111 bit8 reserved6[16]; 1112 } agsaSmpRespReportRouteTable_t; 1113 1114 /**************************************************************** 1115 * configure route information request 1116 ****************************************************************/ 1117 typedef struct agsaSmpReqConfigureRouteInformation_s 1118 { 1119 bit8 reserved1[2]; 1120 bit8 expanderRouteIndex[2]; 1121 bit8 reserved2; 1122 bit8 phyIdentifier; 1123 bit8 reserved3[2]; 1124 bit8 disabledBit_reserved4; 1125 bit8 reserved5[3]; 1126 bit8 routedSasAddressHi[4]; 1127 bit8 routedSasAddressLo[4]; 1128 bit8 reserved6[16]; 1129 } agsaSmpReqConfigureRouteInformation_t; 1130 1131 /**************************************************************** 1132 * report Phy Sata request 1133 ****************************************************************/ 1134 typedef struct agsaSmpReqReportPhySata_s 1135 { 1136 bit8 reserved1[4]; 1137 bit8 reserved2; 1138 bit8 phyIdentifier; 1139 bit8 reserved3[2]; 1140 } agsaSmpReqReportPhySata_t; 1141 1142 /**************************************************************** 1143 * report Phy Sata response 1144 ****************************************************************/ 1145 typedef struct agsaSmpRespReportPhySata_s 1146 { 1147 bit8 reserved1[4]; 1148 bit8 reserved2; 1149 bit8 phyIdentifier; 1150 bit8 reserved3; 1151 bit8 affiliations_sup_valid; 1152 /* b7-2 : reserved */ 1153 /* b1 : Affiliations supported */ 1154 /* b0 : Affiliation valid */ 1155 bit8 reserved5[4]; 1156 bit8 stpSasAddressHi[4]; 1157 bit8 stpSasAddressLo[4]; 1158 bit8 regDevToHostFis[20]; 1159 bit8 reserved6[4]; 1160 bit8 affiliatedStpInitiatorSasAddressHi[4]; 1161 bit8 affiliatedStpInitiatorSasAddressLo[4]; 1162 } agsaSmpRespReportPhySata_t; 1163 1164 /**************************************************************** 1165 * Phy Control request 1166 ****************************************************************/ 1167 typedef struct agsaSmpReqPhyControl_s 1168 { 1169 bit8 reserved1[4]; 1170 bit8 reserved2; 1171 bit8 phyIdentifier; 1172 bit8 phyOperation; 1173 bit8 updatePartialPathwayTOValue; 1174 /* b7-1 : reserved */ 1175 /* b0 : update partial pathway timeout value */ 1176 bit8 reserved3[20]; 1177 bit8 programmedMinPhysicalLinkRate; 1178 /* b7-4 : programmed Minimum Physical Link Rate*/ 1179 /* b3-0 : reserved */ 1180 bit8 programmedMaxPhysicalLinkRate; 1181 /* b7-4 : programmed Maximum Physical Link Rate*/ 1182 /* b3-0 : reserved */ 1183 bit8 reserved4[2]; 1184 bit8 partialPathwayTOValue; 1185 /* b7-4 : reserved */ 1186 /* b3-0 : partial Pathway TO Value */ 1187 bit8 reserved5[3]; 1188 } agsaSmpReqPhyControl_t; 1189 1190 1191 1192 1193 #endif /*__SASPEC_H__ */ 1194