| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1872 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeCopMemInstruction() local
2047 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeAddrMode2IdxInstruction() local
2153 unsigned Rn = fieldFromInstruction(Val, 13, 4); in DecodeSORegMemOperand() local
2211 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeAddrMode3Instruction() local
2402 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeRFEInstruction() local
2434 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeQADDInstruction() local
2457 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeMemMultipleWritebackInstruction() local
2742 unsigned Rn = fieldFromInstruction(Insn, 0, 4); in DecodeSMLAInstruction() local
2771 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeTSTInstruction() local
2823 unsigned Rn = fieldFromInstruction(Val, 13, 4); in DecodeAddrModeImm12Operand() local
[all …]
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/ |
| H A D | EmulateInstructionARM.cpp | 2480 Rn; // This function assumes Rn is the SP, but we should verify that. in EmulateSTRRtSP() local
2951 uint32_t Rn; // the base register which contains the address of the table of in EmulateTB() local
3101 uint64_t Rn = in EmulateADDImmThumb() local
3152 uint32_t Rd, Rn; in EmulateADDImmARM() local
3218 uint32_t Rd, Rn, Rm; in EmulateADDReg() local
3300 uint32_t Rn; // the first operand in EmulateCMNImm() local
3348 uint32_t Rn; // the first operand in EmulateCMNReg() local
3413 uint32_t Rn; // the first operand in EmulateCMPImm() local
3465 uint32_t Rn; // the first operand in EmulateCMPReg() local
3839 uint32_t Rn; // the first operand register in EmulateShiftReg() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 502 unsigned Rn = fieldFromInstruction(Insn, 5, 5); in DecodeFMOVLaneInstruction() local
605 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeThreeAddrSRegInstruction() local
708 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeUnsignedLdStInstruction() local
775 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeSignedLdStInstruction() local
982 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeExclusiveLdStInstruction() local
1076 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodePairLdStInstruction() local
1222 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeAuthLoadInstruction() local
1257 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeAddSubERegInstruction() local
1332 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeLogicalImmInstruction() local
1449 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeAddSubImmShift() local
[all …]
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| /freebsd/sys/arm64/arm64/ |
| H A D | undefined.c | 206 int attempts, error, Rn, Rd, Rm; in swp_emulate() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 933 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); getThumbAddrModeRegRegOpValue() local
1069 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg()); getMveAddrModeRQOpValue() local
1287 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); getLdStSORegOpValue() local
1384 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. getAddrMode3OpValue() local
1394 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); getAddrMode3OpValue() local
1431 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); getAddrModeISOpValue() local
[all...] |
| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/ |
| H A D | EmulateInstructionARM64.cpp | 621 const uint32_t Rn = Bits32(opcode, 9, 5); in EmulateADDSUBImm() local
702 uint32_t Rn = Bits32(opcode, 9, 5); in EmulateLDPSTP() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 466 Register Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); in ReduceLoadStore() local
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| H A D | ARMBaseInstrInfo.cpp | 3596 Register Rn = MI.getOperand(2).getReg(); in getNumMicroOpsSwiftLdSt() local
3622 Register Rn = MI.getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
3632 Register Rn = MI.getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
3669 Register Rn = MI.getOperand(2).getReg(); in getNumMicroOpsSwiftLdSt() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 5356 unsigned Rn = Inst.getOperand(3).getReg(); in validateInstruction() local
5410 unsigned Rn = Inst.getOperand(3).getReg(); in validateInstruction() local
5442 unsigned Rn = Inst.getOperand(2).getReg(); in validateInstruction() local
5461 unsigned Rn = Inst.getOperand(2).getReg(); in validateInstruction() local
5477 unsigned Rn = Inst.getOperand(2).getReg(); in validateInstruction() local
5491 unsigned Rn = Inst.getOperand(3).getReg(); in validateInstruction() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 7588 unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg()); in validateLDRDSTRD() local
7821 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); in validateInstruction() local
7834 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction() local
7982 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); in validateInstruction() local
8057 unsigned Rn = Inst.getOperand(0).getReg(); in validateInstruction() local
10789 unsigned Rn = Inst.getOperand(0).getReg(); in processInstruction() local
10815 unsigned Rn = Inst.getOperand(0).getReg(); in processInstruction() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 954 int Rn = 0, Rm = 0; buildHvxVectorReg() local
|