| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyMachineFunctionInfo.cpp | 51 MVT RegisterVT = TLI.getRegisterType(Ctx, VT); in computeLegalValueVTs() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 388 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs() local
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| H A D | SelectionDAGBuilder.cpp | 356 MVT RegisterVT; in getCopyFromPartsVector() local
761 MVT RegisterVT; in getCopyToPartsVector() local
865 MVT RegisterVT = in RegsForValue() local
894 MVT RegisterVT = isABIMangled() in getCopyFromRegs() local
977 MVT RegisterVT = isABIMangled() in getCopyToRegs() local
1062 MVT RegisterVT = RegVTs[Value]; in AddInlineAsmOperands() local
1079 MVT RegisterVT = std::get<1>(CountAndVT); in getRegsAndSizes() local
10816 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), RetVT); in LowerCallTo() local
10882 MVT RegisterVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(), in LowerCallTo() local
11166 MVT RegisterVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(), in LowerCallTo() local
[all …]
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| H A D | FastISel.cpp | 1015 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT); in lowerCallTo() local
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| H A D | SelectionDAG.cpp | 2477 MVT RegisterVT; in getReducedAlign() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 443 std::optional<MVT> RegisterVT) const override { in getNumRegisters()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1065 MVT &RegisterVT, in getVectorTypeBreakdownMVT()
1451 MVT RegisterVT; in computeRegisterProperties() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLoweringCall.cpp | 110 MVT RegisterVT; in getRegisterTypeForCallingConv() local
144 MVT RegisterVT; in getNumRegistersForCallingConv() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1181 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
1722 MVT RegisterVT; in getRegisterType() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 3141 std::optional<MVT> RegisterVT = std::nullopt) const { in getNumRegisters()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1191 MVT RegisterVT = getRegisterTypeForCallingConv(Ctx, CC, ArgVT); in analyzeFormalArgumentsCompute() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 22076 MVT RegisterVT = OutArg.VT; constructArgInfos() local
22109 MVT RegisterVT = constructArgInfos() local
22123 MVT RegisterVT = constructArgInfos() local
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 28632 MVT RegisterVT; in getRegisterTypeForCallingConv() local
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