| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 810 isAnyMOVZMovAlias(uint64_t Value,int RegWidth) isAnyMOVZMovAlias() argument
818 isMOVZMovAlias(uint64_t Value,int Shift,int RegWidth) isMOVZMovAlias() argument
829 isMOVNMovAlias(uint64_t Value,int Shift,int RegWidth) isMOVNMovAlias() argument
841 isAnyMOVWMovAlias(uint64_t Value,int RegWidth) isAnyMOVWMovAlias() argument
[all...] |
| H A D | AArch64InstPrinter.cpp | 285 __anonc553032e0102(uint64_t Value, int RegWidth) printInst() argument
309 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32; printInst() local
322 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32; printInst() local
338 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32; printInst() local
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 1281 unsigned RegWidth) { in usesRegister()
2499 static int getRegClass(RegisterKind Is, unsigned RegWidth) { in getRegClass()
2684 bool AMDGPUAsmParser::AddNextRegisterToList(unsigned &Reg, unsigned &RegWidth, in AddNextRegisterToList()
2809 unsigned SubReg, unsigned RegWidth, in getRegularReg()
2852 bool AMDGPUAsmParser::ParseRegRange(unsigned &Num, unsigned &RegWidth) { in ParseRegRange()
2895 unsigned &RegNum, unsigned &RegWidth, in ParseSpecialReg()
2910 unsigned &RegNum, unsigned &RegWidth, in ParseRegularReg()
2954 unsigned &RegWidth, in ParseRegList()
3008 unsigned &RegNum, unsigned &RegWidth, in ParseAMDGPURegister()
3040 unsigned &RegNum, unsigned &RegWidth, in ParseAMDGPURegister()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetTransformInfo.cpp | 183 unsigned RegWidth = in getMemoryOpCost() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 1926 TypeSize RegWidth = in getMaximumVF() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 3855 unsigned RegWidth, in checkCVTFixedPointOperandWithFBits()
3904 unsigned RegWidth) { in SelectCVTFixedPosOperand()
3911 unsigned RegWidth) { in SelectCVTFixedPosRecipOperand()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 6262 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
6318 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
6382 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 1352 const unsigned RegWidth = AMDGPU::getRegBitWidth(*RC) / 8; in buildSpillLoadStore() local
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1761 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); variable
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 7428 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchType() local
|