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Searched defs:RegUnits (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRegUnits.h144 void addUnits(const BitVector &RegUnits) { in addUnits()
148 void removeUnits(const BitVector &RegUnits) { in removeUnits()
H A DRegisterScavenging.h186 setUsed(const BitVector & RegUnits) setUsed() argument
189 setUnused(const BitVector & RegUnits) setUnused() argument
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineTraceMetrics.cpp718 SparseSet<LiveRegUnit> &RegUnits, in updatePhysDepsDownwards()
796 SparseSet<LiveRegUnit> &RegUnits) { in updateDepth()
835 SparseSet<LiveRegUnit> &RegUnits) { in updateDepth()
842 SparseSet<LiveRegUnit> &RegUnits) { in updateDepths()
868 SparseSet<LiveRegUnit> RegUnits; in computeInstrDepths() local
906 SparseSet<LiveRegUnit> &RegUnits, in updatePhysDepsUpwards()
1029 SparseSet<LiveRegUnit> RegUnits; in computeInstrHeights() local
H A DInterferenceCache.h92 SmallVector<RegUnitInfo, 4> RegUnits; variable
H A DMachineCombiner.cpp488 SparseSet<LiveRegUnit> &RegUnits, in insertDeleteInstructions()
571 SparseSet<LiveRegUnit> RegUnits; in combineInstructions() local
H A DRegisterPressure.cpp370 static LaneBitmask getRegLanes(ArrayRef<RegisterMaskPair> RegUnits, in getRegLanes()
380 static void addRegLanes(SmallVectorImpl<RegisterMaskPair> &RegUnits, in addRegLanes()
394 static void setRegZero(SmallVectorImpl<RegisterMaskPair> &RegUnits, in setRegZero()
406 static void removeRegLanes(SmallVectorImpl<RegisterMaskPair> &RegUnits, in removeRegLanes()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInsertSingleUseVDST.cpp194 const auto RegUnits = TRI->regunits(Reg); in runOnMachineFunction() local
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp193 const RegUnitSet &RegUnits = Bank.getRegSetAt(i); in runEnums() local
223 std::vector<unsigned> RegUnits; in EmitRegUnitPressure() local
273 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); in EmitRegUnitPressure() local
289 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); in EmitRegUnitPressure() local
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.h302 RegUnitList RegUnits; variable
603 SmallVector<RegUnit, 8> RegUnits; variable
H A DCodeGenRegisters.cpp2167 const auto &RegUnits = Register.getRegUnits(); in computeRegUnitLaneMasks() local
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h124 uint32_t RegUnits; member