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Searched defs:RegSeq (Results 1 – 4 of 4) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1477 SDValue RegSeq = createQTuple(Regs); in SelectTable() local
2176 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore() local
2195 SDValue RegSeq = createZTuple(Regs); in SelectPredicatedStore() local
2240 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore() local
2299 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane() local
2337 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane() local
2391 SDValue RegSeq = createQTuple(Regs); in SelectStoreLane() local
2419 SDValue RegSeq = createQTuple(Regs); in SelectPostStoreLane() local
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/
H A DCSKYAsmParser.cpp190 RegSeqOp RegSeq; member
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp5134 auto RegSeq = createQTuple(Regs, MIB); in selectShuffleVector() local
6862 Register RegSeq = createQTuple(Regs, MIB); in SelectTable() local
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2380 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVST() local