| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | DetectDeadLanes.h | 57 const VRegInfo &getVRegInfo(unsigned RegIdx) const { in getVRegInfo()
61 bool isDefinedByCopy(unsigned RegIdx) const { in isDefinedByCopy()
101 void PutInWorklist(unsigned RegIdx) { in PutInWorklist()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | SplitKit.cpp | 471 VNInfo *SplitEditor::defValue(unsigned RegIdx, in defValue()
508 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo &ParentVNI) { in forceRecompute()
548 MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) { in buildCopy()
592 VNInfo *SplitEditor::defFromParent(unsigned RegIdx, const VNInfo *ParentVNI, in defFromParent()
809 unsigned RegIdx = 0; in leaveIntvAtTop() local
884 unsigned RegIdx = AssignI.value(); in removeBackCopies() local
1146 unsigned RegIdx; in transferValues() local
1285 unsigned RegIdx = RegAssign.lookup(V->def); in extendPHIKillRanges() local
1300 unsigned RegIdx = RegAssign.lookup(V->def); in extendPHIKillRanges() local
1323 unsigned RegIdx; in rewriteAssigned() member
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| H A D | DetectDeadLanes.cpp | 279 unsigned RegIdx = Register::virtReg2Index(Reg); in determineInitialDefinedLanes() local
456 for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { in computeSubRegisterLaneBitInfo() local
467 unsigned RegIdx = Worklist.front(); in computeSubRegisterLaneBitInfo() local
509 unsigned RegIdx = Register::virtReg2Index(Reg); in modifySubRegisterOperandStatus() local
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| H A D | SplitKit.h | 343 getLICalc(unsigned RegIdx) getLICalc() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMCallingConv.cpp | 201 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local
247 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local
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| H A D | ARMISelLowering.cpp | 4542 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs); in LowerFormalArguments() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 315 unsigned RegIdx = Imm & 0xff; in DECODE_OPERAND_REG_8() local
326 unsigned RegIdx = Imm & 0x7f; in DecodeVGPR_16_Lo128RegisterClass() local
340 unsigned RegIdx = Imm & 0x7f; in decodeOperand_VSrcT16_Lo128() local
356 unsigned RegIdx = Imm & 0xff; in decodeOperand_VSrcT16() local
860 unsigned RegIdx = OpEnc & AMDGPU::HWEncoding::REG_IDX_MASK; in convertTrue16OpSel() local
1239 MCOperand AMDGPUDisassembler::createVGPR16Operand(unsigned RegIdx, in createVGPR16Operand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRAsmPrinter.cpp | 132 unsigned RegIdx = ByteNumber / BytesPerReg; in PrintAsmOperand() local
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| H A D | AVRISelLowering.cpp | 1266 unsigned RegIdx = RegLastIdx + TotalBytes; in analyzeArguments() local
1349 int RegIdx = TotalBytes - 1; in analyzeReturnValues() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64CollectLOH.cpp | 551 int RegIdx = mapRegToGPRIndex(LI.PhysReg); runOnMachineFunction() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 853 SDValue RegIdx = Node->getOperand(2); in trySelect() local
922 SDValue RegIdx = Node->getOperand(2); in trySelect() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUMCCodeEmitter.cpp | 652 unsigned RegIdx = Encoding & AMDGPU::HWEncoding::REG_IDX_MASK; in getMachineOpValueT16Lo128() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ExpandPseudo.cpp | 764 for (int64_t OpndIdx = 7, RegIdx = 0; in expandVastartSaveXmmRegs() local
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| H A D | X86SpeculativeLoadHardening.cpp | 1867 unsigned RegIdx = Log2_32(RegBytes); in canHardenRegister() local
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| H A D | X86FastISel.cpp | 2631 unsigned RegIdx = X86::sub_16bit; in fastLowerIntrinsicCall() local
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| H A D | X86InstrInfo.cpp | 5796 unsigned RegIdx = UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr); in foldImmediateImpl() local
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| H A D | X86ISelLowering.cpp | 36476 for (unsigned RegIdx = 0; SavedRegs[RegIdx]; ++RegIdx) { in EmitSjLjDispatchBlock() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/ |
| H A D | VarLocBasedImpl.cpp | 1456 LocIndex RegIdx = LocIndex::fromRawInteger(*It); in collectAllVarLocs() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 2825 unsigned RegIdx = RegNum / AlignSize; in getRegularReg() local
4893 auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0); in validateGWS() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 4773 unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); in CC_LoongArch() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 891 struct RegIdxOp RegIdx; member
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 2297 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs); in allocateVGPR32Input() local
2319 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgSGPRs); in allocateSGPR32InputImpl() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 19075 unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); CC_RISCV() local
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