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Searched defs:RegB (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h484 bool isSubRegister(MCRegister RegA, MCRegister RegB) const { in isSubRegister()
492 bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSubRegisterEq()
498 bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperRegisterEq()
504 bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperOrSubRegisterEq()
626 inline bool MCRegisterInfo::isSuperRegister(MCRegister RegA, MCRegister RegB) const{ in isSuperRegister()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTwoAddressInstructionPass.cpp637 Register RegB, in isProfitableToCommute()
773 Register RegB) { in isProfitableToConv3Addr()
791 Register RegA, Register RegB, unsigned &Dist) { in convertInstTo3Addr()
1566 Register RegB = 0; in processTiedPairs() local
1748 Register RegB = TO.first; in processStatepoint() local
H A DImplicitNullChecks.cpp290 Register RegB = MOB.getReg(); in canReorder() local
H A DTargetInstrInfo.cpp1332 Register RegB = OpB.getReg(); in reassociateOps() local
H A DMachinePipeliner.cpp3043 Register RegB = BaseOpB->getReg(), RegO = BaseOpO->getReg(); in mayOverlapInLaterIter() local
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.cpp686 auto IsSubReg = [&](MCRegister RegA, MCRegister RegB) { in isArgumentRegister()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h462 bool regsOverlap(Register RegA, Register RegB) const { in regsOverlap()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp498 Register RegB = Root.getOperand(AddOpIdx).getReg(); in getFMAPatterns() local
857 RegA21, RegB; in reassociateFMA() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp2228 for (auto &RegB : UsesB) { in isDependent() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp7735 Register RegB = AddMI->getOperand(IdxOpd1).getReg(); in genSubAdd2SubSub() local