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Searched defs:Reg0 (Results 1 – 25 of 25) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp175 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR()
184 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, in emitRX()
194 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, in emitRI()
199 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR()
214 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX()
226 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR()
232 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRRX()
245 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI()
251 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0, in emitRRIII()
H A DMipsMCCodeEmitter.cpp96 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0); LowerCompactBranch() local
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupSetCC.cpp89 Register Reg0 = MI.getOperand(0).getReg(); in runOnMachineFunction() local
H A DX86CompressEVEX.cpp193 Register Reg0 = MI.getOperand(0).getReg(); in CompressEVEXImpl() local
H A DX86ExpandPseudo.cpp467 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in expandMI() local
503 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in expandMI() local
H A DX86InstrInfo.cpp7323 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in commuteOperandsForFold() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp233 Register Reg0 = Op0.getReg(); in runOnMachineFunction() local
H A DHexagonBitTracker.cpp314 unsigned Reg0 = Reg[0].Reg; in evaluate() local
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2173 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
2308 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
2480 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDSTLane() local
3018 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDDup() local
3367 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
3415 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
3437 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
3458 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
3808 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
3827 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
[all …]
H A DThumb2SizeReduction.cpp754 Register Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
H A DARMAsmPrinter.cpp336 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand() local
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVLegalizerInfo.cpp346 Register Reg0 = Op0.getReg(); in legalizeCustom() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp234 Register Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp461 unsigned Reg0 = in emitPrologue() local
479 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp200 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in selectInlineAsm() local
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineInstr.cpp2521 Register Reg0 = getOperand(0).getReg(); in getFirst2RegLLTs() local
2529 Register Reg0 = getOperand(0).getReg(); in getFirst3RegLLTs() local
2539 Register Reg0 = getOperand(0).getReg(); in getFirst4RegLLTs() local
2551 Register Reg0 = getOperand(0).getReg(); in getFirst5RegLLTs() local
H A DRegAllocFast.cpp1339 Register Reg0 = MO0.getReg(); in findAndSortDefOperandIndexes() local
H A DTargetInstrInfo.cpp185 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in commuteInstructionImpl() local
H A DRegisterCoalescer.cpp2719 Register Reg0; in valuesIdentical() local
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp1494 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1507 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1562 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1609 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp1246 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
1259 Register Reg0 = MBBI->getOperand(1).getReg(); in InsertSEH() local
1297 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in InsertSEH() local
1308 Register Reg0 = MBBI->getOperand(0).getReg(); in InsertSEH() local
1342 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in InsertSEH() local
1355 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h701 uint16_t Reg0 = 0; variable
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp985 Register Reg0 = UseMI->getOperand(0).getReg(); in foldOperand() local
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp2229 Register Reg0 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass); in loadImmediate() local
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1158 Register Reg0 = MI.getOperand(0).getReg(); in commuteInstructionImpl() local
1188 Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg(); in commuteInstructionImpl() local