| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 153 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, in addIntraChainConstraint()
237 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, in addInterChainConstraint()
357 Register Rd = MI.getOperand(0).getReg(); in apply() local
367 Register Rd = MI.getOperand(0).getReg(); in apply() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 501 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction() local
604 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local
672 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local
1256 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubERegInstruction() local
1331 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeLogicalImmInstruction() local
1368 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmInstruction() local
1409 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmTiedInstruction() local
1429 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAdrInstruction() local
1448 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubImmShift() local
1688 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeCPYMemOpInstruction() local
[all …]
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| /freebsd/contrib/llvm-project/compiler-rt/lib/xray/ |
| H A D | xray_loongarch64.cpp | 31 encodeInstruction2RIx(uint32_t Opcode, uint32_t Rd, uint32_t Rj, in encodeInstruction2RIx()
38 encodeInstruction1RI20(uint32_t Opcode, uint32_t Rd, in encodeInstruction1RI20()
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| H A D | xray_mips.cpp | 47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
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| H A D | xray_mips64.cpp | 48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
| H A D | RISCVInstructions.h | 22 struct Rd { struct
45 Rd rd; \ argument
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| H A D | RISCVCInstructions.h | 25 operator Rd() { return Rd{rd + (shift ? 8 : 0)}; } in Rd() function
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/ |
| H A D | EmulateInstructionARM.cpp | 1168 uint32_t Rd; // the destination register in EmulateADDRdSPImm() local
1229 uint32_t Rd; // the destination register in EmulateMOVRdSP() local
1289 uint32_t Rd; // the destination register in EmulateMOVRdRm() local
1377 uint32_t Rd; // the destination register in EmulateMOVRdImm() local
1619 uint32_t Rd; // the destination register in EmulateMVNImm() local
1681 uint32_t Rd; // the destination register in EmulateMVNReg() local
2397 uint32_t Rd; in EmulateSUBSPImm() local
3152 uint32_t Rd, Rn; in EmulateADDImmARM() local
3218 uint32_t Rd, Rn, Rm; in EmulateADDReg() local
3753 uint32_t Rd; // the destination register in EmulateShiftImm() local
[all …]
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| H A D | EmulateInstructionARM.h | 202 const uint32_t Rd) { in WriteCoreReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 2432 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeQADDInstruction() local
2688 unsigned Rd = fieldFromInstruction(Insn, 8, 4); in DecodeT2MOVTWInstruction() local
2713 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeArmMOVTWInstruction() local
2741 unsigned Rd = fieldFromInstruction(Insn, 16, 4); in DecodeSMLAInstruction() local
2965 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLDInstruction() local
3297 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVSTInstruction() local
3568 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD1DupInstruction() local
3616 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD2DupInstruction() local
3665 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD3DupInstruction() local
3701 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD4DupInstruction() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/ |
| H A D | RISCVDisassembler.cpp | 389 uint32_t Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs1ImmZero() local
436 uint32_t Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs2() local
446 uint32_t Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs1Rs2() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/ |
| H A D | LoongArchMCCodeEmitter.cpp | 378 MCOperand Rd = MI.getOperand(0); in expandAddTPRel() local
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| /freebsd/sys/arm64/arm64/ |
| H A D | undefined.c | 206 int attempts, error, Rn, Rd, Rm; in swp_emulate() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/ |
| H A D | MSP430Disassembler.cpp | 194 unsigned Rd = fieldFromInstruction(Insn, 0, 4); in DecodeDstAddrMode() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/AsmParser/ |
| H A D | LoongArchAsmParser.cpp | 1409 unsigned Rd = Inst.getOperand(0).getReg(); in checkTargetMatchPredicate() local
1420 unsigned Rd = Inst.getOperand(0).getReg(); in checkTargetMatchPredicate() local
1430 unsigned Rd = Inst.getOperand(0).getReg(); in checkTargetMatchPredicate() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 1746 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1779 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1789 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1977 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/ |
| H A D | EmulateInstructionARM64.cpp | 622 const uint32_t Rd = Bits32(opcode, 4, 0); in EmulateADDSUBImm() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstExtenders.cpp | 325 Register Rd; member
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| H A D | HexagonFrameLowering.cpp | 2510 Register Rd = RdOp.getReg(), Rs = RsOp.getReg(); in expandAlloca() local
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| H A D | HexagonInstrInfo.cpp | 1345 Register Rd = Op0.getReg(); in expandPostRAPseudo() local
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