1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_MAIN_H_ 6 #define __RTK_MAIN_H_ 7 8 #include <net/mac80211.h> 9 #include <linux/vmalloc.h> 10 #include <linux/firmware.h> 11 #include <linux/average.h> 12 #include <linux/bitops.h> 13 #include <linux/bitfield.h> 14 #include <linux/iopoll.h> 15 #include <linux/interrupt.h> 16 #include <linux/workqueue.h> 17 #if defined(__FreeBSD__) 18 #include <linux/kernel.h> 19 #include <linux/delay.h> 20 #include <linux/etherdevice.h> 21 #include <linux/rcupdate.h> 22 #include <linux/lockdep.h> 23 #include <linux/seq_file.h> 24 #endif 25 26 #include "util.h" 27 28 #define RTW_MAX_MAC_ID_NUM 32 29 #define RTW_MAX_SEC_CAM_NUM 32 30 #define MAX_PG_CAM_BACKUP_NUM 8 31 32 #define RTW_SCAN_MAX_SSIDS 4 33 34 #define RTW_MAX_PATTERN_NUM 12 35 #define RTW_MAX_PATTERN_MASK_SIZE 16 36 #define RTW_MAX_PATTERN_SIZE 128 37 38 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2) 39 40 #define RFREG_MASK 0xfffff 41 #define INV_RF_DATA 0xffffffff 42 #define TX_PAGE_SIZE_SHIFT 7 43 #define TX_PAGE_SIZE (1 << TX_PAGE_SIZE_SHIFT) 44 45 #define RTW_CHANNEL_WIDTH_MAX 3 46 #define RTW_RF_PATH_MAX 4 47 #define HW_FEATURE_LEN 13 48 49 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */ 50 51 extern bool rtw_bf_support; 52 extern bool rtw_disable_lps_deep_mode; 53 extern unsigned int rtw_debug_mask; 54 extern bool rtw_edcca_enabled; 55 extern const struct ieee80211_ops rtw_ops; 56 57 #define RTW_MAX_CHANNEL_NUM_2G 14 58 #define RTW_MAX_CHANNEL_NUM_5G 49 59 60 struct rtw_dev; 61 62 enum rtw_hci_type { 63 RTW_HCI_TYPE_PCIE, 64 RTW_HCI_TYPE_USB, 65 RTW_HCI_TYPE_SDIO, 66 67 RTW_HCI_TYPE_UNDEFINE, 68 }; 69 70 struct rtw_hci { 71 struct rtw_hci_ops *ops; 72 enum rtw_hci_type type; 73 74 u32 rpwm_addr; 75 u32 cpwm_addr; 76 77 u8 bulkout_num; 78 }; 79 80 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48)) 81 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64)) 82 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144)) 83 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177)) 84 85 #define IS_CH_5G_BAND_MID(channel) \ 86 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel)) 87 88 #define IS_CH_2G_BAND(channel) ((channel) <= 14) 89 #define IS_CH_5G_BAND(channel) \ 90 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \ 91 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel)) 92 93 enum rtw_supported_band { 94 RTW_BAND_2G = BIT(NL80211_BAND_2GHZ), 95 RTW_BAND_5G = BIT(NL80211_BAND_5GHZ), 96 RTW_BAND_60G = BIT(NL80211_BAND_60GHZ), 97 }; 98 99 /* now, support up to 80M bw */ 100 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80 101 102 enum rtw_bandwidth { 103 RTW_CHANNEL_WIDTH_20 = 0, 104 RTW_CHANNEL_WIDTH_40 = 1, 105 RTW_CHANNEL_WIDTH_80 = 2, 106 RTW_CHANNEL_WIDTH_160 = 3, 107 RTW_CHANNEL_WIDTH_80_80 = 4, 108 RTW_CHANNEL_WIDTH_5 = 5, 109 RTW_CHANNEL_WIDTH_10 = 6, 110 }; 111 112 enum rtw_sc_offset { 113 RTW_SC_DONT_CARE = 0, 114 RTW_SC_20_UPPER = 1, 115 RTW_SC_20_LOWER = 2, 116 RTW_SC_20_UPMOST = 3, 117 RTW_SC_20_LOWEST = 4, 118 RTW_SC_40_UPPER = 9, 119 RTW_SC_40_LOWER = 10, 120 }; 121 122 enum rtw_net_type { 123 RTW_NET_NO_LINK = 0, 124 RTW_NET_AD_HOC = 1, 125 RTW_NET_MGD_LINKED = 2, 126 RTW_NET_AP_MODE = 3, 127 }; 128 129 enum rtw_rf_type { 130 RF_1T1R = 0, 131 RF_1T2R = 1, 132 RF_2T2R = 2, 133 RF_2T3R = 3, 134 RF_2T4R = 4, 135 RF_3T3R = 5, 136 RF_3T4R = 6, 137 RF_4T4R = 7, 138 RF_TYPE_MAX, 139 }; 140 141 enum rtw_rf_path { 142 RF_PATH_A = 0, 143 RF_PATH_B = 1, 144 RF_PATH_C = 2, 145 RF_PATH_D = 3, 146 }; 147 148 enum rtw_bb_path { 149 BB_PATH_A = BIT(0), 150 BB_PATH_B = BIT(1), 151 BB_PATH_C = BIT(2), 152 BB_PATH_D = BIT(3), 153 154 BB_PATH_AB = (BB_PATH_A | BB_PATH_B), 155 BB_PATH_AC = (BB_PATH_A | BB_PATH_C), 156 BB_PATH_AD = (BB_PATH_A | BB_PATH_D), 157 BB_PATH_BC = (BB_PATH_B | BB_PATH_C), 158 BB_PATH_BD = (BB_PATH_B | BB_PATH_D), 159 BB_PATH_CD = (BB_PATH_C | BB_PATH_D), 160 161 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), 162 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), 163 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), 164 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), 165 166 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), 167 }; 168 169 enum rtw_rate_section { 170 RTW_RATE_SECTION_CCK = 0, 171 RTW_RATE_SECTION_OFDM, 172 RTW_RATE_SECTION_HT_1S, 173 RTW_RATE_SECTION_HT_2S, 174 RTW_RATE_SECTION_VHT_1S, 175 RTW_RATE_SECTION_VHT_2S, 176 177 /* keep last */ 178 RTW_RATE_SECTION_MAX, 179 }; 180 181 enum rtw_wireless_set { 182 WIRELESS_CCK = 0x00000001, 183 WIRELESS_OFDM = 0x00000002, 184 WIRELESS_HT = 0x00000004, 185 WIRELESS_VHT = 0x00000008, 186 }; 187 188 #define HT_STBC_EN BIT(0) 189 #define VHT_STBC_EN BIT(1) 190 #define HT_LDPC_EN BIT(0) 191 #define VHT_LDPC_EN BIT(1) 192 193 enum rtw_chip_type { 194 RTW_CHIP_TYPE_8822B, 195 RTW_CHIP_TYPE_8822C, 196 RTW_CHIP_TYPE_8723D, 197 RTW_CHIP_TYPE_8821C, 198 RTW_CHIP_TYPE_8703B, 199 }; 200 201 enum rtw_tx_queue_type { 202 /* the order of AC queues matters */ 203 RTW_TX_QUEUE_BK = 0x0, 204 RTW_TX_QUEUE_BE = 0x1, 205 RTW_TX_QUEUE_VI = 0x2, 206 RTW_TX_QUEUE_VO = 0x3, 207 208 RTW_TX_QUEUE_BCN = 0x4, 209 RTW_TX_QUEUE_MGMT = 0x5, 210 RTW_TX_QUEUE_HI0 = 0x6, 211 RTW_TX_QUEUE_H2C = 0x7, 212 /* keep it last */ 213 RTK_MAX_TX_QUEUE_NUM 214 }; 215 216 enum rtw_rx_queue_type { 217 RTW_RX_QUEUE_MPDU = 0x0, 218 RTW_RX_QUEUE_C2H = 0x1, 219 /* keep it last */ 220 RTK_MAX_RX_QUEUE_NUM 221 }; 222 223 enum rtw_fw_type { 224 RTW_NORMAL_FW = 0x0, 225 RTW_WOWLAN_FW = 0x1, 226 }; 227 228 enum rtw_rate_index { 229 RTW_RATEID_BGN_40M_2SS = 0, 230 RTW_RATEID_BGN_40M_1SS = 1, 231 RTW_RATEID_BGN_20M_2SS = 2, 232 RTW_RATEID_BGN_20M_1SS = 3, 233 RTW_RATEID_GN_N2SS = 4, 234 RTW_RATEID_GN_N1SS = 5, 235 RTW_RATEID_BG = 6, 236 RTW_RATEID_G = 7, 237 RTW_RATEID_B_20M = 8, 238 RTW_RATEID_ARFR0_AC_2SS = 9, 239 RTW_RATEID_ARFR1_AC_1SS = 10, 240 RTW_RATEID_ARFR2_AC_2G_1SS = 11, 241 RTW_RATEID_ARFR3_AC_2G_2SS = 12, 242 RTW_RATEID_ARFR4_AC_3SS = 13, 243 RTW_RATEID_ARFR5_N_3SS = 14, 244 RTW_RATEID_ARFR7_N_4SS = 15, 245 RTW_RATEID_ARFR6_AC_4SS = 16 246 }; 247 248 enum rtw_trx_desc_rate { 249 DESC_RATE1M = 0x00, 250 DESC_RATE2M = 0x01, 251 DESC_RATE5_5M = 0x02, 252 DESC_RATE11M = 0x03, 253 254 DESC_RATE6M = 0x04, 255 DESC_RATE9M = 0x05, 256 DESC_RATE12M = 0x06, 257 DESC_RATE18M = 0x07, 258 DESC_RATE24M = 0x08, 259 DESC_RATE36M = 0x09, 260 DESC_RATE48M = 0x0a, 261 DESC_RATE54M = 0x0b, 262 263 DESC_RATEMCS0 = 0x0c, 264 DESC_RATEMCS1 = 0x0d, 265 DESC_RATEMCS2 = 0x0e, 266 DESC_RATEMCS3 = 0x0f, 267 DESC_RATEMCS4 = 0x10, 268 DESC_RATEMCS5 = 0x11, 269 DESC_RATEMCS6 = 0x12, 270 DESC_RATEMCS7 = 0x13, 271 DESC_RATEMCS8 = 0x14, 272 DESC_RATEMCS9 = 0x15, 273 DESC_RATEMCS10 = 0x16, 274 DESC_RATEMCS11 = 0x17, 275 DESC_RATEMCS12 = 0x18, 276 DESC_RATEMCS13 = 0x19, 277 DESC_RATEMCS14 = 0x1a, 278 DESC_RATEMCS15 = 0x1b, 279 DESC_RATEMCS16 = 0x1c, 280 DESC_RATEMCS17 = 0x1d, 281 DESC_RATEMCS18 = 0x1e, 282 DESC_RATEMCS19 = 0x1f, 283 DESC_RATEMCS20 = 0x20, 284 DESC_RATEMCS21 = 0x21, 285 DESC_RATEMCS22 = 0x22, 286 DESC_RATEMCS23 = 0x23, 287 DESC_RATEMCS24 = 0x24, 288 DESC_RATEMCS25 = 0x25, 289 DESC_RATEMCS26 = 0x26, 290 DESC_RATEMCS27 = 0x27, 291 DESC_RATEMCS28 = 0x28, 292 DESC_RATEMCS29 = 0x29, 293 DESC_RATEMCS30 = 0x2a, 294 DESC_RATEMCS31 = 0x2b, 295 296 DESC_RATEVHT1SS_MCS0 = 0x2c, 297 DESC_RATEVHT1SS_MCS1 = 0x2d, 298 DESC_RATEVHT1SS_MCS2 = 0x2e, 299 DESC_RATEVHT1SS_MCS3 = 0x2f, 300 DESC_RATEVHT1SS_MCS4 = 0x30, 301 DESC_RATEVHT1SS_MCS5 = 0x31, 302 DESC_RATEVHT1SS_MCS6 = 0x32, 303 DESC_RATEVHT1SS_MCS7 = 0x33, 304 DESC_RATEVHT1SS_MCS8 = 0x34, 305 DESC_RATEVHT1SS_MCS9 = 0x35, 306 307 DESC_RATEVHT2SS_MCS0 = 0x36, 308 DESC_RATEVHT2SS_MCS1 = 0x37, 309 DESC_RATEVHT2SS_MCS2 = 0x38, 310 DESC_RATEVHT2SS_MCS3 = 0x39, 311 DESC_RATEVHT2SS_MCS4 = 0x3a, 312 DESC_RATEVHT2SS_MCS5 = 0x3b, 313 DESC_RATEVHT2SS_MCS6 = 0x3c, 314 DESC_RATEVHT2SS_MCS7 = 0x3d, 315 DESC_RATEVHT2SS_MCS8 = 0x3e, 316 DESC_RATEVHT2SS_MCS9 = 0x3f, 317 318 DESC_RATEVHT3SS_MCS0 = 0x40, 319 DESC_RATEVHT3SS_MCS1 = 0x41, 320 DESC_RATEVHT3SS_MCS2 = 0x42, 321 DESC_RATEVHT3SS_MCS3 = 0x43, 322 DESC_RATEVHT3SS_MCS4 = 0x44, 323 DESC_RATEVHT3SS_MCS5 = 0x45, 324 DESC_RATEVHT3SS_MCS6 = 0x46, 325 DESC_RATEVHT3SS_MCS7 = 0x47, 326 DESC_RATEVHT3SS_MCS8 = 0x48, 327 DESC_RATEVHT3SS_MCS9 = 0x49, 328 329 DESC_RATEVHT4SS_MCS0 = 0x4a, 330 DESC_RATEVHT4SS_MCS1 = 0x4b, 331 DESC_RATEVHT4SS_MCS2 = 0x4c, 332 DESC_RATEVHT4SS_MCS3 = 0x4d, 333 DESC_RATEVHT4SS_MCS4 = 0x4e, 334 DESC_RATEVHT4SS_MCS5 = 0x4f, 335 DESC_RATEVHT4SS_MCS6 = 0x50, 336 DESC_RATEVHT4SS_MCS7 = 0x51, 337 DESC_RATEVHT4SS_MCS8 = 0x52, 338 DESC_RATEVHT4SS_MCS9 = 0x53, 339 340 DESC_RATE_MAX, 341 }; 342 343 enum rtw_regulatory_domains { 344 RTW_REGD_FCC = 0, 345 RTW_REGD_MKK = 1, 346 RTW_REGD_ETSI = 2, 347 RTW_REGD_IC = 3, 348 RTW_REGD_KCC = 4, 349 RTW_REGD_ACMA = 5, 350 RTW_REGD_CHILE = 6, 351 RTW_REGD_UKRAINE = 7, 352 RTW_REGD_MEXICO = 8, 353 RTW_REGD_CN = 9, 354 RTW_REGD_QATAR = 10, 355 RTW_REGD_UK = 11, 356 357 RTW_REGD_WW, 358 RTW_REGD_MAX 359 }; 360 361 enum rtw_txq_flags { 362 RTW_TXQ_AMPDU, 363 RTW_TXQ_BLOCK_BA, 364 }; 365 366 enum rtw_flags { 367 RTW_FLAG_RUNNING, 368 RTW_FLAG_FW_RUNNING, 369 RTW_FLAG_SCANNING, 370 RTW_FLAG_POWERON, 371 RTW_FLAG_LEISURE_PS, 372 RTW_FLAG_LEISURE_PS_DEEP, 373 RTW_FLAG_DIG_DISABLE, 374 RTW_FLAG_BUSY_TRAFFIC, 375 RTW_FLAG_WOWLAN, 376 RTW_FLAG_RESTARTING, 377 RTW_FLAG_RESTART_TRIGGERING, 378 RTW_FLAG_FORCE_LOWEST_RATE, 379 380 NUM_OF_RTW_FLAGS, 381 }; 382 383 enum rtw_evm { 384 RTW_EVM_OFDM = 0, 385 RTW_EVM_1SS, 386 RTW_EVM_2SS_A, 387 RTW_EVM_2SS_B, 388 /* keep it last */ 389 RTW_EVM_NUM 390 }; 391 392 enum rtw_snr { 393 RTW_SNR_OFDM_A = 0, 394 RTW_SNR_OFDM_B, 395 RTW_SNR_OFDM_C, 396 RTW_SNR_OFDM_D, 397 RTW_SNR_1SS_A, 398 RTW_SNR_1SS_B, 399 RTW_SNR_1SS_C, 400 RTW_SNR_1SS_D, 401 RTW_SNR_2SS_A, 402 RTW_SNR_2SS_B, 403 RTW_SNR_2SS_C, 404 RTW_SNR_2SS_D, 405 /* keep it last */ 406 RTW_SNR_NUM 407 }; 408 409 enum rtw_port { 410 RTW_PORT_0 = 0, 411 RTW_PORT_1 = 1, 412 RTW_PORT_2 = 2, 413 RTW_PORT_3 = 3, 414 RTW_PORT_4 = 4, 415 RTW_PORT_NUM 416 }; 417 418 enum rtw_wow_flags { 419 RTW_WOW_FLAG_EN_MAGIC_PKT, 420 RTW_WOW_FLAG_EN_REKEY_PKT, 421 RTW_WOW_FLAG_EN_DISCONNECT, 422 423 /* keep it last */ 424 RTW_WOW_FLAG_MAX, 425 }; 426 427 /* the power index is represented by differences, which cck-1s & ht40-1s are 428 * the base values, so for 1s's differences, there are only ht20 & ofdm 429 */ 430 struct rtw_2g_1s_pwr_idx_diff { 431 #ifdef __LITTLE_ENDIAN 432 s8 ofdm:4; 433 s8 bw20:4; 434 #else 435 s8 bw20:4; 436 s8 ofdm:4; 437 #endif 438 } __packed; 439 440 struct rtw_2g_ns_pwr_idx_diff { 441 #ifdef __LITTLE_ENDIAN 442 s8 bw20:4; 443 s8 bw40:4; 444 s8 cck:4; 445 s8 ofdm:4; 446 #else 447 s8 ofdm:4; 448 s8 cck:4; 449 s8 bw40:4; 450 s8 bw20:4; 451 #endif 452 } __packed; 453 454 struct rtw_2g_txpwr_idx { 455 u8 cck_base[6]; 456 u8 bw40_base[5]; 457 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff; 458 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff; 459 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff; 460 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff; 461 }; 462 463 struct rtw_5g_ht_1s_pwr_idx_diff { 464 #ifdef __LITTLE_ENDIAN 465 s8 ofdm:4; 466 s8 bw20:4; 467 #else 468 s8 bw20:4; 469 s8 ofdm:4; 470 #endif 471 } __packed; 472 473 struct rtw_5g_ht_ns_pwr_idx_diff { 474 #ifdef __LITTLE_ENDIAN 475 s8 bw20:4; 476 s8 bw40:4; 477 #else 478 s8 bw40:4; 479 s8 bw20:4; 480 #endif 481 } __packed; 482 483 struct rtw_5g_ofdm_ns_pwr_idx_diff { 484 #ifdef __LITTLE_ENDIAN 485 s8 ofdm_3s:4; 486 s8 ofdm_2s:4; 487 s8 ofdm_4s:4; 488 s8 res:4; 489 #else 490 s8 res:4; 491 s8 ofdm_4s:4; 492 s8 ofdm_2s:4; 493 s8 ofdm_3s:4; 494 #endif 495 } __packed; 496 497 struct rtw_5g_vht_ns_pwr_idx_diff { 498 #ifdef __LITTLE_ENDIAN 499 s8 bw160:4; 500 s8 bw80:4; 501 #else 502 s8 bw80:4; 503 s8 bw160:4; 504 #endif 505 } __packed; 506 507 struct rtw_5g_txpwr_idx { 508 u8 bw40_base[14]; 509 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff; 510 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff; 511 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff; 512 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff; 513 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff; 514 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff; 515 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff; 516 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff; 517 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff; 518 }; 519 520 struct rtw_txpwr_idx { 521 struct rtw_2g_txpwr_idx pwr_idx_2g; 522 struct rtw_5g_txpwr_idx pwr_idx_5g; 523 }; 524 525 struct rtw_channel_params { 526 u8 center_chan; 527 u8 primary_chan; 528 u8 bandwidth; 529 }; 530 531 struct rtw_hw_reg { 532 u32 addr; 533 u32 mask; 534 }; 535 536 struct rtw_hw_reg_desc { 537 u32 addr; 538 u32 mask; 539 const char *desc; 540 }; 541 542 struct rtw_ltecoex_addr { 543 u32 ctrl; 544 u32 wdata; 545 u32 rdata; 546 }; 547 548 struct rtw_reg_domain { 549 u32 addr; 550 u32 mask; 551 #define RTW_REG_DOMAIN_MAC32 0 552 #define RTW_REG_DOMAIN_MAC16 1 553 #define RTW_REG_DOMAIN_MAC8 2 554 #define RTW_REG_DOMAIN_RF_A 3 555 #define RTW_REG_DOMAIN_RF_B 4 556 #define RTW_REG_DOMAIN_NL 0xFF 557 u8 domain; 558 }; 559 560 struct rtw_rf_sipi_addr { 561 u32 hssi_1; 562 u32 hssi_2; 563 u32 lssi_read; 564 u32 lssi_read_pi; 565 }; 566 567 struct rtw_hw_reg_offset { 568 struct rtw_hw_reg hw_reg; 569 u8 offset; 570 }; 571 572 struct rtw_backup_info { 573 u8 len; 574 u32 reg; 575 u32 val; 576 }; 577 578 enum rtw_vif_port_set { 579 PORT_SET_MAC_ADDR = BIT(0), 580 PORT_SET_BSSID = BIT(1), 581 PORT_SET_NET_TYPE = BIT(2), 582 PORT_SET_AID = BIT(3), 583 PORT_SET_BCN_CTRL = BIT(4), 584 }; 585 586 struct rtw_vif_port { 587 struct rtw_hw_reg mac_addr; 588 struct rtw_hw_reg bssid; 589 struct rtw_hw_reg net_type; 590 struct rtw_hw_reg aid; 591 struct rtw_hw_reg bcn_ctrl; 592 }; 593 594 struct rtw_tx_pkt_info { 595 u32 tx_pkt_size; 596 u8 offset; 597 u8 pkt_offset; 598 u8 tim_offset; 599 u8 mac_id; 600 u8 rate_id; 601 u8 rate; 602 u8 qsel; 603 u8 bw; 604 u8 sec_type; 605 u8 sn; 606 bool ampdu_en; 607 u8 ampdu_factor; 608 u8 ampdu_density; 609 u16 seq; 610 bool stbc; 611 bool ldpc; 612 bool dis_rate_fallback; 613 bool bmc; 614 bool use_rate; 615 bool ls; 616 bool fs; 617 bool short_gi; 618 bool report; 619 bool rts; 620 bool dis_qselseq; 621 bool en_hwseq; 622 u8 hw_ssn_sel; 623 bool nav_use_hdr; 624 bool bt_null; 625 }; 626 627 struct rtw_rx_pkt_stat { 628 bool phy_status; 629 bool icv_err; 630 bool crc_err; 631 bool decrypted; 632 bool is_c2h; 633 634 s32 signal_power; 635 u16 pkt_len; 636 u8 bw; 637 u8 drv_info_sz; 638 u8 shift; 639 u8 rate; 640 u8 mac_id; 641 u8 cam_id; 642 u8 ppdu_cnt; 643 u32 tsf_low; 644 s8 rx_power[RTW_RF_PATH_MAX]; 645 u8 rssi; 646 u8 rxsc; 647 s8 rx_snr[RTW_RF_PATH_MAX]; 648 u8 rx_evm[RTW_RF_PATH_MAX]; 649 s8 cfo_tail[RTW_RF_PATH_MAX]; 650 u16 freq; 651 u8 band; 652 653 struct rtw_sta_info *si; 654 struct ieee80211_vif *vif; 655 struct ieee80211_hdr *hdr; 656 }; 657 658 DECLARE_EWMA(tp, 10, 2); 659 660 struct rtw_traffic_stats { 661 /* units in bytes */ 662 u64 tx_unicast; 663 u64 rx_unicast; 664 665 /* count for packets */ 666 u64 tx_cnt; 667 u64 rx_cnt; 668 669 /* units in Mbps */ 670 u32 tx_throughput; 671 u32 rx_throughput; 672 struct ewma_tp tx_ewma_tp; 673 struct ewma_tp rx_ewma_tp; 674 }; 675 676 enum rtw_lps_mode { 677 RTW_MODE_ACTIVE = 0, 678 RTW_MODE_LPS = 1, 679 RTW_MODE_WMM_PS = 2, 680 }; 681 682 enum rtw_lps_deep_mode { 683 LPS_DEEP_MODE_NONE = 0, 684 LPS_DEEP_MODE_LCLK = 1, 685 LPS_DEEP_MODE_PG = 2, 686 }; 687 688 enum rtw_pwr_state { 689 RTW_RF_OFF = 0x0, 690 RTW_RF_ON = 0x4, 691 RTW_ALL_ON = 0xc, 692 }; 693 694 struct rtw_lps_conf { 695 enum rtw_lps_mode mode; 696 enum rtw_lps_deep_mode deep_mode; 697 enum rtw_lps_deep_mode wow_deep_mode; 698 enum rtw_pwr_state state; 699 u8 awake_interval; 700 u8 rlbm; 701 u8 smart_ps; 702 u8 port_id; 703 bool sec_cam_backup; 704 bool pattern_cam_backup; 705 }; 706 707 enum rtw_hw_key_type { 708 RTW_CAM_NONE = 0, 709 RTW_CAM_WEP40 = 1, 710 RTW_CAM_TKIP = 2, 711 RTW_CAM_AES = 4, 712 RTW_CAM_WEP104 = 5, 713 }; 714 715 struct rtw_cam_entry { 716 bool valid; 717 bool group; 718 u8 addr[ETH_ALEN]; 719 u8 hw_key_type; 720 struct ieee80211_key_conf *key; 721 }; 722 723 struct rtw_sec_desc { 724 /* search strategy */ 725 bool default_key_search; 726 727 u32 total_cam_num; 728 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM]; 729 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM); 730 }; 731 732 struct rtw_tx_report { 733 /* protect the tx report queue */ 734 spinlock_t q_lock; 735 struct sk_buff_head queue; 736 atomic_t sn; 737 struct timer_list purge_timer; 738 }; 739 740 struct rtw_ra_report { 741 struct rate_info txrate; 742 u32 bit_rate; 743 u8 desc_rate; 744 }; 745 746 struct rtw_txq { 747 struct list_head list; 748 unsigned long flags; 749 }; 750 751 #define RTW_BC_MC_MACID 1 752 DECLARE_EWMA(rssi, 10, 16); 753 754 struct rtw_sta_info { 755 struct rtw_dev *rtwdev; 756 struct ieee80211_sta *sta; 757 struct ieee80211_vif *vif; 758 759 struct ewma_rssi avg_rssi; 760 u8 rssi_level; 761 762 u8 mac_id; 763 u8 rate_id; 764 enum rtw_bandwidth bw_mode; 765 enum rtw_rf_type rf_type; 766 u8 stbc_en:2; 767 u8 ldpc_en:2; 768 bool sgi_enable; 769 bool vht_enable; 770 u8 init_ra_lv; 771 u64 ra_mask; 772 773 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS); 774 775 struct rtw_ra_report ra_report; 776 777 bool use_cfg_mask; 778 struct cfg80211_bitrate_mask *mask; 779 780 struct work_struct rc_work; 781 }; 782 783 enum rtw_bfee_role { 784 RTW_BFEE_NONE, 785 RTW_BFEE_SU, 786 RTW_BFEE_MU 787 }; 788 789 struct rtw_bfee { 790 enum rtw_bfee_role role; 791 792 u16 p_aid; 793 u8 g_id; 794 u8 mac_addr[ETH_ALEN]; 795 u8 sound_dim; 796 797 /* SU-MIMO */ 798 u8 su_reg_index; 799 800 /* MU-MIMO */ 801 u16 aid; 802 }; 803 804 struct rtw_bf_info { 805 u8 bfer_mu_cnt; 806 u8 bfer_su_cnt; 807 DECLARE_BITMAP(bfer_su_reg_maping, 2); 808 u8 cur_csi_rpt_rate; 809 }; 810 811 struct rtw_vif { 812 enum rtw_net_type net_type; 813 u16 aid; 814 u8 mac_id; /* for STA mode only */ 815 u8 mac_addr[ETH_ALEN]; 816 u8 bssid[ETH_ALEN]; 817 u8 port; 818 u8 bcn_ctrl; 819 struct list_head rsvd_page_list; 820 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 821 const struct rtw_vif_port *conf; 822 struct cfg80211_scan_request *scan_req; 823 struct ieee80211_scan_ies *scan_ies; 824 825 struct rtw_traffic_stats stats; 826 827 struct rtw_bfee bfee; 828 }; 829 830 struct rtw_regulatory { 831 char alpha2[2]; 832 u8 txpwr_regd_2g; 833 u8 txpwr_regd_5g; 834 }; 835 836 enum rtw_regd_state { 837 RTW_REGD_STATE_WORLDWIDE, 838 RTW_REGD_STATE_PROGRAMMED, 839 RTW_REGD_STATE_SETTING, 840 841 RTW_REGD_STATE_NR, 842 }; 843 844 struct rtw_regd { 845 enum rtw_regd_state state; 846 const struct rtw_regulatory *regulatory; 847 enum nl80211_dfs_regions dfs_region; 848 }; 849 850 struct rtw_chip_ops { 851 int (*mac_init)(struct rtw_dev *rtwdev); 852 int (*dump_fw_crash)(struct rtw_dev *rtwdev); 853 void (*shutdown)(struct rtw_dev *rtwdev); 854 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map); 855 void (*phy_set_param)(struct rtw_dev *rtwdev); 856 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel, 857 u8 bandwidth, u8 primary_chan_idx); 858 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc, 859 struct rtw_rx_pkt_stat *pkt_stat, 860 struct ieee80211_rx_status *rx_status); 861 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 862 u32 addr, u32 mask); 863 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 864 u32 addr, u32 mask, u32 data); 865 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 866 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset, 867 u32 size); 868 int (*set_antenna)(struct rtw_dev *rtwdev, 869 u32 antenna_tx, 870 u32 antenna_rx); 871 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 872 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable); 873 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 874 void (*phy_calibration)(struct rtw_dev *rtwdev); 875 void (*dpk_track)(struct rtw_dev *rtwdev); 876 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level); 877 void (*pwr_track)(struct rtw_dev *rtwdev); 878 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif, 879 struct rtw_bfee *bfee, bool enable); 880 void (*set_gid_table)(struct rtw_dev *rtwdev, 881 struct ieee80211_vif *vif, 882 struct ieee80211_bss_conf *conf); 883 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate, 884 u8 fixrate_en, u8 *new_rate); 885 void (*adaptivity_init)(struct rtw_dev *rtwdev); 886 void (*adaptivity)(struct rtw_dev *rtwdev); 887 void (*cfo_init)(struct rtw_dev *rtwdev); 888 void (*cfo_track)(struct rtw_dev *rtwdev); 889 void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path, 890 enum rtw_bb_path tx_path_1ss, 891 enum rtw_bb_path tx_path_cck, 892 bool is_tx2_path); 893 void (*config_txrx_mode)(struct rtw_dev *rtwdev, u8 tx_path, 894 u8 rx_path, bool is_tx2_path); 895 /* for USB/SDIO only */ 896 void (*fill_txdesc_checksum)(struct rtw_dev *rtwdev, 897 struct rtw_tx_pkt_info *pkt_info, 898 u8 *txdesc); 899 900 /* for coex */ 901 void (*coex_set_init)(struct rtw_dev *rtwdev); 902 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev, 903 u8 ctrl_type, u8 pos_type); 904 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev); 905 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev); 906 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev); 907 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr); 908 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain); 909 }; 910 911 #define RTW_PWR_POLLING_CNT 20000 912 913 #define RTW_PWR_CMD_READ 0x00 914 #define RTW_PWR_CMD_WRITE 0x01 915 #define RTW_PWR_CMD_POLLING 0x02 916 #define RTW_PWR_CMD_DELAY 0x03 917 #define RTW_PWR_CMD_END 0x04 918 919 /* define the base address of each block */ 920 #define RTW_PWR_ADDR_MAC 0x00 921 #define RTW_PWR_ADDR_USB 0x01 922 #define RTW_PWR_ADDR_PCIE 0x02 923 #define RTW_PWR_ADDR_SDIO 0x03 924 925 #define RTW_PWR_INTF_SDIO_MSK BIT(0) 926 #define RTW_PWR_INTF_USB_MSK BIT(1) 927 #define RTW_PWR_INTF_PCI_MSK BIT(2) 928 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 929 930 #define RTW_PWR_CUT_TEST_MSK BIT(0) 931 #define RTW_PWR_CUT_A_MSK BIT(1) 932 #define RTW_PWR_CUT_B_MSK BIT(2) 933 #define RTW_PWR_CUT_C_MSK BIT(3) 934 #define RTW_PWR_CUT_D_MSK BIT(4) 935 #define RTW_PWR_CUT_E_MSK BIT(5) 936 #define RTW_PWR_CUT_F_MSK BIT(6) 937 #define RTW_PWR_CUT_G_MSK BIT(7) 938 #define RTW_PWR_CUT_ALL_MSK 0xFF 939 940 enum rtw_pwr_seq_cmd_delay_unit { 941 RTW_PWR_DELAY_US, 942 RTW_PWR_DELAY_MS, 943 }; 944 945 struct rtw_pwr_seq_cmd { 946 u16 offset; 947 u8 cut_mask; 948 u8 intf_mask; 949 u8 base:4; 950 u8 cmd:4; 951 u8 mask; 952 u8 value; 953 }; 954 955 enum rtw_chip_ver { 956 RTW_CHIP_VER_CUT_A = 0x00, 957 RTW_CHIP_VER_CUT_B = 0x01, 958 RTW_CHIP_VER_CUT_C = 0x02, 959 RTW_CHIP_VER_CUT_D = 0x03, 960 RTW_CHIP_VER_CUT_E = 0x04, 961 RTW_CHIP_VER_CUT_F = 0x05, 962 RTW_CHIP_VER_CUT_G = 0x06, 963 }; 964 965 #define RTW_INTF_PHY_PLATFORM_ALL 0 966 967 enum rtw_intf_phy_cut { 968 RTW_INTF_PHY_CUT_A = BIT(0), 969 RTW_INTF_PHY_CUT_B = BIT(1), 970 RTW_INTF_PHY_CUT_C = BIT(2), 971 RTW_INTF_PHY_CUT_D = BIT(3), 972 RTW_INTF_PHY_CUT_E = BIT(4), 973 RTW_INTF_PHY_CUT_F = BIT(5), 974 RTW_INTF_PHY_CUT_G = BIT(6), 975 RTW_INTF_PHY_CUT_ALL = 0xFFFF, 976 }; 977 978 enum rtw_ip_sel { 979 RTW_IP_SEL_PHY = 0, 980 RTW_IP_SEL_MAC = 1, 981 RTW_IP_SEL_DBI = 2, 982 983 RTW_IP_SEL_UNDEF = 0xFFFF 984 }; 985 986 enum rtw_pq_map_id { 987 RTW_PQ_MAP_VO = 0x0, 988 RTW_PQ_MAP_VI = 0x1, 989 RTW_PQ_MAP_BE = 0x2, 990 RTW_PQ_MAP_BK = 0x3, 991 RTW_PQ_MAP_MG = 0x4, 992 RTW_PQ_MAP_HI = 0x5, 993 RTW_PQ_MAP_NUM = 0x6, 994 995 RTW_PQ_MAP_UNDEF, 996 }; 997 998 enum rtw_dma_mapping { 999 RTW_DMA_MAPPING_EXTRA = 0, 1000 RTW_DMA_MAPPING_LOW = 1, 1001 RTW_DMA_MAPPING_NORMAL = 2, 1002 RTW_DMA_MAPPING_HIGH = 3, 1003 1004 RTW_DMA_MAPPING_MAX, 1005 RTW_DMA_MAPPING_UNDEF, 1006 }; 1007 1008 struct rtw_rqpn { 1009 enum rtw_dma_mapping dma_map_vo; 1010 enum rtw_dma_mapping dma_map_vi; 1011 enum rtw_dma_mapping dma_map_be; 1012 enum rtw_dma_mapping dma_map_bk; 1013 enum rtw_dma_mapping dma_map_mg; 1014 enum rtw_dma_mapping dma_map_hi; 1015 }; 1016 1017 struct rtw_prioq_addr { 1018 u32 rsvd; 1019 u32 avail; 1020 }; 1021 1022 struct rtw_prioq_addrs { 1023 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX]; 1024 bool wsize; 1025 }; 1026 1027 struct rtw_page_table { 1028 u16 hq_num; 1029 u16 nq_num; 1030 u16 lq_num; 1031 u16 exq_num; 1032 u16 gapq_num; 1033 }; 1034 1035 struct rtw_intf_phy_para { 1036 u16 offset; 1037 u16 value; 1038 u16 ip_sel; 1039 u16 cut_mask; 1040 u16 platform; 1041 }; 1042 1043 struct rtw_wow_pattern { 1044 u16 crc; 1045 u8 type; 1046 u8 valid; 1047 u8 mask[RTW_MAX_PATTERN_MASK_SIZE]; 1048 }; 1049 1050 struct rtw_pno_request { 1051 bool inited; 1052 u32 match_set_cnt; 1053 struct cfg80211_match_set *match_sets; 1054 u8 channel_cnt; 1055 struct ieee80211_channel *channels; 1056 struct cfg80211_sched_scan_plan scan_plan; 1057 }; 1058 1059 struct rtw_wow_param { 1060 struct ieee80211_vif *wow_vif; 1061 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX); 1062 u8 txpause; 1063 u8 pattern_cnt; 1064 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM]; 1065 1066 bool ips_enabled; 1067 struct rtw_pno_request pno_req; 1068 }; 1069 1070 struct rtw_intf_phy_para_table { 1071 const struct rtw_intf_phy_para *usb2_para; 1072 const struct rtw_intf_phy_para *usb3_para; 1073 const struct rtw_intf_phy_para *gen1_para; 1074 const struct rtw_intf_phy_para *gen2_para; 1075 u8 n_usb2_para; 1076 u8 n_usb3_para; 1077 u8 n_gen1_para; 1078 u8 n_gen2_para; 1079 }; 1080 1081 struct rtw_table { 1082 const void *data; 1083 const u32 size; 1084 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 1085 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1086 u32 addr, u32 data); 1087 enum rtw_rf_path rf_path; 1088 }; 1089 1090 static inline void rtw_load_table(struct rtw_dev *rtwdev, 1091 const struct rtw_table *tbl) 1092 { 1093 (*tbl->parse)(rtwdev, tbl); 1094 } 1095 1096 enum rtw_rfe_fem { 1097 RTW_RFE_IFEM, 1098 RTW_RFE_EFEM, 1099 RTW_RFE_IFEM2G_EFEM5G, 1100 RTW_RFE_NUM, 1101 }; 1102 1103 struct rtw_rfe_def { 1104 const struct rtw_table *phy_pg_tbl; 1105 const struct rtw_table *txpwr_lmt_tbl; 1106 const struct rtw_table *agc_btg_tbl; 1107 }; 1108 1109 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \ 1110 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1111 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1112 } 1113 1114 #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, btg) { \ 1115 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1116 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1117 .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \ 1118 } 1119 1120 #define RTW_PWR_TRK_5G_1 0 1121 #define RTW_PWR_TRK_5G_2 1 1122 #define RTW_PWR_TRK_5G_3 2 1123 #define RTW_PWR_TRK_5G_NUM 3 1124 1125 #define RTW_PWR_TRK_TBL_SZ 30 1126 1127 /* This table stores the values of TX power that will be adjusted by power 1128 * tracking. 1129 * 1130 * For 5G bands, there are 3 different settings. 1131 * For 2G there are cck rate and ofdm rate with different settings. 1132 */ 1133 struct rtw_pwr_track_tbl { 1134 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM]; 1135 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM]; 1136 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM]; 1137 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM]; 1138 const u8 *pwrtrk_2gb_n; 1139 const u8 *pwrtrk_2gb_p; 1140 const u8 *pwrtrk_2ga_n; 1141 const u8 *pwrtrk_2ga_p; 1142 const u8 *pwrtrk_2g_cckb_n; 1143 const u8 *pwrtrk_2g_cckb_p; 1144 const u8 *pwrtrk_2g_ccka_n; 1145 const u8 *pwrtrk_2g_ccka_p; 1146 const s8 *pwrtrk_xtal_n; 1147 const s8 *pwrtrk_xtal_p; 1148 }; 1149 1150 enum rtw_wlan_cpu { 1151 RTW_WCPU_11AC, 1152 RTW_WCPU_11N, 1153 }; 1154 1155 enum rtw_fw_fifo_sel { 1156 RTW_FW_FIFO_SEL_TX, 1157 RTW_FW_FIFO_SEL_RX, 1158 RTW_FW_FIFO_SEL_RSVD_PAGE, 1159 RTW_FW_FIFO_SEL_REPORT, 1160 RTW_FW_FIFO_SEL_LLT, 1161 RTW_FW_FIFO_SEL_RXBUF_FW, 1162 1163 RTW_FW_FIFO_MAX, 1164 }; 1165 1166 enum rtw_fwcd_item { 1167 RTW_FWCD_TLV, 1168 RTW_FWCD_REG, 1169 RTW_FWCD_ROM, 1170 RTW_FWCD_IMEM, 1171 RTW_FWCD_DMEM, 1172 RTW_FWCD_EMEM, 1173 }; 1174 1175 /* hardware configuration for each IC */ 1176 struct rtw_chip_info { 1177 struct rtw_chip_ops *ops; 1178 u8 id; 1179 1180 const char *fw_name; 1181 enum rtw_wlan_cpu wlan_cpu; 1182 u8 tx_pkt_desc_sz; 1183 u8 tx_buf_desc_sz; 1184 u8 rx_pkt_desc_sz; 1185 u8 rx_buf_desc_sz; 1186 u32 phy_efuse_size; 1187 u32 log_efuse_size; 1188 u32 ptct_efuse_size; 1189 u32 txff_size; 1190 u32 rxff_size; 1191 u32 fw_rxff_size; 1192 u16 rsvd_drv_pg_num; 1193 u8 band; 1194 u8 page_size; 1195 u8 csi_buf_pg_num; 1196 u8 dig_max; 1197 u8 dig_min; 1198 u8 txgi_factor; 1199 bool is_pwr_by_rate_dec; 1200 bool rx_ldpc; 1201 bool tx_stbc; 1202 u8 max_power_index; 1203 u8 ampdu_density; 1204 1205 u16 fw_fifo_addr[RTW_FW_FIFO_MAX]; 1206 const struct rtw_fwcd_segs *fwcd_segs; 1207 1208 u8 usb_tx_agg_desc_num; 1209 1210 u8 default_1ss_tx_path; 1211 1212 bool path_div_supported; 1213 bool ht_supported; 1214 bool vht_supported; 1215 u8 lps_deep_mode_supported; 1216 1217 /* init values */ 1218 u8 sys_func_en; 1219 const struct rtw_pwr_seq_cmd **pwr_on_seq; 1220 const struct rtw_pwr_seq_cmd **pwr_off_seq; 1221 const struct rtw_rqpn *rqpn_table; 1222 const struct rtw_prioq_addrs *prioq_addrs; 1223 const struct rtw_page_table *page_table; 1224 const struct rtw_intf_phy_para_table *intf_table; 1225 1226 const struct rtw_hw_reg *dig; 1227 const struct rtw_hw_reg *dig_cck; 1228 u32 rf_base_addr[2]; 1229 u32 rf_sipi_addr[2]; 1230 const struct rtw_rf_sipi_addr *rf_sipi_read_addr; 1231 u8 fix_rf_phy_num; 1232 const struct rtw_ltecoex_addr *ltecoex_addr; 1233 1234 const struct rtw_table *mac_tbl; 1235 const struct rtw_table *agc_tbl; 1236 const struct rtw_table *bb_tbl; 1237 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX]; 1238 const struct rtw_table *rfk_init_tbl; 1239 1240 const struct rtw_rfe_def *rfe_defs; 1241 u32 rfe_defs_size; 1242 1243 bool en_dis_dpd; 1244 u16 dpd_ratemask; 1245 u8 iqk_threshold; 1246 u8 lck_threshold; 1247 const struct rtw_pwr_track_tbl *pwr_track_tbl; 1248 1249 u8 bfer_su_max_num; 1250 u8 bfer_mu_max_num; 1251 1252 struct rtw_hw_reg_offset *edcca_th; 1253 s8 l2h_th_ini_cs; 1254 s8 l2h_th_ini_ad; 1255 1256 const char *wow_fw_name; 1257 const struct wiphy_wowlan_support *wowlan_stub; 1258 const u8 max_sched_scan_ssids; 1259 const u16 max_scan_ie_len; 1260 1261 /* coex paras */ 1262 u32 coex_para_ver; 1263 u8 bt_desired_ver; 1264 bool scbd_support; 1265 bool new_scbd10_def; /* true: fix 2M(8822c) */ 1266 bool ble_hid_profile_support; 1267 bool wl_mimo_ps_support; 1268 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */ 1269 u8 bt_rssi_type; 1270 u8 ant_isolation; 1271 u8 rssi_tolerance; 1272 u8 table_sant_num; 1273 u8 table_nsant_num; 1274 u8 tdma_sant_num; 1275 u8 tdma_nsant_num; 1276 u8 bt_afh_span_bw20; 1277 u8 bt_afh_span_bw40; 1278 u8 afh_5g_num; 1279 u8 wl_rf_para_num; 1280 u8 coex_info_hw_regs_num; 1281 const u8 *bt_rssi_step; 1282 const u8 *wl_rssi_step; 1283 const struct coex_table_para *table_nsant; 1284 const struct coex_table_para *table_sant; 1285 const struct coex_tdma_para *tdma_sant; 1286 const struct coex_tdma_para *tdma_nsant; 1287 const struct coex_rf_para *wl_rf_para_tx; 1288 const struct coex_rf_para *wl_rf_para_rx; 1289 const struct coex_5g_afh_map *afh_5g; 1290 const struct rtw_hw_reg *btg_reg; 1291 const struct rtw_reg_domain *coex_info_hw_regs; 1292 u32 wl_fw_desired_ver; 1293 }; 1294 1295 enum rtw_coex_bt_state_cnt { 1296 COEX_CNT_BT_RETRY, 1297 COEX_CNT_BT_REINIT, 1298 COEX_CNT_BT_REENABLE, 1299 COEX_CNT_BT_POPEVENT, 1300 COEX_CNT_BT_SETUPLINK, 1301 COEX_CNT_BT_IGNWLANACT, 1302 COEX_CNT_BT_INQ, 1303 COEX_CNT_BT_PAGE, 1304 COEX_CNT_BT_ROLESWITCH, 1305 COEX_CNT_BT_AFHUPDATE, 1306 COEX_CNT_BT_INFOUPDATE, 1307 COEX_CNT_BT_IQK, 1308 COEX_CNT_BT_IQKFAIL, 1309 1310 COEX_CNT_BT_MAX 1311 }; 1312 1313 enum rtw_coex_wl_state_cnt { 1314 COEX_CNT_WL_SCANAP, 1315 COEX_CNT_WL_CONNPKT, 1316 COEX_CNT_WL_COEXRUN, 1317 COEX_CNT_WL_NOISY0, 1318 COEX_CNT_WL_NOISY1, 1319 COEX_CNT_WL_NOISY2, 1320 COEX_CNT_WL_5MS_NOEXTEND, 1321 COEX_CNT_WL_FW_NOTIFY, 1322 1323 COEX_CNT_WL_MAX 1324 }; 1325 1326 struct rtw_coex_rfe { 1327 bool ant_switch_exist; 1328 bool ant_switch_diversity; 1329 bool ant_switch_with_bt; 1330 u8 rfe_module_type; 1331 u8 ant_switch_polarity; 1332 1333 /* true if WLG at BTG, else at WLAG */ 1334 bool wlg_at_btg; 1335 }; 1336 1337 #define COEX_WL_TDMA_PARA_LENGTH 5 1338 1339 struct rtw_coex_dm { 1340 bool cur_ps_tdma_on; 1341 bool cur_wl_rx_low_gain_en; 1342 bool ignore_wl_act; 1343 1344 u8 reason; 1345 u8 bt_rssi_state[4]; 1346 u8 wl_rssi_state[4]; 1347 u8 wl_ch_info[3]; 1348 u8 cur_ps_tdma; 1349 u8 cur_table; 1350 u8 ps_tdma_para[5]; 1351 u8 cur_bt_pwr_lvl; 1352 u8 cur_bt_lna_lvl; 1353 u8 cur_wl_pwr_lvl; 1354 u8 bt_status; 1355 u32 cur_ant_pos_type; 1356 u32 cur_switch_status; 1357 u32 setting_tdma; 1358 u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH]; 1359 }; 1360 1361 #define COEX_BTINFO_SRC_WL_FW 0x0 1362 #define COEX_BTINFO_SRC_BT_RSP 0x1 1363 #define COEX_BTINFO_SRC_BT_ACT 0x2 1364 #define COEX_BTINFO_SRC_BT_IQK 0x3 1365 #define COEX_BTINFO_SRC_BT_SCBD 0x4 1366 #define COEX_BTINFO_SRC_H2C60 0x5 1367 #define COEX_BTINFO_SRC_MAX 0x6 1368 1369 #define COEX_INFO_FTP BIT(7) 1370 #define COEX_INFO_A2DP BIT(6) 1371 #define COEX_INFO_HID BIT(5) 1372 #define COEX_INFO_SCO_BUSY BIT(4) 1373 #define COEX_INFO_ACL_BUSY BIT(3) 1374 #define COEX_INFO_INQ_PAGE BIT(2) 1375 #define COEX_INFO_SCO_ESCO BIT(1) 1376 #define COEX_INFO_CONNECTION BIT(0) 1377 #define COEX_BTINFO_LENGTH_MAX 10 1378 #define COEX_BTINFO_LENGTH 7 1379 1380 #define COEX_BT_HIDINFO_LIST 0x0 1381 #define COEX_BT_HIDINFO_A 0x1 1382 #define COEX_BT_HIDINFO_NAME 3 1383 1384 #define COEX_BT_HIDINFO_LENGTH 6 1385 #define COEX_BT_HIDINFO_HANDLE_NUM 4 1386 #define COEX_BT_HIDINFO_C2H_HANDLE 0 1387 #define COEX_BT_HIDINFO_C2H_VENDOR 1 1388 #define COEX_BT_BLE_HANDLE_THRS 0x10 1389 #define COEX_BT_HIDINFO_NOTCON 0xff 1390 1391 struct rtw_coex_hid { 1392 u8 hid_handle; 1393 u8 hid_vendor; 1394 u8 hid_name[COEX_BT_HIDINFO_NAME]; 1395 bool hid_info_completed; 1396 bool is_game_hid; 1397 }; 1398 1399 struct rtw_coex_hid_handle_list { 1400 u8 cmd_id; 1401 u8 len; 1402 u8 subid; 1403 u8 handle_cnt; 1404 u8 handle[COEX_BT_HIDINFO_HANDLE_NUM]; 1405 } __packed; 1406 1407 struct rtw_coex_hid_info_a { 1408 u8 cmd_id; 1409 u8 len; 1410 u8 subid; 1411 u8 handle; 1412 u8 vendor; 1413 u8 name[COEX_BT_HIDINFO_NAME]; 1414 } __packed; 1415 1416 struct rtw_coex_stat { 1417 bool bt_disabled; 1418 bool bt_disabled_pre; 1419 bool bt_link_exist; 1420 bool bt_whck_test; 1421 bool bt_inq_page; 1422 bool bt_inq_remain; 1423 bool bt_inq; 1424 bool bt_page; 1425 bool bt_ble_voice; 1426 bool bt_ble_exist; 1427 bool bt_hfp_exist; 1428 bool bt_a2dp_exist; 1429 bool bt_hid_exist; 1430 bool bt_pan_exist; /* PAN or OPP */ 1431 bool bt_opp_exist; /* OPP only */ 1432 bool bt_acl_busy; 1433 bool bt_fix_2M; 1434 bool bt_setup_link; 1435 bool bt_multi_link; 1436 bool bt_multi_link_pre; 1437 bool bt_multi_link_remain; 1438 bool bt_a2dp_sink; 1439 bool bt_a2dp_active; 1440 bool bt_reenable; 1441 bool bt_ble_scan_en; 1442 bool bt_init_scan; 1443 bool bt_slave; 1444 bool bt_418_hid_exist; 1445 bool bt_ble_hid_exist; 1446 bool bt_game_hid_exist; 1447 bool bt_hid_handle_cnt; 1448 bool bt_mailbox_reply; 1449 1450 bool wl_under_lps; 1451 bool wl_under_ips; 1452 bool wl_hi_pri_task1; 1453 bool wl_hi_pri_task2; 1454 bool wl_force_lps_ctrl; 1455 bool wl_gl_busy; 1456 bool wl_linkscan_proc; 1457 bool wl_ps_state_fail; 1458 bool wl_tx_limit_en; 1459 bool wl_ampdu_limit_en; 1460 bool wl_connected; 1461 bool wl_slot_extend; 1462 bool wl_cck_lock; 1463 bool wl_cck_lock_pre; 1464 bool wl_cck_lock_ever; 1465 bool wl_connecting; 1466 bool wl_slot_toggle; 1467 bool wl_slot_toggle_change; /* if toggle to no-toggle */ 1468 bool wl_mimo_ps; 1469 1470 u32 bt_supported_version; 1471 u32 bt_supported_feature; 1472 u32 hi_pri_tx; 1473 u32 hi_pri_rx; 1474 u32 lo_pri_tx; 1475 u32 lo_pri_rx; 1476 u32 patch_ver; 1477 u16 bt_reg_vendor_ae; 1478 u16 bt_reg_vendor_ac; 1479 s8 bt_rssi; 1480 u8 kt_ver; 1481 u8 gnt_workaround_state; 1482 u8 tdma_timer_base; 1483 u8 bt_profile_num; 1484 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX]; 1485 u8 bt_info_lb2; 1486 u8 bt_info_lb3; 1487 u8 bt_info_hb0; 1488 u8 bt_info_hb1; 1489 u8 bt_info_hb2; 1490 u8 bt_info_hb3; 1491 u8 bt_ble_scan_type; 1492 u8 bt_hid_pair_num; 1493 u8 bt_hid_slot; 1494 u8 bt_a2dp_bitpool; 1495 u8 bt_iqk_state; 1496 1497 u16 wl_beacon_interval; 1498 u8 wl_noisy_level; 1499 u8 wl_fw_dbg_info[10]; 1500 u8 wl_fw_dbg_info_pre[10]; 1501 u8 wl_rx_rate; 1502 u8 wl_tx_rate; 1503 u8 wl_rts_rx_rate; 1504 u8 wl_coex_mode; 1505 u8 wl_iot_peer; 1506 u8 ampdu_max_time; 1507 u8 wl_tput_dir; 1508 1509 u8 wl_toggle_para[6]; 1510 u8 wl_toggle_interval; 1511 1512 u16 score_board; 1513 u16 retry_limit; 1514 1515 /* counters to record bt states */ 1516 u32 cnt_bt[COEX_CNT_BT_MAX]; 1517 1518 /* counters to record wifi states */ 1519 u32 cnt_wl[COEX_CNT_WL_MAX]; 1520 1521 /* counters to record bt c2h data */ 1522 u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX]; 1523 1524 u32 darfrc; 1525 u32 darfrch; 1526 1527 struct rtw_coex_hid hid_info[COEX_BT_HIDINFO_HANDLE_NUM]; 1528 struct rtw_coex_hid_handle_list hid_handle_list; 1529 }; 1530 1531 struct rtw_coex { 1532 struct sk_buff_head queue; 1533 wait_queue_head_t wait; 1534 1535 bool under_5g; 1536 bool stop_dm; 1537 bool freeze; 1538 bool freerun; 1539 bool wl_rf_off; 1540 bool manual_control; 1541 1542 struct rtw_coex_stat stat; 1543 struct rtw_coex_dm dm; 1544 struct rtw_coex_rfe rfe; 1545 1546 struct delayed_work bt_relink_work; 1547 struct delayed_work bt_reenable_work; 1548 struct delayed_work defreeze_work; 1549 struct delayed_work wl_remain_work; 1550 struct delayed_work bt_remain_work; 1551 struct delayed_work wl_connecting_work; 1552 struct delayed_work bt_multi_link_remain_work; 1553 struct delayed_work wl_ccklock_work; 1554 1555 }; 1556 1557 #define DPK_RF_REG_NUM 7 1558 #define DPK_RF_PATH_NUM 2 1559 #define DPK_BB_REG_NUM 18 1560 #define DPK_CHANNEL_WIDTH_80 1 1561 1562 DECLARE_EWMA(thermal, 10, 4); 1563 1564 struct rtw_dpk_info { 1565 bool is_dpk_pwr_on; 1566 bool is_reload; 1567 1568 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM); 1569 1570 u8 thermal_dpk[DPK_RF_PATH_NUM]; 1571 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM]; 1572 1573 u32 gnt_control; 1574 u32 gnt_value; 1575 1576 u8 result[RTW_RF_PATH_MAX]; 1577 u8 dpk_txagc[RTW_RF_PATH_MAX]; 1578 u32 coef[RTW_RF_PATH_MAX][20]; 1579 u16 dpk_gs[RTW_RF_PATH_MAX]; 1580 u8 thermal_dpk_delta[RTW_RF_PATH_MAX]; 1581 u8 pre_pwsf[RTW_RF_PATH_MAX]; 1582 1583 u8 dpk_band; 1584 u8 dpk_ch; 1585 u8 dpk_bw; 1586 }; 1587 1588 struct rtw_phy_cck_pd_reg { 1589 u32 reg_pd; 1590 u32 mask_pd; 1591 u32 reg_cs; 1592 u32 mask_cs; 1593 }; 1594 1595 #define DACK_MSBK_BACKUP_NUM 0xf 1596 #define DACK_DCK_BACKUP_NUM 0x2 1597 1598 struct rtw_swing_table { 1599 const u8 *p[RTW_RF_PATH_MAX]; 1600 const u8 *n[RTW_RF_PATH_MAX]; 1601 }; 1602 1603 struct rtw_pkt_count { 1604 u16 num_bcn_pkt; 1605 u16 num_qry_pkt[DESC_RATE_MAX]; 1606 }; 1607 1608 DECLARE_EWMA(evm, 10, 4); 1609 DECLARE_EWMA(snr, 10, 4); 1610 1611 struct rtw_iqk_info { 1612 bool done; 1613 struct { 1614 u32 s1_x; 1615 u32 s1_y; 1616 u32 s0_x; 1617 u32 s0_y; 1618 } result; 1619 }; 1620 1621 enum rtw_rf_band { 1622 RF_BAND_2G_CCK, 1623 RF_BAND_2G_OFDM, 1624 RF_BAND_5G_L, 1625 RF_BAND_5G_M, 1626 RF_BAND_5G_H, 1627 RF_BAND_MAX 1628 }; 1629 1630 #define RF_GAIN_NUM 11 1631 #define RF_HW_OFFSET_NUM 10 1632 1633 struct rtw_gapk_info { 1634 u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1635 u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM]; 1636 bool txgapk_bp_done; 1637 s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1638 s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1639 u8 read_txgain; 1640 u8 channel; 1641 }; 1642 1643 #define EDCCA_TH_L2H_IDX 0 1644 #define EDCCA_TH_H2L_IDX 1 1645 #define EDCCA_TH_L2H_LB 48 1646 #define EDCCA_ADC_BACKOFF 12 1647 #define EDCCA_IGI_BASE 50 1648 #define EDCCA_IGI_L2H_DIFF 8 1649 #define EDCCA_L2H_H2L_DIFF 7 1650 #define EDCCA_L2H_H2L_DIFF_NORMAL 8 1651 1652 enum rtw_edcca_mode { 1653 RTW_EDCCA_NORMAL = 0, 1654 RTW_EDCCA_ADAPTIVITY = 1, 1655 }; 1656 1657 struct rtw_cfo_track { 1658 bool is_adjust; 1659 u8 crystal_cap; 1660 s32 cfo_tail[RTW_RF_PATH_MAX]; 1661 s32 cfo_cnt[RTW_RF_PATH_MAX]; 1662 u32 packet_count; 1663 u32 packet_count_pre; 1664 }; 1665 1666 #define RRSR_INIT_2G 0x15f 1667 #define RRSR_INIT_5G 0x150 1668 1669 enum rtw_dm_cap { 1670 RTW_DM_CAP_NA, 1671 RTW_DM_CAP_TXGAPK, 1672 RTW_DM_CAP_NUM 1673 }; 1674 1675 struct rtw_dm_info { 1676 u32 cck_fa_cnt; 1677 u32 ofdm_fa_cnt; 1678 u32 total_fa_cnt; 1679 u32 cck_cca_cnt; 1680 u32 ofdm_cca_cnt; 1681 u32 total_cca_cnt; 1682 1683 u32 cck_ok_cnt; 1684 u32 cck_err_cnt; 1685 u32 ofdm_ok_cnt; 1686 u32 ofdm_err_cnt; 1687 u32 ht_ok_cnt; 1688 u32 ht_err_cnt; 1689 u32 vht_ok_cnt; 1690 u32 vht_err_cnt; 1691 1692 u8 min_rssi; 1693 u8 pre_min_rssi; 1694 u16 fa_history[4]; 1695 u8 igi_history[4]; 1696 u8 igi_bitmap; 1697 bool damping; 1698 u8 damping_cnt; 1699 u8 damping_rssi; 1700 1701 u8 cck_gi_u_bnd; 1702 u8 cck_gi_l_bnd; 1703 1704 u8 fix_rate; 1705 u8 tx_rate; 1706 u32 rrsr_val_init; 1707 u32 rrsr_mask_min; 1708 u8 thermal_avg[RTW_RF_PATH_MAX]; 1709 u8 thermal_meter_k; 1710 u8 thermal_meter_lck; 1711 s8 delta_power_index[RTW_RF_PATH_MAX]; 1712 s8 delta_power_index_last[RTW_RF_PATH_MAX]; 1713 u8 default_ofdm_index; 1714 u8 default_cck_index; 1715 bool pwr_trk_triggered; 1716 bool pwr_trk_init_trigger; 1717 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX]; 1718 s8 txagc_remnant_cck; 1719 s8 txagc_remnant_ofdm; 1720 u8 rx_cck_agc_report_type; 1721 1722 /* backup dack results for each path and I/Q */ 1723 u32 dack_adck[RTW_RF_PATH_MAX]; 1724 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM]; 1725 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM]; 1726 1727 struct rtw_dpk_info dpk_info; 1728 struct rtw_cfo_track cfo_track; 1729 1730 /* [bandwidth 0:20M/1:40M][number of path] */ 1731 u8 cck_pd_lv[2][RTW_RF_PATH_MAX]; 1732 u32 cck_fa_avg; 1733 u8 cck_pd_default; 1734 1735 /* save the last rx phy status for debug */ 1736 s8 rx_snr[RTW_RF_PATH_MAX]; 1737 u8 rx_evm_dbm[RTW_RF_PATH_MAX]; 1738 s16 cfo_tail[RTW_RF_PATH_MAX]; 1739 u8 rssi[RTW_RF_PATH_MAX]; 1740 u8 curr_rx_rate; 1741 struct rtw_pkt_count cur_pkt_count; 1742 struct rtw_pkt_count last_pkt_count; 1743 struct ewma_evm ewma_evm[RTW_EVM_NUM]; 1744 struct ewma_snr ewma_snr[RTW_SNR_NUM]; 1745 1746 u32 dm_flags; /* enum rtw_dm_cap */ 1747 struct rtw_iqk_info iqk; 1748 struct rtw_gapk_info gapk; 1749 bool is_bt_iqk_timeout; 1750 1751 s8 l2h_th_ini; 1752 enum rtw_edcca_mode edcca_mode; 1753 u8 scan_density; 1754 }; 1755 1756 struct rtw_efuse { 1757 u32 size; 1758 u32 physical_size; 1759 u32 logical_size; 1760 u32 protect_size; 1761 1762 u8 addr[ETH_ALEN]; 1763 u8 channel_plan; 1764 u8 country_code[2]; 1765 u8 rf_board_option; 1766 u8 rfe_option; 1767 u8 power_track_type; 1768 u8 thermal_meter[RTW_RF_PATH_MAX]; 1769 u8 thermal_meter_k; 1770 u8 crystal_cap; 1771 u8 ant_div_cfg; 1772 u8 ant_div_type; 1773 u8 regd; 1774 u8 afe; 1775 1776 u8 lna_type_2g; 1777 u8 lna_type_5g; 1778 u8 glna_type; 1779 u8 alna_type; 1780 bool ext_lna_2g; 1781 bool ext_lna_5g; 1782 u8 pa_type_2g; 1783 u8 pa_type_5g; 1784 u8 gpa_type; 1785 u8 apa_type; 1786 bool ext_pa_2g; 1787 bool ext_pa_5g; 1788 u8 tx_bb_swing_setting_2g; 1789 u8 tx_bb_swing_setting_5g; 1790 1791 bool btcoex; 1792 /* bt share antenna with wifi */ 1793 bool share_ant; 1794 u8 bt_setting; 1795 1796 struct { 1797 u8 hci; 1798 u8 bw; 1799 u8 ptcl; 1800 u8 nss; 1801 u8 ant_num; 1802 } hw_cap; 1803 1804 struct rtw_txpwr_idx txpwr_idx_table[4]; 1805 }; 1806 1807 struct rtw_phy_cond { 1808 #ifdef __LITTLE_ENDIAN 1809 u32 rfe:8; 1810 u32 intf:4; 1811 u32 pkg:4; 1812 u32 plat:4; 1813 u32 intf_rsvd:4; 1814 u32 cut:4; 1815 u32 branch:2; 1816 u32 neg:1; 1817 u32 pos:1; 1818 #else 1819 u32 pos:1; 1820 u32 neg:1; 1821 u32 branch:2; 1822 u32 cut:4; 1823 u32 intf_rsvd:4; 1824 u32 plat:4; 1825 u32 pkg:4; 1826 u32 intf:4; 1827 u32 rfe:8; 1828 #endif 1829 /* for intf:4 */ 1830 #define INTF_PCIE BIT(0) 1831 #define INTF_USB BIT(1) 1832 #define INTF_SDIO BIT(2) 1833 /* for branch:2 */ 1834 #define BRANCH_IF 0 1835 #define BRANCH_ELIF 1 1836 #define BRANCH_ELSE 2 1837 #define BRANCH_ENDIF 3 1838 }; 1839 1840 struct rtw_fifo_conf { 1841 /* tx fifo information */ 1842 u16 rsvd_boundary; 1843 u16 rsvd_pg_num; 1844 u16 rsvd_drv_pg_num; 1845 u16 txff_pg_num; 1846 u16 acq_pg_num; 1847 u16 rsvd_drv_addr; 1848 u16 rsvd_h2c_info_addr; 1849 u16 rsvd_h2c_sta_info_addr; 1850 u16 rsvd_h2cq_addr; 1851 u16 rsvd_cpu_instr_addr; 1852 u16 rsvd_fw_txbuf_addr; 1853 u16 rsvd_csibuf_addr; 1854 const struct rtw_rqpn *rqpn; 1855 }; 1856 1857 struct rtw_fwcd_desc { 1858 u32 size; 1859 u8 *next; 1860 u8 *data; 1861 }; 1862 1863 struct rtw_fwcd_segs { 1864 const u32 *segs; 1865 u8 num; 1866 }; 1867 1868 #define FW_CD_TYPE 0xffff 1869 #define FW_CD_LEN 4 1870 #define FW_CD_VAL 0xaabbccdd 1871 struct rtw_fw_state { 1872 const struct firmware *firmware; 1873 struct rtw_dev *rtwdev; 1874 struct completion completion; 1875 struct rtw_fwcd_desc fwcd_desc; 1876 u16 version; 1877 u8 sub_version; 1878 u8 sub_index; 1879 u16 h2c_version; 1880 u32 feature; 1881 u32 feature_ext; 1882 enum rtw_fw_type type; 1883 }; 1884 1885 enum rtw_sar_sources { 1886 RTW_SAR_SOURCE_NONE, 1887 RTW_SAR_SOURCE_COMMON, 1888 }; 1889 1890 enum rtw_sar_bands { 1891 RTW_SAR_BAND_0, 1892 RTW_SAR_BAND_1, 1893 /* RTW_SAR_BAND_2, not used now */ 1894 RTW_SAR_BAND_3, 1895 RTW_SAR_BAND_4, 1896 1897 RTW_SAR_BAND_NR, 1898 }; 1899 1900 /* the union is reserved for other kinds of SAR sources 1901 * which might not re-use same format with array common. 1902 */ 1903 union rtw_sar_cfg { 1904 s8 common[RTW_SAR_BAND_NR]; 1905 }; 1906 1907 struct rtw_sar { 1908 enum rtw_sar_sources src; 1909 union rtw_sar_cfg cfg[RTW_RF_PATH_MAX][RTW_RATE_SECTION_MAX]; 1910 }; 1911 1912 struct rtw_hal { 1913 u32 rcr; 1914 1915 u32 chip_version; 1916 u8 cut_version; 1917 u8 mp_chip; 1918 u8 oem_id; 1919 u8 pkg_type; 1920 struct rtw_phy_cond phy_cond; 1921 bool rfe_btg; 1922 1923 u8 ps_mode; 1924 u8 current_channel; 1925 u8 current_primary_channel_index; 1926 u8 current_band_width; 1927 u8 current_band_type; 1928 u8 primary_channel; 1929 1930 /* center channel for different available bandwidth, 1931 * val of (bw > current_band_width) is invalid 1932 */ 1933 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 1934 1935 u8 sec_ch_offset; 1936 u8 rf_type; 1937 u8 rf_path_num; 1938 u8 rf_phy_num; 1939 u32 antenna_tx; 1940 u32 antenna_rx; 1941 u8 bfee_sts_cap; 1942 bool txrx_1ss; 1943 1944 /* protect tx power section */ 1945 struct mutex tx_power_mutex; 1946 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX] 1947 [DESC_RATE_MAX]; 1948 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX] 1949 [DESC_RATE_MAX]; 1950 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX] 1951 [RTW_RATE_SECTION_MAX]; 1952 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX] 1953 [RTW_RATE_SECTION_MAX]; 1954 s8 tx_pwr_limit_2g[RTW_REGD_MAX] 1955 [RTW_CHANNEL_WIDTH_MAX] 1956 [RTW_RATE_SECTION_MAX] 1957 [RTW_MAX_CHANNEL_NUM_2G]; 1958 s8 tx_pwr_limit_5g[RTW_REGD_MAX] 1959 [RTW_CHANNEL_WIDTH_MAX] 1960 [RTW_RATE_SECTION_MAX] 1961 [RTW_MAX_CHANNEL_NUM_5G]; 1962 s8 tx_pwr_tbl[RTW_RF_PATH_MAX] 1963 [DESC_RATE_MAX]; 1964 1965 enum rtw_sar_bands sar_band; 1966 struct rtw_sar sar; 1967 1968 /* for 8821c set channel */ 1969 u32 ch_param[3]; 1970 }; 1971 1972 struct rtw_path_div { 1973 enum rtw_bb_path current_tx_path; 1974 u32 path_a_sum; 1975 u32 path_b_sum; 1976 u16 path_a_cnt; 1977 u16 path_b_cnt; 1978 }; 1979 1980 struct rtw_chan_info { 1981 int pri_ch_idx; 1982 int action_id; 1983 int bw; 1984 u8 extra_info; 1985 u8 channel; 1986 u16 timeout; 1987 }; 1988 1989 struct rtw_chan_list { 1990 u32 buf_size; 1991 u32 ch_num; 1992 u32 size; 1993 u16 addr; 1994 }; 1995 1996 struct rtw_hw_scan_info { 1997 struct ieee80211_vif *scanning_vif; 1998 u8 probe_pg_size; 1999 u8 op_pri_ch_idx; 2000 u8 op_pri_ch; 2001 u8 op_chan; 2002 u8 op_bw; 2003 }; 2004 2005 struct rtw_dev { 2006 struct ieee80211_hw *hw; 2007 struct device *dev; 2008 2009 struct rtw_hci hci; 2010 2011 struct rtw_hw_scan_info scan_info; 2012 const struct rtw_chip_info *chip; 2013 struct rtw_hal hal; 2014 struct rtw_fifo_conf fifo; 2015 struct rtw_fw_state fw; 2016 struct rtw_efuse efuse; 2017 struct rtw_sec_desc sec; 2018 struct rtw_traffic_stats stats; 2019 struct rtw_regd regd; 2020 struct rtw_bf_info bf_info; 2021 2022 struct rtw_dm_info dm_info; 2023 struct rtw_coex coex; 2024 2025 /* ensures exclusive access from mac80211 callbacks */ 2026 struct mutex mutex; 2027 2028 /* watch dog every 2 sec */ 2029 struct delayed_work watch_dog_work; 2030 u32 watch_dog_cnt; 2031 2032 struct list_head rsvd_page_list; 2033 2034 /* c2h cmd queue & handler work */ 2035 struct sk_buff_head c2h_queue; 2036 struct work_struct c2h_work; 2037 struct work_struct ips_work; 2038 struct work_struct fw_recovery_work; 2039 struct work_struct update_beacon_work; 2040 2041 /* used to protect txqs list */ 2042 spinlock_t txq_lock; 2043 struct list_head txqs; 2044 struct workqueue_struct *tx_wq; 2045 struct work_struct tx_work; 2046 struct work_struct ba_work; 2047 2048 struct rtw_tx_report tx_report; 2049 2050 struct { 2051 /* indicate the mail box to use with fw */ 2052 u8 last_box_num; 2053 u32 seq; 2054 } h2c; 2055 2056 /* lps power state & handler work */ 2057 struct rtw_lps_conf lps_conf; 2058 bool ps_enabled; 2059 bool beacon_loss; 2060 struct completion lps_leave_check; 2061 2062 struct dentry *debugfs; 2063 2064 u8 sta_cnt; 2065 u32 rts_threshold; 2066 2067 DECLARE_BITMAP(hw_port, RTW_PORT_NUM); 2068 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM); 2069 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS); 2070 2071 u8 mp_mode; 2072 struct rtw_path_div dm_path_div; 2073 2074 struct rtw_fw_state wow_fw; 2075 struct rtw_wow_param wow; 2076 2077 bool need_rfk; 2078 struct completion fw_scan_density; 2079 bool ap_active; 2080 2081 /* hci related data, must be last */ 2082 u8 priv[] __aligned(sizeof(void *)); 2083 }; 2084 2085 #include "hci.h" 2086 2087 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev) 2088 { 2089 return !!rtwdev->sta_cnt; 2090 } 2091 2092 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq) 2093 { 2094 void *p = rtwtxq; 2095 2096 return container_of(p, struct ieee80211_txq, drv_priv); 2097 } 2098 2099 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif) 2100 { 2101 void *p = rtwvif; 2102 2103 return container_of(p, struct ieee80211_vif, drv_priv); 2104 } 2105 2106 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev) 2107 { 2108 if (rtwdev->chip->ops->efuse_grant) 2109 rtwdev->chip->ops->efuse_grant(rtwdev, true); 2110 } 2111 2112 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev) 2113 { 2114 if (rtwdev->chip->ops->efuse_grant) 2115 rtwdev->chip->ops->efuse_grant(rtwdev, false); 2116 } 2117 2118 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev) 2119 { 2120 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N; 2121 } 2122 2123 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev) 2124 { 2125 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC; 2126 } 2127 2128 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev) 2129 { 2130 return rtwdev->chip->rx_ldpc; 2131 } 2132 2133 static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev) 2134 { 2135 return rtwdev->chip->tx_stbc; 2136 } 2137 2138 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id) 2139 { 2140 clear_bit(mac_id, rtwdev->mac_id_map); 2141 } 2142 2143 static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev) 2144 { 2145 if (rtwdev->chip->ops->dump_fw_crash) 2146 return rtwdev->chip->ops->dump_fw_crash(rtwdev); 2147 2148 return 0; 2149 } 2150 2151 static inline 2152 enum nl80211_band rtw_hw_to_nl80211_band(enum rtw_supported_band hw_band) 2153 { 2154 switch (hw_band) { 2155 default: 2156 case RTW_BAND_2G: 2157 return NL80211_BAND_2GHZ; 2158 case RTW_BAND_5G: 2159 return NL80211_BAND_5GHZ; 2160 case RTW_BAND_60G: 2161 return NL80211_BAND_60GHZ; 2162 } 2163 } 2164 2165 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel); 2166 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period); 2167 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 2168 struct rtw_channel_params *ch_param); 2169 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); 2170 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); 2171 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value); 2172 void rtw_restore_reg(struct rtw_dev *rtwdev, 2173 struct rtw_backup_info *bckp, u32 num); 2174 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss); 2175 void rtw_set_channel(struct rtw_dev *rtwdev); 2176 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev); 2177 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 2178 u32 config); 2179 void rtw_tx_report_purge_timer(struct timer_list *t); 2180 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 2181 bool reset_ra_mask); 2182 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 2183 const u8 *mac_addr, bool hw_scan); 2184 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 2185 bool hw_scan); 2186 int rtw_core_start(struct rtw_dev *rtwdev); 2187 void rtw_core_stop(struct rtw_dev *rtwdev); 2188 int rtw_chip_info_setup(struct rtw_dev *rtwdev); 2189 int rtw_core_init(struct rtw_dev *rtwdev); 2190 void rtw_core_deinit(struct rtw_dev *rtwdev); 2191 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 2192 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 2193 u16 rtw_desc_to_bitrate(u8 desc_rate); 2194 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 2195 struct ieee80211_bss_conf *conf); 2196 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 2197 struct ieee80211_vif *vif); 2198 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 2199 bool fw_exist); 2200 void rtw_fw_recovery(struct rtw_dev *rtwdev); 2201 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start); 2202 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 2203 u32 fwcd_item); 2204 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size); 2205 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool config_1ss); 2206 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel, 2207 u8 primary_channel, enum rtw_supported_band band, 2208 enum rtw_bandwidth bandwidth); 2209 void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif); 2210 bool rtw_core_check_sta_active(struct rtw_dev *rtwdev); 2211 void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable); 2212 #if defined(__linux__) 2213 #define rtw88_static_assert(_x) static_assert(_x) 2214 #elif defined(__FreeBSD__) 2215 #define rtw88_static_assert(_x) _Static_assert(_x, "bad array size") 2216 #endif 2217 2218 #endif 2219