1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_TXRX_H__ 6 #define __RTW89_TXRX_H__ 7 8 #include "debug.h" 9 10 #define DATA_RATE_MODE_CTRL_MASK GENMASK(8, 7) 11 #define DATA_RATE_MODE_CTRL_MASK_V1 GENMASK(10, 8) 12 #define DATA_RATE_NOT_HT_IDX_MASK GENMASK(3, 0) 13 #define DATA_RATE_MODE_NON_HT 0x0 14 #define DATA_RATE_HT_IDX_MASK GENMASK(4, 0) 15 #define DATA_RATE_HT_IDX_MASK_V1 GENMASK(4, 0) 16 #define DATA_RATE_MODE_HT 0x1 17 #define DATA_RATE_VHT_HE_NSS_MASK GENMASK(6, 4) 18 #define DATA_RATE_VHT_HE_IDX_MASK GENMASK(3, 0) 19 #define DATA_RATE_NSS_MASK_V1 GENMASK(7, 5) 20 #define DATA_RATE_MCS_MASK_V1 GENMASK(4, 0) 21 #define DATA_RATE_MODE_VHT 0x2 22 #define DATA_RATE_MODE_HE 0x3 23 #define DATA_RATE_MODE_EHT 0x4 24 25 static inline u8 rtw89_get_data_rate_mode(struct rtw89_dev *rtwdev, u16 hw_rate) 26 { 27 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 28 return u16_get_bits(hw_rate, DATA_RATE_MODE_CTRL_MASK_V1); 29 30 return u16_get_bits(hw_rate, DATA_RATE_MODE_CTRL_MASK); 31 } 32 33 static inline u8 rtw89_get_data_not_ht_idx(struct rtw89_dev *rtwdev, u16 hw_rate) 34 { 35 return u16_get_bits(hw_rate, DATA_RATE_NOT_HT_IDX_MASK); 36 } 37 38 static inline u8 rtw89_get_data_ht_mcs(struct rtw89_dev *rtwdev, u16 hw_rate) 39 { 40 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 41 return u16_get_bits(hw_rate, DATA_RATE_HT_IDX_MASK_V1); 42 43 return u16_get_bits(hw_rate, DATA_RATE_HT_IDX_MASK); 44 } 45 46 static inline u8 rtw89_get_data_mcs(struct rtw89_dev *rtwdev, u16 hw_rate) 47 { 48 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 49 return u16_get_bits(hw_rate, DATA_RATE_MCS_MASK_V1); 50 51 return u16_get_bits(hw_rate, DATA_RATE_VHT_HE_IDX_MASK); 52 } 53 54 static inline u8 rtw89_get_data_nss(struct rtw89_dev *rtwdev, u16 hw_rate) 55 { 56 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 57 return u16_get_bits(hw_rate, DATA_RATE_NSS_MASK_V1); 58 59 return u16_get_bits(hw_rate, DATA_RATE_VHT_HE_NSS_MASK); 60 } 61 62 /* TX WD BODY DWORD 0 */ 63 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24) 64 #define RTW89_TXWD_BODY0_WP_OFFSET_V1 GENMASK(28, 24) 65 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23) 66 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22) 67 #define RTW89_TXWD_BODY0_FW_DL BIT(20) 68 #define RTW89_TXWD_BODY0_CHANNEL_DMA GENMASK(19, 16) 69 #define RTW89_TXWD_BODY0_HDR_LLC_LEN GENMASK(15, 11) 70 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7) 71 #define RTW89_TXWD_BODY0_HW_AMSDU BIT(5) 72 #define RTW89_TXWD_BODY0_HW_SSN_SEL GENMASK(3, 2) 73 #define RTW89_TXWD_BODY0_HW_SSN_MODE GENMASK(1, 0) 74 75 /* TX WD BODY DWORD 1 */ 76 #define RTW89_TXWD_BODY1_ADDR_INFO_NUM GENMASK(31, 26) 77 #define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16) 78 #define RTW89_TXWD_BODY1_SEC_KEYID GENMASK(5, 4) 79 #define RTW89_TXWD_BODY1_SEC_TYPE GENMASK(3, 0) 80 81 /* TX WD BODY DWORD 2 */ 82 #define RTW89_TXWD_BODY2_MACID GENMASK(30, 24) 83 #define RTW89_TXWD_BODY2_TID_INDICATE BIT(23) 84 #define RTW89_TXWD_BODY2_QSEL GENMASK(22, 17) 85 #define RTW89_TXWD_BODY2_TXPKT_SIZE GENMASK(13, 0) 86 87 /* TX WD BODY DWORD 3 */ 88 #define RTW89_TXWD_BODY3_BK BIT(13) 89 #define RTW89_TXWD_BODY3_AGG_EN BIT(12) 90 #define RTW89_TXWD_BODY3_SW_SEQ GENMASK(11, 0) 91 92 /* TX WD BODY DWORD 4 */ 93 #define RTW89_TXWD_BODY4_SEC_IV_L1 GENMASK(31, 24) 94 #define RTW89_TXWD_BODY4_SEC_IV_L0 GENMASK(23, 16) 95 96 /* TX WD BODY DWORD 5 */ 97 #define RTW89_TXWD_BODY5_SEC_IV_H5 GENMASK(31, 24) 98 #define RTW89_TXWD_BODY5_SEC_IV_H4 GENMASK(23, 16) 99 #define RTW89_TXWD_BODY5_SEC_IV_H3 GENMASK(15, 8) 100 #define RTW89_TXWD_BODY5_SEC_IV_H2 GENMASK(7, 0) 101 102 /* TX WD BODY DWORD 6 (V1) */ 103 104 /* TX WD BODY DWORD 7 (V1) */ 105 #define RTW89_TXWD_BODY7_USE_RATE_V1 BIT(31) 106 #define RTW89_TXWD_BODY7_DATA_BW GENMASK(29, 28) 107 #define RTW89_TXWD_BODY7_GI_LTF GENMASK(27, 25) 108 #define RTW89_TXWD_BODY7_DATA_RATE GENMASK(24, 16) 109 110 /* TX WD INFO DWORD 0 */ 111 #define RTW89_TXWD_INFO0_USE_RATE BIT(30) 112 #define RTW89_TXWD_INFO0_DATA_BW GENMASK(29, 28) 113 #define RTW89_TXWD_INFO0_GI_LTF GENMASK(27, 25) 114 #define RTW89_TXWD_INFO0_DATA_RATE GENMASK(24, 16) 115 #define RTW89_TXWD_INFO0_DATA_ER BIT(15) 116 #define RTW89_TXWD_INFO0_DATA_STBC BIT(12) 117 #define RTW89_TXWD_INFO0_DATA_LDPC BIT(11) 118 #define RTW89_TXWD_INFO0_DISDATAFB BIT(10) 119 #define RTW89_TXWD_INFO0_DATA_BW_ER BIT(8) 120 #define RTW89_TXWD_INFO0_MULTIPORT_ID GENMASK(6, 4) 121 122 /* TX WD INFO DWORD 1 */ 123 #define RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(24, 16) 124 #define RTW89_TXWD_INFO1_A_CTRL_BSR BIT(14) 125 #define RTW89_TXWD_INFO1_MAX_AGGNUM GENMASK(7, 0) 126 127 /* TX WD INFO DWORD 2 */ 128 #define RTW89_TXWD_INFO2_AMPDU_DENSITY GENMASK(20, 18) 129 #define RTW89_TXWD_INFO2_SEC_TYPE GENMASK(12, 9) 130 #define RTW89_TXWD_INFO2_SEC_HW_ENC BIT(8) 131 #define RTW89_TXWD_INFO2_FORCE_KEY_EN BIT(8) 132 #define RTW89_TXWD_INFO2_SEC_CAM_IDX GENMASK(7, 0) 133 134 /* TX WD INFO DWORD 3 */ 135 136 /* TX WD INFO DWORD 4 */ 137 #define RTW89_TXWD_INFO4_RTS_EN BIT(27) 138 #define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31) 139 140 /* TX WD INFO DWORD 5 */ 141 142 /* TX WD BODY DWORD 0 */ 143 #define BE_TXD_BODY0_EN_HWSEQ_MODE GENMASK(1, 0) 144 #define BE_TXD_BODY0_HW_SSN_SEL GENMASK(4, 2) 145 #define BE_TXD_BODY0_HWAMSDU BIT(5) 146 #define BE_TXD_BODY0_HW_SEC_IV BIT(6) 147 #define BE_TXD_BODY0_WD_PAGE BIT(7) 148 #define BE_TXD_BODY0_CHK_EN BIT(8) 149 #define BE_TXD_BODY0_WP_INT BIT(9) 150 #define BE_TXD_BODY0_STF_MODE BIT(10) 151 #define BE_TXD_BODY0_HDR_LLC_LEN GENMASK(15, 11) 152 #define BE_TXD_BODY0_CH_DMA GENMASK(19, 16) 153 #define BE_TXD_BODY0_SMH_EN BIT(20) 154 #define BE_TXD_BODY0_PKT_OFFSET BIT(21) 155 #define BE_TXD_BODY0_WDINFO_EN BIT(22) 156 #define BE_TXD_BODY0_MOREDATA BIT(23) 157 #define BE_TXD_BODY0_WP_OFFSET_V1 GENMASK(27, 24) 158 #define BE_TXD_BODY0_AZ_FTM_SEC_V1 BIT(28) 159 #define BE_TXD_BODY0_WD_SOURCE GENMASK(30, 29) 160 #define BE_TXD_BODY0_HCI_SEQNUM_MODE BIT(31) 161 162 /* TX WD BODY DWORD 1 */ 163 #define BE_TXD_BODY1_DMA_TXAGG_NUM GENMASK(6, 0) 164 #define BE_TXD_BODY1_REUSE_NUM GENMASK(11, 7) 165 #define BE_TXD_BODY1_SEC_TYPE GENMASK(15, 12) 166 #define BE_TXD_BODY1_SEC_KEYID GENMASK(17, 16) 167 #define BE_TXD_BODY1_SW_SEC_IV BIT(18) 168 #define BE_TXD_BODY1_REUSE_SIZE GENMASK(23, 20) 169 #define BE_TXD_BODY1_REUSE_START_OFFSET GENMASK(25, 24) 170 #define BE_TXD_BODY1_ADDR_INFO_NUM GENMASK(31, 26) 171 172 /* TX WD BODY DWORD 2 */ 173 #define BE_TXD_BODY2_TXPKTSIZE GENMASK(13, 0) 174 #define BE_TXD_BODY2_AGG_EN BIT(14) 175 #define BE_TXD_BODY2_BK BIT(15) 176 #define BE_TXD_BODY2_MACID_EXTEND BIT(16) 177 #define BE_TXD_BODY2_QSEL GENMASK(22, 17) 178 #define BE_TXD_BODY2_TID_IND BIT(23) 179 #define BE_TXD_BODY2_MACID GENMASK(31, 24) 180 181 /* TX WD BODY DWORD 3 */ 182 #define BE_TXD_BODY3_WIFI_SEQ GENMASK(11, 0) 183 #define BE_TXD_BODY3_MLO_FLAG BIT(12) 184 #define BE_TXD_BODY3_IS_MLD_SW_EN BIT(13) 185 #define BE_TXD_BODY3_TRY_RATE BIT(14) 186 #define BE_TXD_BODY3_RELINK_FLAG_V1 BIT(15) 187 #define BE_TXD_BODY3_BAND0_SU_TC_V1 GENMASK(21, 16) 188 #define BE_TXD_BODY3_TOTAL_TC GENMASK(27, 22) 189 #define BE_TXD_BODY3_RU_RTY BIT(28) 190 #define BE_TXD_BODY3_MU_PRI_RTY BIT(29) 191 #define BE_TXD_BODY3_MU_2ND_RTY BIT(30) 192 #define BE_TXD_BODY3_BAND1_SU_RTY_V1 BIT(31) 193 194 /* TX WD BODY DWORD 4 */ 195 #define BE_TXD_BODY4_TXDESC_CHECKSUM GENMASK(15, 0) 196 #define BE_TXD_BODY4_SEC_IV_L0 GENMASK(23, 16) 197 #define BE_TXD_BODY4_SEC_IV_L1 GENMASK(31, 24) 198 199 /* TX WD BODY DWORD 5 */ 200 #define BE_TXD_BODY5_SEC_IV_H2 GENMASK(7, 0) 201 #define BE_TXD_BODY5_SEC_IV_H3 GENMASK(15, 8) 202 #define BE_TXD_BODY5_SEC_IV_H4 GENMASK(23, 16) 203 #define BE_TXD_BODY5_SEC_IV_H5 GENMASK(31, 24) 204 205 /* TX WD BODY DWORD 6 */ 206 #define BE_TXD_BODY6_MU_TC GENMASK(4, 0) 207 #define BE_TXD_BODY6_RU_TC GENMASK(9, 5) 208 #define BE_TXD_BODY6_PS160 BIT(10) 209 #define BE_TXD_BODY6_BMC BIT(11) 210 #define BE_TXD_BODY6_NO_ACK BIT(12) 211 #define BE_TXD_BODY6_UPD_WLAN_HDR BIT(13) 212 #define BE_TXD_BODY6_A4_HDR BIT(14) 213 #define BE_TXD_BODY6_EOSP_BIT BIT(15) 214 #define BE_TXD_BODY6_S_IDX GENMASK(23, 16) 215 #define BE_TXD_BODY6_RU_POS GENMASK(31, 24) 216 217 /* TX WD BODY DWORD 7 */ 218 #define BE_TXD_BODY7_RTS_TC GENMASK(5, 0) 219 #define BE_TXD_BODY7_MSDU_NUM GENMASK(9, 6) 220 #define BE_TXD_BODY7_DATA_ER BIT(10) 221 #define BE_TXD_BODY7_DATA_BW_ER BIT(11) 222 #define BE_TXD_BODY7_DATA_DCM BIT(12) 223 #define BE_TXD_BODY7_GI_LTF GENMASK(15, 13) 224 #define BE_TXD_BODY7_DATARATE GENMASK(27, 16) 225 #define BE_TXD_BODY7_DATA_BW GENMASK(30, 28) 226 #define BE_TXD_BODY7_USERATE_SEL BIT(31) 227 228 /* TX WD INFO DWORD 0 */ 229 #define BE_TXD_INFO0_MBSSID GENMASK(3, 0) 230 #define BE_TXD_INFO0_MULTIPORT_ID GENMASK(6, 4) 231 #define BE_TXD_INFO0_DISRTSFB BIT(9) 232 #define BE_TXD_INFO0_DISDATAFB BIT(10) 233 #define BE_TXD_INFO0_DATA_LDPC BIT(11) 234 #define BE_TXD_INFO0_DATA_STBC BIT(12) 235 #define BE_TXD_INFO0_DATA_TXCNT_LMT GENMASK(21, 16) 236 #define BE_TXD_INFO0_DATA_TXCNT_LMT_SEL BIT(22) 237 #define BE_TXD_INFO0_RESP_PHYSTS_CSI_EN_V1 BIT(23) 238 #define BE_TXD_INFO0_RLS_TO_CPUIO BIT(30) 239 #define BE_TXD_INFO0_ACK_CH_INFO BIT(31) 240 241 /* TX WD INFO DWORD 1 */ 242 #define BE_TXD_INFO1_MAX_AGG_NUM GENMASK(7, 0) 243 #define BE_TXD_INFO1_BCN_SRCH_SEQ GENMASK(9, 8) 244 #define BE_TXD_INFO1_NAVUSEHDR BIT(10) 245 #define BE_TXD_INFO1_A_CTRL_BQR BIT(12) 246 #define BE_TXD_INFO1_A_CTRL_BSR BIT(14) 247 #define BE_TXD_INFO1_A_CTRL_CAS BIT(15) 248 #define BE_TXD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(27, 16) 249 #define BE_TXD_INFO1_SW_DEFINE GENMASK(31, 28) 250 251 /* TX WD INFO DWORD 2 */ 252 #define BE_TXD_INFO2_SEC_CAM_IDX GENMASK(7, 0) 253 #define BE_TXD_INFO2_FORCE_KEY_EN BIT(8) 254 #define BE_TXD_INFO2_LIFETIME_SEL GENMASK(15, 13) 255 #define BE_TXD_INFO2_FORCE_TXOP BIT(17) 256 #define BE_TXD_INFO2_AMPDU_DENSITY GENMASK(20, 18) 257 #define BE_TXD_INFO2_LSIG_TXOP_EN BIT(21) 258 #define BE_TXD_INFO2_OBW_CTS2SELF_DUP_TYPE GENMASK(29, 26) 259 #define BE_TXD_INFO2_SPE_RPT_V1 BIT(30) 260 #define BE_TXD_INFO2_SIFS_TX_V1 BIT(31) 261 262 /* TX WD INFO DWORD 3 */ 263 #define BE_TXD_INFO3_SPE_PKT GENMASK(3, 0) 264 #define BE_TXD_INFO3_SPE_PKT_TYPE GENMASK(7, 4) 265 #define BE_TXD_INFO3_CQI_SND BIT(8) 266 #define BE_TXD_INFO3_RTT_EN BIT(9) 267 #define BE_TXD_INFO3_HT_DATA_SND_V1 BIT(10) 268 #define BE_TXD_INFO3_BT_NULL BIT(11) 269 #define BE_TXD_INFO3_TRI_FRAME BIT(12) 270 #define BE_TXD_INFO3_NULL_0 BIT(13) 271 #define BE_TXD_INFO3_NULL_1 BIT(14) 272 #define BE_TXD_INFO3_RAW BIT(15) 273 #define BE_TXD_INFO3_GROUP_BIT_IE_OFFSET GENMASK(23, 16) 274 #define BE_TXD_INFO3_SIGNALING_TA_PKT_EN BIT(25) 275 #define BE_TXD_INFO3_BCNPKT_TSF_CTRL BIT(26) 276 #define BE_TXD_INFO3_SIGNALING_TA_PKT_SC GENMASK(30, 27) 277 #define BE_TXD_INFO3_FORCE_BSS_CLR BIT(31) 278 279 /* TX WD INFO DWORD 4 */ 280 #define BE_TXD_INFO4_PUNCTURE_PATTERN GENMASK(15, 0) 281 #define BE_TXD_INFO4_PUNC_MODE GENMASK(17, 16) 282 #define BE_TXD_INFO4_SW_TX_OK_0 BIT(18) 283 #define BE_TXD_INFO4_SW_TX_OK_1 BIT(19) 284 #define BE_TXD_INFO4_SW_TX_PWR_DBM GENMASK(26, 23) 285 #define BE_TXD_INFO4_RTS_EN BIT(27) 286 #define BE_TXD_INFO4_CTS2SELF BIT(28) 287 #define BE_TXD_INFO4_CCA_RTS GENMASK(30, 29) 288 #define BE_TXD_INFO4_HW_RTS_EN BIT(31) 289 290 /* TX WD INFO DWORD 5 */ 291 #define BE_TXD_INFO5_SR_RATE_V1 GENMASK(4, 0) 292 #define BE_TXD_INFO5_SR_EN_V1 BIT(5) 293 #define BE_TXD_INFO5_NDPA_DURATION GENMASK(31, 16) 294 295 /* TX WD INFO DWORD 6 */ 296 #define BE_TXD_INFO6_UL_APEP_LEN GENMASK(11, 0) 297 #define BE_TXD_INFO6_UL_GI_LTF GENMASK(14, 12) 298 #define BE_TXD_INFO6_UL_DOPPLER BIT(15) 299 #define BE_TXD_INFO6_UL_STBC BIT(16) 300 #define BE_TXD_INFO6_UL_LENGTH_REF GENMASK(21, 18) 301 #define BE_TXD_INFO6_UL_RF_GAIN_IDX GENMASK(31, 22) 302 303 /* TX WD INFO DWORD 7 */ 304 #define BE_TXD_INFO7_UL_FIXED_GAIN_EN BIT(0) 305 #define BE_TXD_INFO7_UL_PRI_EXP_RSSI_DBM GENMASK(7, 1) 306 #define BE_TXD_INFO7_ELNA_IDX BIT(8) 307 #define BE_TXD_INFO7_UL_APEP_UNIT GENMASK(10, 9) 308 #define BE_TXD_INFO7_UL_TRI_PAD GENMASK(13, 11) 309 #define BE_TXD_INFO7_UL_T_PE GENMASK(15, 14) 310 #define BE_TXD_INFO7_UL_EHT_USR_PRES BIT(16) 311 #define BE_TXD_INFO7_UL_HELTF_SYMBOL_NUM GENMASK(19, 17) 312 #define BE_TXD_INFO7_ULBW GENMASK(21, 20) 313 #define BE_TXD_INFO7_ULBW_EXT GENMASK(23, 22) 314 #define BE_TXD_INFO7_USE_WD_UL GENMASK(25, 24) 315 #define BE_TXD_INFO7_EXTEND_MODE_SEL GENMASK(31, 28) 316 317 /* RX WD dword0 */ 318 #define AX_RXD_RPKT_LEN_MASK GENMASK(13, 0) 319 #define AX_RXD_SHIFT_MASK GENMASK(15, 14) 320 #define AX_RXD_WL_HD_IV_LEN_MASK GENMASK(21, 16) 321 #define AX_RXD_BB_SEL BIT(22) 322 #define AX_RXD_MAC_INFO_VLD BIT(23) 323 #define AX_RXD_RPKT_TYPE_MASK GENMASK(27, 24) 324 #define AX_RXD_DRV_INFO_SIZE_MASK GENMASK(30, 28) 325 #define AX_RXD_LONG_RXD BIT(31) 326 327 /* RX WD dword1 */ 328 #define AX_RXD_PPDU_TYPE_MASK GENMASK(3, 0) 329 #define AX_RXD_PPDU_CNT_MASK GENMASK(6, 4) 330 #define AX_RXD_SR_EN BIT(7) 331 #define AX_RXD_USER_ID_MASK GENMASK(15, 8) 332 #define AX_RXD_USER_ID_v1_MASK GENMASK(13, 8) 333 #define AX_RXD_RX_DATARATE_MASK GENMASK(24, 16) 334 #define AX_RXD_RX_GI_LTF_MASK GENMASK(27, 25) 335 #define AX_RXD_NON_SRG_PPDU BIT(28) 336 #define AX_RXD_INTER_PPDU BIT(29) 337 #define AX_RXD_NON_SRG_PPDU_v1 BIT(14) 338 #define AX_RXD_INTER_PPDU_v1 BIT(15) 339 #define AX_RXD_BW_MASK GENMASK(31, 30) 340 #define AX_RXD_BW_v1_MASK GENMASK(31, 29) 341 342 /* RX WD dword2 */ 343 #define AX_RXD_FREERUN_CNT_MASK GENMASK(31, 0) 344 345 /* RX WD dword3 */ 346 #define AX_RXD_A1_MATCH BIT(0) 347 #define AX_RXD_SW_DEC BIT(1) 348 #define AX_RXD_HW_DEC BIT(2) 349 #define AX_RXD_AMPDU BIT(3) 350 #define AX_RXD_AMPDU_END_PKT BIT(4) 351 #define AX_RXD_AMSDU BIT(5) 352 #define AX_RXD_AMSDU_CUT BIT(6) 353 #define AX_RXD_LAST_MSDU BIT(7) 354 #define AX_RXD_BYPASS BIT(8) 355 #define AX_RXD_CRC32_ERR BIT(9) 356 #define AX_RXD_ICV_ERR BIT(10) 357 #define AX_RXD_MAGIC_WAKE BIT(11) 358 #define AX_RXD_UNICAST_WAKE BIT(12) 359 #define AX_RXD_PATTERN_WAKE BIT(13) 360 #define AX_RXD_GET_CH_INFO_MASK GENMASK(15, 14) 361 #define AX_RXD_PATTERN_IDX_MASK GENMASK(20, 16) 362 #define AX_RXD_TARGET_IDC_MASK GENMASK(23, 21) 363 #define AX_RXD_CHKSUM_OFFLOAD_EN BIT(24) 364 #define AX_RXD_WITH_LLC BIT(25) 365 #define AX_RXD_RX_STATISTICS BIT(26) 366 367 /* RX WD dword4 */ 368 #define AX_RXD_TYPE_MASK GENMASK(1, 0) 369 #define AX_RXD_MC BIT(2) 370 #define AX_RXD_BC BIT(3) 371 #define AX_RXD_MD BIT(4) 372 #define AX_RXD_MF BIT(5) 373 #define AX_RXD_PWR BIT(6) 374 #define AX_RXD_QOS BIT(7) 375 #define AX_RXD_TID_MASK GENMASK(11, 8) 376 #define AX_RXD_EOSP BIT(12) 377 #define AX_RXD_HTC BIT(13) 378 #define AX_RXD_QNULL BIT(14) 379 #define AX_RXD_SEQ_MASK GENMASK(27, 16) 380 #define AX_RXD_FRAG_MASK GENMASK(31, 28) 381 382 /* RX WD dword5 */ 383 #define AX_RXD_SEC_CAM_IDX_MASK GENMASK(7, 0) 384 #define AX_RXD_ADDR_CAM_MASK GENMASK(15, 8) 385 #define AX_RXD_MAC_ID_MASK GENMASK(23, 16) 386 #define AX_RXD_RX_PL_ID_MASK GENMASK(27, 24) 387 #define AX_RXD_ADDR_CAM_VLD BIT(28) 388 #define AX_RXD_ADDR_FWD_EN BIT(29) 389 #define AX_RXD_RX_PL_MATCH BIT(30) 390 391 /* RX WD dword6 */ 392 #define AX_RXD_MAC_ADDR_MASK GENMASK(31, 0) 393 394 /* RX WD dword7 */ 395 #define AX_RXD_MAC_ADDR_H_MASK GENMASK(15, 0) 396 #define AX_RXD_SMART_ANT BIT(16) 397 #define AX_RXD_SEC_TYPE_MASK GENMASK(20, 17) 398 #define AX_RXD_HDR_CNV BIT(21) 399 #define AX_RXD_HDR_OFFSET_MASK GENMASK(26, 22) 400 #define AX_RXD_BIP_KEYID BIT(27) 401 #define AX_RXD_BIP_ENC BIT(28) 402 403 struct rtw89_rxinfo_user { 404 __le32 w0; 405 }; 406 407 #define RTW89_RXINFO_USER_MAC_ID_VALID BIT(0) 408 #define RTW89_RXINFO_USER_DATA BIT(1) 409 #define RTW89_RXINFO_USER_CTRL BIT(2) 410 #define RTW89_RXINFO_USER_MGMT BIT(3) 411 #define RTW89_RXINFO_USER_BCM BIT(4) 412 #define RTW89_RXINFO_USER_MACID GENMASK(15, 8) 413 414 struct rtw89_rxinfo { 415 __le32 w0; 416 __le32 w1; 417 struct rtw89_rxinfo_user user[]; 418 } __packed; 419 420 #define RTW89_RXINFO_W0_USR_NUM GENMASK(3, 0) 421 #define RTW89_RXINFO_W0_USR_NUM_V1 GENMASK(4, 0) 422 #define RTW89_RXINFO_W0_FW_DEFINE GENMASK(15, 8) 423 #define RTW89_RXINFO_W0_PLCP_LEN_V1 GENMASK(23, 16) 424 #define RTW89_RXINFO_W0_LSIG_LEN GENMASK(27, 16) 425 #define RTW89_RXINFO_W0_INVALID_V1 BIT(27) 426 #define RTW89_RXINFO_W0_IS_TO_SELF BIT(28) 427 #define RTW89_RXINFO_W0_RX_CNT_VLD BIT(29) 428 #define RTW89_RXINFO_W0_LONG_RXD GENMASK(31, 30) 429 #define RTW89_RXINFO_W1_SERVICE GENMASK(15, 0) 430 #define RTW89_RXINFO_W1_PLCP_LEN GENMASK(23, 16) 431 432 struct rtw89_phy_sts_hdr { 433 __le32 w0; 434 __le32 w1; 435 } __packed; 436 437 #define RTW89_PHY_STS_HDR_W0_IE_MAP GENMASK(4, 0) 438 #define RTW89_PHY_STS_HDR_W0_VALID BIT(7) 439 #define RTW89_PHY_STS_HDR_W0_LEN GENMASK(15, 8) 440 #define RTW89_PHY_STS_HDR_W0_RSSI_AVG GENMASK(31, 24) 441 #define RTW89_PHY_STS_HDR_W1_RSSI_A GENMASK(7, 0) 442 #define RTW89_PHY_STS_HDR_W1_RSSI_B GENMASK(15, 8) 443 #define RTW89_PHY_STS_HDR_W1_RSSI_C GENMASK(23, 16) 444 #define RTW89_PHY_STS_HDR_W1_RSSI_D GENMASK(31, 24) 445 446 struct rtw89_phy_sts_iehdr { 447 __le32 w0; 448 }; 449 450 #define RTW89_PHY_STS_IEHDR_TYPE GENMASK(4, 0) 451 #define RTW89_PHY_STS_IEHDR_LEN GENMASK(11, 5) 452 453 /* BE RXD dword0 */ 454 #define BE_RXD_RPKT_LEN_MASK GENMASK(13, 0) 455 #define BE_RXD_SHIFT_MASK GENMASK(15, 14) 456 #define BE_RXD_DRV_INFO_SZ_MASK GENMASK(19, 18) 457 #define BE_RXD_HDR_CNV_SZ_MASK GENMASK(21, 20) 458 #define BE_RXD_PHY_RPT_SZ_MASK GENMASK(23, 22) 459 #define BE_RXD_RPKT_TYPE_MASK GENMASK(29, 24) 460 #define BE_RXD_BB_SEL BIT(30) 461 #define BE_RXD_LONG_RXD BIT(31) 462 463 /* BE RXD dword1 */ 464 #define BE_RXD_PKT_ID_MASK GENMASK(11, 0) 465 #define BE_RXD_FWD_TARGET_MASK GENMASK(23, 16) 466 #define BE_RXD_BCN_FW_INFO_MASK GENMASK(25, 24) 467 #define BE_RXD_FW_RLS BIT(26) 468 469 /* BE RXD dword2 */ 470 #define BE_RXD_MAC_ID_MASK GENMASK(7, 0) 471 #define BE_RXD_TYPE_MASK GENMASK(11, 10) 472 #define BE_RXD_LAST_MSDU BIT(12) 473 #define BE_RXD_AMSDU_CUT BIT(13) 474 #define BE_RXD_ADDR_CAM_VLD BIT(14) 475 #define BE_RXD_REORDER BIT(15) 476 #define BE_RXD_SEQ_MASK GENMASK(27, 16) 477 #define BE_RXD_TID_MASK GENMASK(31, 28) 478 479 /* BE RXD dword3 */ 480 #define BE_RXD_SEC_TYPE_MASK GENMASK(3, 0) 481 #define BE_RXD_BIP_KEYID BIT(4) 482 #define BE_RXD_BIP_ENC BIT(5) 483 #define BE_RXD_CRC32_ERR BIT(6) 484 #define BE_RXD_ICV_ERR BIT(7) 485 #define BE_RXD_HW_DEC BIT(8) 486 #define BE_RXD_SW_DEC BIT(9) 487 #define BE_RXD_A1_MATCH BIT(10) 488 #define BE_RXD_AMPDU BIT(11) 489 #define BE_RXD_AMPDU_EOF BIT(12) 490 #define BE_RXD_AMSDU BIT(13) 491 #define BE_RXD_MC BIT(14) 492 #define BE_RXD_BC BIT(15) 493 #define BE_RXD_MD BIT(16) 494 #define BE_RXD_MF BIT(17) 495 #define BE_RXD_PWR BIT(18) 496 #define BE_RXD_QOS BIT(19) 497 #define BE_RXD_EOSP BIT(20) 498 #define BE_RXD_HTC BIT(21) 499 #define BE_RXD_QNULL BIT(22) 500 #define BE_RXD_A4_FRAME BIT(23) 501 #define BE_RXD_FRAG_MASK GENMASK(27, 24) 502 #define BE_RXD_GET_CH_INFO_V1_MASK GENMASK(31, 30) 503 504 /* BE RXD dword4 */ 505 #define BE_RXD_PPDU_TYPE_MASK GENMASK(7, 0) 506 #define BE_RXD_PPDU_CNT_MASK GENMASK(10, 8) 507 #define BE_RXD_BW_MASK GENMASK(14, 12) 508 #define BE_RXD_RX_GI_LTF_MASK GENMASK(18, 16) 509 #define BE_RXD_RX_REORDER_FIELD_EN BIT(19) 510 #define BE_RXD_RX_DATARATE_MASK GENMASK(31, 20) 511 512 /* BE RXD dword5 */ 513 #define BE_RXD_FREERUN_CNT_MASK GENMASK(31, 0) 514 515 /* BE RXD dword6 */ 516 #define BE_RXD_ADDR_CAM_MASK GENMASK(7, 0) 517 #define BE_RXD_SR_EN BIT(13) 518 #define BE_RXD_NON_SRG_PPDU BIT(14) 519 #define BE_RXD_INTER_PPDU BIT(15) 520 #define BE_RXD_USER_ID_MASK GENMASK(21, 16) 521 #define BE_RXD_RX_STATISTICS BIT(22) 522 #define BE_RXD_SMART_ANT BIT(23) 523 #define BE_RXD_SEC_CAM_IDX_MASK GENMASK(31, 24) 524 525 /* BE RXD dword7 */ 526 #define BE_RXD_PATTERN_IDX_MASK GENMASK(4, 0) 527 #define BE_RXD_MAGIC_WAKE BIT(5) 528 #define BE_RXD_UNICAST_WAKE BIT(6) 529 #define BE_RXD_PATTERN_WAKE BIT(7) 530 #define BE_RXD_RX_PL_MATCH BIT(8) 531 #define BE_RXD_RX_PL_ID_MASK GENMASK(15, 12) 532 #define BE_RXD_HDR_CNV BIT(16) 533 #define BE_RXD_NAT25_HIT BIT(17) 534 #define BE_RXD_IS_DA BIT(18) 535 #define BE_RXD_CHKSUM_OFFLOAD_EN BIT(19) 536 #define BE_RXD_RXSC_ENTRY_MASK GENMASK(22, 20) 537 #define BE_RXD_RXSC_HIT BIT(23) 538 #define BE_RXD_WITH_LLC BIT(24) 539 #define BE_RXD_RX_AGG_FIELD_EN BIT(25) 540 541 /* BE RXD dword8 */ 542 #define BE_RXD_MAC_ADDR_MASK GENMASK(31, 0) 543 544 /* BE RXD dword9 */ 545 #define BE_RXD_MAC_ADDR_H_MASK GENMASK(15, 0) 546 #define BE_RXD_HDR_OFFSET_MASK GENMASK(20, 16) 547 #define BE_RXD_WL_HD_IV_LEN_MASK GENMASK(26, 21) 548 549 struct rtw89_phy_sts_ie0 { 550 __le32 w0; 551 __le32 w1; 552 __le32 w2; 553 } __packed; 554 555 #define RTW89_PHY_STS_IE01_W0_CH_IDX GENMASK(23, 16) 556 #define RTW89_PHY_STS_IE01_W1_FD_CFO GENMASK(19, 8) 557 #define RTW89_PHY_STS_IE01_W1_PREMB_CFO GENMASK(31, 20) 558 #define RTW89_PHY_STS_IE01_W2_AVG_SNR GENMASK(5, 0) 559 #define RTW89_PHY_STS_IE01_W2_EVM_MAX GENMASK(15, 8) 560 #define RTW89_PHY_STS_IE01_W2_EVM_MIN GENMASK(23, 16) 561 #define RTW89_PHY_STS_IE01_W2_LDPC BIT(28) 562 #define RTW89_PHY_STS_IE01_W2_STBC BIT(30) 563 564 enum rtw89_tx_channel { 565 RTW89_TXCH_ACH0 = 0, 566 RTW89_TXCH_ACH1 = 1, 567 RTW89_TXCH_ACH2 = 2, 568 RTW89_TXCH_ACH3 = 3, 569 RTW89_TXCH_ACH4 = 4, 570 RTW89_TXCH_ACH5 = 5, 571 RTW89_TXCH_ACH6 = 6, 572 RTW89_TXCH_ACH7 = 7, 573 RTW89_TXCH_CH8 = 8, /* MGMT Band 0 */ 574 RTW89_TXCH_CH9 = 9, /* HI Band 0 */ 575 RTW89_TXCH_CH10 = 10, /* MGMT Band 1 */ 576 RTW89_TXCH_CH11 = 11, /* HI Band 1 */ 577 RTW89_TXCH_CH12 = 12, /* FW CMD */ 578 579 /* keep last */ 580 RTW89_TXCH_NUM, 581 RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1 582 }; 583 584 enum rtw89_rx_channel { 585 RTW89_RXCH_RXQ = 0, 586 RTW89_RXCH_RPQ = 1, 587 588 /* keep last */ 589 RTW89_RXCH_NUM, 590 RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1 591 }; 592 593 enum rtw89_tx_qsel { 594 RTW89_TX_QSEL_BE_0 = 0x00, 595 RTW89_TX_QSEL_BK_0 = 0x01, 596 RTW89_TX_QSEL_VI_0 = 0x02, 597 RTW89_TX_QSEL_VO_0 = 0x03, 598 RTW89_TX_QSEL_BE_1 = 0x04, 599 RTW89_TX_QSEL_BK_1 = 0x05, 600 RTW89_TX_QSEL_VI_1 = 0x06, 601 RTW89_TX_QSEL_VO_1 = 0x07, 602 RTW89_TX_QSEL_BE_2 = 0x08, 603 RTW89_TX_QSEL_BK_2 = 0x09, 604 RTW89_TX_QSEL_VI_2 = 0x0a, 605 RTW89_TX_QSEL_VO_2 = 0x0b, 606 RTW89_TX_QSEL_BE_3 = 0x0c, 607 RTW89_TX_QSEL_BK_3 = 0x0d, 608 RTW89_TX_QSEL_VI_3 = 0x0e, 609 RTW89_TX_QSEL_VO_3 = 0x0f, 610 RTW89_TX_QSEL_B0_BCN = 0x10, 611 RTW89_TX_QSEL_B0_HI = 0x11, 612 RTW89_TX_QSEL_B0_MGMT = 0x12, 613 RTW89_TX_QSEL_B0_NOPS = 0x13, 614 RTW89_TX_QSEL_B0_MGMT_FAST = 0x14, 615 /* reserved */ 616 /* reserved */ 617 /* reserved */ 618 RTW89_TX_QSEL_B1_BCN = 0x18, 619 RTW89_TX_QSEL_B1_HI = 0x19, 620 RTW89_TX_QSEL_B1_MGMT = 0x1a, 621 RTW89_TX_QSEL_B1_NOPS = 0x1b, 622 RTW89_TX_QSEL_B1_MGMT_FAST = 0x1c, 623 /* reserved */ 624 /* reserved */ 625 /* reserved */ 626 }; 627 628 static inline u8 rtw89_core_get_qsel(struct rtw89_dev *rtwdev, u8 tid) 629 { 630 switch (tid) { 631 default: 632 rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid); 633 fallthrough; 634 case 0: 635 case 3: 636 return RTW89_TX_QSEL_BE_0; 637 case 1: 638 case 2: 639 return RTW89_TX_QSEL_BK_0; 640 case 4: 641 case 5: 642 return RTW89_TX_QSEL_VI_0; 643 case 6: 644 case 7: 645 return RTW89_TX_QSEL_VO_0; 646 } 647 } 648 649 static inline u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel) 650 { 651 switch (qsel) { 652 default: 653 rtw89_warn(rtwdev, "Cannot map qsel to dma: %d\n", qsel); 654 fallthrough; 655 case RTW89_TX_QSEL_BE_0: 656 return RTW89_TXCH_ACH0; 657 case RTW89_TX_QSEL_BK_0: 658 return RTW89_TXCH_ACH1; 659 case RTW89_TX_QSEL_VI_0: 660 return RTW89_TXCH_ACH2; 661 case RTW89_TX_QSEL_VO_0: 662 return RTW89_TXCH_ACH3; 663 case RTW89_TX_QSEL_B0_MGMT: 664 return RTW89_TXCH_CH8; 665 case RTW89_TX_QSEL_B0_HI: 666 return RTW89_TXCH_CH9; 667 case RTW89_TX_QSEL_B1_MGMT: 668 return RTW89_TXCH_CH10; 669 case RTW89_TX_QSEL_B1_HI: 670 return RTW89_TXCH_CH11; 671 } 672 } 673 674 static inline u8 rtw89_core_get_tid_indicate(struct rtw89_dev *rtwdev, u8 tid) 675 { 676 switch (tid) { 677 case 3: 678 case 2: 679 case 5: 680 case 7: 681 return 1; 682 default: 683 rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid); 684 fallthrough; 685 case 0: 686 case 1: 687 case 4: 688 case 6: 689 return 0; 690 } 691 } 692 693 #endif 694