1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2015-2016 Hiroki Mori.
5 * Copyright (c) 2011-2012 Stefan Bethke.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include "opt_etherswitch.h"
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/errno.h>
35 #include <sys/kernel.h>
36 #include <sys/lock.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <sys/mutex.h>
40 #include <sys/socket.h>
41 #include <sys/sockio.h>
42 #include <sys/sysctl.h>
43 #include <sys/systm.h>
44
45 #include <net/if.h>
46 #include <net/if_var.h>
47 #include <net/ethernet.h>
48 #include <net/if_media.h>
49 #include <net/if_types.h>
50
51 #include <machine/bus.h>
52 #include <dev/iicbus/iic.h>
53 #include <dev/iicbus/iiconf.h>
54 #include <dev/iicbus/iicbus.h>
55 #include <dev/mii/mii.h>
56 #include <dev/mii/miivar.h>
57 #include <dev/mdio/mdio.h>
58
59 #include <dev/etherswitch/etherswitch.h>
60 #include <dev/etherswitch/rtl8366/rtl8366rbvar.h>
61
62 #include "mdio_if.h"
63 #include "iicbus_if.h"
64 #include "miibus_if.h"
65 #include "etherswitch_if.h"
66
67
68 struct rtl8366rb_softc {
69 struct mtx sc_mtx; /* serialize access to softc */
70 int smi_acquired; /* serialize access to SMI/I2C bus */
71 struct mtx callout_mtx; /* serialize callout */
72 device_t dev;
73 int vid[RTL8366_NUM_VLANS];
74 char *ifname[RTL8366_NUM_PHYS];
75 device_t miibus[RTL8366_NUM_PHYS];
76 if_t ifp[RTL8366_NUM_PHYS];
77 struct callout callout_tick;
78 etherswitch_info_t info;
79 int chip_type;
80 int phy4cpu;
81 int numphys;
82 };
83
84 #define RTL_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
85 #define RTL_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
86 #define RTL_LOCK_ASSERT(_sc, _what) mtx_assert(&(_s)c->sc_mtx, (_what))
87 #define RTL_TRYLOCK(_sc) mtx_trylock(&(_sc)->sc_mtx)
88
89 #define RTL_WAITOK 0
90 #define RTL_NOWAIT 1
91
92 #define RTL_SMI_ACQUIRED 1
93 #define RTL_SMI_ACQUIRED_ASSERT(_sc) \
94 KASSERT((_sc)->smi_acquired == RTL_SMI_ACQUIRED, ("smi must be acquired @%s", __FUNCTION__))
95
96 #if defined(DEBUG)
97 #define DPRINTF(dev, args...) device_printf(dev, args)
98 #define DEVERR(dev, err, fmt, args...) do { \
99 if (err != 0) device_printf(dev, fmt, err, args); \
100 } while (0)
101 #define DEBUG_INCRVAR(var) do { \
102 var++; \
103 } while (0)
104
105 static int callout_blocked = 0;
106 static int iic_select_retries = 0;
107 static int phy_access_retries = 0;
108 static SYSCTL_NODE(_debug, OID_AUTO, rtl8366rb, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
109 "rtl8366rb");
110 SYSCTL_INT(_debug_rtl8366rb, OID_AUTO, callout_blocked, CTLFLAG_RW, &callout_blocked, 0,
111 "number of times the callout couldn't acquire the bus");
112 SYSCTL_INT(_debug_rtl8366rb, OID_AUTO, iic_select_retries, CTLFLAG_RW, &iic_select_retries, 0,
113 "number of times the I2C bus selection had to be retried");
114 SYSCTL_INT(_debug_rtl8366rb, OID_AUTO, phy_access_retries, CTLFLAG_RW, &phy_access_retries, 0,
115 "number of times PHY register access had to be retried");
116 #else
117 #define DPRINTF(dev, args...)
118 #define DEVERR(dev, err, fmt, args...)
119 #define DEBUG_INCRVAR(var)
120 #endif
121
122 static int smi_probe(device_t dev);
123 static int smi_read(device_t dev, uint16_t addr, uint16_t *data, int sleep);
124 static int smi_write(device_t dev, uint16_t addr, uint16_t data, int sleep);
125 static int smi_rmw(device_t dev, uint16_t addr, uint16_t mask, uint16_t data, int sleep);
126 static void rtl8366rb_tick(void *arg);
127 static int rtl8366rb_ifmedia_upd(if_t);
128 static void rtl8366rb_ifmedia_sts(if_t, struct ifmediareq *);
129
130 static void
rtl8366rb_identify(driver_t * driver,device_t parent)131 rtl8366rb_identify(driver_t *driver, device_t parent)
132 {
133 device_t child;
134 struct iicbus_ivar *devi;
135
136 if (device_find_child(parent, "rtl8366rb", -1) == NULL) {
137 child = BUS_ADD_CHILD(parent, 0, "rtl8366rb", DEVICE_UNIT_ANY);
138 devi = IICBUS_IVAR(child);
139 devi->addr = RTL8366_IIC_ADDR;
140 }
141 }
142
143 static int
rtl8366rb_probe(device_t dev)144 rtl8366rb_probe(device_t dev)
145 {
146 struct rtl8366rb_softc *sc;
147
148 sc = device_get_softc(dev);
149
150 bzero(sc, sizeof(*sc));
151 if (smi_probe(dev) != 0)
152 return (ENXIO);
153 if (sc->chip_type == RTL8366RB)
154 device_set_desc(dev, "RTL8366RB Ethernet Switch Controller");
155 else
156 device_set_desc(dev, "RTL8366SR Ethernet Switch Controller");
157 return (BUS_PROBE_DEFAULT);
158 }
159
160 static void
rtl8366rb_init(device_t dev)161 rtl8366rb_init(device_t dev)
162 {
163 struct rtl8366rb_softc *sc;
164 int i;
165
166 sc = device_get_softc(dev);
167
168 /* Initialisation for TL-WR1043ND */
169 #ifdef RTL8366_SOFT_RESET
170 smi_rmw(dev, RTL8366_RCR,
171 RTL8366_RCR_SOFT_RESET,
172 RTL8366_RCR_SOFT_RESET, RTL_WAITOK);
173 #else
174 smi_rmw(dev, RTL8366_RCR,
175 RTL8366_RCR_HARD_RESET,
176 RTL8366_RCR_HARD_RESET, RTL_WAITOK);
177 #endif
178 /* hard reset not return ack */
179 DELAY(100000);
180 /* Enable 16 VLAN mode */
181 smi_rmw(dev, RTL8366_SGCR,
182 RTL8366_SGCR_EN_VLAN | RTL8366_SGCR_EN_VLAN_4KTB,
183 RTL8366_SGCR_EN_VLAN, RTL_WAITOK);
184 /* Initialize our vlan table. */
185 for (i = 0; i <= 1; i++)
186 sc->vid[i] = (i + 1) | ETHERSWITCH_VID_VALID;
187 /* Remove port 0 from VLAN 1. */
188 smi_rmw(dev, RTL8366_VMCR(RTL8366_VMCR_MU_REG, 0),
189 (1 << 0), 0, RTL_WAITOK);
190 /* Add port 0 untagged and port 5 tagged to VLAN 2. */
191 smi_rmw(dev, RTL8366_VMCR(RTL8366_VMCR_MU_REG, 1),
192 ((1 << 5 | 1 << 0) << RTL8366_VMCR_MU_MEMBER_SHIFT)
193 | ((1 << 5 | 1 << 0) << RTL8366_VMCR_MU_UNTAG_SHIFT),
194 ((1 << 5 | 1 << 0) << RTL8366_VMCR_MU_MEMBER_SHIFT
195 | ((1 << 0) << RTL8366_VMCR_MU_UNTAG_SHIFT)),
196 RTL_WAITOK);
197 /* Set PVID 2 for port 0. */
198 smi_rmw(dev, RTL8366_PVCR_REG(0),
199 RTL8366_PVCR_VAL(0, RTL8366_PVCR_PORT_MASK),
200 RTL8366_PVCR_VAL(0, 1), RTL_WAITOK);
201 }
202
203 static int
rtl8366rb_attach(device_t dev)204 rtl8366rb_attach(device_t dev)
205 {
206 struct rtl8366rb_softc *sc;
207 uint16_t rev = 0;
208 char name[IFNAMSIZ];
209 int err = 0;
210 int i;
211
212 sc = device_get_softc(dev);
213
214 sc->dev = dev;
215 mtx_init(&sc->sc_mtx, "rtl8366rb", NULL, MTX_DEF);
216 sc->smi_acquired = 0;
217 mtx_init(&sc->callout_mtx, "rtl8366rbcallout", NULL, MTX_DEF);
218
219 rtl8366rb_init(dev);
220 smi_read(dev, RTL8366_CVCR, &rev, RTL_WAITOK);
221 device_printf(dev, "rev. %d\n", rev & 0x000f);
222
223 sc->phy4cpu = 0;
224 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
225 "phy4cpu", &sc->phy4cpu);
226
227 sc->numphys = sc->phy4cpu ? RTL8366_NUM_PHYS - 1 : RTL8366_NUM_PHYS;
228
229 sc->info.es_nports = sc->numphys + 1;
230 sc->info.es_nvlangroups = RTL8366_NUM_VLANS;
231 sc->info.es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q;
232 if (sc->chip_type == RTL8366RB)
233 sprintf(sc->info.es_name, "Realtek RTL8366RB");
234 else
235 sprintf(sc->info.es_name, "Realtek RTL8366SR");
236
237 /* attach miibus and phys */
238 /* PHYs need an interface, so we generate a dummy one */
239 for (i = 0; i < sc->numphys; i++) {
240 sc->ifp[i] = if_alloc(IFT_ETHER);
241 if_setsoftc(sc->ifp[i], sc);
242 if_setflagbits(sc->ifp[i], IFF_UP | IFF_BROADCAST | IFF_DRV_RUNNING
243 | IFF_SIMPLEX, 0);
244 snprintf(name, IFNAMSIZ, "%sport", device_get_nameunit(dev));
245 sc->ifname[i] = malloc(strlen(name)+1, M_DEVBUF, M_WAITOK);
246 bcopy(name, sc->ifname[i], strlen(name)+1);
247 if_initname(sc->ifp[i], sc->ifname[i], i);
248 err = mii_attach(dev, &sc->miibus[i], sc->ifp[i], rtl8366rb_ifmedia_upd, \
249 rtl8366rb_ifmedia_sts, BMSR_DEFCAPMASK, \
250 i, MII_OFFSET_ANY, 0);
251 if (err != 0) {
252 device_printf(dev, "attaching PHY %d failed\n", i);
253 return (err);
254 }
255 }
256
257 bus_identify_children(dev);
258 bus_enumerate_hinted_children(dev);
259 bus_attach_children(dev);
260
261 callout_init_mtx(&sc->callout_tick, &sc->callout_mtx, 0);
262 rtl8366rb_tick(sc);
263
264 return (err);
265 }
266
267 static int
rtl8366rb_detach(device_t dev)268 rtl8366rb_detach(device_t dev)
269 {
270 struct rtl8366rb_softc *sc;
271 int error, i;
272
273 error = bus_generic_detach(dev);
274 if (error != 0)
275 return (error);
276
277 sc = device_get_softc(dev);
278
279 for (i=0; i < sc->numphys; i++) {
280 if (sc->ifp[i] != NULL)
281 if_free(sc->ifp[i]);
282 free(sc->ifname[i], M_DEVBUF);
283 }
284 callout_drain(&sc->callout_tick);
285 mtx_destroy(&sc->callout_mtx);
286 mtx_destroy(&sc->sc_mtx);
287
288 return (0);
289 }
290
291 static void
rtl8366rb_update_ifmedia(int portstatus,u_int * media_status,u_int * media_active)292 rtl8366rb_update_ifmedia(int portstatus, u_int *media_status, u_int *media_active)
293 {
294 *media_active = IFM_ETHER;
295 *media_status = IFM_AVALID;
296 if ((portstatus & RTL8366_PLSR_LINK) != 0)
297 *media_status |= IFM_ACTIVE;
298 else {
299 *media_active |= IFM_NONE;
300 return;
301 }
302 switch (portstatus & RTL8366_PLSR_SPEED_MASK) {
303 case RTL8366_PLSR_SPEED_10:
304 *media_active |= IFM_10_T;
305 break;
306 case RTL8366_PLSR_SPEED_100:
307 *media_active |= IFM_100_TX;
308 break;
309 case RTL8366_PLSR_SPEED_1000:
310 *media_active |= IFM_1000_T;
311 break;
312 }
313 if ((portstatus & RTL8366_PLSR_FULLDUPLEX) != 0)
314 *media_active |= IFM_FDX;
315 else
316 *media_active |= IFM_HDX;
317 if ((portstatus & RTL8366_PLSR_TXPAUSE) != 0)
318 *media_active |= IFM_ETH_TXPAUSE;
319 if ((portstatus & RTL8366_PLSR_RXPAUSE) != 0)
320 *media_active |= IFM_ETH_RXPAUSE;
321 }
322
323 static void
rtl833rb_miipollstat(struct rtl8366rb_softc * sc)324 rtl833rb_miipollstat(struct rtl8366rb_softc *sc)
325 {
326 int i;
327 struct mii_data *mii;
328 struct mii_softc *miisc;
329 uint16_t value;
330 int portstatus;
331
332 for (i = 0; i < sc->numphys; i++) {
333 mii = device_get_softc(sc->miibus[i]);
334 if ((i % 2) == 0) {
335 if (smi_read(sc->dev, RTL8366_PLSR_BASE + i/2, &value, RTL_NOWAIT) != 0) {
336 DEBUG_INCRVAR(callout_blocked);
337 return;
338 }
339 portstatus = value & 0xff;
340 } else {
341 portstatus = (value >> 8) & 0xff;
342 }
343 rtl8366rb_update_ifmedia(portstatus, &mii->mii_media_status, &mii->mii_media_active);
344 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
345 if (IFM_INST(mii->mii_media.ifm_cur->ifm_media) != miisc->mii_inst)
346 continue;
347 mii_phy_update(miisc, MII_POLLSTAT);
348 }
349 }
350 }
351
352 static void
rtl8366rb_tick(void * arg)353 rtl8366rb_tick(void *arg)
354 {
355 struct rtl8366rb_softc *sc;
356
357 sc = arg;
358
359 rtl833rb_miipollstat(sc);
360 callout_reset(&sc->callout_tick, hz, rtl8366rb_tick, sc);
361 }
362
363 static int
smi_probe(device_t dev)364 smi_probe(device_t dev)
365 {
366 struct rtl8366rb_softc *sc;
367 device_t iicbus, iicha;
368 int err, i, j;
369 uint16_t chipid;
370 char bytes[2];
371 int xferd;
372
373 sc = device_get_softc(dev);
374
375 iicbus = device_get_parent(dev);
376 iicha = device_get_parent(iicbus);
377
378 for (i = 0; i < 2; ++i) {
379 iicbus_reset(iicbus, IIC_FASTEST, RTL8366_IIC_ADDR, NULL);
380 for (j=3; j--; ) {
381 IICBUS_STOP(iicha);
382 /*
383 * we go directly to the host adapter because iicbus.c
384 * only issues a stop on a bus that was successfully started.
385 */
386 }
387 err = iicbus_request_bus(iicbus, dev, IIC_WAIT);
388 if (err != 0)
389 goto out;
390 err = iicbus_start(iicbus, RTL8366_IIC_ADDR | RTL_IICBUS_READ, RTL_IICBUS_TIMEOUT);
391 if (err != 0)
392 goto out;
393 if (i == 0) {
394 bytes[0] = RTL8366RB_CIR & 0xff;
395 bytes[1] = (RTL8366RB_CIR >> 8) & 0xff;
396 } else {
397 bytes[0] = RTL8366SR_CIR & 0xff;
398 bytes[1] = (RTL8366SR_CIR >> 8) & 0xff;
399 }
400 err = iicbus_write(iicbus, bytes, 2, &xferd, RTL_IICBUS_TIMEOUT);
401 if (err != 0)
402 goto out;
403 err = iicbus_read(iicbus, bytes, 2, &xferd, IIC_LAST_READ, 0);
404 if (err != 0)
405 goto out;
406 chipid = ((bytes[1] & 0xff) << 8) | (bytes[0] & 0xff);
407 if (i == 0 && chipid == RTL8366RB_CIR_ID8366RB) {
408 DPRINTF(dev, "chip id 0x%04x\n", chipid);
409 sc->chip_type = RTL8366RB;
410 err = 0;
411 break;
412 }
413 if (i == 1 && chipid == RTL8366SR_CIR_ID8366SR) {
414 DPRINTF(dev, "chip id 0x%04x\n", chipid);
415 sc->chip_type = RTL8366SR;
416 err = 0;
417 break;
418 }
419 if (i == 0) {
420 iicbus_stop(iicbus);
421 iicbus_release_bus(iicbus, dev);
422 }
423 }
424 if (i == 2)
425 err = ENXIO;
426 out:
427 iicbus_stop(iicbus);
428 iicbus_release_bus(iicbus, dev);
429 return (err == 0 ? 0 : ENXIO);
430 }
431
432 static int
smi_acquire(struct rtl8366rb_softc * sc,int sleep)433 smi_acquire(struct rtl8366rb_softc *sc, int sleep)
434 {
435 int r = 0;
436 if (sleep == RTL_WAITOK)
437 RTL_LOCK(sc);
438 else
439 if (RTL_TRYLOCK(sc) == 0)
440 return (EWOULDBLOCK);
441 if (sc->smi_acquired == RTL_SMI_ACQUIRED)
442 r = EBUSY;
443 else {
444 r = iicbus_request_bus(device_get_parent(sc->dev), sc->dev, \
445 sleep == RTL_WAITOK ? IIC_WAIT : IIC_DONTWAIT);
446 if (r == 0)
447 sc->smi_acquired = RTL_SMI_ACQUIRED;
448 }
449 RTL_UNLOCK(sc);
450 return (r);
451 }
452
453 static int
smi_release(struct rtl8366rb_softc * sc,int sleep)454 smi_release(struct rtl8366rb_softc *sc, int sleep)
455 {
456 if (sleep == RTL_WAITOK)
457 RTL_LOCK(sc);
458 else
459 if (RTL_TRYLOCK(sc) == 0)
460 return (EWOULDBLOCK);
461 RTL_SMI_ACQUIRED_ASSERT(sc);
462 iicbus_release_bus(device_get_parent(sc->dev), sc->dev);
463 sc->smi_acquired = 0;
464 RTL_UNLOCK(sc);
465 return (0);
466 }
467
468 static int
smi_select(device_t dev,int op,int sleep)469 smi_select(device_t dev, int op, int sleep)
470 {
471 struct rtl8366rb_softc *sc;
472 int err, i;
473 device_t iicbus;
474 struct iicbus_ivar *devi;
475 int slave;
476
477 sc = device_get_softc(dev);
478
479 iicbus = device_get_parent(dev);
480 devi = IICBUS_IVAR(dev);
481 slave = devi->addr;
482
483 RTL_SMI_ACQUIRED_ASSERT((struct rtl8366rb_softc *)device_get_softc(dev));
484
485 if (sc->chip_type == RTL8366SR) { // RTL8366SR work around
486 // this is same work around at probe
487 for (int i=3; i--; )
488 IICBUS_STOP(device_get_parent(device_get_parent(dev)));
489 }
490 /*
491 * The chip does not use clock stretching when it is busy,
492 * instead ignoring the command. Retry a few times.
493 */
494 for (i = RTL_IICBUS_RETRIES; i--; ) {
495 err = iicbus_start(iicbus, slave | op, RTL_IICBUS_TIMEOUT);
496 if (err != IIC_ENOACK)
497 break;
498 if (sleep == RTL_WAITOK) {
499 DEBUG_INCRVAR(iic_select_retries);
500 pause("smi_select", RTL_IICBUS_RETRY_SLEEP);
501 } else
502 break;
503 }
504 return (err);
505 }
506
507 static int
smi_read_locked(struct rtl8366rb_softc * sc,uint16_t addr,uint16_t * data,int sleep)508 smi_read_locked(struct rtl8366rb_softc *sc, uint16_t addr, uint16_t *data, int sleep)
509 {
510 int err;
511 device_t iicbus;
512 char bytes[2];
513 int xferd;
514
515 iicbus = device_get_parent(sc->dev);
516
517 RTL_SMI_ACQUIRED_ASSERT(sc);
518 bytes[0] = addr & 0xff;
519 bytes[1] = (addr >> 8) & 0xff;
520 err = smi_select(sc->dev, RTL_IICBUS_READ, sleep);
521 if (err != 0)
522 goto out;
523 err = iicbus_write(iicbus, bytes, 2, &xferd, RTL_IICBUS_TIMEOUT);
524 if (err != 0)
525 goto out;
526 err = iicbus_read(iicbus, bytes, 2, &xferd, IIC_LAST_READ, 0);
527 if (err != 0)
528 goto out;
529 *data = ((bytes[1] & 0xff) << 8) | (bytes[0] & 0xff);
530
531 out:
532 iicbus_stop(iicbus);
533 return (err);
534 }
535
536 static int
smi_write_locked(struct rtl8366rb_softc * sc,uint16_t addr,uint16_t data,int sleep)537 smi_write_locked(struct rtl8366rb_softc *sc, uint16_t addr, uint16_t data, int sleep)
538 {
539 int err;
540 device_t iicbus;
541 char bytes[4];
542 int xferd;
543
544 iicbus = device_get_parent(sc->dev);
545
546 RTL_SMI_ACQUIRED_ASSERT(sc);
547 bytes[0] = addr & 0xff;
548 bytes[1] = (addr >> 8) & 0xff;
549 bytes[2] = data & 0xff;
550 bytes[3] = (data >> 8) & 0xff;
551
552 err = smi_select(sc->dev, RTL_IICBUS_WRITE, sleep);
553 if (err == 0)
554 err = iicbus_write(iicbus, bytes, 4, &xferd, RTL_IICBUS_TIMEOUT);
555 iicbus_stop(iicbus);
556
557 return (err);
558 }
559
560 static int
smi_read(device_t dev,uint16_t addr,uint16_t * data,int sleep)561 smi_read(device_t dev, uint16_t addr, uint16_t *data, int sleep)
562 {
563 struct rtl8366rb_softc *sc;
564 int err;
565
566 sc = device_get_softc(dev);
567
568 err = smi_acquire(sc, sleep);
569 if (err != 0)
570 return (EBUSY);
571 err = smi_read_locked(sc, addr, data, sleep);
572 smi_release(sc, sleep);
573 DEVERR(dev, err, "smi_read()=%d: addr=%04x\n", addr);
574 return (err == 0 ? 0 : EIO);
575 }
576
577 static int
smi_write(device_t dev,uint16_t addr,uint16_t data,int sleep)578 smi_write(device_t dev, uint16_t addr, uint16_t data, int sleep)
579 {
580 struct rtl8366rb_softc *sc;
581 int err;
582
583 sc = device_get_softc(dev);
584
585 err = smi_acquire(sc, sleep);
586 if (err != 0)
587 return (EBUSY);
588 err = smi_write_locked(sc, addr, data, sleep);
589 smi_release(sc, sleep);
590 DEVERR(dev, err, "smi_write()=%d: addr=%04x\n", addr);
591 return (err == 0 ? 0 : EIO);
592 }
593
594 static int
smi_rmw(device_t dev,uint16_t addr,uint16_t mask,uint16_t data,int sleep)595 smi_rmw(device_t dev, uint16_t addr, uint16_t mask, uint16_t data, int sleep)
596 {
597 struct rtl8366rb_softc *sc;
598 int err;
599 uint16_t oldv, newv;
600
601 sc = device_get_softc(dev);
602
603 err = smi_acquire(sc, sleep);
604 if (err != 0)
605 return (EBUSY);
606 if (err == 0) {
607 err = smi_read_locked(sc, addr, &oldv, sleep);
608 if (err == 0) {
609 newv = oldv & ~mask;
610 newv |= data & mask;
611 if (newv != oldv)
612 err = smi_write_locked(sc, addr, newv, sleep);
613 }
614 }
615 smi_release(sc, sleep);
616 DEVERR(dev, err, "smi_rmw()=%d: addr=%04x\n", addr);
617 return (err == 0 ? 0 : EIO);
618 }
619
620 static etherswitch_info_t *
rtl_getinfo(device_t dev)621 rtl_getinfo(device_t dev)
622 {
623 struct rtl8366rb_softc *sc;
624
625 sc = device_get_softc(dev);
626
627 return (&sc->info);
628 }
629
630 static int
rtl_readreg(device_t dev,int reg)631 rtl_readreg(device_t dev, int reg)
632 {
633 uint16_t data;
634
635 data = 0;
636
637 smi_read(dev, reg, &data, RTL_WAITOK);
638 return (data);
639 }
640
641 static int
rtl_writereg(device_t dev,int reg,int value)642 rtl_writereg(device_t dev, int reg, int value)
643 {
644 return (smi_write(dev, reg, value, RTL_WAITOK));
645 }
646
647 static int
rtl_getport(device_t dev,etherswitch_port_t * p)648 rtl_getport(device_t dev, etherswitch_port_t *p)
649 {
650 struct rtl8366rb_softc *sc;
651 struct ifmedia *ifm;
652 struct mii_data *mii;
653 struct ifmediareq *ifmr;
654 uint16_t v;
655 int err, vlangroup;
656
657 sc = device_get_softc(dev);
658
659 ifmr = &p->es_ifmr;
660
661 if (p->es_port < 0 || p->es_port >= (sc->numphys + 1))
662 return (ENXIO);
663 if (sc->phy4cpu && p->es_port == sc->numphys) {
664 vlangroup = RTL8366_PVCR_GET(p->es_port + 1,
665 rtl_readreg(dev, RTL8366_PVCR_REG(p->es_port + 1)));
666 } else {
667 vlangroup = RTL8366_PVCR_GET(p->es_port,
668 rtl_readreg(dev, RTL8366_PVCR_REG(p->es_port)));
669 }
670 p->es_pvid = sc->vid[vlangroup] & ETHERSWITCH_VID_MASK;
671
672 if (p->es_port < sc->numphys) {
673 mii = device_get_softc(sc->miibus[p->es_port]);
674 ifm = &mii->mii_media;
675 err = ifmedia_ioctl(sc->ifp[p->es_port], &p->es_ifr, ifm, SIOCGIFMEDIA);
676 if (err)
677 return (err);
678 } else {
679 /* fill in fixed values for CPU port */
680 p->es_flags |= ETHERSWITCH_PORT_CPU;
681 smi_read(dev, RTL8366_PLSR_BASE + (RTL8366_NUM_PHYS)/2, &v, RTL_WAITOK);
682 v = v >> (8 * ((RTL8366_NUM_PHYS) % 2));
683 rtl8366rb_update_ifmedia(v, &ifmr->ifm_status, &ifmr->ifm_active);
684 ifmr->ifm_current = ifmr->ifm_active;
685 ifmr->ifm_mask = 0;
686 ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID;
687 /* Return our static media list. */
688 if (ifmr->ifm_count > 0) {
689 ifmr->ifm_count = 1;
690 ifmr->ifm_ulist[0] = IFM_MAKEWORD(IFM_ETHER, IFM_1000_T,
691 IFM_FDX, 0);
692 } else
693 ifmr->ifm_count = 0;
694 }
695 return (0);
696 }
697
698 static int
rtl_setport(device_t dev,etherswitch_port_t * p)699 rtl_setport(device_t dev, etherswitch_port_t *p)
700 {
701 struct rtl8366rb_softc *sc;
702 int i, err, vlangroup;
703 struct ifmedia *ifm;
704 struct mii_data *mii;
705 int port;
706
707 sc = device_get_softc(dev);
708
709 if (p->es_port < 0 || p->es_port >= (sc->numphys + 1))
710 return (ENXIO);
711 vlangroup = -1;
712 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
713 if ((sc->vid[i] & ETHERSWITCH_VID_MASK) == p->es_pvid) {
714 vlangroup = i;
715 break;
716 }
717 }
718 if (vlangroup == -1)
719 return (ENXIO);
720 if (sc->phy4cpu && p->es_port == sc->numphys) {
721 port = p->es_port + 1;
722 } else {
723 port = p->es_port;
724 }
725 err = smi_rmw(dev, RTL8366_PVCR_REG(port),
726 RTL8366_PVCR_VAL(port, RTL8366_PVCR_PORT_MASK),
727 RTL8366_PVCR_VAL(port, vlangroup), RTL_WAITOK);
728 if (err)
729 return (err);
730 /* CPU Port */
731 if (p->es_port == sc->numphys)
732 return (0);
733 mii = device_get_softc(sc->miibus[p->es_port]);
734 ifm = &mii->mii_media;
735 err = ifmedia_ioctl(sc->ifp[p->es_port], &p->es_ifr, ifm, SIOCSIFMEDIA);
736 return (err);
737 }
738
739 static int
rtl_getvgroup(device_t dev,etherswitch_vlangroup_t * vg)740 rtl_getvgroup(device_t dev, etherswitch_vlangroup_t *vg)
741 {
742 struct rtl8366rb_softc *sc;
743 uint16_t vmcr[3];
744 int i;
745 int member, untagged;
746
747 sc = device_get_softc(dev);
748
749 for (i=0; i<RTL8366_VMCR_MULT; i++)
750 vmcr[i] = rtl_readreg(dev, RTL8366_VMCR(i, vg->es_vlangroup));
751
752 vg->es_vid = sc->vid[vg->es_vlangroup];
753 member = RTL8366_VMCR_MEMBER(vmcr);
754 untagged = RTL8366_VMCR_UNTAG(vmcr);
755 if (sc->phy4cpu) {
756 vg->es_member_ports = ((member & 0x20) >> 1) | (member & 0x0f);
757 vg->es_untagged_ports = ((untagged & 0x20) >> 1) | (untagged & 0x0f);
758 } else {
759 vg->es_member_ports = member;
760 vg->es_untagged_ports = untagged;
761 }
762 vg->es_fid = RTL8366_VMCR_FID(vmcr);
763 return (0);
764 }
765
766 static int
rtl_setvgroup(device_t dev,etherswitch_vlangroup_t * vg)767 rtl_setvgroup(device_t dev, etherswitch_vlangroup_t *vg)
768 {
769 struct rtl8366rb_softc *sc;
770 int g;
771 int member, untagged;
772
773 sc = device_get_softc(dev);
774
775 g = vg->es_vlangroup;
776
777 sc->vid[g] = vg->es_vid;
778 /* VLAN group disabled ? */
779 if (vg->es_member_ports == 0 && vg->es_untagged_ports == 0 && vg->es_vid == 0)
780 return (0);
781 sc->vid[g] |= ETHERSWITCH_VID_VALID;
782 rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_DOT1Q_REG, g),
783 (vg->es_vid << RTL8366_VMCR_DOT1Q_VID_SHIFT) & RTL8366_VMCR_DOT1Q_VID_MASK);
784 if (sc->phy4cpu) {
785 /* add space at phy4 */
786 member = (vg->es_member_ports & 0x0f) |
787 ((vg->es_member_ports & 0x10) << 1);
788 untagged = (vg->es_untagged_ports & 0x0f) |
789 ((vg->es_untagged_ports & 0x10) << 1);
790 } else {
791 member = vg->es_member_ports;
792 untagged = vg->es_untagged_ports;
793 }
794 if (sc->chip_type == RTL8366RB) {
795 rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_MU_REG, g),
796 ((member << RTL8366_VMCR_MU_MEMBER_SHIFT) & RTL8366_VMCR_MU_MEMBER_MASK) |
797 ((untagged << RTL8366_VMCR_MU_UNTAG_SHIFT) & RTL8366_VMCR_MU_UNTAG_MASK));
798 rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_FID_REG, g),
799 vg->es_fid);
800 } else {
801 rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_MU_REG, g),
802 ((member << RTL8366_VMCR_MU_MEMBER_SHIFT) & RTL8366_VMCR_MU_MEMBER_MASK) |
803 ((untagged << RTL8366_VMCR_MU_UNTAG_SHIFT) & RTL8366_VMCR_MU_UNTAG_MASK) |
804 ((vg->es_fid << RTL8366_VMCR_FID_FID_SHIFT) & RTL8366_VMCR_FID_FID_MASK));
805 }
806 return (0);
807 }
808
809 static int
rtl_getconf(device_t dev,etherswitch_conf_t * conf)810 rtl_getconf(device_t dev, etherswitch_conf_t *conf)
811 {
812
813 /* Return the VLAN mode. */
814 conf->cmd = ETHERSWITCH_CONF_VLAN_MODE;
815 conf->vlan_mode = ETHERSWITCH_VLAN_DOT1Q;
816
817 return (0);
818 }
819
820 static int
rtl_readphy(device_t dev,int phy,int reg)821 rtl_readphy(device_t dev, int phy, int reg)
822 {
823 struct rtl8366rb_softc *sc;
824 uint16_t data;
825 int err, i, sleep;
826
827 sc = device_get_softc(dev);
828
829 data = 0;
830
831 if (phy < 0 || phy >= RTL8366_NUM_PHYS)
832 return (ENXIO);
833 if (reg < 0 || reg >= RTL8366_NUM_PHY_REG)
834 return (ENXIO);
835 sleep = RTL_WAITOK;
836 err = smi_acquire(sc, sleep);
837 if (err != 0)
838 return (EBUSY);
839 for (i = RTL_IICBUS_RETRIES; i--; ) {
840 err = smi_write_locked(sc, RTL8366_PACR, RTL8366_PACR_READ, sleep);
841 if (err == 0)
842 err = smi_write_locked(sc, RTL8366_PHYREG(phy, 0, reg), 0, sleep);
843 if (err == 0) {
844 err = smi_read_locked(sc, RTL8366_PADR, &data, sleep);
845 break;
846 }
847 DEBUG_INCRVAR(phy_access_retries);
848 DPRINTF(dev, "rtl_readphy(): chip not responsive, retrying %d more times\n", i);
849 pause("rtl_readphy", RTL_IICBUS_RETRY_SLEEP);
850 }
851 smi_release(sc, sleep);
852 DEVERR(dev, err, "rtl_readphy()=%d: phy=%d.%02x\n", phy, reg);
853 return (data);
854 }
855
856 static int
rtl_writephy(device_t dev,int phy,int reg,int data)857 rtl_writephy(device_t dev, int phy, int reg, int data)
858 {
859 struct rtl8366rb_softc *sc;
860 int err, i, sleep;
861
862 sc = device_get_softc(dev);
863
864 if (phy < 0 || phy >= RTL8366_NUM_PHYS)
865 return (ENXIO);
866 if (reg < 0 || reg >= RTL8366_NUM_PHY_REG)
867 return (ENXIO);
868 sleep = RTL_WAITOK;
869 err = smi_acquire(sc, sleep);
870 if (err != 0)
871 return (EBUSY);
872 for (i = RTL_IICBUS_RETRIES; i--; ) {
873 err = smi_write_locked(sc, RTL8366_PACR, RTL8366_PACR_WRITE, sleep);
874 if (err == 0)
875 err = smi_write_locked(sc, RTL8366_PHYREG(phy, 0, reg), data, sleep);
876 if (err == 0) {
877 break;
878 }
879 DEBUG_INCRVAR(phy_access_retries);
880 DPRINTF(dev, "rtl_writephy(): chip not responsive, retrying %d more tiems\n", i);
881 pause("rtl_writephy", RTL_IICBUS_RETRY_SLEEP);
882 }
883 smi_release(sc, sleep);
884 DEVERR(dev, err, "rtl_writephy()=%d: phy=%d.%02x\n", phy, reg);
885 return (err == 0 ? 0 : EIO);
886 }
887
888 static int
rtl8366rb_ifmedia_upd(if_t ifp)889 rtl8366rb_ifmedia_upd(if_t ifp)
890 {
891 struct rtl8366rb_softc *sc;
892 struct mii_data *mii;
893
894 sc = if_getsoftc(ifp);
895 mii = device_get_softc(sc->miibus[if_getdunit(ifp)]);
896
897 mii_mediachg(mii);
898 return (0);
899 }
900
901 static void
rtl8366rb_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)902 rtl8366rb_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
903 {
904 struct rtl8366rb_softc *sc;
905 struct mii_data *mii;
906
907 sc = if_getsoftc(ifp);
908 mii = device_get_softc(sc->miibus[if_getdunit(ifp)]);
909
910 mii_pollstat(mii);
911 ifmr->ifm_active = mii->mii_media_active;
912 ifmr->ifm_status = mii->mii_media_status;
913 }
914
915
916 static device_method_t rtl8366rb_methods[] = {
917 /* Device interface */
918 DEVMETHOD(device_identify, rtl8366rb_identify),
919 DEVMETHOD(device_probe, rtl8366rb_probe),
920 DEVMETHOD(device_attach, rtl8366rb_attach),
921 DEVMETHOD(device_detach, rtl8366rb_detach),
922
923 /* bus interface */
924 DEVMETHOD(bus_add_child, device_add_child_ordered),
925
926 /* MII interface */
927 DEVMETHOD(miibus_readreg, rtl_readphy),
928 DEVMETHOD(miibus_writereg, rtl_writephy),
929
930 /* MDIO interface */
931 DEVMETHOD(mdio_readreg, rtl_readphy),
932 DEVMETHOD(mdio_writereg, rtl_writephy),
933
934 /* etherswitch interface */
935 DEVMETHOD(etherswitch_getconf, rtl_getconf),
936 DEVMETHOD(etherswitch_getinfo, rtl_getinfo),
937 DEVMETHOD(etherswitch_readreg, rtl_readreg),
938 DEVMETHOD(etherswitch_writereg, rtl_writereg),
939 DEVMETHOD(etherswitch_readphyreg, rtl_readphy),
940 DEVMETHOD(etherswitch_writephyreg, rtl_writephy),
941 DEVMETHOD(etherswitch_getport, rtl_getport),
942 DEVMETHOD(etherswitch_setport, rtl_setport),
943 DEVMETHOD(etherswitch_getvgroup, rtl_getvgroup),
944 DEVMETHOD(etherswitch_setvgroup, rtl_setvgroup),
945
946 DEVMETHOD_END
947 };
948
949 DEFINE_CLASS_0(rtl8366rb, rtl8366rb_driver, rtl8366rb_methods,
950 sizeof(struct rtl8366rb_softc));
951
952 DRIVER_MODULE(rtl8366rb, iicbus, rtl8366rb_driver, 0, 0);
953 DRIVER_MODULE(miibus, rtl8366rb, miibus_driver, 0, 0);
954 DRIVER_MODULE(mdio, rtl8366rb, mdio_driver, 0, 0);
955 DRIVER_MODULE(etherswitch, rtl8366rb, etherswitch_driver, 0, 0);
956 MODULE_VERSION(rtl8366rb, 1);
957 MODULE_DEPEND(rtl8366rb, iicbus, 1, 1, 1); /* XXX which versions? */
958 MODULE_DEPEND(rtl8366rb, miibus, 1, 1, 1); /* XXX which versions? */
959 MODULE_DEPEND(rtl8366rb, etherswitch, 1, 1, 1); /* XXX which versions? */
960