1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe host controller driver for Texas Instruments Keystone SoCs
4 *
5 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
6 * https://www.ti.com
7 *
8 * Author: Murali Karicheri <m-karicheri2@ti.com>
9 * Implementation based on pci-exynos.c and pcie-designware.c
10 */
11
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/irqchip/chained_irq.h>
18 #include <linux/irqdomain.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/msi.h>
21 #include <linux/of.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_pci.h>
24 #include <linux/phy/phy.h>
25 #include <linux/platform_device.h>
26 #include <linux/regmap.h>
27 #include <linux/resource.h>
28 #include <linux/signal.h>
29
30 #include "../../pci.h"
31 #include "pcie-designware.h"
32
33 #define PCIE_VENDORID_MASK 0xffff
34 #define PCIE_DEVICEID_SHIFT 16
35
36 /* Application registers */
37 #define PID 0x000
38 #define RTL GENMASK(15, 11)
39 #define RTL_SHIFT 11
40 #define AM6_PCI_PG1_RTL_VER 0x15
41
42 #define CMD_STATUS 0x004
43 #define LTSSM_EN_VAL BIT(0)
44 #define OB_XLAT_EN_VAL BIT(1)
45 #define DBI_CS2 BIT(5)
46
47 #define CFG_SETUP 0x008
48 #define CFG_BUS(x) (((x) & 0xff) << 16)
49 #define CFG_DEVICE(x) (((x) & 0x1f) << 8)
50 #define CFG_FUNC(x) ((x) & 0x7)
51 #define CFG_TYPE1 BIT(24)
52
53 #define OB_SIZE 0x030
54 #define OB_OFFSET_INDEX(n) (0x200 + (8 * (n)))
55 #define OB_OFFSET_HI(n) (0x204 + (8 * (n)))
56 #define OB_ENABLEN BIT(0)
57 #define OB_WIN_SIZE 8 /* 8MB */
58
59 #define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1)))
60 #define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1)))
61 #define PCIE_EP_IRQ_SET 0x64
62 #define PCIE_EP_IRQ_CLR 0x68
63 #define INT_ENABLE BIT(0)
64
65 /* IRQ register defines */
66 #define IRQ_EOI 0x050
67
68 #define MSI_IRQ 0x054
69 #define MSI_IRQ_STATUS(n) (0x104 + ((n) << 4))
70 #define MSI_IRQ_ENABLE_SET(n) (0x108 + ((n) << 4))
71 #define MSI_IRQ_ENABLE_CLR(n) (0x10c + ((n) << 4))
72 #define MSI_IRQ_OFFSET 4
73
74 #define IRQ_STATUS(n) (0x184 + ((n) << 4))
75 #define IRQ_ENABLE_SET(n) (0x188 + ((n) << 4))
76 #define INTx_EN BIT(0)
77
78 #define ERR_IRQ_STATUS 0x1c4
79 #define ERR_IRQ_ENABLE_SET 0x1c8
80 #define ERR_AER BIT(5) /* ECRC error */
81 #define AM6_ERR_AER BIT(4) /* AM6 ECRC error */
82 #define ERR_AXI BIT(4) /* AXI tag lookup fatal error */
83 #define ERR_CORR BIT(3) /* Correctable error */
84 #define ERR_NONFATAL BIT(2) /* Non-fatal error */
85 #define ERR_FATAL BIT(1) /* Fatal error */
86 #define ERR_SYS BIT(0) /* System error */
87 #define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \
88 ERR_NONFATAL | ERR_FATAL | ERR_SYS)
89
90 /* PCIE controller device IDs */
91 #define PCIE_RC_K2HK 0xb008
92 #define PCIE_RC_K2E 0xb009
93 #define PCIE_RC_K2L 0xb00a
94 #define PCIE_RC_K2G 0xb00b
95
96 #define KS_PCIE_DEV_TYPE_MASK (0x3 << 1)
97 #define KS_PCIE_DEV_TYPE(mode) ((mode) << 1)
98
99 #define EP 0x0
100 #define LEG_EP 0x1
101 #define RC 0x2
102
103 #define KS_PCIE_SYSCLOCKOUTEN BIT(0)
104
105 #define AM654_PCIE_DEV_TYPE_MASK 0x3
106 #define AM654_WIN_SIZE SZ_64K
107
108 #define APP_ADDR_SPACE_0 (16 * SZ_1K)
109
110 #define to_keystone_pcie(x) dev_get_drvdata((x)->dev)
111
112 #define PCI_DEVICE_ID_TI_AM654X 0xb00c
113
114 struct ks_pcie_of_data {
115 enum dw_pcie_device_mode mode;
116 const struct dw_pcie_host_ops *host_ops;
117 const struct dw_pcie_ep_ops *ep_ops;
118 u32 version;
119 };
120
121 struct keystone_pcie {
122 struct dw_pcie *pci;
123 /* PCI Device ID */
124 u32 device_id;
125 int intx_host_irqs[PCI_NUM_INTX];
126
127 int msi_host_irq;
128 int num_lanes;
129 u32 num_viewport;
130 struct phy **phy;
131 struct device_link **link;
132 struct device_node *msi_intc_np;
133 struct irq_domain *intx_irq_domain;
134 struct device_node *np;
135
136 /* Application register space */
137 void __iomem *va_app_base; /* DT 1st resource */
138 struct resource app;
139 bool is_am6;
140 };
141
ks_pcie_app_readl(struct keystone_pcie * ks_pcie,u32 offset)142 static u32 ks_pcie_app_readl(struct keystone_pcie *ks_pcie, u32 offset)
143 {
144 return readl(ks_pcie->va_app_base + offset);
145 }
146
ks_pcie_app_writel(struct keystone_pcie * ks_pcie,u32 offset,u32 val)147 static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset,
148 u32 val)
149 {
150 writel(val, ks_pcie->va_app_base + offset);
151 }
152
ks_pcie_msi_irq_ack(struct irq_data * data)153 static void ks_pcie_msi_irq_ack(struct irq_data *data)
154 {
155 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data);
156 struct keystone_pcie *ks_pcie;
157 u32 irq = data->hwirq;
158 struct dw_pcie *pci;
159 u32 reg_offset;
160 u32 bit_pos;
161
162 pci = to_dw_pcie_from_pp(pp);
163 ks_pcie = to_keystone_pcie(pci);
164
165 reg_offset = irq % 8;
166 bit_pos = irq >> 3;
167
168 ks_pcie_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset),
169 BIT(bit_pos));
170 ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET);
171 }
172
ks_pcie_compose_msi_msg(struct irq_data * data,struct msi_msg * msg)173 static void ks_pcie_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
174 {
175 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data);
176 struct keystone_pcie *ks_pcie;
177 struct dw_pcie *pci;
178 u64 msi_target;
179
180 pci = to_dw_pcie_from_pp(pp);
181 ks_pcie = to_keystone_pcie(pci);
182
183 msi_target = ks_pcie->app.start + MSI_IRQ;
184 msg->address_lo = lower_32_bits(msi_target);
185 msg->address_hi = upper_32_bits(msi_target);
186 msg->data = data->hwirq;
187
188 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
189 (int)data->hwirq, msg->address_hi, msg->address_lo);
190 }
191
ks_pcie_msi_mask(struct irq_data * data)192 static void ks_pcie_msi_mask(struct irq_data *data)
193 {
194 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data);
195 struct keystone_pcie *ks_pcie;
196 u32 irq = data->hwirq;
197 struct dw_pcie *pci;
198 unsigned long flags;
199 u32 reg_offset;
200 u32 bit_pos;
201
202 raw_spin_lock_irqsave(&pp->lock, flags);
203
204 pci = to_dw_pcie_from_pp(pp);
205 ks_pcie = to_keystone_pcie(pci);
206
207 reg_offset = irq % 8;
208 bit_pos = irq >> 3;
209
210 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset),
211 BIT(bit_pos));
212
213 raw_spin_unlock_irqrestore(&pp->lock, flags);
214 }
215
ks_pcie_msi_unmask(struct irq_data * data)216 static void ks_pcie_msi_unmask(struct irq_data *data)
217 {
218 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data);
219 struct keystone_pcie *ks_pcie;
220 u32 irq = data->hwirq;
221 struct dw_pcie *pci;
222 unsigned long flags;
223 u32 reg_offset;
224 u32 bit_pos;
225
226 raw_spin_lock_irqsave(&pp->lock, flags);
227
228 pci = to_dw_pcie_from_pp(pp);
229 ks_pcie = to_keystone_pcie(pci);
230
231 reg_offset = irq % 8;
232 bit_pos = irq >> 3;
233
234 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset),
235 BIT(bit_pos));
236
237 raw_spin_unlock_irqrestore(&pp->lock, flags);
238 }
239
240 static struct irq_chip ks_pcie_msi_irq_chip = {
241 .name = "KEYSTONE-PCI-MSI",
242 .irq_ack = ks_pcie_msi_irq_ack,
243 .irq_compose_msi_msg = ks_pcie_compose_msi_msg,
244 .irq_mask = ks_pcie_msi_mask,
245 .irq_unmask = ks_pcie_msi_unmask,
246 };
247
248 /**
249 * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers
250 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
251 * PCIe host controller driver information.
252 *
253 * Since modification of dbi_cs2 involves different clock domain, read the
254 * status back to ensure the transition is complete.
255 */
ks_pcie_set_dbi_mode(struct keystone_pcie * ks_pcie)256 static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)
257 {
258 u32 val;
259
260 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
261 val |= DBI_CS2;
262 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
263
264 do {
265 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
266 } while (!(val & DBI_CS2));
267 }
268
269 /**
270 * ks_pcie_clear_dbi_mode() - Disable DBI mode
271 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
272 * PCIe host controller driver information.
273 *
274 * Since modification of dbi_cs2 involves different clock domain, read the
275 * status back to ensure the transition is complete.
276 */
ks_pcie_clear_dbi_mode(struct keystone_pcie * ks_pcie)277 static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
278 {
279 u32 val;
280
281 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
282 val &= ~DBI_CS2;
283 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
284
285 do {
286 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
287 } while (val & DBI_CS2);
288 }
289
ks_pcie_msi_host_init(struct dw_pcie_rp * pp)290 static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp)
291 {
292 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
293 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
294
295 /* Configure and set up BAR0 */
296 ks_pcie_set_dbi_mode(ks_pcie);
297
298 /* Enable BAR0 */
299 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
300 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
301
302 ks_pcie_clear_dbi_mode(ks_pcie);
303
304 /*
305 * For BAR0, just setting bus address for inbound writes (MSI) should
306 * be sufficient. Use physical address to avoid any conflicts.
307 */
308 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
309
310 pp->msi_irq_chip = &ks_pcie_msi_irq_chip;
311 return dw_pcie_allocate_domains(pp);
312 }
313
ks_pcie_handle_intx_irq(struct keystone_pcie * ks_pcie,int offset)314 static void ks_pcie_handle_intx_irq(struct keystone_pcie *ks_pcie,
315 int offset)
316 {
317 struct dw_pcie *pci = ks_pcie->pci;
318 struct device *dev = pci->dev;
319 u32 pending;
320
321 pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(offset));
322
323 if (BIT(0) & pending) {
324 dev_dbg(dev, ": irq: irq_offset %d", offset);
325 generic_handle_domain_irq(ks_pcie->intx_irq_domain, offset);
326 }
327
328 /* EOI the INTx interrupt */
329 ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset);
330 }
331
ks_pcie_enable_error_irq(struct keystone_pcie * ks_pcie)332 static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie)
333 {
334 ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL);
335 }
336
ks_pcie_handle_error_irq(struct keystone_pcie * ks_pcie)337 static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie)
338 {
339 u32 reg;
340 struct device *dev = ks_pcie->pci->dev;
341
342 reg = ks_pcie_app_readl(ks_pcie, ERR_IRQ_STATUS);
343 if (!reg)
344 return IRQ_NONE;
345
346 if (reg & ERR_SYS)
347 dev_err(dev, "System Error\n");
348
349 if (reg & ERR_FATAL)
350 dev_err(dev, "Fatal Error\n");
351
352 if (reg & ERR_NONFATAL)
353 dev_dbg(dev, "Non Fatal Error\n");
354
355 if (reg & ERR_CORR)
356 dev_dbg(dev, "Correctable Error\n");
357
358 if (!ks_pcie->is_am6 && (reg & ERR_AXI))
359 dev_err(dev, "AXI tag lookup fatal Error\n");
360
361 if (reg & ERR_AER || (ks_pcie->is_am6 && (reg & AM6_ERR_AER)))
362 dev_err(dev, "ECRC Error\n");
363
364 ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, reg);
365
366 return IRQ_HANDLED;
367 }
368
ks_pcie_ack_intx_irq(struct irq_data * d)369 static void ks_pcie_ack_intx_irq(struct irq_data *d)
370 {
371 }
372
ks_pcie_mask_intx_irq(struct irq_data * d)373 static void ks_pcie_mask_intx_irq(struct irq_data *d)
374 {
375 }
376
ks_pcie_unmask_intx_irq(struct irq_data * d)377 static void ks_pcie_unmask_intx_irq(struct irq_data *d)
378 {
379 }
380
381 static struct irq_chip ks_pcie_intx_irq_chip = {
382 .name = "Keystone-PCI-INTX-IRQ",
383 .irq_ack = ks_pcie_ack_intx_irq,
384 .irq_mask = ks_pcie_mask_intx_irq,
385 .irq_unmask = ks_pcie_unmask_intx_irq,
386 };
387
ks_pcie_init_intx_irq_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw_irq)388 static int ks_pcie_init_intx_irq_map(struct irq_domain *d,
389 unsigned int irq, irq_hw_number_t hw_irq)
390 {
391 irq_set_chip_and_handler(irq, &ks_pcie_intx_irq_chip,
392 handle_level_irq);
393 irq_set_chip_data(irq, d->host_data);
394
395 return 0;
396 }
397
398 static const struct irq_domain_ops ks_pcie_intx_irq_domain_ops = {
399 .map = ks_pcie_init_intx_irq_map,
400 .xlate = irq_domain_xlate_onetwocell,
401 };
402
ks_pcie_setup_rc_app_regs(struct keystone_pcie * ks_pcie)403 static int ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
404 {
405 u32 val;
406 u32 num_viewport = ks_pcie->num_viewport;
407 struct dw_pcie *pci = ks_pcie->pci;
408 struct dw_pcie_rp *pp = &pci->pp;
409 struct resource_entry *entry;
410 struct resource *mem;
411 u64 start, end;
412 int i;
413
414 entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
415 if (!entry)
416 return -ENODEV;
417
418 mem = entry->res;
419 start = mem->start;
420 end = mem->end;
421
422 /* Disable BARs for inbound access */
423 ks_pcie_set_dbi_mode(ks_pcie);
424 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
425 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0);
426 ks_pcie_clear_dbi_mode(ks_pcie);
427
428 if (ks_pcie->is_am6)
429 return 0;
430
431 val = ilog2(OB_WIN_SIZE);
432 ks_pcie_app_writel(ks_pcie, OB_SIZE, val);
433
434 /* Using Direct 1:1 mapping of RC <-> PCI memory space */
435 for (i = 0; i < num_viewport && (start < end); i++) {
436 ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i),
437 lower_32_bits(start) | OB_ENABLEN);
438 ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i),
439 upper_32_bits(start));
440 start += OB_WIN_SIZE * SZ_1M;
441 }
442
443 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
444 val |= OB_XLAT_EN_VAL;
445 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
446
447 return 0;
448 }
449
ks_pcie_other_map_bus(struct pci_bus * bus,unsigned int devfn,int where)450 static void __iomem *ks_pcie_other_map_bus(struct pci_bus *bus,
451 unsigned int devfn, int where)
452 {
453 struct dw_pcie_rp *pp = bus->sysdata;
454 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
455 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
456 u32 reg;
457
458 /*
459 * Checking whether the link is up here is a last line of defense
460 * against platforms that forward errors on the system bus as
461 * SError upon PCI configuration transactions issued when the link
462 * is down. This check is racy by definition and does not stop
463 * the system from triggering an SError if the link goes down
464 * after this check is performed.
465 */
466 if (!dw_pcie_link_up(pci))
467 return NULL;
468
469 reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) |
470 CFG_FUNC(PCI_FUNC(devfn));
471 if (!pci_is_root_bus(bus->parent))
472 reg |= CFG_TYPE1;
473 ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg);
474
475 return pp->va_cfg0_base + where;
476 }
477
478 static struct pci_ops ks_child_pcie_ops = {
479 .map_bus = ks_pcie_other_map_bus,
480 .read = pci_generic_config_read,
481 .write = pci_generic_config_write,
482 };
483
484 static struct pci_ops ks_pcie_ops = {
485 .map_bus = dw_pcie_own_conf_map_bus,
486 .read = pci_generic_config_read,
487 .write = pci_generic_config_write,
488 };
489
490 /**
491 * ks_pcie_link_up() - Check if link up
492 * @pci: A pointer to the dw_pcie structure which holds the DesignWare PCIe host
493 * controller driver information.
494 */
ks_pcie_link_up(struct dw_pcie * pci)495 static bool ks_pcie_link_up(struct dw_pcie *pci)
496 {
497 u32 val;
498
499 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0);
500 return (val & PORT_LOGIC_LTSSM_STATE_MASK) == PORT_LOGIC_LTSSM_STATE_L0;
501 }
502
ks_pcie_stop_link(struct dw_pcie * pci)503 static void ks_pcie_stop_link(struct dw_pcie *pci)
504 {
505 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
506 u32 val;
507
508 /* Disable Link training */
509 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
510 val &= ~LTSSM_EN_VAL;
511 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
512 }
513
ks_pcie_start_link(struct dw_pcie * pci)514 static int ks_pcie_start_link(struct dw_pcie *pci)
515 {
516 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
517 u32 val;
518
519 /* Initiate Link Training */
520 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
521 ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
522
523 return 0;
524 }
525
ks_pcie_quirk(struct pci_dev * dev)526 static void ks_pcie_quirk(struct pci_dev *dev)
527 {
528 struct pci_bus *bus = dev->bus;
529 struct keystone_pcie *ks_pcie;
530 struct device *bridge_dev;
531 struct pci_dev *bridge;
532 u32 val;
533
534 static const struct pci_device_id rc_pci_devids[] = {
535 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK),
536 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, },
537 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E),
538 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, },
539 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L),
540 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, },
541 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2G),
542 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, },
543 { 0, },
544 };
545 static const struct pci_device_id am6_pci_devids[] = {
546 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654X),
547 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
548 { 0, },
549 };
550
551 if (pci_is_root_bus(bus))
552 bridge = dev;
553
554 /* look for the host bridge */
555 while (!pci_is_root_bus(bus)) {
556 bridge = bus->self;
557 bus = bus->parent;
558 }
559
560 if (!bridge)
561 return;
562
563 /*
564 * Keystone PCI controller has a h/w limitation of
565 * 256 bytes maximum read request size. It can't handle
566 * anything higher than this. So force this limit on
567 * all downstream devices.
568 */
569 if (pci_match_id(rc_pci_devids, bridge)) {
570 if (pcie_get_readrq(dev) > 256) {
571 dev_info(&dev->dev, "limiting MRRS to 256 bytes\n");
572 pcie_set_readrq(dev, 256);
573 }
574 }
575
576 /*
577 * Memory transactions fail with PCI controller in AM654 PG1.0
578 * when MRRS is set to more than 128 bytes. Force the MRRS to
579 * 128 bytes in all downstream devices.
580 */
581 if (pci_match_id(am6_pci_devids, bridge)) {
582 bridge_dev = pci_get_host_bridge_device(dev);
583 if (!bridge_dev || !bridge_dev->parent)
584 return;
585
586 ks_pcie = dev_get_drvdata(bridge_dev->parent);
587 if (!ks_pcie)
588 return;
589
590 val = ks_pcie_app_readl(ks_pcie, PID);
591 val &= RTL;
592 val >>= RTL_SHIFT;
593 if (val != AM6_PCI_PG1_RTL_VER)
594 return;
595
596 if (pcie_get_readrq(dev) > 128) {
597 dev_info(&dev->dev, "limiting MRRS to 128 bytes\n");
598 pcie_set_readrq(dev, 128);
599 }
600 }
601 }
602 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk);
603
ks_pcie_msi_irq_handler(struct irq_desc * desc)604 static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
605 {
606 unsigned int irq = desc->irq_data.hwirq;
607 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
608 u32 offset = irq - ks_pcie->msi_host_irq;
609 struct dw_pcie *pci = ks_pcie->pci;
610 struct dw_pcie_rp *pp = &pci->pp;
611 struct device *dev = pci->dev;
612 struct irq_chip *chip = irq_desc_get_chip(desc);
613 u32 vector, reg, pos;
614
615 dev_dbg(dev, "%s, irq %d\n", __func__, irq);
616
617 /*
618 * The chained irq handler installation would have replaced normal
619 * interrupt driver handler so we need to take care of mask/unmask and
620 * ack operation.
621 */
622 chained_irq_enter(chip, desc);
623
624 reg = ks_pcie_app_readl(ks_pcie, MSI_IRQ_STATUS(offset));
625 /*
626 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
627 * shows 1, 9, 17, 25 and so forth
628 */
629 for (pos = 0; pos < 4; pos++) {
630 if (!(reg & BIT(pos)))
631 continue;
632
633 vector = offset + (pos << 3);
634 dev_dbg(dev, "irq: bit %d, vector %d\n", pos, vector);
635 generic_handle_domain_irq(pp->irq_domain, vector);
636 }
637
638 chained_irq_exit(chip, desc);
639 }
640
641 /**
642 * ks_pcie_intx_irq_handler() - Handle INTX interrupt
643 * @desc: Pointer to irq descriptor
644 *
645 * Traverse through pending INTX interrupts and invoke handler for each. Also
646 * takes care of interrupt controller level mask/ack operation.
647 */
ks_pcie_intx_irq_handler(struct irq_desc * desc)648 static void ks_pcie_intx_irq_handler(struct irq_desc *desc)
649 {
650 unsigned int irq = irq_desc_get_irq(desc);
651 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
652 struct dw_pcie *pci = ks_pcie->pci;
653 struct device *dev = pci->dev;
654 u32 irq_offset = irq - ks_pcie->intx_host_irqs[0];
655 struct irq_chip *chip = irq_desc_get_chip(desc);
656
657 dev_dbg(dev, ": Handling INTX irq %d\n", irq);
658
659 /*
660 * The chained irq handler installation would have replaced normal
661 * interrupt driver handler so we need to take care of mask/unmask and
662 * ack operation.
663 */
664 chained_irq_enter(chip, desc);
665 ks_pcie_handle_intx_irq(ks_pcie, irq_offset);
666 chained_irq_exit(chip, desc);
667 }
668
ks_pcie_config_msi_irq(struct keystone_pcie * ks_pcie)669 static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie)
670 {
671 struct device *dev = ks_pcie->pci->dev;
672 struct device_node *np = ks_pcie->np;
673 struct device_node *intc_np;
674 struct irq_data *irq_data;
675 int irq_count, irq, ret, i;
676
677 if (!IS_ENABLED(CONFIG_PCI_MSI))
678 return 0;
679
680 intc_np = of_get_child_by_name(np, "msi-interrupt-controller");
681 if (!intc_np) {
682 if (ks_pcie->is_am6)
683 return 0;
684 dev_warn(dev, "msi-interrupt-controller node is absent\n");
685 return -EINVAL;
686 }
687
688 irq_count = of_irq_count(intc_np);
689 if (!irq_count) {
690 dev_err(dev, "No IRQ entries in msi-interrupt-controller\n");
691 ret = -EINVAL;
692 goto err;
693 }
694
695 for (i = 0; i < irq_count; i++) {
696 irq = irq_of_parse_and_map(intc_np, i);
697 if (!irq) {
698 ret = -EINVAL;
699 goto err;
700 }
701
702 if (!ks_pcie->msi_host_irq) {
703 irq_data = irq_get_irq_data(irq);
704 if (!irq_data) {
705 ret = -EINVAL;
706 goto err;
707 }
708 ks_pcie->msi_host_irq = irq_data->hwirq;
709 }
710
711 irq_set_chained_handler_and_data(irq, ks_pcie_msi_irq_handler,
712 ks_pcie);
713 }
714
715 of_node_put(intc_np);
716 return 0;
717
718 err:
719 of_node_put(intc_np);
720 return ret;
721 }
722
ks_pcie_config_intx_irq(struct keystone_pcie * ks_pcie)723 static int ks_pcie_config_intx_irq(struct keystone_pcie *ks_pcie)
724 {
725 struct device *dev = ks_pcie->pci->dev;
726 struct irq_domain *intx_irq_domain;
727 struct device_node *np = ks_pcie->np;
728 struct device_node *intc_np;
729 int irq_count, irq, ret = 0, i;
730
731 intc_np = of_get_child_by_name(np, "legacy-interrupt-controller");
732 if (!intc_np) {
733 /*
734 * Since INTX interrupts are modeled as edge-interrupts in
735 * AM6, keep it disabled for now.
736 */
737 if (ks_pcie->is_am6)
738 return 0;
739 dev_warn(dev, "legacy-interrupt-controller node is absent\n");
740 return -EINVAL;
741 }
742
743 irq_count = of_irq_count(intc_np);
744 if (!irq_count) {
745 dev_err(dev, "No IRQ entries in legacy-interrupt-controller\n");
746 ret = -EINVAL;
747 goto err;
748 }
749
750 for (i = 0; i < irq_count; i++) {
751 irq = irq_of_parse_and_map(intc_np, i);
752 if (!irq) {
753 ret = -EINVAL;
754 goto err;
755 }
756 ks_pcie->intx_host_irqs[i] = irq;
757
758 irq_set_chained_handler_and_data(irq,
759 ks_pcie_intx_irq_handler,
760 ks_pcie);
761 }
762
763 intx_irq_domain = irq_domain_create_linear(of_fwnode_handle(intc_np), PCI_NUM_INTX,
764 &ks_pcie_intx_irq_domain_ops, NULL);
765 if (!intx_irq_domain) {
766 dev_err(dev, "Failed to add irq domain for INTX irqs\n");
767 ret = -EINVAL;
768 goto err;
769 }
770 ks_pcie->intx_irq_domain = intx_irq_domain;
771
772 for (i = 0; i < PCI_NUM_INTX; i++)
773 ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(i), INTx_EN);
774
775 err:
776 of_node_put(intc_np);
777 return ret;
778 }
779
780 #ifdef CONFIG_ARM
781 /*
782 * When a PCI device does not exist during config cycles, keystone host
783 * gets a bus error instead of returning 0xffffffff (PCI_ERROR_RESPONSE).
784 * This handler always returns 0 for this kind of fault.
785 */
ks_pcie_fault(unsigned long addr,unsigned int fsr,struct pt_regs * regs)786 static int ks_pcie_fault(unsigned long addr, unsigned int fsr,
787 struct pt_regs *regs)
788 {
789 unsigned long instr = *(unsigned long *) instruction_pointer(regs);
790
791 if ((instr & 0x0e100090) == 0x00100090) {
792 int reg = (instr >> 12) & 15;
793
794 regs->uregs[reg] = -1;
795 regs->ARM_pc += 4;
796 }
797
798 return 0;
799 }
800 #endif
801
ks_pcie_init_id(struct keystone_pcie * ks_pcie)802 static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie)
803 {
804 int ret;
805 unsigned int id;
806 struct regmap *devctrl_regs;
807 struct dw_pcie *pci = ks_pcie->pci;
808 struct device *dev = pci->dev;
809 struct device_node *np = dev->of_node;
810 struct of_phandle_args args;
811 unsigned int offset = 0;
812
813 devctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-id");
814 if (IS_ERR(devctrl_regs))
815 return PTR_ERR(devctrl_regs);
816
817 /* Do not error out to maintain old DT compatibility */
818 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-id", 1, 0, &args);
819 if (!ret)
820 offset = args.args[0];
821
822 ret = regmap_read(devctrl_regs, offset, &id);
823 if (ret)
824 return ret;
825
826 dw_pcie_dbi_ro_wr_en(pci);
827 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, id & PCIE_VENDORID_MASK);
828 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, id >> PCIE_DEVICEID_SHIFT);
829 dw_pcie_dbi_ro_wr_dis(pci);
830
831 return 0;
832 }
833
ks_pcie_host_init(struct dw_pcie_rp * pp)834 static int __init ks_pcie_host_init(struct dw_pcie_rp *pp)
835 {
836 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
837 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
838 int ret;
839
840 pp->bridge->ops = &ks_pcie_ops;
841 if (!ks_pcie->is_am6)
842 pp->bridge->child_ops = &ks_child_pcie_ops;
843
844 ret = ks_pcie_config_intx_irq(ks_pcie);
845 if (ret)
846 return ret;
847
848 ret = ks_pcie_config_msi_irq(ks_pcie);
849 if (ret)
850 return ret;
851
852 ks_pcie_stop_link(pci);
853 ret = ks_pcie_setup_rc_app_regs(ks_pcie);
854 if (ret)
855 return ret;
856
857 writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
858 pci->dbi_base + PCI_IO_BASE);
859
860 ret = ks_pcie_init_id(ks_pcie);
861 if (ret < 0)
862 return ret;
863
864 #ifdef CONFIG_ARM
865 /*
866 * PCIe access errors that result into OCP errors are caught by ARM as
867 * "External aborts"
868 */
869 hook_fault_code(17, ks_pcie_fault, SIGBUS, 0,
870 "Asynchronous external abort");
871 #endif
872
873 return 0;
874 }
875
876 static const struct dw_pcie_host_ops ks_pcie_host_ops = {
877 .init = ks_pcie_host_init,
878 .msi_init = ks_pcie_msi_host_init,
879 };
880
881 static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = {
882 .init = ks_pcie_host_init,
883 };
884
ks_pcie_err_irq_handler(int irq,void * priv)885 static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv)
886 {
887 struct keystone_pcie *ks_pcie = priv;
888
889 return ks_pcie_handle_error_irq(ks_pcie);
890 }
891
ks_pcie_am654_write_dbi2(struct dw_pcie * pci,void __iomem * base,u32 reg,size_t size,u32 val)892 static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base,
893 u32 reg, size_t size, u32 val)
894 {
895 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
896
897 ks_pcie_set_dbi_mode(ks_pcie);
898 dw_pcie_write(base + reg, size, val);
899 ks_pcie_clear_dbi_mode(ks_pcie);
900 }
901
902 static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = {
903 .start_link = ks_pcie_start_link,
904 .stop_link = ks_pcie_stop_link,
905 .link_up = ks_pcie_link_up,
906 .write_dbi2 = ks_pcie_am654_write_dbi2,
907 };
908
ks_pcie_am654_ep_init(struct dw_pcie_ep * ep)909 static void ks_pcie_am654_ep_init(struct dw_pcie_ep *ep)
910 {
911 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
912 int flags;
913
914 ep->page_size = AM654_WIN_SIZE;
915 flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32;
916 dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1);
917 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, flags);
918 }
919
ks_pcie_am654_raise_intx_irq(struct keystone_pcie * ks_pcie)920 static void ks_pcie_am654_raise_intx_irq(struct keystone_pcie *ks_pcie)
921 {
922 struct dw_pcie *pci = ks_pcie->pci;
923 u8 int_pin;
924
925 int_pin = dw_pcie_readb_dbi(pci, PCI_INTERRUPT_PIN);
926 if (int_pin == 0 || int_pin > 4)
927 return;
928
929 ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_SET(int_pin),
930 INT_ENABLE);
931 ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_SET, INT_ENABLE);
932 mdelay(1);
933 ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_CLR, INT_ENABLE);
934 ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_CLR(int_pin),
935 INT_ENABLE);
936 }
937
ks_pcie_am654_raise_irq(struct dw_pcie_ep * ep,u8 func_no,unsigned int type,u16 interrupt_num)938 static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
939 unsigned int type, u16 interrupt_num)
940 {
941 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
942 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
943
944 switch (type) {
945 case PCI_IRQ_INTX:
946 ks_pcie_am654_raise_intx_irq(ks_pcie);
947 break;
948 case PCI_IRQ_MSI:
949 dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
950 break;
951 case PCI_IRQ_MSIX:
952 dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
953 break;
954 default:
955 dev_err(pci->dev, "UNKNOWN IRQ type\n");
956 return -EINVAL;
957 }
958
959 return 0;
960 }
961
962 static const struct pci_epc_features ks_pcie_am654_epc_features = {
963 .linkup_notifier = false,
964 .msi_capable = true,
965 .msix_capable = true,
966 .bar[BAR_0] = { .type = BAR_RESERVED, },
967 .bar[BAR_1] = { .type = BAR_RESERVED, },
968 .bar[BAR_2] = { .type = BAR_RESIZABLE, },
969 .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_64K, },
970 .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256, },
971 .bar[BAR_5] = { .type = BAR_RESIZABLE, },
972 .align = SZ_64K,
973 };
974
975 static const struct pci_epc_features*
ks_pcie_am654_get_features(struct dw_pcie_ep * ep)976 ks_pcie_am654_get_features(struct dw_pcie_ep *ep)
977 {
978 return &ks_pcie_am654_epc_features;
979 }
980
981 static const struct dw_pcie_ep_ops ks_pcie_am654_ep_ops = {
982 .init = ks_pcie_am654_ep_init,
983 .raise_irq = ks_pcie_am654_raise_irq,
984 .get_features = &ks_pcie_am654_get_features,
985 };
986
ks_pcie_disable_phy(struct keystone_pcie * ks_pcie)987 static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie)
988 {
989 int num_lanes = ks_pcie->num_lanes;
990
991 while (num_lanes--) {
992 phy_power_off(ks_pcie->phy[num_lanes]);
993 phy_exit(ks_pcie->phy[num_lanes]);
994 }
995 }
996
ks_pcie_enable_phy(struct keystone_pcie * ks_pcie)997 static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie)
998 {
999 int i;
1000 int ret;
1001 int num_lanes = ks_pcie->num_lanes;
1002
1003 for (i = 0; i < num_lanes; i++) {
1004 ret = phy_reset(ks_pcie->phy[i]);
1005 if (ret < 0)
1006 goto err_phy;
1007
1008 ret = phy_init(ks_pcie->phy[i]);
1009 if (ret < 0)
1010 goto err_phy;
1011
1012 ret = phy_power_on(ks_pcie->phy[i]);
1013 if (ret < 0) {
1014 phy_exit(ks_pcie->phy[i]);
1015 goto err_phy;
1016 }
1017 }
1018
1019 return 0;
1020
1021 err_phy:
1022 while (--i >= 0) {
1023 phy_power_off(ks_pcie->phy[i]);
1024 phy_exit(ks_pcie->phy[i]);
1025 }
1026
1027 return ret;
1028 }
1029
ks_pcie_set_mode(struct device * dev)1030 static int ks_pcie_set_mode(struct device *dev)
1031 {
1032 struct device_node *np = dev->of_node;
1033 struct of_phandle_args args;
1034 unsigned int offset = 0;
1035 struct regmap *syscon;
1036 u32 val;
1037 u32 mask;
1038 int ret = 0;
1039
1040 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode");
1041 if (IS_ERR(syscon))
1042 return 0;
1043
1044 /* Do not error out to maintain old DT compatibility */
1045 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args);
1046 if (!ret)
1047 offset = args.args[0];
1048
1049 mask = KS_PCIE_DEV_TYPE_MASK | KS_PCIE_SYSCLOCKOUTEN;
1050 val = KS_PCIE_DEV_TYPE(RC) | KS_PCIE_SYSCLOCKOUTEN;
1051
1052 ret = regmap_update_bits(syscon, offset, mask, val);
1053 if (ret) {
1054 dev_err(dev, "failed to set pcie mode\n");
1055 return ret;
1056 }
1057
1058 return 0;
1059 }
1060
ks_pcie_am654_set_mode(struct device * dev,enum dw_pcie_device_mode mode)1061 static int ks_pcie_am654_set_mode(struct device *dev,
1062 enum dw_pcie_device_mode mode)
1063 {
1064 struct device_node *np = dev->of_node;
1065 struct of_phandle_args args;
1066 unsigned int offset = 0;
1067 struct regmap *syscon;
1068 u32 val;
1069 u32 mask;
1070 int ret = 0;
1071
1072 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode");
1073 if (IS_ERR(syscon))
1074 return 0;
1075
1076 /* Do not error out to maintain old DT compatibility */
1077 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args);
1078 if (!ret)
1079 offset = args.args[0];
1080
1081 mask = AM654_PCIE_DEV_TYPE_MASK;
1082
1083 switch (mode) {
1084 case DW_PCIE_RC_TYPE:
1085 val = RC;
1086 break;
1087 case DW_PCIE_EP_TYPE:
1088 val = EP;
1089 break;
1090 default:
1091 dev_err(dev, "INVALID device type %d\n", mode);
1092 return -EINVAL;
1093 }
1094
1095 ret = regmap_update_bits(syscon, offset, mask, val);
1096 if (ret) {
1097 dev_err(dev, "failed to set pcie mode\n");
1098 return ret;
1099 }
1100
1101 return 0;
1102 }
1103
1104 static const struct ks_pcie_of_data ks_pcie_rc_of_data = {
1105 .host_ops = &ks_pcie_host_ops,
1106 .mode = DW_PCIE_RC_TYPE,
1107 .version = DW_PCIE_VER_365A,
1108 };
1109
1110 static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = {
1111 .host_ops = &ks_pcie_am654_host_ops,
1112 .mode = DW_PCIE_RC_TYPE,
1113 .version = DW_PCIE_VER_490A,
1114 };
1115
1116 static const struct ks_pcie_of_data ks_pcie_am654_ep_of_data = {
1117 .ep_ops = &ks_pcie_am654_ep_ops,
1118 .mode = DW_PCIE_EP_TYPE,
1119 .version = DW_PCIE_VER_490A,
1120 };
1121
1122 static const struct of_device_id ks_pcie_of_match[] = {
1123 {
1124 .type = "pci",
1125 .data = &ks_pcie_rc_of_data,
1126 .compatible = "ti,keystone-pcie",
1127 },
1128 {
1129 .data = &ks_pcie_am654_rc_of_data,
1130 .compatible = "ti,am654-pcie-rc",
1131 },
1132 {
1133 .data = &ks_pcie_am654_ep_of_data,
1134 .compatible = "ti,am654-pcie-ep",
1135 },
1136 { },
1137 };
1138
ks_pcie_probe(struct platform_device * pdev)1139 static int ks_pcie_probe(struct platform_device *pdev)
1140 {
1141 const struct dw_pcie_host_ops *host_ops;
1142 const struct dw_pcie_ep_ops *ep_ops;
1143 struct device *dev = &pdev->dev;
1144 struct device_node *np = dev->of_node;
1145 const struct ks_pcie_of_data *data;
1146 enum dw_pcie_device_mode mode;
1147 struct dw_pcie *pci;
1148 struct keystone_pcie *ks_pcie;
1149 struct device_link **link;
1150 struct gpio_desc *gpiod;
1151 struct resource *res;
1152 void __iomem *base;
1153 u32 num_viewport;
1154 struct phy **phy;
1155 u32 num_lanes;
1156 char name[10];
1157 u32 version;
1158 int ret;
1159 int irq;
1160 int i;
1161
1162 data = of_device_get_match_data(dev);
1163 if (!data)
1164 return -EINVAL;
1165
1166 version = data->version;
1167 host_ops = data->host_ops;
1168 ep_ops = data->ep_ops;
1169 mode = data->mode;
1170
1171 ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL);
1172 if (!ks_pcie)
1173 return -ENOMEM;
1174
1175 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1176 if (!pci)
1177 return -ENOMEM;
1178
1179 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app");
1180 ks_pcie->va_app_base = devm_ioremap_resource(dev, res);
1181 if (IS_ERR(ks_pcie->va_app_base))
1182 return PTR_ERR(ks_pcie->va_app_base);
1183
1184 ks_pcie->app = *res;
1185
1186 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics");
1187 base = devm_pci_remap_cfg_resource(dev, res);
1188 if (IS_ERR(base))
1189 return PTR_ERR(base);
1190
1191 if (of_device_is_compatible(np, "ti,am654-pcie-rc"))
1192 ks_pcie->is_am6 = true;
1193
1194 pci->dbi_base = base;
1195 pci->dbi_base2 = base;
1196 pci->dev = dev;
1197 pci->ops = &ks_pcie_dw_pcie_ops;
1198 pci->version = version;
1199
1200 irq = platform_get_irq(pdev, 0);
1201 if (irq < 0)
1202 return irq;
1203
1204 ret = request_irq(irq, ks_pcie_err_irq_handler, IRQF_SHARED,
1205 "ks-pcie-error-irq", ks_pcie);
1206 if (ret < 0) {
1207 dev_err(dev, "failed to request error IRQ %d\n",
1208 irq);
1209 return ret;
1210 }
1211
1212 ret = of_property_read_u32(np, "num-lanes", &num_lanes);
1213 if (ret)
1214 num_lanes = 1;
1215
1216 phy = devm_kzalloc(dev, sizeof(*phy) * num_lanes, GFP_KERNEL);
1217 if (!phy)
1218 return -ENOMEM;
1219
1220 link = devm_kzalloc(dev, sizeof(*link) * num_lanes, GFP_KERNEL);
1221 if (!link)
1222 return -ENOMEM;
1223
1224 for (i = 0; i < num_lanes; i++) {
1225 snprintf(name, sizeof(name), "pcie-phy%d", i);
1226 phy[i] = devm_phy_optional_get(dev, name);
1227 if (IS_ERR(phy[i])) {
1228 ret = PTR_ERR(phy[i]);
1229 goto err_link;
1230 }
1231
1232 if (!phy[i])
1233 continue;
1234
1235 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
1236 if (!link[i]) {
1237 ret = -EINVAL;
1238 goto err_link;
1239 }
1240 }
1241
1242 ks_pcie->np = np;
1243 ks_pcie->pci = pci;
1244 ks_pcie->link = link;
1245 ks_pcie->num_lanes = num_lanes;
1246 ks_pcie->phy = phy;
1247
1248 gpiod = devm_gpiod_get_optional(dev, "reset",
1249 GPIOD_OUT_LOW);
1250 if (IS_ERR(gpiod)) {
1251 ret = PTR_ERR(gpiod);
1252 if (ret != -EPROBE_DEFER)
1253 dev_err(dev, "Failed to get reset GPIO\n");
1254 goto err_link;
1255 }
1256
1257 /* Obtain references to the PHYs */
1258 for (i = 0; i < num_lanes; i++)
1259 phy_pm_runtime_get_sync(ks_pcie->phy[i]);
1260
1261 ret = ks_pcie_enable_phy(ks_pcie);
1262
1263 /* Release references to the PHYs */
1264 for (i = 0; i < num_lanes; i++)
1265 phy_pm_runtime_put_sync(ks_pcie->phy[i]);
1266
1267 if (ret) {
1268 dev_err(dev, "failed to enable phy\n");
1269 goto err_link;
1270 }
1271
1272 platform_set_drvdata(pdev, ks_pcie);
1273 pm_runtime_enable(dev);
1274 ret = pm_runtime_get_sync(dev);
1275 if (ret < 0) {
1276 dev_err(dev, "pm_runtime_get_sync failed\n");
1277 goto err_get_sync;
1278 }
1279
1280 if (dw_pcie_ver_is_ge(pci, 480A))
1281 ret = ks_pcie_am654_set_mode(dev, mode);
1282 else
1283 ret = ks_pcie_set_mode(dev);
1284 if (ret < 0)
1285 goto err_get_sync;
1286
1287 switch (mode) {
1288 case DW_PCIE_RC_TYPE:
1289 if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) {
1290 ret = -ENODEV;
1291 goto err_get_sync;
1292 }
1293
1294 ret = of_property_read_u32(np, "num-viewport", &num_viewport);
1295 if (ret < 0) {
1296 dev_err(dev, "unable to read *num-viewport* property\n");
1297 goto err_get_sync;
1298 }
1299
1300 /*
1301 * "Power Sequencing and Reset Signal Timings" table in
1302 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0
1303 * indicates PERST# should be deasserted after minimum of 100us
1304 * once REFCLK is stable. The REFCLK to the connector in RC
1305 * mode is selected while enabling the PHY. So deassert PERST#
1306 * after 100 us.
1307 */
1308 if (gpiod) {
1309 usleep_range(100, 200);
1310 gpiod_set_value_cansleep(gpiod, 1);
1311 }
1312
1313 ks_pcie->num_viewport = num_viewport;
1314 pci->pp.ops = host_ops;
1315 ret = dw_pcie_host_init(&pci->pp);
1316 if (ret < 0)
1317 goto err_get_sync;
1318 break;
1319 case DW_PCIE_EP_TYPE:
1320 if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_EP)) {
1321 ret = -ENODEV;
1322 goto err_get_sync;
1323 }
1324
1325 pci->ep.ops = ep_ops;
1326 ret = dw_pcie_ep_init(&pci->ep);
1327 if (ret < 0)
1328 goto err_get_sync;
1329
1330 ret = dw_pcie_ep_init_registers(&pci->ep);
1331 if (ret) {
1332 dev_err(dev, "Failed to initialize DWC endpoint registers\n");
1333 goto err_ep_init;
1334 }
1335
1336 pci_epc_init_notify(pci->ep.epc);
1337
1338 break;
1339 default:
1340 dev_err(dev, "INVALID device type %d\n", mode);
1341 }
1342
1343 ks_pcie_enable_error_irq(ks_pcie);
1344
1345 return 0;
1346
1347 err_ep_init:
1348 dw_pcie_ep_deinit(&pci->ep);
1349 err_get_sync:
1350 pm_runtime_put(dev);
1351 pm_runtime_disable(dev);
1352 ks_pcie_disable_phy(ks_pcie);
1353
1354 err_link:
1355 while (--i >= 0 && link[i])
1356 device_link_del(link[i]);
1357
1358 return ret;
1359 }
1360
ks_pcie_remove(struct platform_device * pdev)1361 static void ks_pcie_remove(struct platform_device *pdev)
1362 {
1363 struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
1364 struct device_link **link = ks_pcie->link;
1365 int num_lanes = ks_pcie->num_lanes;
1366 struct device *dev = &pdev->dev;
1367
1368 pm_runtime_put(dev);
1369 pm_runtime_disable(dev);
1370 ks_pcie_disable_phy(ks_pcie);
1371 while (num_lanes--)
1372 device_link_del(link[num_lanes]);
1373 }
1374
1375 static struct platform_driver ks_pcie_driver = {
1376 .probe = ks_pcie_probe,
1377 .remove = ks_pcie_remove,
1378 .driver = {
1379 .name = "keystone-pcie",
1380 .of_match_table = ks_pcie_of_match,
1381 },
1382 };
1383 builtin_platform_driver(ks_pcie_driver);
1384