xref: /titanic_41/usr/src/uts/common/io/ral/rt2560_reg.h (revision ff3124eff995e6cd8ebd8c6543648e0670920034)
1 /*
2  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
3  * Use is subject to license terms.
4  */
5 
6 /*
7  * Copyright (c) 2005, 2006
8  *	Damien Bergamini <damien.bergamini@free.fr>
9  *
10  * Permission to use, copy, modify, and distribute this software for any
11  * purpose with or without fee is hereby granted, provided that the above
12  * copyright notice and this permission notice appear in all copies.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
16  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
19  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
20  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21  */
22 
23 #ifndef _RT2560_REG_H
24 #define	_RT2560_REG_H
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
32 #define	RT2560_TX_RING_COUNT		250	/* 48 */
33 #define	RT2560_ATIM_RING_COUNT		4
34 #define	RT2560_PRIO_RING_COUNT		32	/* 16 */
35 #define	RT2560_BEACON_RING_COUNT	1
36 #define	RT2560_RX_RING_COUNT		250	/* 32 */
37 
38 #define	RT2560_TX_DESC_SIZE		(sizeof (struct rt2560_tx_desc))
39 #define	RT2560_RX_DESC_SIZE		(sizeof (struct rt2560_rx_desc))
40 
41 #define	RT2560_MAX_SCATTER		1
42 
43 /*
44  * Control and status registers.
45  */
46 #define	RT2560_CSR0		0x0000	/* ASIC version number */
47 #define	RT2560_CSR1		0x0004	/* System control */
48 #define	RT2560_CSR3		0x000c	/* STA MAC address 0 */
49 #define	RT2560_CSR4		0x0010	/* STA MAC address 1 */
50 #define	RT2560_CSR5		0x0014	/* BSSID 0 */
51 #define	RT2560_CSR6		0x0018	/* BSSID 1 */
52 #define	RT2560_CSR7		0x001c	/* Interrupt source */
53 #define	RT2560_CSR8		0x0020	/* Interrupt mask */
54 #define	RT2560_CSR9		0x0024	/* Maximum frame length */
55 #define	RT2560_SECCSR0		0x0028	/* WEP control */
56 #define	RT2560_CSR11		0x002c	/* Back-off control */
57 #define	RT2560_CSR12		0x0030	/* Synchronization configuration 0 */
58 #define	RT2560_CSR13		0x0034	/* Synchronization configuration 1 */
59 #define	RT2560_CSR14		0x0038	/* Synchronization control */
60 #define	RT2560_CSR15		0x003c	/* Synchronization status */
61 #define	RT2560_CSR16		0x0040	/* TSF timer 0 */
62 #define	RT2560_CSR17		0x0044	/* TSF timer 1 */
63 #define	RT2560_CSR18		0x0048	/* IFS timer 0 */
64 #define	RT2560_CSR19		0x004c	/* IFS timer 1 */
65 #define	RT2560_CSR20		0x0050	/* WAKEUP timer */
66 #define	RT2560_CSR21		0x0054	/* EEPROM control */
67 #define	RT2560_CSR22		0x0058	/* CFP control */
68 #define	RT2560_TXCSR0		0x0060	/* TX control */
69 #define	RT2560_TXCSR1		0x0064	/* TX configuration */
70 #define	RT2560_TXCSR2		0x0068	/* TX descriptor configuration */
71 #define	RT2560_TXCSR3		0x006c	/* TX ring base address */
72 #define	RT2560_TXCSR4		0x0070	/* TX ATIM ring base address */
73 #define	RT2560_TXCSR5		0x0074	/* TX PRIO ring base address */
74 #define	RT2560_TXCSR6		0x0078	/* Beacon base address */
75 #define	RT2560_TXCSR7		0x007c	/* AutoResponder control */
76 #define	RT2560_RXCSR0		0x0080	/* RX control */
77 #define	RT2560_RXCSR1		0x0084	/* RX descriptor configuration */
78 #define	RT2560_RXCSR2		0x0088	/* RX ring base address */
79 #define	RT2560_PCICSR		0x008c	/* PCI control */
80 #define	RT2560_RXCSR3		0x0090	/* BBP ID 0 */
81 #define	RT2560_TXCSR9		0x0094	/* OFDM TX BBP */
82 #define	RT2560_ARSP_PLCP_0	0x0098	/* Auto Responder PLCP address */
83 #define	RT2560_ARSP_PLCP_1	0x009c	/* Auto Responder Basic Rate mask */
84 #define	RT2560_CNT0		0x00a0	/* FCS error counter */
85 #define	RT2560_CNT1		0x00ac	/* PLCP error counter */
86 #define	RT2560_CNT2		0x00b0	/* Long error counter */
87 #define	RT2560_CNT3		0x00b8	/* CCA false alarm counter */
88 #define	RT2560_CNT4		0x00bc	/* RX FIFO Overflow counter */
89 #define	RT2560_CNT5		0x00c0	/* Tx FIFO Underrun counter */
90 #define	RT2560_PWRCSR0		0x00c4	/* Power mode configuration */
91 #define	RT2560_PSCSR0		0x00c8	/* Power state transition time */
92 #define	RT2560_PSCSR1		0x00cc	/* Power state transition time */
93 #define	RT2560_PSCSR2		0x00d0	/* Power state transition time */
94 #define	RT2560_PSCSR3		0x00d4	/* Power state transition time */
95 #define	RT2560_PWRCSR1		0x00d8	/* Manual power control/status */
96 #define	RT2560_TIMECSR		0x00dc	/* Timer control */
97 #define	RT2560_MACCSR0		0x00e0	/* MAC configuration */
98 #define	RT2560_MACCSR1		0x00e4	/* MAC configuration */
99 #define	RT2560_RALINKCSR	0x00e8	/* Ralink RX auto-reset BBCR */
100 #define	RT2560_BCNCSR		0x00ec	/* Beacon interval control */
101 #define	RT2560_BBPCSR		0x00f0	/* BBP serial control */
102 #define	RT2560_RFCSR		0x00f4	/* RF serial control */
103 #define	RT2560_LEDCSR		0x00f8	/* LED control */
104 #define	RT2560_SECCSR3		0x00fc	/* XXX not documented */
105 #define	RT2560_DMACSR0		0x0100	/* Current RX ring address */
106 #define	RT2560_DMACSR1		0x0104	/* Current Tx ring address */
107 #define	RT2560_DMACSR2		0x0104	/* Current Priority ring address */
108 #define	RT2560_DMACSR3		0x0104	/* Current ATIM ring address */
109 #define	RT2560_TXACKCSR0	0x0110	/* XXX not documented */
110 #define	RT2560_GPIOCSR		0x0120	/* */
111 #define	RT2560_BBBPPCSR		0x0124	/* BBP Pin Control */
112 #define	RT2560_FIFOCSR0		0x0128	/* TX FIFO pointer */
113 #define	RT2560_FIFOCSR1		0x012c	/* RX FIFO pointer */
114 #define	RT2560_BCNOCSR		0x0130	/* Beacon time offset */
115 #define	RT2560_RLPWCSR		0x0134	/* RX_PE Low Width */
116 #define	RT2560_TESTCSR		0x0138	/* Test Mode Select */
117 #define	RT2560_PLCP1MCSR	0x013c	/* Signal/Service/Length of ACK @1M */
118 #define	RT2560_PLCP2MCSR	0x0140	/* Signal/Service/Length of ACK @2M */
119 #define	RT2560_PLCP5p5MCSR	0x0144	/* Signal/Service/Length of ACK @5.5M */
120 #define	RT2560_PLCP11MCSR	0x0148	/* Signal/Service/Length of ACK @11M */
121 #define	RT2560_ACKPCTCSR	0x014c	/* ACK/CTS padload consume time */
122 #define	RT2560_ARTCSR1		0x0150	/* ACK/CTS padload consume time */
123 #define	RT2560_ARTCSR2		0x0154	/* ACK/CTS padload consume time */
124 #define	RT2560_SECCSR1		0x0158	/* WEP control */
125 #define	RT2560_BBPCSR1		0x015c	/* BBP TX Configuration */
126 
127 
128 /* possible flags for register RXCSR0 */
129 #define	RT2560_DISABLE_RX		(1 << 0)
130 #define	RT2560_DROP_CRC_ERROR		(1 << 1)
131 #define	RT2560_DROP_PHY_ERROR		(1 << 2)
132 #define	RT2560_DROP_CTL			(1 << 3)
133 #define	RT2560_DROP_NOT_TO_ME		(1 << 4)
134 #define	RT2560_DROP_TODS		(1 << 5)
135 #define	RT2560_DROP_VERSION_ERROR	(1 << 6)
136 
137 /* possible flags for register CSR1 */
138 #define	RT2560_RESET_ASIC		(1 << 0)
139 #define	RT2560_RESET_BBP		(1 << 1)
140 #define	RT2560_HOST_READY		(1 << 2)
141 
142 /* possible flags for register CSR14 */
143 #define	RT2560_ENABLE_TSF		(1 << 0)
144 #define	RT2560_ENABLE_TSF_SYNC(x)	(((x) & 0x3) << 1)
145 #define	RT2560_ENABLE_TBCN		(1 << 3)
146 #define	RT2560_ENABLE_BEACON_GENERATOR	(1 << 6)
147 
148 /* possible flags for register CSR21 */
149 #define	RT2560_C			(1 << 1)
150 #define	RT2560_S			(1 << 2)
151 #define	RT2560_D			(1 << 3)
152 #define	RT2560_Q			(1 << 4)
153 #define	RT2560_93C46			(1 << 5)
154 
155 #define	RT2560_SHIFT_D			3
156 #define	RT2560_SHIFT_Q			4
157 
158 /* possible flags for register TXCSR0 */
159 #define	RT2560_KICK_TX			(1 << 0)
160 #define	RT2560_KICK_ATIM		(1 << 1)
161 #define	RT2560_KICK_PRIO		(1 << 2)
162 #define	RT2560_ABORT_TX			(1 << 3)
163 
164 /* possible flags for register SECCSR0 */
165 #define	RT2560_KICK_DECRYPT		(1 << 0)
166 
167 /* possible flags for register SECCSR1 */
168 #define	RT2560_KICK_ENCRYPT		(1 << 0)
169 
170 /* possible flags for register CSR7 */
171 #define	RT2560_BEACON_EXPIRE		0x00000001
172 #define	RT2560_WAKEUP_EXPIRE		0x00000002
173 #define	RT2560_ATIM_EXPIRE		0x00000004
174 #define	RT2560_TX_DONE			0x00000008
175 #define	RT2560_ATIM_DONE		0x00000010
176 #define	RT2560_PRIO_DONE		0x00000020
177 #define	RT2560_RX_DONE			0x00000040
178 #define	RT2560_DECRYPTION_DONE		0x00000080
179 #define	RT2560_ENCRYPTION_DONE		0x00000100
180 
181 #define	RT2560_INTR_MASK						\
182 	(~(RT2560_BEACON_EXPIRE | RT2560_WAKEUP_EXPIRE | RT2560_TX_DONE | \
183 	RT2560_PRIO_DONE | RT2560_RX_DONE | RT2560_DECRYPTION_DONE |	  \
184 	RT2560_ENCRYPTION_DONE))
185 
186 #define	RT2560_INTR_ALL							\
187 	(RT2560_BEACON_EXPIRE | RT2560_WAKEUP_EXPIRE | RT2560_TX_DONE |	\
188 	RT2560_PRIO_DONE | RT2560_RX_DONE | RT2560_DECRYPTION_DONE |	\
189 	RT2560_ENCRYPTION_DONE)
190 
191 #pragma pack(1)
192 /* Tx descriptor */
193 struct rt2560_tx_desc {
194 	uint32_t	flags;
195 #define	RT2560_TX_BUSY			(1 << 0)
196 #define	RT2560_TX_VALID			(1 << 1)
197 
198 #define	RT2560_TX_RESULT_MASK		0x0000001c
199 #define	RT2560_TX_SUCCESS		(0 << 2)
200 #define	RT2560_TX_SUCCESS_RETRY		(1 << 2)
201 #define	RT2560_TX_FAIL_RETRY		(2 << 2)
202 #define	RT2560_TX_FAIL_INVALID		(3 << 2)
203 #define	RT2560_TX_FAIL_OTHER		(4 << 2)
204 
205 #define	RT2560_TX_MORE_FRAG		(1 << 8)
206 #define	RT2560_TX_ACK			(1 << 9)
207 #define	RT2560_TX_TIMESTAMP		(1 << 10)
208 #define	RT2560_TX_OFDM			(1 << 11)
209 #define	RT2560_TX_CIPHER_BUSY		(1 << 12)
210 
211 #define	RT2560_TX_IFS_MASK		0x00006000
212 #define	RT2560_TX_IFS_BACKOFF		(0 << 13)
213 #define	RT2560_TX_IFS_SIFS		(1 << 13)
214 #define	RT2560_TX_IFS_NEWBACKOFF	(2 << 13)
215 #define	RT2560_TX_IFS_NONE		(3 << 13)
216 
217 #define	RT2560_TX_LONG_RETRY		(1 << 15)
218 
219 #define	RT2560_TX_CIPHER_MASK		0xe0000000
220 #define	RT2560_TX_CIPHER_NONE		(0 << 29)
221 #define	RT2560_TX_CIPHER_WEP40		(1 << 29)
222 #define	RT2560_TX_CIPHER_WEP104		(2 << 29)
223 #define	RT2560_TX_CIPHER_TKIP		(3 << 29)
224 #define	RT2560_TX_CIPHER_AES		(4 << 29)
225 
226 	uint32_t	physaddr;
227 	uint16_t	wme;
228 #define	RT2560_LOGCWMAX(x)		(((x) & 0xf) << 12)
229 #define	RT2560_LOGCWMIN(x)		(((x) & 0xf) << 8)
230 #define	RT2560_AIFSN(x)			(((x) & 0x3) << 6)
231 #define	RT2560_IVOFFSET(x)		(((x) & 0x3f))
232 
233 	uint16_t	reserved1;
234 	uint8_t		plcp_signal;
235 	uint8_t		plcp_service;
236 #define	RT2560_PLCP_LENGEXT		0x80
237 
238 	uint8_t		plcp_length_lo;
239 	uint8_t		plcp_length_hi;
240 	uint32_t	iv;
241 	uint32_t	eiv;
242 	uint8_t		key[IEEE80211_KEYBUF_SIZE];
243 	uint32_t	reserved2[2];
244 };
245 #pragma pack()
246 
247 #pragma pack(1)
248 /* Rx descriptor */
249 struct rt2560_rx_desc {
250 	uint32_t	flags;
251 #define	RT2560_RX_BUSY		(1 << 0)
252 #define	RT2560_RX_CRC_ERROR	(1 << 5)
253 #define	RT2560_RX_OFDM		(1 << 6)
254 #define	RT2560_RX_PHY_ERROR	(1 << 7)
255 #define	RT2560_RX_CIPHER_BUSY	(1 << 8)
256 #define	RT2560_RX_ICV_ERROR	(1 << 9)
257 
258 #define	RT2560_RX_CIPHER_MASK	0xe0000000
259 #define	RT2560_RX_CIPHER_NONE	(0 << 29)
260 #define	RT2560_RX_CIPHER_WEP40	(1 << 29)
261 #define	RT2560_RX_CIPHER_WEP104	(2 << 29)
262 #define	RT2560_RX_CIPHER_TKIP	(3 << 29)
263 #define	RT2560_RX_CIPHER_AES	(4 << 29)
264 
265 	uint32_t	physaddr;
266 	uint8_t		rate;
267 	uint8_t		rssi;
268 	uint8_t		ta[IEEE80211_ADDR_LEN];
269 	uint32_t	iv;
270 	uint32_t	eiv;
271 	uint8_t		key[IEEE80211_KEYBUF_SIZE];
272 	uint32_t	reserved[2];
273 };
274 #pragma pack()
275 
276 #define	RAL_RF1				0
277 #define	RAL_RF2				2
278 #define	RAL_RF3				1
279 #define	RAL_RF4				3
280 
281 #define	RT2560_RF1_AUTOTUNE		0x08000
282 #define	RT2560_RF3_AUTOTUNE		0x00040
283 
284 #define	RT2560_BBP_BUSY			(1 << 15)
285 #define	RT2560_BBP_WRITE		(1 << 16)
286 #define	RT2560_RF_20BIT			(20 << 24)
287 #define	RT2560_RF_BUSY			((uint32_t)1 << 31)
288 
289 #define	RT2560_RF_2522			0x00
290 #define	RT2560_RF_2523			0x01
291 #define	RT2560_RF_2524			0x02
292 #define	RT2560_RF_2525			0x03
293 #define	RT2560_RF_2525E			0x04
294 #define	RT2560_RF_2526			0x05
295 /* dual-band RF */
296 #define	RT2560_RF_5222			0x10
297 
298 #define	RT2560_BBP_VERSION		0
299 #define	RT2560_BBP_TX			2
300 #define	RT2560_BBP_RX			14
301 
302 #define	RT2560_BBP_ANTA			0x00
303 #define	RT2560_BBP_DIVERSITY		0x01
304 #define	RT2560_BBP_ANTB			0x02
305 #define	RT2560_BBP_ANTMASK		0x03
306 #define	RT2560_BBP_FLIPIQ		0x04
307 
308 #define	RT2560_LED_MODE_DEFAULT		0
309 #define	RT2560_LED_MODE_TXRX_ACTIVITY	1
310 #define	RT2560_LED_MODE_SINGLE		2
311 #define	RT2560_LED_MODE_ASUS		3
312 
313 #define	RT2560_JAPAN_FILTER		0x8
314 
315 #define	RT2560_EEPROM_DELAY		1 /* minimum hold time (microsecond) */
316 
317 #define	RT2560_EEPROM_CONFIG0		16
318 #define	RT2560_EEPROM_BBP_BASE		19
319 #define	RT2560_EEPROM_TXPOWER		35
320 
321 /*
322  * control and status registers access macros
323  */
324 #define	RAL_READ(sc, reg)						\
325 	ddi_get32((sc)->sc_ioh, (uint32_t *)((uintptr_t)(sc)->sc_rbase + (reg)))
326 
327 #define	RAL_WRITE(sc, reg, val)						\
328 	ddi_put32((sc)->sc_ioh,						\
329 	    (uint32_t *)((uintptr_t)(sc)->sc_rbase + (reg)), (val))
330 
331 
332 /*
333  * EEPROM access macro
334  */
335 #define	RT2560_EEPROM_CTL(sc, val) do {					\
336 	_NOTE(CONSTCOND)						\
337 	RAL_WRITE((sc), RT2560_CSR21, (val));				\
338 	drv_usecwait(RT2560_EEPROM_DELAY);				\
339 	_NOTE(CONSTCOND)						\
340 } while (/* CONSTCOND */0)
341 
342 /*
343  * Default values for MAC registers; values taken from the reference driver.
344  */
345 #define	RT2560_DEF_MAC				\
346 	{ RT2560_PSCSR0,	0x00020002 },	\
347 	{ RT2560_PSCSR1,	0x00000002 },	\
348 	{ RT2560_PSCSR2,	0x00020002 },	\
349 	{ RT2560_PSCSR3,	0x00000002 },	\
350 	{ RT2560_TIMECSR,	0x00003f21 },	\
351 	{ RT2560_CSR9,		0x00000780 },	\
352 	{ RT2560_CSR11,		0x07041483 },	\
353 	{ RT2560_CNT3,		0x00000000 },	\
354 	{ RT2560_TXCSR1,	0x07614562 },	\
355 	{ RT2560_ARSP_PLCP_0,	0x8c8d8b8a },	\
356 	{ RT2560_ACKPCTCSR,	0x7038140a },	\
357 	{ RT2560_ARTCSR1,	0x1d21252d },	\
358 	{ RT2560_ARTCSR2,	0x1919191d },	\
359 	{ RT2560_RXCSR0,	0xffffffff },	\
360 	{ RT2560_RXCSR3,	0xb3aab3af },	\
361 	{ RT2560_PCICSR,	0x000003b8 },	\
362 	{ RT2560_PWRCSR0,	0x3f3b3100 },	\
363 	{ RT2560_GPIOCSR,	0x0000ff00 },	\
364 	{ RT2560_TESTCSR,	0x000000f0 },	\
365 	{ RT2560_PWRCSR1,	0x000001ff },	\
366 	{ RT2560_MACCSR0,	0x00213223 },	\
367 	{ RT2560_MACCSR1,	0x00235518 },	\
368 	{ RT2560_RLPWCSR,	0x00000040 },	\
369 	{ RT2560_RALINKCSR,	0x9a009a11 },	\
370 	{ RT2560_CSR7,		0xffffffff },	\
371 	{ RT2560_BBPCSR1,	0x82188200 },	\
372 	{ RT2560_TXACKCSR0,	0x00000020 },	\
373 	{ RT2560_SECCSR3,	0x0000e78f }
374 
375 /*
376  * Default values for BBP registers; values taken from the reference driver.
377  */
378 #define	RT2560_DEF_BBP	\
379 	{  3, 0x02 },	\
380 	{  4, 0x19 },	\
381 	{ 14, 0x1c },	\
382 	{ 15, 0x30 },	\
383 	{ 16, 0xac },	\
384 	{ 17, 0x48 },	\
385 	{ 18, 0x18 },	\
386 	{ 19, 0xff },	\
387 	{ 20, 0x1e },	\
388 	{ 21, 0x08 },	\
389 	{ 22, 0x08 },	\
390 	{ 23, 0x08 },	\
391 	{ 24, 0x80 },	\
392 	{ 25, 0x50 },	\
393 	{ 26, 0x08 },	\
394 	{ 27, 0x23 },	\
395 	{ 30, 0x10 },	\
396 	{ 31, 0x2b },	\
397 	{ 32, 0xb9 },	\
398 	{ 34, 0x12 },	\
399 	{ 35, 0x50 },	\
400 	{ 39, 0xc4 },	\
401 	{ 40, 0x02 },	\
402 	{ 41, 0x60 },	\
403 	{ 53, 0x10 },	\
404 	{ 54, 0x18 },	\
405 	{ 56, 0x08 },	\
406 	{ 57, 0x10 },	\
407 	{ 58, 0x08 },	\
408 	{ 61, 0x60 },	\
409 	{ 62, 0x10 },	\
410 	{ 75, 0xff }
411 
412 /*
413  * Default values for RF register R2 indexed by channel numbers; values taken
414  * from the reference driver.
415  */
416 #define	RT2560_RF2522_R2						\
417 {									\
418 	0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814,	\
419 	0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e	\
420 }
421 
422 #define	RT2560_RF2523_R2						\
423 {									\
424 	0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d,	\
425 	0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346	\
426 }
427 
428 #define	RT2560_RF2524_R2						\
429 {									\
430 	0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d,	\
431 	0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346	\
432 }
433 
434 #define	RT2560_RF2525_R2						\
435 {									\
436 	0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d,	\
437 	0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346	\
438 }
439 
440 #define	RT2560_RF2525_HI_R2						\
441 {									\
442 	0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345,	\
443 	0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e	\
444 }
445 
446 #define	RT2560_RF2525E_R2						\
447 {									\
448 	0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463,	\
449 	0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b	\
450 }
451 
452 #define	RT2560_RF2526_HI_R2						\
453 {									\
454 	0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d,	\
455 	0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241	\
456 }
457 
458 #define	RT2560_RF2526_R2						\
459 {									\
460 	0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229,	\
461 	0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d	\
462 }
463 
464 /*
465  * For dual-band RF, RF registers R1 and R4 also depend on channel number;
466  * values taken from the reference driver.
467  */
468 #define	RT2560_RF5222				\
469 	{   1, 0x08808, 0x0044d, 0x00282 },	\
470 	{   2, 0x08808, 0x0044e, 0x00282 },	\
471 	{   3, 0x08808, 0x0044f, 0x00282 },	\
472 	{   4, 0x08808, 0x00460, 0x00282 },	\
473 	{   5, 0x08808, 0x00461, 0x00282 },	\
474 	{   6, 0x08808, 0x00462, 0x00282 },	\
475 	{   7, 0x08808, 0x00463, 0x00282 },	\
476 	{   8, 0x08808, 0x00464, 0x00282 },	\
477 	{   9, 0x08808, 0x00465, 0x00282 },	\
478 	{  10, 0x08808, 0x00466, 0x00282 },	\
479 	{  11, 0x08808, 0x00467, 0x00282 },	\
480 	{  12, 0x08808, 0x00468, 0x00282 },	\
481 	{  13, 0x08808, 0x00469, 0x00282 },	\
482 	{  14, 0x08808, 0x0046b, 0x00286 },	\
483 						\
484 	{  36, 0x08804, 0x06225, 0x00287 },	\
485 	{  40, 0x08804, 0x06226, 0x00287 },	\
486 	{  44, 0x08804, 0x06227, 0x00287 },	\
487 	{  48, 0x08804, 0x06228, 0x00287 },	\
488 	{  52, 0x08804, 0x06229, 0x00287 },	\
489 	{  56, 0x08804, 0x0622a, 0x00287 },	\
490 	{  60, 0x08804, 0x0622b, 0x00287 },	\
491 	{  64, 0x08804, 0x0622c, 0x00287 },	\
492 						\
493 	{ 100, 0x08804, 0x02200, 0x00283 },	\
494 	{ 104, 0x08804, 0x02201, 0x00283 },	\
495 	{ 108, 0x08804, 0x02202, 0x00283 },	\
496 	{ 112, 0x08804, 0x02203, 0x00283 },	\
497 	{ 116, 0x08804, 0x02204, 0x00283 },	\
498 	{ 120, 0x08804, 0x02205, 0x00283 },	\
499 	{ 124, 0x08804, 0x02206, 0x00283 },	\
500 	{ 128, 0x08804, 0x02207, 0x00283 },	\
501 	{ 132, 0x08804, 0x02208, 0x00283 },	\
502 	{ 136, 0x08804, 0x02209, 0x00283 },	\
503 	{ 140, 0x08804, 0x0220a, 0x00283 },	\
504 						\
505 	{ 149, 0x08808, 0x02429, 0x00281 },	\
506 	{ 153, 0x08808, 0x0242b, 0x00281 },	\
507 	{ 157, 0x08808, 0x0242d, 0x00281 },	\
508 	{ 161, 0x08808, 0x0242f, 0x00281 }
509 
510 #ifdef __cplusplus
511 }
512 #endif
513 
514 #endif /* _RT2560_REG_H */
515