1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2015 Nahanni Systems, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/types.h>
30 #include <sys/mman.h>
31
32 #include <dev/vmm/vmm_mem.h>
33 #include <machine/vmm.h>
34 #include <machine/vmm_snapshot.h>
35 #include <vmmapi.h>
36
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <string.h>
40
41 #include <errno.h>
42 #include <unistd.h>
43
44 #include "bhyvegc.h"
45 #include "bhyverun.h"
46 #include "config.h"
47 #include "debug.h"
48 #include "console.h"
49 #include "pci_emul.h"
50 #include "rfb.h"
51 #ifdef __amd64__
52 #include "amd64/vga.h"
53 #endif
54
55 /*
56 * bhyve Framebuffer device emulation.
57 * BAR0 points to the current mode information.
58 * BAR1 is the 32-bit framebuffer address.
59 *
60 * -s <b>,fbuf,wait,vga=on|io|off,rfb=<ip>:port,w=width,h=height
61 */
62
63 static int fbuf_debug = 1;
64 #define DEBUG_INFO 1
65 #define DEBUG_VERBOSE 4
66 #define DPRINTF(level, params) if (level <= fbuf_debug) PRINTLN params
67
68
69 #define KB (1024UL)
70 #define MB (1024 * 1024UL)
71
72 #define DMEMSZ 128
73
74 #define FB_SIZE (32*MB)
75
76 #define COLS_MAX 3840
77 #define ROWS_MAX 2160
78
79 #define COLS_DEFAULT 1024
80 #define ROWS_DEFAULT 768
81
82 #define COLS_MIN 640
83 #define ROWS_MIN 480
84
85 struct pci_fbuf_softc {
86 struct pci_devinst *fsc_pi;
87 struct {
88 uint32_t fbsize;
89 uint16_t width;
90 uint16_t height;
91 uint16_t depth;
92 uint16_t refreshrate;
93 uint8_t reserved[116];
94 } __packed memregs;
95
96 /* rfb server */
97 char *rfb_host;
98 char *rfb_password;
99 int rfb_port;
100 int rfb_wait;
101 int vga_enabled;
102 int vga_full;
103
104 uint32_t fbaddr;
105 char *fb_base;
106 uint16_t gc_width;
107 uint16_t gc_height;
108 void *vgasc;
109 struct bhyvegc_image *gc_image;
110 };
111
112 static struct pci_fbuf_softc *fbuf_sc;
113
114 #define PCI_FBUF_MSI_MSGS 4
115
116 static void
pci_fbuf_write(struct pci_devinst * pi,int baridx,uint64_t offset,int size,uint64_t value)117 pci_fbuf_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
118 uint64_t value)
119 {
120 struct pci_fbuf_softc *sc;
121 uint8_t *p;
122
123 assert(baridx == 0);
124
125 sc = pi->pi_arg;
126
127 DPRINTF(DEBUG_VERBOSE,
128 ("fbuf wr: offset 0x%lx, size: %d, value: 0x%lx",
129 offset, size, value));
130
131 if (offset + size > DMEMSZ) {
132 printf("fbuf: write too large, offset %ld size %d\n",
133 offset, size);
134 return;
135 }
136
137 p = (uint8_t *)&sc->memregs + offset;
138
139 switch (size) {
140 case 1:
141 *p = value;
142 break;
143 case 2:
144 *(uint16_t *)p = value;
145 break;
146 case 4:
147 *(uint32_t *)p = value;
148 break;
149 case 8:
150 *(uint64_t *)p = value;
151 break;
152 default:
153 printf("fbuf: write unknown size %d\n", size);
154 break;
155 }
156
157 if (!sc->gc_image->vgamode && sc->memregs.width == 0 &&
158 sc->memregs.height == 0) {
159 DPRINTF(DEBUG_INFO, ("switching to VGA mode"));
160 sc->gc_image->vgamode = 1;
161 sc->gc_width = 0;
162 sc->gc_height = 0;
163 } else if (sc->gc_image->vgamode && sc->memregs.width != 0 &&
164 sc->memregs.height != 0) {
165 DPRINTF(DEBUG_INFO, ("switching to VESA mode"));
166 sc->gc_image->vgamode = 0;
167 }
168 }
169
170 static uint64_t
pci_fbuf_read(struct pci_devinst * pi,int baridx,uint64_t offset,int size)171 pci_fbuf_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
172 {
173 struct pci_fbuf_softc *sc;
174 uint8_t *p;
175 uint64_t value;
176
177 assert(baridx == 0);
178
179 sc = pi->pi_arg;
180
181
182 if (offset + size > DMEMSZ) {
183 printf("fbuf: read too large, offset %ld size %d\n",
184 offset, size);
185 return (0);
186 }
187
188 p = (uint8_t *)&sc->memregs + offset;
189 value = 0;
190 switch (size) {
191 case 1:
192 value = *p;
193 break;
194 case 2:
195 value = *(uint16_t *)p;
196 break;
197 case 4:
198 value = *(uint32_t *)p;
199 break;
200 case 8:
201 value = *(uint64_t *)p;
202 break;
203 default:
204 printf("fbuf: read unknown size %d\n", size);
205 break;
206 }
207
208 DPRINTF(DEBUG_VERBOSE,
209 ("fbuf rd: offset 0x%lx, size: %d, value: 0x%lx",
210 offset, size, value));
211
212 return (value);
213 }
214
215 static void
pci_fbuf_baraddr(struct pci_devinst * pi,int baridx,int enabled,uint64_t address)216 pci_fbuf_baraddr(struct pci_devinst *pi, int baridx, int enabled,
217 uint64_t address)
218 {
219 struct pci_fbuf_softc *sc;
220 int prot;
221
222 if (baridx != 1)
223 return;
224
225 sc = pi->pi_arg;
226 if (!enabled) {
227 if (vm_munmap_memseg(pi->pi_vmctx, sc->fbaddr, FB_SIZE) != 0)
228 EPRINTLN("pci_fbuf: munmap_memseg failed");
229 sc->fbaddr = 0;
230 } else {
231 prot = PROT_READ | PROT_WRITE;
232 if (vm_mmap_memseg(pi->pi_vmctx, address, VM_FRAMEBUFFER, 0,
233 FB_SIZE, prot) != 0)
234 EPRINTLN("pci_fbuf: mmap_memseg failed");
235 else
236 sc->fbaddr = address;
237 }
238 }
239
240
241 static int
pci_fbuf_parse_config(struct pci_fbuf_softc * sc,nvlist_t * nvl)242 pci_fbuf_parse_config(struct pci_fbuf_softc *sc, nvlist_t *nvl)
243 {
244 const char *value;
245 char *cp;
246
247 sc->rfb_wait = get_config_bool_node_default(nvl, "wait", false);
248
249 /* Prefer "rfb" to "tcp". */
250 value = get_config_value_node(nvl, "rfb");
251 if (value == NULL)
252 value = get_config_value_node(nvl, "tcp");
253 if (value != NULL) {
254 /*
255 * IPv4 -- host-ip:port
256 * IPv6 -- [host-ip%zone]:port
257 * XXX for now port is mandatory for IPv4.
258 */
259 if (value[0] == '[') {
260 cp = strchr(value + 1, ']');
261 if (cp == NULL || cp == value + 1) {
262 EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"",
263 value);
264 return (-1);
265 }
266 sc->rfb_host = strndup(value + 1, cp - (value + 1));
267 cp++;
268 if (*cp == ':') {
269 cp++;
270 if (*cp == '\0') {
271 EPRINTLN(
272 "fbuf: Missing port number: \"%s\"",
273 value);
274 return (-1);
275 }
276 sc->rfb_port = atoi(cp);
277 } else if (*cp != '\0') {
278 EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"",
279 value);
280 return (-1);
281 }
282 } else {
283 cp = strchr(value, ':');
284 if (cp == NULL) {
285 sc->rfb_port = atoi(value);
286 } else {
287 sc->rfb_host = strndup(value, cp - value);
288 cp++;
289 if (*cp == '\0') {
290 EPRINTLN(
291 "fbuf: Missing port number: \"%s\"",
292 value);
293 return (-1);
294 }
295 sc->rfb_port = atoi(cp);
296 }
297 }
298 }
299
300 value = get_config_value_node(nvl, "vga");
301 if (value != NULL) {
302 if (strcmp(value, "off") == 0) {
303 sc->vga_enabled = 0;
304 } else if (strcmp(value, "io") == 0) {
305 sc->vga_enabled = 1;
306 sc->vga_full = 0;
307 } else if (strcmp(value, "on") == 0) {
308 sc->vga_enabled = 1;
309 sc->vga_full = 1;
310 } else {
311 EPRINTLN("fbuf: Invalid vga setting: \"%s\"", value);
312 return (-1);
313 }
314 }
315
316 value = get_config_value_node(nvl, "w");
317 if (value != NULL)
318 sc->memregs.width = strtol(value, NULL, 10);
319
320 value = get_config_value_node(nvl, "h");
321 if (value != NULL)
322 sc->memregs.height = strtol(value, NULL, 10);
323
324 if (sc->memregs.width > COLS_MAX ||
325 sc->memregs.height > ROWS_MAX) {
326 EPRINTLN("fbuf: max resolution is %ux%u", COLS_MAX, ROWS_MAX);
327 return (-1);
328 }
329 if (sc->memregs.width < COLS_MIN ||
330 sc->memregs.height < ROWS_MIN) {
331 EPRINTLN("fbuf: minimum resolution is %ux%u",
332 COLS_MIN, ROWS_MIN);
333 return (-1);
334 }
335
336 value = get_config_value_node(nvl, "password");
337 if (value != NULL)
338 sc->rfb_password = strdup(value);
339
340 return (0);
341 }
342
343 static void
pci_fbuf_render(struct bhyvegc * gc,void * arg)344 pci_fbuf_render(struct bhyvegc *gc, void *arg)
345 {
346 struct pci_fbuf_softc *sc;
347
348 sc = arg;
349
350 if (sc->vga_full && sc->gc_image->vgamode) {
351 /* TODO: mode switching to vga and vesa should use the special
352 * EFI-bhyve protocol port.
353 */
354 vga_render(gc, sc->vgasc);
355 return;
356 }
357 if (sc->gc_width != sc->memregs.width ||
358 sc->gc_height != sc->memregs.height) {
359 bhyvegc_resize(gc, sc->memregs.width, sc->memregs.height);
360 sc->gc_width = sc->memregs.width;
361 sc->gc_height = sc->memregs.height;
362 }
363 }
364
365 static int
pci_fbuf_init(struct pci_devinst * pi,nvlist_t * nvl)366 pci_fbuf_init(struct pci_devinst *pi, nvlist_t *nvl)
367 {
368 int error;
369 struct pci_fbuf_softc *sc;
370
371 if (fbuf_sc != NULL) {
372 EPRINTLN("Only one frame buffer device is allowed.");
373 return (-1);
374 }
375
376 sc = calloc(1, sizeof(struct pci_fbuf_softc));
377
378 pi->pi_arg = sc;
379
380 /* initialize config space */
381 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x40FB);
382 pci_set_cfgdata16(pi, PCIR_VENDOR, 0xFB5D);
383 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_DISPLAY);
384 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_DISPLAY_VGA);
385
386 sc->fb_base = vm_create_devmem(pi->pi_vmctx, VM_FRAMEBUFFER,
387 "framebuffer", FB_SIZE);
388 if (sc->fb_base == MAP_FAILED) {
389 error = -1;
390 goto done;
391 }
392
393 error = pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, DMEMSZ);
394 assert(error == 0);
395
396 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, FB_SIZE);
397 assert(error == 0);
398
399 error = pci_emul_add_msicap(pi, PCI_FBUF_MSI_MSGS);
400 assert(error == 0);
401
402 sc->memregs.fbsize = FB_SIZE;
403 sc->memregs.width = COLS_DEFAULT;
404 sc->memregs.height = ROWS_DEFAULT;
405 sc->memregs.depth = 32;
406
407 sc->vga_enabled = 1;
408 sc->vga_full = 0;
409
410 sc->fsc_pi = pi;
411
412 error = pci_fbuf_parse_config(sc, nvl);
413 if (error != 0)
414 goto done;
415
416 /* XXX until VGA rendering is enabled */
417 if (sc->vga_full != 0) {
418 EPRINTLN("pci_fbuf: VGA rendering not enabled");
419 goto done;
420 }
421
422 DPRINTF(DEBUG_INFO, ("fbuf frame buffer base: %p [sz %lu]",
423 sc->fb_base, FB_SIZE));
424
425 console_init(sc->memregs.width, sc->memregs.height, sc->fb_base);
426 console_fb_register(pci_fbuf_render, sc);
427
428 if (sc->vga_enabled)
429 sc->vgasc = vga_init(!sc->vga_full);
430 sc->gc_image = console_get_image();
431
432 fbuf_sc = sc;
433
434 memset((void *)sc->fb_base, 0, FB_SIZE);
435
436 error = rfb_init(sc->rfb_host, sc->rfb_port, sc->rfb_wait, sc->rfb_password);
437 done:
438 if (error)
439 free(sc);
440
441 return (error);
442 }
443
444 #ifdef BHYVE_SNAPSHOT
445 static int
pci_fbuf_snapshot(struct vm_snapshot_meta * meta)446 pci_fbuf_snapshot(struct vm_snapshot_meta *meta)
447 {
448 int ret;
449
450 SNAPSHOT_BUF_OR_LEAVE(fbuf_sc->fb_base, FB_SIZE, meta, ret, err);
451
452 err:
453 return (ret);
454 }
455 #endif
456
457 static const struct pci_devemu pci_fbuf = {
458 .pe_emu = "fbuf",
459 .pe_init = pci_fbuf_init,
460 .pe_barwrite = pci_fbuf_write,
461 .pe_barread = pci_fbuf_read,
462 .pe_baraddr = pci_fbuf_baraddr,
463 #ifdef BHYVE_SNAPSHOT
464 .pe_snapshot = pci_fbuf_snapshot,
465 #endif
466 };
467 PCI_EMUL_SET(pci_fbuf);
468