1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio 4 * interfaces 5 * 6 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se> 7 * 8 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control 9 * code. 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/pci.h> 16 #include <linux/module.h> 17 #include <linux/vmalloc.h> 18 #include <linux/io.h> 19 20 #include <sound/core.h> 21 #include <sound/info.h> 22 #include <sound/control.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/asoundef.h> 26 #include <sound/initval.h> 27 28 /* note, two last pcis should be equal, it is not a bug */ 29 30 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>"); 31 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, " 32 "Digi96/8 PAD"); 33 MODULE_LICENSE("GPL"); 34 35 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 36 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 37 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 38 39 module_param_array(index, int, NULL, 0444); 40 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard."); 41 module_param_array(id, charp, NULL, 0444); 42 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard."); 43 module_param_array(enable, bool, NULL, 0444); 44 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard."); 45 46 /* 47 * Defines for RME Digi96 series, from internal RME reference documents 48 * dated 12.01.00 49 */ 50 51 #define RME96_SPDIF_NCHANNELS 2 52 53 /* Playback and capture buffer size */ 54 #define RME96_BUFFER_SIZE 0x10000 55 56 /* IO area size */ 57 #define RME96_IO_SIZE 0x60000 58 59 /* IO area offsets */ 60 #define RME96_IO_PLAY_BUFFER 0x0 61 #define RME96_IO_REC_BUFFER 0x10000 62 #define RME96_IO_CONTROL_REGISTER 0x20000 63 #define RME96_IO_ADDITIONAL_REG 0x20004 64 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008 65 #define RME96_IO_CONFIRM_REC_IRQ 0x2000C 66 #define RME96_IO_SET_PLAY_POS 0x40000 67 #define RME96_IO_RESET_PLAY_POS 0x4FFFC 68 #define RME96_IO_SET_REC_POS 0x50000 69 #define RME96_IO_RESET_REC_POS 0x5FFFC 70 #define RME96_IO_GET_PLAY_POS 0x20000 71 #define RME96_IO_GET_REC_POS 0x30000 72 73 /* Write control register bits */ 74 #define RME96_WCR_START (1 << 0) 75 #define RME96_WCR_START_2 (1 << 1) 76 #define RME96_WCR_GAIN_0 (1 << 2) 77 #define RME96_WCR_GAIN_1 (1 << 3) 78 #define RME96_WCR_MODE24 (1 << 4) 79 #define RME96_WCR_MODE24_2 (1 << 5) 80 #define RME96_WCR_BM (1 << 6) 81 #define RME96_WCR_BM_2 (1 << 7) 82 #define RME96_WCR_ADAT (1 << 8) 83 #define RME96_WCR_FREQ_0 (1 << 9) 84 #define RME96_WCR_FREQ_1 (1 << 10) 85 #define RME96_WCR_DS (1 << 11) 86 #define RME96_WCR_PRO (1 << 12) 87 #define RME96_WCR_EMP (1 << 13) 88 #define RME96_WCR_SEL (1 << 14) 89 #define RME96_WCR_MASTER (1 << 15) 90 #define RME96_WCR_PD (1 << 16) 91 #define RME96_WCR_INP_0 (1 << 17) 92 #define RME96_WCR_INP_1 (1 << 18) 93 #define RME96_WCR_THRU_0 (1 << 19) 94 #define RME96_WCR_THRU_1 (1 << 20) 95 #define RME96_WCR_THRU_2 (1 << 21) 96 #define RME96_WCR_THRU_3 (1 << 22) 97 #define RME96_WCR_THRU_4 (1 << 23) 98 #define RME96_WCR_THRU_5 (1 << 24) 99 #define RME96_WCR_THRU_6 (1 << 25) 100 #define RME96_WCR_THRU_7 (1 << 26) 101 #define RME96_WCR_DOLBY (1 << 27) 102 #define RME96_WCR_MONITOR_0 (1 << 28) 103 #define RME96_WCR_MONITOR_1 (1 << 29) 104 #define RME96_WCR_ISEL (1 << 30) 105 #define RME96_WCR_IDIS (1 << 31) 106 107 #define RME96_WCR_BITPOS_GAIN_0 2 108 #define RME96_WCR_BITPOS_GAIN_1 3 109 #define RME96_WCR_BITPOS_FREQ_0 9 110 #define RME96_WCR_BITPOS_FREQ_1 10 111 #define RME96_WCR_BITPOS_INP_0 17 112 #define RME96_WCR_BITPOS_INP_1 18 113 #define RME96_WCR_BITPOS_MONITOR_0 28 114 #define RME96_WCR_BITPOS_MONITOR_1 29 115 116 /* Read control register bits */ 117 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF 118 #define RME96_RCR_IRQ_2 (1 << 16) 119 #define RME96_RCR_T_OUT (1 << 17) 120 #define RME96_RCR_DEV_ID_0 (1 << 21) 121 #define RME96_RCR_DEV_ID_1 (1 << 22) 122 #define RME96_RCR_LOCK (1 << 23) 123 #define RME96_RCR_VERF (1 << 26) 124 #define RME96_RCR_F0 (1 << 27) 125 #define RME96_RCR_F1 (1 << 28) 126 #define RME96_RCR_F2 (1 << 29) 127 #define RME96_RCR_AUTOSYNC (1 << 30) 128 #define RME96_RCR_IRQ (1 << 31) 129 130 #define RME96_RCR_BITPOS_F0 27 131 #define RME96_RCR_BITPOS_F1 28 132 #define RME96_RCR_BITPOS_F2 29 133 134 /* Additional register bits */ 135 #define RME96_AR_WSEL (1 << 0) 136 #define RME96_AR_ANALOG (1 << 1) 137 #define RME96_AR_FREQPAD_0 (1 << 2) 138 #define RME96_AR_FREQPAD_1 (1 << 3) 139 #define RME96_AR_FREQPAD_2 (1 << 4) 140 #define RME96_AR_PD2 (1 << 5) 141 #define RME96_AR_DAC_EN (1 << 6) 142 #define RME96_AR_CLATCH (1 << 7) 143 #define RME96_AR_CCLK (1 << 8) 144 #define RME96_AR_CDATA (1 << 9) 145 146 #define RME96_AR_BITPOS_F0 2 147 #define RME96_AR_BITPOS_F1 3 148 #define RME96_AR_BITPOS_F2 4 149 150 /* Monitor tracks */ 151 #define RME96_MONITOR_TRACKS_1_2 0 152 #define RME96_MONITOR_TRACKS_3_4 1 153 #define RME96_MONITOR_TRACKS_5_6 2 154 #define RME96_MONITOR_TRACKS_7_8 3 155 156 /* Attenuation */ 157 #define RME96_ATTENUATION_0 0 158 #define RME96_ATTENUATION_6 1 159 #define RME96_ATTENUATION_12 2 160 #define RME96_ATTENUATION_18 3 161 162 /* Input types */ 163 #define RME96_INPUT_OPTICAL 0 164 #define RME96_INPUT_COAXIAL 1 165 #define RME96_INPUT_INTERNAL 2 166 #define RME96_INPUT_XLR 3 167 #define RME96_INPUT_ANALOG 4 168 169 /* Clock modes */ 170 #define RME96_CLOCKMODE_SLAVE 0 171 #define RME96_CLOCKMODE_MASTER 1 172 #define RME96_CLOCKMODE_WORDCLOCK 2 173 174 /* Block sizes in bytes */ 175 #define RME96_SMALL_BLOCK_SIZE 2048 176 #define RME96_LARGE_BLOCK_SIZE 8192 177 178 /* Volume control */ 179 #define RME96_AD1852_VOL_BITS 14 180 #define RME96_AD1855_VOL_BITS 10 181 182 /* Defines for snd_rme96_trigger */ 183 #define RME96_TB_START_PLAYBACK 1 184 #define RME96_TB_START_CAPTURE 2 185 #define RME96_TB_STOP_PLAYBACK 4 186 #define RME96_TB_STOP_CAPTURE 8 187 #define RME96_TB_RESET_PLAYPOS 16 188 #define RME96_TB_RESET_CAPTUREPOS 32 189 #define RME96_TB_CLEAR_PLAYBACK_IRQ 64 190 #define RME96_TB_CLEAR_CAPTURE_IRQ 128 191 #define RME96_RESUME_PLAYBACK (RME96_TB_START_PLAYBACK) 192 #define RME96_RESUME_CAPTURE (RME96_TB_START_CAPTURE) 193 #define RME96_RESUME_BOTH (RME96_RESUME_PLAYBACK \ 194 | RME96_RESUME_CAPTURE) 195 #define RME96_START_PLAYBACK (RME96_TB_START_PLAYBACK \ 196 | RME96_TB_RESET_PLAYPOS) 197 #define RME96_START_CAPTURE (RME96_TB_START_CAPTURE \ 198 | RME96_TB_RESET_CAPTUREPOS) 199 #define RME96_START_BOTH (RME96_START_PLAYBACK \ 200 | RME96_START_CAPTURE) 201 #define RME96_STOP_PLAYBACK (RME96_TB_STOP_PLAYBACK \ 202 | RME96_TB_CLEAR_PLAYBACK_IRQ) 203 #define RME96_STOP_CAPTURE (RME96_TB_STOP_CAPTURE \ 204 | RME96_TB_CLEAR_CAPTURE_IRQ) 205 #define RME96_STOP_BOTH (RME96_STOP_PLAYBACK \ 206 | RME96_STOP_CAPTURE) 207 208 struct rme96 { 209 spinlock_t lock; 210 int irq; 211 unsigned long port; 212 void __iomem *iobase; 213 214 u32 wcreg; /* cached write control register value */ 215 u32 wcreg_spdif; /* S/PDIF setup */ 216 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */ 217 u32 rcreg; /* cached read control register value */ 218 u32 areg; /* cached additional register value */ 219 u16 vol[2]; /* cached volume of analog output */ 220 221 u8 rev; /* card revision number */ 222 223 u32 playback_pointer; 224 u32 capture_pointer; 225 void *playback_suspend_buffer; 226 void *capture_suspend_buffer; 227 228 struct snd_pcm_substream *playback_substream; 229 struct snd_pcm_substream *capture_substream; 230 231 int playback_frlog; /* log2 of framesize */ 232 int capture_frlog; 233 234 size_t playback_periodsize; /* in bytes, zero if not used */ 235 size_t capture_periodsize; /* in bytes, zero if not used */ 236 237 struct snd_card *card; 238 struct snd_pcm *spdif_pcm; 239 struct snd_pcm *adat_pcm; 240 struct pci_dev *pci; 241 struct snd_kcontrol *spdif_ctl; 242 }; 243 244 static const struct pci_device_id snd_rme96_ids[] = { 245 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, }, 246 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, }, 247 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, }, 248 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, }, 249 { 0, } 250 }; 251 252 MODULE_DEVICE_TABLE(pci, snd_rme96_ids); 253 254 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START) 255 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2) 256 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST) 257 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \ 258 (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST) 259 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4) 260 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \ 261 ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2)) 262 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1) 263 264 static int 265 snd_rme96_playback_prepare(struct snd_pcm_substream *substream); 266 267 static int 268 snd_rme96_capture_prepare(struct snd_pcm_substream *substream); 269 270 static int 271 snd_rme96_playback_trigger(struct snd_pcm_substream *substream, 272 int cmd); 273 274 static int 275 snd_rme96_capture_trigger(struct snd_pcm_substream *substream, 276 int cmd); 277 278 static snd_pcm_uframes_t 279 snd_rme96_playback_pointer(struct snd_pcm_substream *substream); 280 281 static snd_pcm_uframes_t 282 snd_rme96_capture_pointer(struct snd_pcm_substream *substream); 283 284 static void snd_rme96_proc_init(struct rme96 *rme96); 285 286 static int 287 snd_rme96_create_switches(struct snd_card *card, 288 struct rme96 *rme96); 289 290 static int 291 snd_rme96_getinputtype(struct rme96 *rme96); 292 293 static inline unsigned int 294 snd_rme96_playback_ptr(struct rme96 *rme96) 295 { 296 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS) 297 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog; 298 } 299 300 static inline unsigned int 301 snd_rme96_capture_ptr(struct rme96 *rme96) 302 { 303 return (readl(rme96->iobase + RME96_IO_GET_REC_POS) 304 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog; 305 } 306 307 static int 308 snd_rme96_playback_silence(struct snd_pcm_substream *substream, 309 int channel, unsigned long pos, unsigned long count) 310 { 311 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 312 313 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, 314 0, count); 315 return 0; 316 } 317 318 static int 319 snd_rme96_playback_copy(struct snd_pcm_substream *substream, 320 int channel, unsigned long pos, 321 struct iov_iter *src, unsigned long count) 322 { 323 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 324 325 if (copy_from_iter_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, 326 count, src) != count) 327 return -EFAULT; 328 return 0; 329 } 330 331 static int 332 snd_rme96_capture_copy(struct snd_pcm_substream *substream, 333 int channel, unsigned long pos, 334 struct iov_iter *dst, unsigned long count) 335 { 336 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 337 338 if (copy_to_iter_fromio(rme96->iobase + RME96_IO_REC_BUFFER + pos, 339 count, dst) != count) 340 return -EFAULT; 341 return 0; 342 } 343 344 /* 345 * Digital output capabilities (S/PDIF) 346 */ 347 static const struct snd_pcm_hardware snd_rme96_playback_spdif_info = 348 { 349 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 350 SNDRV_PCM_INFO_MMAP_VALID | 351 SNDRV_PCM_INFO_SYNC_START | 352 SNDRV_PCM_INFO_RESUME | 353 SNDRV_PCM_INFO_INTERLEAVED | 354 SNDRV_PCM_INFO_PAUSE), 355 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 356 SNDRV_PCM_FMTBIT_S32_LE), 357 .rates = (SNDRV_PCM_RATE_32000 | 358 SNDRV_PCM_RATE_44100 | 359 SNDRV_PCM_RATE_48000 | 360 SNDRV_PCM_RATE_64000 | 361 SNDRV_PCM_RATE_88200 | 362 SNDRV_PCM_RATE_96000), 363 .rate_min = 32000, 364 .rate_max = 96000, 365 .channels_min = 2, 366 .channels_max = 2, 367 .buffer_bytes_max = RME96_BUFFER_SIZE, 368 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 369 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 370 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 371 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 372 .fifo_size = 0, 373 }; 374 375 /* 376 * Digital input capabilities (S/PDIF) 377 */ 378 static const struct snd_pcm_hardware snd_rme96_capture_spdif_info = 379 { 380 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 381 SNDRV_PCM_INFO_MMAP_VALID | 382 SNDRV_PCM_INFO_SYNC_START | 383 SNDRV_PCM_INFO_RESUME | 384 SNDRV_PCM_INFO_INTERLEAVED | 385 SNDRV_PCM_INFO_PAUSE), 386 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 387 SNDRV_PCM_FMTBIT_S32_LE), 388 .rates = (SNDRV_PCM_RATE_32000 | 389 SNDRV_PCM_RATE_44100 | 390 SNDRV_PCM_RATE_48000 | 391 SNDRV_PCM_RATE_64000 | 392 SNDRV_PCM_RATE_88200 | 393 SNDRV_PCM_RATE_96000), 394 .rate_min = 32000, 395 .rate_max = 96000, 396 .channels_min = 2, 397 .channels_max = 2, 398 .buffer_bytes_max = RME96_BUFFER_SIZE, 399 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 400 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 401 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 402 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 403 .fifo_size = 0, 404 }; 405 406 /* 407 * Digital output capabilities (ADAT) 408 */ 409 static const struct snd_pcm_hardware snd_rme96_playback_adat_info = 410 { 411 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 412 SNDRV_PCM_INFO_MMAP_VALID | 413 SNDRV_PCM_INFO_SYNC_START | 414 SNDRV_PCM_INFO_RESUME | 415 SNDRV_PCM_INFO_INTERLEAVED | 416 SNDRV_PCM_INFO_PAUSE), 417 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 418 SNDRV_PCM_FMTBIT_S32_LE), 419 .rates = (SNDRV_PCM_RATE_44100 | 420 SNDRV_PCM_RATE_48000), 421 .rate_min = 44100, 422 .rate_max = 48000, 423 .channels_min = 8, 424 .channels_max = 8, 425 .buffer_bytes_max = RME96_BUFFER_SIZE, 426 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 427 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 428 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 429 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 430 .fifo_size = 0, 431 }; 432 433 /* 434 * Digital input capabilities (ADAT) 435 */ 436 static const struct snd_pcm_hardware snd_rme96_capture_adat_info = 437 { 438 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 439 SNDRV_PCM_INFO_MMAP_VALID | 440 SNDRV_PCM_INFO_SYNC_START | 441 SNDRV_PCM_INFO_RESUME | 442 SNDRV_PCM_INFO_INTERLEAVED | 443 SNDRV_PCM_INFO_PAUSE), 444 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 445 SNDRV_PCM_FMTBIT_S32_LE), 446 .rates = (SNDRV_PCM_RATE_44100 | 447 SNDRV_PCM_RATE_48000), 448 .rate_min = 44100, 449 .rate_max = 48000, 450 .channels_min = 8, 451 .channels_max = 8, 452 .buffer_bytes_max = RME96_BUFFER_SIZE, 453 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 454 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 455 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 456 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 457 .fifo_size = 0, 458 }; 459 460 /* 461 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface 462 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up 463 * on the falling edge of CCLK and be stable on the rising edge. The rising 464 * edge of CLATCH after the last data bit clocks in the whole data word. 465 * A fast processor could probably drive the SPI interface faster than the 466 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1) 467 * limits the data rate to 500KHz and only causes a delay of 33 microsecs. 468 * 469 * NOTE: increased delay from 1 to 10, since there where problems setting 470 * the volume. 471 */ 472 static void 473 snd_rme96_write_SPI(struct rme96 *rme96, u16 val) 474 { 475 int i; 476 477 for (i = 0; i < 16; i++) { 478 if (val & 0x8000) { 479 rme96->areg |= RME96_AR_CDATA; 480 } else { 481 rme96->areg &= ~RME96_AR_CDATA; 482 } 483 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH); 484 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 485 udelay(10); 486 rme96->areg |= RME96_AR_CCLK; 487 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 488 udelay(10); 489 val <<= 1; 490 } 491 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA); 492 rme96->areg |= RME96_AR_CLATCH; 493 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 494 udelay(10); 495 rme96->areg &= ~RME96_AR_CLATCH; 496 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 497 } 498 499 static void 500 snd_rme96_apply_dac_volume(struct rme96 *rme96) 501 { 502 if (RME96_DAC_IS_1852(rme96)) { 503 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0); 504 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2); 505 } else if (RME96_DAC_IS_1855(rme96)) { 506 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000); 507 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400); 508 } 509 } 510 511 static void 512 snd_rme96_reset_dac(struct rme96 *rme96) 513 { 514 writel(rme96->wcreg | RME96_WCR_PD, 515 rme96->iobase + RME96_IO_CONTROL_REGISTER); 516 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 517 } 518 519 static int 520 snd_rme96_getmontracks(struct rme96 *rme96) 521 { 522 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) + 523 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1); 524 } 525 526 static int 527 snd_rme96_setmontracks(struct rme96 *rme96, 528 int montracks) 529 { 530 if (montracks & 1) { 531 rme96->wcreg |= RME96_WCR_MONITOR_0; 532 } else { 533 rme96->wcreg &= ~RME96_WCR_MONITOR_0; 534 } 535 if (montracks & 2) { 536 rme96->wcreg |= RME96_WCR_MONITOR_1; 537 } else { 538 rme96->wcreg &= ~RME96_WCR_MONITOR_1; 539 } 540 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 541 return 0; 542 } 543 544 static int 545 snd_rme96_getattenuation(struct rme96 *rme96) 546 { 547 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) + 548 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1); 549 } 550 551 static int 552 snd_rme96_setattenuation(struct rme96 *rme96, 553 int attenuation) 554 { 555 switch (attenuation) { 556 case 0: 557 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) & 558 ~RME96_WCR_GAIN_1; 559 break; 560 case 1: 561 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) & 562 ~RME96_WCR_GAIN_1; 563 break; 564 case 2: 565 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) | 566 RME96_WCR_GAIN_1; 567 break; 568 case 3: 569 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) | 570 RME96_WCR_GAIN_1; 571 break; 572 default: 573 return -EINVAL; 574 } 575 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 576 return 0; 577 } 578 579 static int 580 snd_rme96_capture_getrate(struct rme96 *rme96, 581 int *is_adat) 582 { 583 int n, rate; 584 585 *is_adat = 0; 586 if (rme96->areg & RME96_AR_ANALOG) { 587 /* Analog input, overrides S/PDIF setting */ 588 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) + 589 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1); 590 switch (n) { 591 case 1: 592 rate = 32000; 593 break; 594 case 2: 595 rate = 44100; 596 break; 597 case 3: 598 rate = 48000; 599 break; 600 default: 601 return -1; 602 } 603 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate; 604 } 605 606 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 607 if (rme96->rcreg & RME96_RCR_LOCK) { 608 /* ADAT rate */ 609 *is_adat = 1; 610 if (rme96->rcreg & RME96_RCR_T_OUT) { 611 return 48000; 612 } 613 return 44100; 614 } 615 616 if (rme96->rcreg & RME96_RCR_VERF) { 617 return -1; 618 } 619 620 /* S/PDIF rate */ 621 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) + 622 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) + 623 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2); 624 625 switch (n) { 626 case 0: 627 if (rme96->rcreg & RME96_RCR_T_OUT) { 628 return 64000; 629 } 630 return -1; 631 case 3: return 96000; 632 case 4: return 88200; 633 case 5: return 48000; 634 case 6: return 44100; 635 case 7: return 32000; 636 default: 637 break; 638 } 639 return -1; 640 } 641 642 static int 643 snd_rme96_playback_getrate(struct rme96 *rme96) 644 { 645 int rate, dummy; 646 647 if (!(rme96->wcreg & RME96_WCR_MASTER) && 648 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) { 649 rate = snd_rme96_capture_getrate(rme96, &dummy); 650 if (rate > 0) { 651 /* slave clock */ 652 return rate; 653 } 654 } 655 656 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) + 657 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1); 658 switch (rate) { 659 case 1: 660 rate = 32000; 661 break; 662 case 2: 663 rate = 44100; 664 break; 665 case 3: 666 rate = 48000; 667 break; 668 default: 669 return -1; 670 } 671 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate; 672 } 673 674 static int 675 snd_rme96_playback_setrate(struct rme96 *rme96, 676 int rate) 677 { 678 int ds; 679 680 ds = rme96->wcreg & RME96_WCR_DS; 681 switch (rate) { 682 case 32000: 683 rme96->wcreg &= ~RME96_WCR_DS; 684 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & 685 ~RME96_WCR_FREQ_1; 686 break; 687 case 44100: 688 rme96->wcreg &= ~RME96_WCR_DS; 689 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & 690 ~RME96_WCR_FREQ_0; 691 break; 692 case 48000: 693 rme96->wcreg &= ~RME96_WCR_DS; 694 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | 695 RME96_WCR_FREQ_1; 696 break; 697 case 64000: 698 rme96->wcreg |= RME96_WCR_DS; 699 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & 700 ~RME96_WCR_FREQ_1; 701 break; 702 case 88200: 703 rme96->wcreg |= RME96_WCR_DS; 704 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & 705 ~RME96_WCR_FREQ_0; 706 break; 707 case 96000: 708 rme96->wcreg |= RME96_WCR_DS; 709 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | 710 RME96_WCR_FREQ_1; 711 break; 712 default: 713 return -EINVAL; 714 } 715 if ((!ds && rme96->wcreg & RME96_WCR_DS) || 716 (ds && !(rme96->wcreg & RME96_WCR_DS))) 717 { 718 /* change to/from double-speed: reset the DAC (if available) */ 719 snd_rme96_reset_dac(rme96); 720 return 1; /* need to restore volume */ 721 } else { 722 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 723 return 0; 724 } 725 } 726 727 static int 728 snd_rme96_capture_analog_setrate(struct rme96 *rme96, 729 int rate) 730 { 731 switch (rate) { 732 case 32000: 733 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & 734 ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; 735 break; 736 case 44100: 737 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | 738 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; 739 break; 740 case 48000: 741 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | 742 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; 743 break; 744 case 64000: 745 if (rme96->rev < 4) { 746 return -EINVAL; 747 } 748 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & 749 ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; 750 break; 751 case 88200: 752 if (rme96->rev < 4) { 753 return -EINVAL; 754 } 755 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | 756 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; 757 break; 758 case 96000: 759 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | 760 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; 761 break; 762 default: 763 return -EINVAL; 764 } 765 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 766 return 0; 767 } 768 769 static int 770 snd_rme96_setclockmode(struct rme96 *rme96, 771 int mode) 772 { 773 switch (mode) { 774 case RME96_CLOCKMODE_SLAVE: 775 /* AutoSync */ 776 rme96->wcreg &= ~RME96_WCR_MASTER; 777 rme96->areg &= ~RME96_AR_WSEL; 778 break; 779 case RME96_CLOCKMODE_MASTER: 780 /* Internal */ 781 rme96->wcreg |= RME96_WCR_MASTER; 782 rme96->areg &= ~RME96_AR_WSEL; 783 break; 784 case RME96_CLOCKMODE_WORDCLOCK: 785 /* Word clock is a master mode */ 786 rme96->wcreg |= RME96_WCR_MASTER; 787 rme96->areg |= RME96_AR_WSEL; 788 break; 789 default: 790 return -EINVAL; 791 } 792 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 793 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 794 return 0; 795 } 796 797 static int 798 snd_rme96_getclockmode(struct rme96 *rme96) 799 { 800 if (rme96->areg & RME96_AR_WSEL) { 801 return RME96_CLOCKMODE_WORDCLOCK; 802 } 803 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER : 804 RME96_CLOCKMODE_SLAVE; 805 } 806 807 static int 808 snd_rme96_setinputtype(struct rme96 *rme96, 809 int type) 810 { 811 int n; 812 813 switch (type) { 814 case RME96_INPUT_OPTICAL: 815 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) & 816 ~RME96_WCR_INP_1; 817 break; 818 case RME96_INPUT_COAXIAL: 819 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) & 820 ~RME96_WCR_INP_1; 821 break; 822 case RME96_INPUT_INTERNAL: 823 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) | 824 RME96_WCR_INP_1; 825 break; 826 case RME96_INPUT_XLR: 827 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && 828 rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) || 829 (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && 830 rme96->rev > 4)) 831 { 832 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */ 833 return -EINVAL; 834 } 835 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) | 836 RME96_WCR_INP_1; 837 break; 838 case RME96_INPUT_ANALOG: 839 if (!RME96_HAS_ANALOG_IN(rme96)) { 840 return -EINVAL; 841 } 842 rme96->areg |= RME96_AR_ANALOG; 843 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 844 if (rme96->rev < 4) { 845 /* 846 * Revision less than 004 does not support 64 and 847 * 88.2 kHz 848 */ 849 if (snd_rme96_capture_getrate(rme96, &n) == 88200) { 850 snd_rme96_capture_analog_setrate(rme96, 44100); 851 } 852 if (snd_rme96_capture_getrate(rme96, &n) == 64000) { 853 snd_rme96_capture_analog_setrate(rme96, 32000); 854 } 855 } 856 return 0; 857 default: 858 return -EINVAL; 859 } 860 if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) { 861 rme96->areg &= ~RME96_AR_ANALOG; 862 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 863 } 864 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 865 return 0; 866 } 867 868 static int 869 snd_rme96_getinputtype(struct rme96 *rme96) 870 { 871 if (rme96->areg & RME96_AR_ANALOG) { 872 return RME96_INPUT_ANALOG; 873 } 874 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) + 875 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1); 876 } 877 878 static void 879 snd_rme96_setframelog(struct rme96 *rme96, 880 int n_channels, 881 int is_playback) 882 { 883 int frlog; 884 885 if (n_channels == 2) { 886 frlog = 1; 887 } else { 888 /* assume 8 channels */ 889 frlog = 3; 890 } 891 if (is_playback) { 892 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1; 893 rme96->playback_frlog = frlog; 894 } else { 895 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1; 896 rme96->capture_frlog = frlog; 897 } 898 } 899 900 static int 901 snd_rme96_playback_setformat(struct rme96 *rme96, snd_pcm_format_t format) 902 { 903 switch (format) { 904 case SNDRV_PCM_FORMAT_S16_LE: 905 rme96->wcreg &= ~RME96_WCR_MODE24; 906 break; 907 case SNDRV_PCM_FORMAT_S32_LE: 908 rme96->wcreg |= RME96_WCR_MODE24; 909 break; 910 default: 911 return -EINVAL; 912 } 913 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 914 return 0; 915 } 916 917 static int 918 snd_rme96_capture_setformat(struct rme96 *rme96, snd_pcm_format_t format) 919 { 920 switch (format) { 921 case SNDRV_PCM_FORMAT_S16_LE: 922 rme96->wcreg &= ~RME96_WCR_MODE24_2; 923 break; 924 case SNDRV_PCM_FORMAT_S32_LE: 925 rme96->wcreg |= RME96_WCR_MODE24_2; 926 break; 927 default: 928 return -EINVAL; 929 } 930 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 931 return 0; 932 } 933 934 static void 935 snd_rme96_set_period_properties(struct rme96 *rme96, 936 size_t period_bytes) 937 { 938 switch (period_bytes) { 939 case RME96_LARGE_BLOCK_SIZE: 940 rme96->wcreg &= ~RME96_WCR_ISEL; 941 break; 942 case RME96_SMALL_BLOCK_SIZE: 943 rme96->wcreg |= RME96_WCR_ISEL; 944 break; 945 default: 946 snd_BUG(); 947 break; 948 } 949 rme96->wcreg &= ~RME96_WCR_IDIS; 950 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 951 } 952 953 static int 954 snd_rme96_playback_hw_params(struct snd_pcm_substream *substream, 955 struct snd_pcm_hw_params *params) 956 { 957 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 958 struct snd_pcm_runtime *runtime = substream->runtime; 959 int err, rate, dummy; 960 bool apply_dac_volume = false; 961 962 runtime->dma_area = (void __force *)(rme96->iobase + 963 RME96_IO_PLAY_BUFFER); 964 runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER; 965 runtime->dma_bytes = RME96_BUFFER_SIZE; 966 967 scoped_guard(spinlock_irq, &rme96->lock) { 968 rate = 0; 969 if (!(rme96->wcreg & RME96_WCR_MASTER) && 970 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) 971 rate = snd_rme96_capture_getrate(rme96, &dummy); 972 if (rate > 0) { 973 /* slave clock */ 974 if ((int)params_rate(params) != rate) 975 return -EIO; 976 } else { 977 err = snd_rme96_playback_setrate(rme96, params_rate(params)); 978 if (err < 0) 979 return err; 980 apply_dac_volume = err > 0; /* need to restore volume later? */ 981 } 982 983 err = snd_rme96_playback_setformat(rme96, params_format(params)); 984 if (err < 0) 985 goto error; 986 snd_rme96_setframelog(rme96, params_channels(params), 1); 987 if (rme96->capture_periodsize != 0) { 988 if (params_period_size(params) << rme96->playback_frlog != 989 rme96->capture_periodsize) { 990 err = -EBUSY; 991 goto error; 992 } 993 } 994 rme96->playback_periodsize = 995 params_period_size(params) << rme96->playback_frlog; 996 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize); 997 /* S/PDIF setup */ 998 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) { 999 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); 1000 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1001 } 1002 1003 err = 0; 1004 } 1005 error: 1006 if (apply_dac_volume) { 1007 usleep_range(3000, 10000); 1008 snd_rme96_apply_dac_volume(rme96); 1009 } 1010 1011 return err; 1012 } 1013 1014 static int 1015 snd_rme96_capture_hw_params(struct snd_pcm_substream *substream, 1016 struct snd_pcm_hw_params *params) 1017 { 1018 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1019 struct snd_pcm_runtime *runtime = substream->runtime; 1020 int err, isadat, rate; 1021 1022 runtime->dma_area = (void __force *)(rme96->iobase + 1023 RME96_IO_REC_BUFFER); 1024 runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER; 1025 runtime->dma_bytes = RME96_BUFFER_SIZE; 1026 1027 guard(spinlock_irq)(&rme96->lock); 1028 err = snd_rme96_capture_setformat(rme96, params_format(params)); 1029 if (err < 0) 1030 return err; 1031 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { 1032 err = snd_rme96_capture_analog_setrate(rme96, params_rate(params)); 1033 if (err < 0) 1034 return err; 1035 } else { 1036 rate = snd_rme96_capture_getrate(rme96, &isadat); 1037 if (rate > 0) { 1038 if ((int)params_rate(params) != rate) 1039 return -EIO; 1040 if ((isadat && runtime->hw.channels_min == 2) || 1041 (!isadat && runtime->hw.channels_min == 8)) 1042 return -EIO; 1043 } 1044 } 1045 snd_rme96_setframelog(rme96, params_channels(params), 0); 1046 if (rme96->playback_periodsize != 0) { 1047 if (params_period_size(params) << rme96->capture_frlog != 1048 rme96->playback_periodsize) 1049 return -EBUSY; 1050 } 1051 rme96->capture_periodsize = 1052 params_period_size(params) << rme96->capture_frlog; 1053 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize); 1054 1055 return 0; 1056 } 1057 1058 static void 1059 snd_rme96_trigger(struct rme96 *rme96, 1060 int op) 1061 { 1062 if (op & RME96_TB_RESET_PLAYPOS) 1063 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); 1064 if (op & RME96_TB_RESET_CAPTUREPOS) 1065 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); 1066 if (op & RME96_TB_CLEAR_PLAYBACK_IRQ) { 1067 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1068 if (rme96->rcreg & RME96_RCR_IRQ) 1069 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); 1070 } 1071 if (op & RME96_TB_CLEAR_CAPTURE_IRQ) { 1072 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1073 if (rme96->rcreg & RME96_RCR_IRQ_2) 1074 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); 1075 } 1076 if (op & RME96_TB_START_PLAYBACK) 1077 rme96->wcreg |= RME96_WCR_START; 1078 if (op & RME96_TB_STOP_PLAYBACK) 1079 rme96->wcreg &= ~RME96_WCR_START; 1080 if (op & RME96_TB_START_CAPTURE) 1081 rme96->wcreg |= RME96_WCR_START_2; 1082 if (op & RME96_TB_STOP_CAPTURE) 1083 rme96->wcreg &= ~RME96_WCR_START_2; 1084 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1085 } 1086 1087 1088 1089 static irqreturn_t 1090 snd_rme96_interrupt(int irq, 1091 void *dev_id) 1092 { 1093 struct rme96 *rme96 = (struct rme96 *)dev_id; 1094 1095 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1096 /* fastpath out, to ease interrupt sharing */ 1097 if (!((rme96->rcreg & RME96_RCR_IRQ) || 1098 (rme96->rcreg & RME96_RCR_IRQ_2))) 1099 { 1100 return IRQ_NONE; 1101 } 1102 1103 if (rme96->rcreg & RME96_RCR_IRQ) { 1104 /* playback */ 1105 snd_pcm_period_elapsed(rme96->playback_substream); 1106 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); 1107 } 1108 if (rme96->rcreg & RME96_RCR_IRQ_2) { 1109 /* capture */ 1110 snd_pcm_period_elapsed(rme96->capture_substream); 1111 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); 1112 } 1113 return IRQ_HANDLED; 1114 } 1115 1116 static const unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE }; 1117 1118 static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = { 1119 .count = ARRAY_SIZE(period_bytes), 1120 .list = period_bytes, 1121 .mask = 0 1122 }; 1123 1124 static void 1125 rme96_set_buffer_size_constraint(struct rme96 *rme96, 1126 struct snd_pcm_runtime *runtime) 1127 { 1128 unsigned int size; 1129 1130 snd_pcm_hw_constraint_single(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1131 RME96_BUFFER_SIZE); 1132 size = rme96->playback_periodsize; 1133 if (!size) 1134 size = rme96->capture_periodsize; 1135 if (size) 1136 snd_pcm_hw_constraint_single(runtime, 1137 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1138 size); 1139 else 1140 snd_pcm_hw_constraint_list(runtime, 0, 1141 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1142 &hw_constraints_period_bytes); 1143 } 1144 1145 static int 1146 snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream) 1147 { 1148 int rate, dummy; 1149 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1150 struct snd_pcm_runtime *runtime = substream->runtime; 1151 1152 snd_pcm_set_sync(substream); 1153 scoped_guard(spinlock_irq, &rme96->lock) { 1154 if (rme96->playback_substream) 1155 return -EBUSY; 1156 rme96->wcreg &= ~RME96_WCR_ADAT; 1157 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1158 rme96->playback_substream = substream; 1159 } 1160 1161 runtime->hw = snd_rme96_playback_spdif_info; 1162 if (!(rme96->wcreg & RME96_WCR_MASTER) && 1163 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) { 1164 rate = snd_rme96_capture_getrate(rme96, &dummy); 1165 if (rate > 0) { 1166 /* slave clock */ 1167 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1168 runtime->hw.rate_min = rate; 1169 runtime->hw.rate_max = rate; 1170 } 1171 } 1172 rme96_set_buffer_size_constraint(rme96, runtime); 1173 1174 rme96->wcreg_spdif_stream = rme96->wcreg_spdif; 1175 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1176 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | 1177 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id); 1178 return 0; 1179 } 1180 1181 static int 1182 snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream) 1183 { 1184 int isadat, rate; 1185 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1186 struct snd_pcm_runtime *runtime = substream->runtime; 1187 1188 snd_pcm_set_sync(substream); 1189 runtime->hw = snd_rme96_capture_spdif_info; 1190 if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) { 1191 rate = snd_rme96_capture_getrate(rme96, &isadat); 1192 if (rate > 0) { 1193 if (isadat) 1194 return -EIO; 1195 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1196 runtime->hw.rate_min = rate; 1197 runtime->hw.rate_max = rate; 1198 } 1199 } 1200 1201 scoped_guard(spinlock_irq, &rme96->lock) { 1202 if (rme96->capture_substream) 1203 return -EBUSY; 1204 rme96->capture_substream = substream; 1205 } 1206 1207 rme96_set_buffer_size_constraint(rme96, runtime); 1208 return 0; 1209 } 1210 1211 static int 1212 snd_rme96_playback_adat_open(struct snd_pcm_substream *substream) 1213 { 1214 int rate, dummy; 1215 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1216 struct snd_pcm_runtime *runtime = substream->runtime; 1217 1218 snd_pcm_set_sync(substream); 1219 scoped_guard(spinlock_irq, &rme96->lock) { 1220 if (rme96->playback_substream) 1221 return -EBUSY; 1222 rme96->wcreg |= RME96_WCR_ADAT; 1223 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1224 rme96->playback_substream = substream; 1225 } 1226 1227 runtime->hw = snd_rme96_playback_adat_info; 1228 if (!(rme96->wcreg & RME96_WCR_MASTER) && 1229 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) { 1230 rate = snd_rme96_capture_getrate(rme96, &dummy); 1231 if (rate > 0) { 1232 /* slave clock */ 1233 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1234 runtime->hw.rate_min = rate; 1235 runtime->hw.rate_max = rate; 1236 } 1237 } 1238 1239 rme96_set_buffer_size_constraint(rme96, runtime); 1240 return 0; 1241 } 1242 1243 static int 1244 snd_rme96_capture_adat_open(struct snd_pcm_substream *substream) 1245 { 1246 int isadat, rate; 1247 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1248 struct snd_pcm_runtime *runtime = substream->runtime; 1249 1250 snd_pcm_set_sync(substream); 1251 runtime->hw = snd_rme96_capture_adat_info; 1252 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { 1253 /* makes no sense to use analog input. Note that analog 1254 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */ 1255 return -EIO; 1256 } 1257 rate = snd_rme96_capture_getrate(rme96, &isadat); 1258 if (rate > 0) { 1259 if (!isadat) { 1260 return -EIO; 1261 } 1262 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1263 runtime->hw.rate_min = rate; 1264 runtime->hw.rate_max = rate; 1265 } 1266 1267 scoped_guard(spinlock_irq, &rme96->lock) { 1268 if (rme96->capture_substream) 1269 return -EBUSY; 1270 rme96->capture_substream = substream; 1271 } 1272 1273 rme96_set_buffer_size_constraint(rme96, runtime); 1274 return 0; 1275 } 1276 1277 static int 1278 snd_rme96_playback_close(struct snd_pcm_substream *substream) 1279 { 1280 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1281 int spdif = 0; 1282 1283 scoped_guard(spinlock_irq, &rme96->lock) { 1284 if (RME96_ISPLAYING(rme96)) 1285 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK); 1286 rme96->playback_substream = NULL; 1287 rme96->playback_periodsize = 0; 1288 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0; 1289 } 1290 if (spdif) { 1291 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1292 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | 1293 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id); 1294 } 1295 return 0; 1296 } 1297 1298 static int 1299 snd_rme96_capture_close(struct snd_pcm_substream *substream) 1300 { 1301 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1302 1303 guard(spinlock_irq)(&rme96->lock); 1304 if (RME96_ISRECORDING(rme96)) { 1305 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE); 1306 } 1307 rme96->capture_substream = NULL; 1308 rme96->capture_periodsize = 0; 1309 return 0; 1310 } 1311 1312 static int 1313 snd_rme96_playback_prepare(struct snd_pcm_substream *substream) 1314 { 1315 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1316 1317 guard(spinlock_irq)(&rme96->lock); 1318 if (RME96_ISPLAYING(rme96)) { 1319 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK); 1320 } 1321 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); 1322 return 0; 1323 } 1324 1325 static int 1326 snd_rme96_capture_prepare(struct snd_pcm_substream *substream) 1327 { 1328 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1329 1330 guard(spinlock_irq)(&rme96->lock); 1331 if (RME96_ISRECORDING(rme96)) { 1332 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE); 1333 } 1334 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); 1335 return 0; 1336 } 1337 1338 static int 1339 snd_rme96_playback_trigger(struct snd_pcm_substream *substream, 1340 int cmd) 1341 { 1342 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1343 struct snd_pcm_substream *s; 1344 bool sync; 1345 1346 snd_pcm_group_for_each_entry(s, substream) { 1347 if (snd_pcm_substream_chip(s) == rme96) 1348 snd_pcm_trigger_done(s, substream); 1349 } 1350 1351 sync = (rme96->playback_substream && rme96->capture_substream) && 1352 (rme96->playback_substream->group == 1353 rme96->capture_substream->group); 1354 1355 switch (cmd) { 1356 case SNDRV_PCM_TRIGGER_START: 1357 if (!RME96_ISPLAYING(rme96)) { 1358 if (substream != rme96->playback_substream) 1359 return -EBUSY; 1360 snd_rme96_trigger(rme96, sync ? RME96_START_BOTH 1361 : RME96_START_PLAYBACK); 1362 } 1363 break; 1364 1365 case SNDRV_PCM_TRIGGER_SUSPEND: 1366 case SNDRV_PCM_TRIGGER_STOP: 1367 if (RME96_ISPLAYING(rme96)) { 1368 if (substream != rme96->playback_substream) 1369 return -EBUSY; 1370 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH 1371 : RME96_STOP_PLAYBACK); 1372 } 1373 break; 1374 1375 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1376 if (RME96_ISPLAYING(rme96)) 1377 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH 1378 : RME96_STOP_PLAYBACK); 1379 break; 1380 1381 case SNDRV_PCM_TRIGGER_RESUME: 1382 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1383 if (!RME96_ISPLAYING(rme96)) 1384 snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH 1385 : RME96_RESUME_PLAYBACK); 1386 break; 1387 1388 default: 1389 return -EINVAL; 1390 } 1391 1392 return 0; 1393 } 1394 1395 static int 1396 snd_rme96_capture_trigger(struct snd_pcm_substream *substream, 1397 int cmd) 1398 { 1399 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1400 struct snd_pcm_substream *s; 1401 bool sync; 1402 1403 snd_pcm_group_for_each_entry(s, substream) { 1404 if (snd_pcm_substream_chip(s) == rme96) 1405 snd_pcm_trigger_done(s, substream); 1406 } 1407 1408 sync = (rme96->playback_substream && rme96->capture_substream) && 1409 (rme96->playback_substream->group == 1410 rme96->capture_substream->group); 1411 1412 switch (cmd) { 1413 case SNDRV_PCM_TRIGGER_START: 1414 if (!RME96_ISRECORDING(rme96)) { 1415 if (substream != rme96->capture_substream) 1416 return -EBUSY; 1417 snd_rme96_trigger(rme96, sync ? RME96_START_BOTH 1418 : RME96_START_CAPTURE); 1419 } 1420 break; 1421 1422 case SNDRV_PCM_TRIGGER_SUSPEND: 1423 case SNDRV_PCM_TRIGGER_STOP: 1424 if (RME96_ISRECORDING(rme96)) { 1425 if (substream != rme96->capture_substream) 1426 return -EBUSY; 1427 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH 1428 : RME96_STOP_CAPTURE); 1429 } 1430 break; 1431 1432 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1433 if (RME96_ISRECORDING(rme96)) 1434 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH 1435 : RME96_STOP_CAPTURE); 1436 break; 1437 1438 case SNDRV_PCM_TRIGGER_RESUME: 1439 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1440 if (!RME96_ISRECORDING(rme96)) 1441 snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH 1442 : RME96_RESUME_CAPTURE); 1443 break; 1444 1445 default: 1446 return -EINVAL; 1447 } 1448 1449 return 0; 1450 } 1451 1452 static snd_pcm_uframes_t 1453 snd_rme96_playback_pointer(struct snd_pcm_substream *substream) 1454 { 1455 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1456 return snd_rme96_playback_ptr(rme96); 1457 } 1458 1459 static snd_pcm_uframes_t 1460 snd_rme96_capture_pointer(struct snd_pcm_substream *substream) 1461 { 1462 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1463 return snd_rme96_capture_ptr(rme96); 1464 } 1465 1466 static const struct snd_pcm_ops snd_rme96_playback_spdif_ops = { 1467 .open = snd_rme96_playback_spdif_open, 1468 .close = snd_rme96_playback_close, 1469 .hw_params = snd_rme96_playback_hw_params, 1470 .prepare = snd_rme96_playback_prepare, 1471 .trigger = snd_rme96_playback_trigger, 1472 .pointer = snd_rme96_playback_pointer, 1473 .copy = snd_rme96_playback_copy, 1474 .fill_silence = snd_rme96_playback_silence, 1475 .mmap = snd_pcm_lib_mmap_iomem, 1476 }; 1477 1478 static const struct snd_pcm_ops snd_rme96_capture_spdif_ops = { 1479 .open = snd_rme96_capture_spdif_open, 1480 .close = snd_rme96_capture_close, 1481 .hw_params = snd_rme96_capture_hw_params, 1482 .prepare = snd_rme96_capture_prepare, 1483 .trigger = snd_rme96_capture_trigger, 1484 .pointer = snd_rme96_capture_pointer, 1485 .copy = snd_rme96_capture_copy, 1486 .mmap = snd_pcm_lib_mmap_iomem, 1487 }; 1488 1489 static const struct snd_pcm_ops snd_rme96_playback_adat_ops = { 1490 .open = snd_rme96_playback_adat_open, 1491 .close = snd_rme96_playback_close, 1492 .hw_params = snd_rme96_playback_hw_params, 1493 .prepare = snd_rme96_playback_prepare, 1494 .trigger = snd_rme96_playback_trigger, 1495 .pointer = snd_rme96_playback_pointer, 1496 .copy = snd_rme96_playback_copy, 1497 .fill_silence = snd_rme96_playback_silence, 1498 .mmap = snd_pcm_lib_mmap_iomem, 1499 }; 1500 1501 static const struct snd_pcm_ops snd_rme96_capture_adat_ops = { 1502 .open = snd_rme96_capture_adat_open, 1503 .close = snd_rme96_capture_close, 1504 .hw_params = snd_rme96_capture_hw_params, 1505 .prepare = snd_rme96_capture_prepare, 1506 .trigger = snd_rme96_capture_trigger, 1507 .pointer = snd_rme96_capture_pointer, 1508 .copy = snd_rme96_capture_copy, 1509 .mmap = snd_pcm_lib_mmap_iomem, 1510 }; 1511 1512 static void 1513 snd_rme96_free(struct rme96 *rme96) 1514 { 1515 if (rme96->irq >= 0) { 1516 snd_rme96_trigger(rme96, RME96_STOP_BOTH); 1517 rme96->areg &= ~RME96_AR_DAC_EN; 1518 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1519 } 1520 vfree(rme96->playback_suspend_buffer); 1521 vfree(rme96->capture_suspend_buffer); 1522 } 1523 1524 static void 1525 snd_rme96_free_spdif_pcm(struct snd_pcm *pcm) 1526 { 1527 struct rme96 *rme96 = pcm->private_data; 1528 rme96->spdif_pcm = NULL; 1529 } 1530 1531 static void 1532 snd_rme96_free_adat_pcm(struct snd_pcm *pcm) 1533 { 1534 struct rme96 *rme96 = pcm->private_data; 1535 rme96->adat_pcm = NULL; 1536 } 1537 1538 static int 1539 snd_rme96_create(struct rme96 *rme96) 1540 { 1541 struct pci_dev *pci = rme96->pci; 1542 int err; 1543 1544 rme96->irq = -1; 1545 spin_lock_init(&rme96->lock); 1546 1547 err = pcim_enable_device(pci); 1548 if (err < 0) 1549 return err; 1550 1551 err = pcim_request_all_regions(pci, "RME96"); 1552 if (err < 0) 1553 return err; 1554 rme96->port = pci_resource_start(rme96->pci, 0); 1555 1556 rme96->iobase = devm_ioremap(&pci->dev, rme96->port, RME96_IO_SIZE); 1557 if (!rme96->iobase) { 1558 dev_err(rme96->card->dev, 1559 "unable to remap memory region 0x%lx-0x%lx\n", 1560 rme96->port, rme96->port + RME96_IO_SIZE - 1); 1561 return -EBUSY; 1562 } 1563 1564 if (devm_request_irq(&pci->dev, pci->irq, snd_rme96_interrupt, 1565 IRQF_SHARED, KBUILD_MODNAME, rme96)) { 1566 dev_err(rme96->card->dev, "unable to grab IRQ %d\n", pci->irq); 1567 return -EBUSY; 1568 } 1569 rme96->irq = pci->irq; 1570 rme96->card->sync_irq = rme96->irq; 1571 1572 /* read the card's revision number */ 1573 pci_read_config_byte(pci, 8, &rme96->rev); 1574 1575 /* set up ALSA pcm device for S/PDIF */ 1576 err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0, 1577 1, 1, &rme96->spdif_pcm); 1578 if (err < 0) 1579 return err; 1580 1581 rme96->spdif_pcm->private_data = rme96; 1582 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm; 1583 strscpy(rme96->spdif_pcm->name, "Digi96 IEC958"); 1584 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops); 1585 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops); 1586 1587 rme96->spdif_pcm->info_flags = 0; 1588 1589 /* set up ALSA pcm device for ADAT */ 1590 if (pci->device == PCI_DEVICE_ID_RME_DIGI96) { 1591 /* ADAT is not available on the base model */ 1592 rme96->adat_pcm = NULL; 1593 } else { 1594 err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1, 1595 1, 1, &rme96->adat_pcm); 1596 if (err < 0) 1597 return err; 1598 rme96->adat_pcm->private_data = rme96; 1599 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm; 1600 strscpy(rme96->adat_pcm->name, "Digi96 ADAT"); 1601 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops); 1602 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops); 1603 1604 rme96->adat_pcm->info_flags = 0; 1605 } 1606 1607 rme96->playback_periodsize = 0; 1608 rme96->capture_periodsize = 0; 1609 1610 /* make sure playback/capture is stopped, if by some reason active */ 1611 snd_rme96_trigger(rme96, RME96_STOP_BOTH); 1612 1613 /* set default values in registers */ 1614 rme96->wcreg = 1615 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */ 1616 RME96_WCR_SEL | /* normal playback */ 1617 RME96_WCR_MASTER | /* set to master clock mode */ 1618 RME96_WCR_INP_0; /* set coaxial input */ 1619 1620 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */ 1621 1622 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1623 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1624 1625 /* reset the ADC */ 1626 writel(rme96->areg | RME96_AR_PD2, 1627 rme96->iobase + RME96_IO_ADDITIONAL_REG); 1628 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1629 1630 /* reset and enable the DAC (order is important). */ 1631 snd_rme96_reset_dac(rme96); 1632 rme96->areg |= RME96_AR_DAC_EN; 1633 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1634 1635 /* reset playback and record buffer pointers */ 1636 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); 1637 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); 1638 1639 /* reset volume */ 1640 rme96->vol[0] = rme96->vol[1] = 0; 1641 if (RME96_HAS_ANALOG_OUT(rme96)) { 1642 snd_rme96_apply_dac_volume(rme96); 1643 } 1644 1645 /* init switch interface */ 1646 err = snd_rme96_create_switches(rme96->card, rme96); 1647 if (err < 0) 1648 return err; 1649 1650 /* init proc interface */ 1651 snd_rme96_proc_init(rme96); 1652 1653 return 0; 1654 } 1655 1656 /* 1657 * proc interface 1658 */ 1659 1660 static void 1661 snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) 1662 { 1663 int n; 1664 struct rme96 *rme96 = entry->private_data; 1665 1666 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1667 1668 snd_iprintf(buffer, rme96->card->longname); 1669 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1); 1670 1671 snd_iprintf(buffer, "\nGeneral settings\n"); 1672 if (rme96->wcreg & RME96_WCR_IDIS) { 1673 snd_iprintf(buffer, " period size: N/A (interrupts " 1674 "disabled)\n"); 1675 } else if (rme96->wcreg & RME96_WCR_ISEL) { 1676 snd_iprintf(buffer, " period size: 2048 bytes\n"); 1677 } else { 1678 snd_iprintf(buffer, " period size: 8192 bytes\n"); 1679 } 1680 snd_iprintf(buffer, "\nInput settings\n"); 1681 switch (snd_rme96_getinputtype(rme96)) { 1682 case RME96_INPUT_OPTICAL: 1683 snd_iprintf(buffer, " input: optical"); 1684 break; 1685 case RME96_INPUT_COAXIAL: 1686 snd_iprintf(buffer, " input: coaxial"); 1687 break; 1688 case RME96_INPUT_INTERNAL: 1689 snd_iprintf(buffer, " input: internal"); 1690 break; 1691 case RME96_INPUT_XLR: 1692 snd_iprintf(buffer, " input: XLR"); 1693 break; 1694 case RME96_INPUT_ANALOG: 1695 snd_iprintf(buffer, " input: analog"); 1696 break; 1697 } 1698 if (snd_rme96_capture_getrate(rme96, &n) < 0) { 1699 snd_iprintf(buffer, "\n sample rate: no valid signal\n"); 1700 } else { 1701 if (n) { 1702 snd_iprintf(buffer, " (8 channels)\n"); 1703 } else { 1704 snd_iprintf(buffer, " (2 channels)\n"); 1705 } 1706 snd_iprintf(buffer, " sample rate: %d Hz\n", 1707 snd_rme96_capture_getrate(rme96, &n)); 1708 } 1709 if (rme96->wcreg & RME96_WCR_MODE24_2) { 1710 snd_iprintf(buffer, " sample format: 24 bit\n"); 1711 } else { 1712 snd_iprintf(buffer, " sample format: 16 bit\n"); 1713 } 1714 1715 snd_iprintf(buffer, "\nOutput settings\n"); 1716 if (rme96->wcreg & RME96_WCR_SEL) { 1717 snd_iprintf(buffer, " output signal: normal playback\n"); 1718 } else { 1719 snd_iprintf(buffer, " output signal: same as input\n"); 1720 } 1721 snd_iprintf(buffer, " sample rate: %d Hz\n", 1722 snd_rme96_playback_getrate(rme96)); 1723 if (rme96->wcreg & RME96_WCR_MODE24) { 1724 snd_iprintf(buffer, " sample format: 24 bit\n"); 1725 } else { 1726 snd_iprintf(buffer, " sample format: 16 bit\n"); 1727 } 1728 if (rme96->areg & RME96_AR_WSEL) { 1729 snd_iprintf(buffer, " sample clock source: word clock\n"); 1730 } else if (rme96->wcreg & RME96_WCR_MASTER) { 1731 snd_iprintf(buffer, " sample clock source: internal\n"); 1732 } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { 1733 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n"); 1734 } else if (snd_rme96_capture_getrate(rme96, &n) < 0) { 1735 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n"); 1736 } else { 1737 snd_iprintf(buffer, " sample clock source: autosync\n"); 1738 } 1739 if (rme96->wcreg & RME96_WCR_PRO) { 1740 snd_iprintf(buffer, " format: AES/EBU (professional)\n"); 1741 } else { 1742 snd_iprintf(buffer, " format: IEC958 (consumer)\n"); 1743 } 1744 if (rme96->wcreg & RME96_WCR_EMP) { 1745 snd_iprintf(buffer, " emphasis: on\n"); 1746 } else { 1747 snd_iprintf(buffer, " emphasis: off\n"); 1748 } 1749 if (rme96->wcreg & RME96_WCR_DOLBY) { 1750 snd_iprintf(buffer, " non-audio (dolby): on\n"); 1751 } else { 1752 snd_iprintf(buffer, " non-audio (dolby): off\n"); 1753 } 1754 if (RME96_HAS_ANALOG_IN(rme96)) { 1755 snd_iprintf(buffer, "\nAnalog output settings\n"); 1756 switch (snd_rme96_getmontracks(rme96)) { 1757 case RME96_MONITOR_TRACKS_1_2: 1758 snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n"); 1759 break; 1760 case RME96_MONITOR_TRACKS_3_4: 1761 snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n"); 1762 break; 1763 case RME96_MONITOR_TRACKS_5_6: 1764 snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n"); 1765 break; 1766 case RME96_MONITOR_TRACKS_7_8: 1767 snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n"); 1768 break; 1769 } 1770 switch (snd_rme96_getattenuation(rme96)) { 1771 case RME96_ATTENUATION_0: 1772 snd_iprintf(buffer, " attenuation: 0 dB\n"); 1773 break; 1774 case RME96_ATTENUATION_6: 1775 snd_iprintf(buffer, " attenuation: -6 dB\n"); 1776 break; 1777 case RME96_ATTENUATION_12: 1778 snd_iprintf(buffer, " attenuation: -12 dB\n"); 1779 break; 1780 case RME96_ATTENUATION_18: 1781 snd_iprintf(buffer, " attenuation: -18 dB\n"); 1782 break; 1783 } 1784 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]); 1785 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]); 1786 } 1787 } 1788 1789 static void snd_rme96_proc_init(struct rme96 *rme96) 1790 { 1791 snd_card_ro_proc_new(rme96->card, "rme96", rme96, snd_rme96_proc_read); 1792 } 1793 1794 /* 1795 * control interface 1796 */ 1797 1798 #define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info 1799 1800 static int 1801 snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1802 { 1803 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1804 1805 guard(spinlock_irq)(&rme96->lock); 1806 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1; 1807 return 0; 1808 } 1809 static int 1810 snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1811 { 1812 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1813 unsigned int val; 1814 int change; 1815 1816 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL; 1817 guard(spinlock_irq)(&rme96->lock); 1818 val = (rme96->wcreg & ~RME96_WCR_SEL) | val; 1819 change = val != rme96->wcreg; 1820 rme96->wcreg = val; 1821 writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1822 return change; 1823 } 1824 1825 static int 1826 snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1827 { 1828 static const char * const _texts[5] = { 1829 "Optical", "Coaxial", "Internal", "XLR", "Analog" 1830 }; 1831 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1832 const char *texts[5] = { 1833 _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] 1834 }; 1835 int num_items; 1836 1837 switch (rme96->pci->device) { 1838 case PCI_DEVICE_ID_RME_DIGI96: 1839 case PCI_DEVICE_ID_RME_DIGI96_8: 1840 num_items = 3; 1841 break; 1842 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 1843 num_items = 4; 1844 break; 1845 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 1846 if (rme96->rev > 4) { 1847 /* PST */ 1848 num_items = 4; 1849 texts[3] = _texts[4]; /* Analog instead of XLR */ 1850 } else { 1851 /* PAD */ 1852 num_items = 5; 1853 } 1854 break; 1855 default: 1856 snd_BUG(); 1857 return -EINVAL; 1858 } 1859 return snd_ctl_enum_info(uinfo, 1, num_items, texts); 1860 } 1861 static int 1862 snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1863 { 1864 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1865 unsigned int items = 3; 1866 1867 guard(spinlock_irq)(&rme96->lock); 1868 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96); 1869 1870 switch (rme96->pci->device) { 1871 case PCI_DEVICE_ID_RME_DIGI96: 1872 case PCI_DEVICE_ID_RME_DIGI96_8: 1873 items = 3; 1874 break; 1875 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 1876 items = 4; 1877 break; 1878 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 1879 if (rme96->rev > 4) { 1880 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */ 1881 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) { 1882 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR; 1883 } 1884 items = 4; 1885 } else { 1886 items = 5; 1887 } 1888 break; 1889 default: 1890 snd_BUG(); 1891 break; 1892 } 1893 if (ucontrol->value.enumerated.item[0] >= items) { 1894 ucontrol->value.enumerated.item[0] = items - 1; 1895 } 1896 1897 return 0; 1898 } 1899 static int 1900 snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1901 { 1902 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1903 unsigned int val; 1904 int change, items = 3; 1905 1906 switch (rme96->pci->device) { 1907 case PCI_DEVICE_ID_RME_DIGI96: 1908 case PCI_DEVICE_ID_RME_DIGI96_8: 1909 items = 3; 1910 break; 1911 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 1912 items = 4; 1913 break; 1914 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 1915 if (rme96->rev > 4) { 1916 items = 4; 1917 } else { 1918 items = 5; 1919 } 1920 break; 1921 default: 1922 snd_BUG(); 1923 break; 1924 } 1925 val = ucontrol->value.enumerated.item[0] % items; 1926 1927 /* special case for PST */ 1928 if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) { 1929 if (val == RME96_INPUT_XLR) { 1930 val = RME96_INPUT_ANALOG; 1931 } 1932 } 1933 1934 guard(spinlock_irq)(&rme96->lock); 1935 change = (int)val != snd_rme96_getinputtype(rme96); 1936 snd_rme96_setinputtype(rme96, val); 1937 return change; 1938 } 1939 1940 static int 1941 snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1942 { 1943 static const char * const texts[3] = { "AutoSync", "Internal", "Word" }; 1944 1945 return snd_ctl_enum_info(uinfo, 1, 3, texts); 1946 } 1947 static int 1948 snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1949 { 1950 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1951 1952 guard(spinlock_irq)(&rme96->lock); 1953 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96); 1954 return 0; 1955 } 1956 static int 1957 snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1958 { 1959 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1960 unsigned int val; 1961 int change; 1962 1963 val = ucontrol->value.enumerated.item[0] % 3; 1964 guard(spinlock_irq)(&rme96->lock); 1965 change = (int)val != snd_rme96_getclockmode(rme96); 1966 snd_rme96_setclockmode(rme96, val); 1967 return change; 1968 } 1969 1970 static int 1971 snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1972 { 1973 static const char * const texts[4] = { 1974 "0 dB", "-6 dB", "-12 dB", "-18 dB" 1975 }; 1976 1977 return snd_ctl_enum_info(uinfo, 1, 4, texts); 1978 } 1979 static int 1980 snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1981 { 1982 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1983 1984 guard(spinlock_irq)(&rme96->lock); 1985 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96); 1986 return 0; 1987 } 1988 static int 1989 snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1990 { 1991 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1992 unsigned int val; 1993 int change; 1994 1995 val = ucontrol->value.enumerated.item[0] % 4; 1996 guard(spinlock_irq)(&rme96->lock); 1997 1998 change = (int)val != snd_rme96_getattenuation(rme96); 1999 snd_rme96_setattenuation(rme96, val); 2000 return change; 2001 } 2002 2003 static int 2004 snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2005 { 2006 static const char * const texts[4] = { "1+2", "3+4", "5+6", "7+8" }; 2007 2008 return snd_ctl_enum_info(uinfo, 1, 4, texts); 2009 } 2010 static int 2011 snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2012 { 2013 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2014 2015 guard(spinlock_irq)(&rme96->lock); 2016 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96); 2017 return 0; 2018 } 2019 static int 2020 snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2021 { 2022 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2023 unsigned int val; 2024 int change; 2025 2026 val = ucontrol->value.enumerated.item[0] % 4; 2027 guard(spinlock_irq)(&rme96->lock); 2028 change = (int)val != snd_rme96_getmontracks(rme96); 2029 snd_rme96_setmontracks(rme96, val); 2030 return change; 2031 } 2032 2033 static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes) 2034 { 2035 u32 val = 0; 2036 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0; 2037 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0; 2038 if (val & RME96_WCR_PRO) 2039 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0; 2040 else 2041 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0; 2042 return val; 2043 } 2044 2045 static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) 2046 { 2047 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) | 2048 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0); 2049 if (val & RME96_WCR_PRO) 2050 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; 2051 else 2052 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; 2053 } 2054 2055 static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2056 { 2057 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2058 uinfo->count = 1; 2059 return 0; 2060 } 2061 2062 static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2063 { 2064 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2065 2066 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif); 2067 return 0; 2068 } 2069 2070 static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2071 { 2072 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2073 int change; 2074 u32 val; 2075 2076 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); 2077 guard(spinlock_irq)(&rme96->lock); 2078 change = val != rme96->wcreg_spdif; 2079 rme96->wcreg_spdif = val; 2080 return change; 2081 } 2082 2083 static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2084 { 2085 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2086 uinfo->count = 1; 2087 return 0; 2088 } 2089 2090 static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2091 { 2092 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2093 2094 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream); 2095 return 0; 2096 } 2097 2098 static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2099 { 2100 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2101 int change; 2102 u32 val; 2103 2104 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); 2105 guard(spinlock_irq)(&rme96->lock); 2106 change = val != rme96->wcreg_spdif_stream; 2107 rme96->wcreg_spdif_stream = val; 2108 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); 2109 rme96->wcreg |= val; 2110 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 2111 return change; 2112 } 2113 2114 static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2115 { 2116 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2117 uinfo->count = 1; 2118 return 0; 2119 } 2120 2121 static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2122 { 2123 ucontrol->value.iec958.status[0] = kcontrol->private_value; 2124 return 0; 2125 } 2126 2127 static int 2128 snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2129 { 2130 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2131 2132 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2133 uinfo->count = 2; 2134 uinfo->value.integer.min = 0; 2135 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96); 2136 return 0; 2137 } 2138 2139 static int 2140 snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u) 2141 { 2142 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2143 2144 guard(spinlock_irq)(&rme96->lock); 2145 u->value.integer.value[0] = rme96->vol[0]; 2146 u->value.integer.value[1] = rme96->vol[1]; 2147 2148 return 0; 2149 } 2150 2151 static int 2152 snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u) 2153 { 2154 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2155 int change = 0; 2156 unsigned int vol, maxvol; 2157 2158 2159 if (!RME96_HAS_ANALOG_OUT(rme96)) 2160 return -EINVAL; 2161 maxvol = RME96_185X_MAX_OUT(rme96); 2162 guard(spinlock_irq)(&rme96->lock); 2163 vol = u->value.integer.value[0]; 2164 if (vol != rme96->vol[0] && vol <= maxvol) { 2165 rme96->vol[0] = vol; 2166 change = 1; 2167 } 2168 vol = u->value.integer.value[1]; 2169 if (vol != rme96->vol[1] && vol <= maxvol) { 2170 rme96->vol[1] = vol; 2171 change = 1; 2172 } 2173 if (change) 2174 snd_rme96_apply_dac_volume(rme96); 2175 2176 return change; 2177 } 2178 2179 static const struct snd_kcontrol_new snd_rme96_controls[] = { 2180 { 2181 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2182 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 2183 .info = snd_rme96_control_spdif_info, 2184 .get = snd_rme96_control_spdif_get, 2185 .put = snd_rme96_control_spdif_put 2186 }, 2187 { 2188 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 2189 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2190 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 2191 .info = snd_rme96_control_spdif_stream_info, 2192 .get = snd_rme96_control_spdif_stream_get, 2193 .put = snd_rme96_control_spdif_stream_put 2194 }, 2195 { 2196 .access = SNDRV_CTL_ELEM_ACCESS_READ, 2197 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2198 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), 2199 .info = snd_rme96_control_spdif_mask_info, 2200 .get = snd_rme96_control_spdif_mask_get, 2201 .private_value = IEC958_AES0_NONAUDIO | 2202 IEC958_AES0_PROFESSIONAL | 2203 IEC958_AES0_CON_EMPHASIS 2204 }, 2205 { 2206 .access = SNDRV_CTL_ELEM_ACCESS_READ, 2207 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2208 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK), 2209 .info = snd_rme96_control_spdif_mask_info, 2210 .get = snd_rme96_control_spdif_mask_get, 2211 .private_value = IEC958_AES0_NONAUDIO | 2212 IEC958_AES0_PROFESSIONAL | 2213 IEC958_AES0_PRO_EMPHASIS 2214 }, 2215 { 2216 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2217 .name = "Input Connector", 2218 .info = snd_rme96_info_inputtype_control, 2219 .get = snd_rme96_get_inputtype_control, 2220 .put = snd_rme96_put_inputtype_control 2221 }, 2222 { 2223 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2224 .name = "Loopback Input", 2225 .info = snd_rme96_info_loopback_control, 2226 .get = snd_rme96_get_loopback_control, 2227 .put = snd_rme96_put_loopback_control 2228 }, 2229 { 2230 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2231 .name = "Sample Clock Source", 2232 .info = snd_rme96_info_clockmode_control, 2233 .get = snd_rme96_get_clockmode_control, 2234 .put = snd_rme96_put_clockmode_control 2235 }, 2236 { 2237 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2238 .name = "Monitor Tracks", 2239 .info = snd_rme96_info_montracks_control, 2240 .get = snd_rme96_get_montracks_control, 2241 .put = snd_rme96_put_montracks_control 2242 }, 2243 { 2244 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2245 .name = "Attenuation", 2246 .info = snd_rme96_info_attenuation_control, 2247 .get = snd_rme96_get_attenuation_control, 2248 .put = snd_rme96_put_attenuation_control 2249 }, 2250 { 2251 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2252 .name = "DAC Playback Volume", 2253 .info = snd_rme96_dac_volume_info, 2254 .get = snd_rme96_dac_volume_get, 2255 .put = snd_rme96_dac_volume_put 2256 } 2257 }; 2258 2259 static int 2260 snd_rme96_create_switches(struct snd_card *card, 2261 struct rme96 *rme96) 2262 { 2263 int idx, err; 2264 struct snd_kcontrol *kctl; 2265 2266 for (idx = 0; idx < 7; idx++) { 2267 kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96); 2268 err = snd_ctl_add(card, kctl); 2269 if (err < 0) 2270 return err; 2271 if (idx == 1) /* IEC958 (S/PDIF) Stream */ 2272 rme96->spdif_ctl = kctl; 2273 } 2274 2275 if (RME96_HAS_ANALOG_OUT(rme96)) { 2276 for (idx = 7; idx < 10; idx++) { 2277 err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96)); 2278 if (err < 0) 2279 return err; 2280 } 2281 } 2282 2283 return 0; 2284 } 2285 2286 /* 2287 * Card initialisation 2288 */ 2289 2290 static int rme96_suspend(struct device *dev) 2291 { 2292 struct snd_card *card = dev_get_drvdata(dev); 2293 struct rme96 *rme96 = card->private_data; 2294 2295 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2296 2297 /* save capture & playback pointers */ 2298 rme96->playback_pointer = readl(rme96->iobase + RME96_IO_GET_PLAY_POS) 2299 & RME96_RCR_AUDIO_ADDR_MASK; 2300 rme96->capture_pointer = readl(rme96->iobase + RME96_IO_GET_REC_POS) 2301 & RME96_RCR_AUDIO_ADDR_MASK; 2302 2303 /* save playback and capture buffers */ 2304 memcpy_fromio(rme96->playback_suspend_buffer, 2305 rme96->iobase + RME96_IO_PLAY_BUFFER, RME96_BUFFER_SIZE); 2306 memcpy_fromio(rme96->capture_suspend_buffer, 2307 rme96->iobase + RME96_IO_REC_BUFFER, RME96_BUFFER_SIZE); 2308 2309 /* disable the DAC */ 2310 rme96->areg &= ~RME96_AR_DAC_EN; 2311 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 2312 return 0; 2313 } 2314 2315 static int rme96_resume(struct device *dev) 2316 { 2317 struct snd_card *card = dev_get_drvdata(dev); 2318 struct rme96 *rme96 = card->private_data; 2319 2320 /* reset playback and record buffer pointers */ 2321 writel(0, rme96->iobase + RME96_IO_SET_PLAY_POS 2322 + rme96->playback_pointer); 2323 writel(0, rme96->iobase + RME96_IO_SET_REC_POS 2324 + rme96->capture_pointer); 2325 2326 /* restore playback and capture buffers */ 2327 memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER, 2328 rme96->playback_suspend_buffer, RME96_BUFFER_SIZE); 2329 memcpy_toio(rme96->iobase + RME96_IO_REC_BUFFER, 2330 rme96->capture_suspend_buffer, RME96_BUFFER_SIZE); 2331 2332 /* reset the ADC */ 2333 writel(rme96->areg | RME96_AR_PD2, 2334 rme96->iobase + RME96_IO_ADDITIONAL_REG); 2335 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 2336 2337 /* reset and enable DAC, restore analog volume */ 2338 snd_rme96_reset_dac(rme96); 2339 rme96->areg |= RME96_AR_DAC_EN; 2340 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 2341 if (RME96_HAS_ANALOG_OUT(rme96)) { 2342 usleep_range(3000, 10000); 2343 snd_rme96_apply_dac_volume(rme96); 2344 } 2345 2346 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2347 2348 return 0; 2349 } 2350 2351 static DEFINE_SIMPLE_DEV_PM_OPS(rme96_pm, rme96_suspend, rme96_resume); 2352 2353 static void snd_rme96_card_free(struct snd_card *card) 2354 { 2355 snd_rme96_free(card->private_data); 2356 } 2357 2358 static int 2359 __snd_rme96_probe(struct pci_dev *pci, 2360 const struct pci_device_id *pci_id) 2361 { 2362 static int dev; 2363 struct rme96 *rme96; 2364 struct snd_card *card; 2365 int err; 2366 u8 val; 2367 2368 if (dev >= SNDRV_CARDS) { 2369 return -ENODEV; 2370 } 2371 if (!enable[dev]) { 2372 dev++; 2373 return -ENOENT; 2374 } 2375 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2376 sizeof(*rme96), &card); 2377 if (err < 0) 2378 return err; 2379 card->private_free = snd_rme96_card_free; 2380 rme96 = card->private_data; 2381 rme96->card = card; 2382 rme96->pci = pci; 2383 err = snd_rme96_create(rme96); 2384 if (err) 2385 return err; 2386 2387 if (IS_ENABLED(CONFIG_PM_SLEEP)) { 2388 rme96->playback_suspend_buffer = vmalloc(RME96_BUFFER_SIZE); 2389 if (!rme96->playback_suspend_buffer) 2390 return -ENOMEM; 2391 rme96->capture_suspend_buffer = vmalloc(RME96_BUFFER_SIZE); 2392 if (!rme96->capture_suspend_buffer) 2393 return -ENOMEM; 2394 } 2395 2396 strscpy(card->driver, "Digi96"); 2397 switch (rme96->pci->device) { 2398 case PCI_DEVICE_ID_RME_DIGI96: 2399 strscpy(card->shortname, "RME Digi96"); 2400 break; 2401 case PCI_DEVICE_ID_RME_DIGI96_8: 2402 strscpy(card->shortname, "RME Digi96/8"); 2403 break; 2404 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 2405 strscpy(card->shortname, "RME Digi96/8 PRO"); 2406 break; 2407 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 2408 pci_read_config_byte(rme96->pci, 8, &val); 2409 if (val < 5) { 2410 strscpy(card->shortname, "RME Digi96/8 PAD"); 2411 } else { 2412 strscpy(card->shortname, "RME Digi96/8 PST"); 2413 } 2414 break; 2415 } 2416 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname, 2417 rme96->port, rme96->irq); 2418 err = snd_card_register(card); 2419 if (err) 2420 return err; 2421 2422 pci_set_drvdata(pci, card); 2423 dev++; 2424 return 0; 2425 } 2426 2427 static int snd_rme96_probe(struct pci_dev *pci, 2428 const struct pci_device_id *pci_id) 2429 { 2430 return snd_card_free_on_error(&pci->dev, __snd_rme96_probe(pci, pci_id)); 2431 } 2432 2433 static struct pci_driver rme96_driver = { 2434 .name = KBUILD_MODNAME, 2435 .id_table = snd_rme96_ids, 2436 .probe = snd_rme96_probe, 2437 .driver = { 2438 .pm = &rme96_pm, 2439 }, 2440 }; 2441 2442 module_pci_driver(rme96_driver); 2443