1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/param.h>
29 #include <sys/bus.h>
30 #include <sys/kernel.h>
31 #include <sys/module.h>
32 #include <sys/mutex.h>
33 #include <sys/rman.h>
34 #include <machine/bus.h>
35
36 #include <dev/ofw/ofw_bus.h>
37 #include <dev/ofw/ofw_bus_subr.h>
38
39 #include <dev/iicbus/iiconf.h>
40 #include <dev/iicbus/iicbus.h>
41
42 #include <dev/clk/clk.h>
43
44 #include "iicbus_if.h"
45
46 #define RK_I2C_CON 0x00
47 #define RK_I2C_CON_EN (1 << 0)
48 #define RK_I2C_CON_MODE_SHIFT 1
49 #define RK_I2C_CON_MODE_TX 0
50 #define RK_I2C_CON_MODE_RRX 1
51 #define RK_I2C_CON_MODE_RX 2
52 #define RK_I2C_CON_MODE_RTX 3
53 #define RK_I2C_CON_MODE_MASK 0x6
54 #define RK_I2C_CON_START (1 << 3)
55 #define RK_I2C_CON_STOP (1 << 4)
56 #define RK_I2C_CON_LASTACK (1 << 5)
57 #define RK_I2C_CON_NAKSTOP (1 << 6)
58 #define RK_I2C_CON_CTRL_MASK 0xFF
59
60 #define RK_I2C_CLKDIV 0x04
61 #define RK_I2C_CLKDIVL_MASK 0xFFFF
62 #define RK_I2C_CLKDIVL_SHIFT 0
63 #define RK_I2C_CLKDIVH_MASK 0xFFFF0000
64 #define RK_I2C_CLKDIVH_SHIFT 16
65 #define RK_I2C_CLKDIV_MUL 8
66
67 #define RK_I2C_MRXADDR 0x08
68 #define RK_I2C_MRXADDR_SADDR_MASK 0xFFFFFF
69 #define RK_I2C_MRXADDR_VALID(x) (1 << (24 + x))
70
71 #define RK_I2C_MRXRADDR 0x0C
72 #define RK_I2C_MRXRADDR_SRADDR_MASK 0xFFFFFF
73 #define RK_I2C_MRXRADDR_VALID(x) (1 << (24 + x))
74
75 #define RK_I2C_MTXCNT 0x10
76 #define RK_I2C_MTXCNT_MASK 0x3F
77
78 #define RK_I2C_MRXCNT 0x14
79 #define RK_I2C_MRXCNT_MASK 0x3F
80
81 #define RK_I2C_IEN 0x18
82 #define RK_I2C_IEN_BTFIEN (1 << 0)
83 #define RK_I2C_IEN_BRFIEN (1 << 1)
84 #define RK_I2C_IEN_MBTFIEN (1 << 2)
85 #define RK_I2C_IEN_MBRFIEN (1 << 3)
86 #define RK_I2C_IEN_STARTIEN (1 << 4)
87 #define RK_I2C_IEN_STOPIEN (1 << 5)
88 #define RK_I2C_IEN_NAKRCVIEN (1 << 6)
89 #define RK_I2C_IEN_ALL (RK_I2C_IEN_MBTFIEN | RK_I2C_IEN_MBRFIEN | \
90 RK_I2C_IEN_STARTIEN | RK_I2C_IEN_STOPIEN | RK_I2C_IEN_NAKRCVIEN)
91
92 #define RK_I2C_IPD 0x1C
93 #define RK_I2C_IPD_BTFIPD (1 << 0)
94 #define RK_I2C_IPD_BRFIPD (1 << 1)
95 #define RK_I2C_IPD_MBTFIPD (1 << 2)
96 #define RK_I2C_IPD_MBRFIPD (1 << 3)
97 #define RK_I2C_IPD_STARTIPD (1 << 4)
98 #define RK_I2C_IPD_STOPIPD (1 << 5)
99 #define RK_I2C_IPD_NAKRCVIPD (1 << 6)
100 #define RK_I2C_IPD_ALL (RK_I2C_IPD_MBTFIPD | RK_I2C_IPD_MBRFIPD | \
101 RK_I2C_IPD_STARTIPD | RK_I2C_IPD_STOPIPD | RK_I2C_IPD_NAKRCVIPD)
102
103 #define RK_I2C_FNCT 0x20
104 #define RK_I2C_FNCT_MASK 0x3F
105
106 #define RK_I2C_TXDATA_BASE 0x100
107
108 #define RK_I2C_RXDATA_BASE 0x200
109
110 /* 8 data registers, 4 bytes each. */
111 #define RK_I2C_MAX_RXTX_LEN 32
112
113 enum rk_i2c_state {
114 STATE_IDLE = 0,
115 STATE_START,
116 STATE_READ,
117 STATE_WRITE,
118 STATE_STOP
119 };
120
121 struct rk_i2c_softc {
122 device_t dev;
123 struct resource *res[2];
124 struct mtx mtx;
125 clk_t sclk;
126 clk_t pclk;
127 int busy;
128 void * intrhand;
129 uint32_t intr;
130 uint32_t ipd;
131 struct iic_msg *msg;
132 size_t cnt;
133 bool transfer_done;
134 bool nak_recv;
135 bool tx_slave_addr;
136 uint8_t mode;
137 uint8_t state;
138
139 device_t iicbus;
140 };
141
142 static struct ofw_compat_data compat_data[] = {
143 {"rockchip,rk3288-i2c", 1},
144 {"rockchip,rk3328-i2c", 1},
145 {"rockchip,rk3399-i2c", 1},
146 {NULL, 0}
147 };
148
149 static struct resource_spec rk_i2c_spec[] = {
150 { SYS_RES_MEMORY, 0, RF_ACTIVE },
151 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
152 { -1, 0 }
153 };
154
155 static int rk_i2c_probe(device_t dev);
156 static int rk_i2c_attach(device_t dev);
157 static int rk_i2c_detach(device_t dev);
158
159 #define RK_I2C_LOCK(sc) mtx_lock(&(sc)->mtx)
160 #define RK_I2C_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
161 #define RK_I2C_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
162 #define RK_I2C_READ(sc, reg) bus_read_4((sc)->res[0], (reg))
163 #define RK_I2C_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
164
165 static uint32_t
rk_i2c_get_clkdiv(struct rk_i2c_softc * sc,uint32_t speed)166 rk_i2c_get_clkdiv(struct rk_i2c_softc *sc, uint32_t speed)
167 {
168 uint64_t sclk_freq;
169 uint32_t clkdiv;
170 int err;
171
172 err = clk_get_freq(sc->sclk, &sclk_freq);
173 if (err != 0)
174 return (err);
175
176 clkdiv = (sclk_freq / speed / RK_I2C_CLKDIV_MUL / 2) - 1;
177 clkdiv &= RK_I2C_CLKDIVL_MASK;
178
179 clkdiv = clkdiv << RK_I2C_CLKDIVH_SHIFT | clkdiv;
180
181 return (clkdiv);
182 }
183
184 static int
rk_i2c_reset(device_t dev,u_char speed,u_char addr,u_char * oldaddr)185 rk_i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
186 {
187 struct rk_i2c_softc *sc;
188 uint32_t clkdiv;
189 u_int busfreq;
190
191 sc = device_get_softc(dev);
192
193 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed);
194
195 clkdiv = rk_i2c_get_clkdiv(sc, busfreq);
196
197 RK_I2C_LOCK(sc);
198
199 /* Set the clock divider */
200 RK_I2C_WRITE(sc, RK_I2C_CLKDIV, clkdiv);
201
202 /* Disable the module */
203 RK_I2C_WRITE(sc, RK_I2C_CON, 0);
204
205 RK_I2C_UNLOCK(sc);
206
207 return (0);
208 }
209
210 static uint8_t
rk_i2c_fill_tx(struct rk_i2c_softc * sc)211 rk_i2c_fill_tx(struct rk_i2c_softc *sc)
212 {
213 uint32_t buf32;
214 uint8_t buf;
215 int i, j, len;
216
217 len = sc->msg->len - sc->cnt;
218 if (sc->tx_slave_addr) {
219 KASSERT(sc->cnt == 0, ("tx_slave_addr in the middle of data"));
220 len++;
221 }
222
223 if (len > RK_I2C_MAX_RXTX_LEN)
224 len = RK_I2C_MAX_RXTX_LEN;
225
226 for (i = 0; i < len; ) {
227 buf32 = 0;
228
229 /* Process next 4 bytes or whatever remains. */
230 for (j = 0; j < MIN(len - i, 4); j++) {
231 /* Fill the addr if needed */
232 if (sc->tx_slave_addr) {
233 buf = sc->msg->slave;
234 sc->tx_slave_addr = false;
235 } else {
236 KASSERT(sc->cnt < sc->msg->len,
237 ("%s: data buffer overrun", __func__));
238 buf = sc->msg->buf[sc->cnt];
239 sc->cnt++;
240 }
241 buf32 |= (uint32_t)buf << (j * 8);
242 }
243
244 KASSERT(i % 4 == 0, ("%s: misaligned write offset", __func__));
245 RK_I2C_WRITE(sc, RK_I2C_TXDATA_BASE + i, buf32);
246
247 i += j;
248 }
249
250 return (len);
251 }
252
253 static void
rk_i2c_drain_rx(struct rk_i2c_softc * sc)254 rk_i2c_drain_rx(struct rk_i2c_softc *sc)
255 {
256 uint32_t buf32 = 0;
257 uint8_t buf8;
258 int len;
259 int i;
260
261 if (sc->msg == NULL) {
262 device_printf(sc->dev, "No current iic msg\n");
263 return;
264 }
265
266 len = sc->msg->len - sc->cnt;
267 if (len > RK_I2C_MAX_RXTX_LEN)
268 len = RK_I2C_MAX_RXTX_LEN;
269
270 for (i = 0; i < len; i++) {
271 if (i % 4 == 0)
272 buf32 = RK_I2C_READ(sc, RK_I2C_RXDATA_BASE + i);
273
274 buf8 = (buf32 >> ((i % 4) * 8)) & 0xFF;
275 sc->msg->buf[sc->cnt++] = buf8;
276 }
277 }
278
279 static void
rk_i2c_send_stop(struct rk_i2c_softc * sc)280 rk_i2c_send_stop(struct rk_i2c_softc *sc)
281 {
282 uint32_t reg;
283
284 if (!(sc->msg->flags & IIC_M_NOSTOP)) {
285 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_STOPIEN);
286
287 sc->state = STATE_STOP;
288
289 reg = RK_I2C_READ(sc, RK_I2C_CON);
290 reg |= RK_I2C_CON_STOP;
291 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
292 } else {
293 /*
294 * Do not actually set stop bit, set up conditions to
295 * emulate repeated start by clearing all state.
296 */
297 sc->state = STATE_IDLE;
298 sc->transfer_done = 1;
299
300 reg = RK_I2C_READ(sc, RK_I2C_CON);
301 reg &= ~RK_I2C_CON_CTRL_MASK;
302 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
303 }
304 }
305
306 static void
rk_i2c_intr_locked(struct rk_i2c_softc * sc)307 rk_i2c_intr_locked(struct rk_i2c_softc *sc)
308 {
309 uint32_t reg;
310 int transfer_len;
311
312 sc->ipd = RK_I2C_READ(sc, RK_I2C_IPD);
313
314 /* Something to handle? */
315 if ((sc->ipd & RK_I2C_IPD_ALL) == 0)
316 return;
317
318 RK_I2C_WRITE(sc, RK_I2C_IPD, sc->ipd);
319 sc->ipd &= RK_I2C_IPD_ALL;
320
321 if (sc->ipd & RK_I2C_IPD_NAKRCVIPD) {
322 /* NACK received */
323 sc->ipd &= ~RK_I2C_IPD_NAKRCVIPD;
324 sc->nak_recv = true;
325 /* XXXX last byte !!!, signal error !!! */
326 sc->transfer_done = true;
327 sc->state = STATE_IDLE;
328 goto err;
329 }
330
331 switch (sc->state) {
332 case STATE_START:
333 /* Disable start bit */
334 reg = RK_I2C_READ(sc, RK_I2C_CON);
335 reg &= ~RK_I2C_CON_START;
336 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
337
338 if (sc->mode == RK_I2C_CON_MODE_RRX ||
339 sc->mode == RK_I2C_CON_MODE_RX) {
340 sc->state = STATE_READ;
341 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBRFIEN |
342 RK_I2C_IEN_NAKRCVIEN);
343
344 if ((sc->msg->len - sc->cnt) > 32)
345 transfer_len = 32;
346 else {
347 transfer_len = sc->msg->len - sc->cnt;
348 reg = RK_I2C_READ(sc, RK_I2C_CON);
349 reg |= RK_I2C_CON_LASTACK;
350 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
351 }
352
353 RK_I2C_WRITE(sc, RK_I2C_MRXCNT, transfer_len);
354 } else {
355 sc->state = STATE_WRITE;
356 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBTFIEN |
357 RK_I2C_IEN_NAKRCVIEN);
358
359 transfer_len = rk_i2c_fill_tx(sc);
360 RK_I2C_WRITE(sc, RK_I2C_MTXCNT, transfer_len);
361 }
362 break;
363 case STATE_READ:
364 rk_i2c_drain_rx(sc);
365
366 if (sc->cnt == sc->msg->len) {
367 rk_i2c_send_stop(sc);
368 } else {
369 sc->mode = RK_I2C_CON_MODE_RX;
370 reg = RK_I2C_READ(sc, RK_I2C_CON) & \
371 ~RK_I2C_CON_CTRL_MASK;
372 reg |= sc->mode << RK_I2C_CON_MODE_SHIFT;
373 reg |= RK_I2C_CON_EN;
374
375 if ((sc->msg->len - sc->cnt) > 32)
376 transfer_len = 32;
377 else {
378 transfer_len = sc->msg->len - sc->cnt;
379 reg |= RK_I2C_CON_LASTACK;
380 }
381
382 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
383 RK_I2C_WRITE(sc, RK_I2C_MRXCNT, transfer_len);
384 }
385 break;
386 case STATE_WRITE:
387 if (sc->cnt < sc->msg->len) {
388 /* Keep writing. */
389 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBTFIEN |
390 RK_I2C_IEN_NAKRCVIEN);
391 transfer_len = rk_i2c_fill_tx(sc);
392 RK_I2C_WRITE(sc, RK_I2C_MTXCNT, transfer_len);
393 } else {
394 rk_i2c_send_stop(sc);
395 }
396 break;
397 case STATE_STOP:
398 /* Disable stop bit */
399 reg = RK_I2C_READ(sc, RK_I2C_CON);
400 reg &= ~RK_I2C_CON_STOP;
401 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
402
403 sc->transfer_done = 1;
404 sc->state = STATE_IDLE;
405 break;
406 case STATE_IDLE:
407 break;
408 }
409
410 err:
411 wakeup(sc);
412 }
413
414 static void
rk_i2c_intr(void * arg)415 rk_i2c_intr(void *arg)
416 {
417 struct rk_i2c_softc *sc;
418
419 sc = (struct rk_i2c_softc *)arg;
420
421 RK_I2C_LOCK(sc);
422 rk_i2c_intr_locked(sc);
423 RK_I2C_UNLOCK(sc);
424 }
425
426 static void
rk_i2c_start_xfer(struct rk_i2c_softc * sc,struct iic_msg * msg,boolean_t last)427 rk_i2c_start_xfer(struct rk_i2c_softc *sc, struct iic_msg *msg, boolean_t last)
428 {
429 uint32_t reg;
430 uint8_t len;
431
432 sc->transfer_done = false;
433 sc->nak_recv = false;
434 sc->tx_slave_addr = false;
435 sc->cnt = 0;
436 sc->state = STATE_IDLE;
437 sc->msg = msg;
438
439 reg = RK_I2C_READ(sc, RK_I2C_CON) & ~RK_I2C_CON_CTRL_MASK;
440 if (!(sc->msg->flags & IIC_M_NOSTART)) {
441 /* Stadard message */
442 if (sc->mode == RK_I2C_CON_MODE_TX) {
443 sc->tx_slave_addr = true;
444 }
445 sc->state = STATE_START;
446 reg |= RK_I2C_CON_START;
447
448 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_STARTIEN);
449 } else {
450 /* Continuation message */
451 if (sc->mode == RK_I2C_CON_MODE_RX) {
452 sc->state = STATE_READ;
453 if (last)
454 reg |= RK_I2C_CON_LASTACK;
455
456 RK_I2C_WRITE(sc, RK_I2C_MRXCNT, sc->msg->len);
457 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBRFIEN |
458 RK_I2C_IEN_NAKRCVIEN);
459 } else {
460 sc->state = STATE_WRITE;
461 len = rk_i2c_fill_tx(sc);
462
463 RK_I2C_WRITE(sc, RK_I2C_MTXCNT, len);
464
465 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBTFIEN |
466 RK_I2C_IEN_NAKRCVIEN);
467 }
468 }
469 reg |= RK_I2C_CON_NAKSTOP;
470 reg |= sc->mode << RK_I2C_CON_MODE_SHIFT;
471 reg |= RK_I2C_CON_EN;
472 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
473 }
474
475 static int
rk_i2c_transfer(device_t dev,struct iic_msg * msgs,uint32_t nmsgs)476 rk_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
477 {
478 struct rk_i2c_softc *sc;
479 uint32_t reg;
480 bool last_msg;
481 int i, j, timeout, err;
482
483 sc = device_get_softc(dev);
484
485 RK_I2C_LOCK(sc);
486
487 while (sc->busy)
488 mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0);
489 sc->busy = 1;
490
491 /* Disable the module and interrupts */
492 RK_I2C_WRITE(sc, RK_I2C_CON, 0);
493 RK_I2C_WRITE(sc, RK_I2C_IEN, 0);
494
495 /* Clean stale interrupts */
496 RK_I2C_WRITE(sc, RK_I2C_IPD, RK_I2C_IPD_ALL);
497
498 err = 0;
499 for (i = 0; i < nmsgs; i++) {
500 /* Validate parameters. */
501 if (msgs == NULL || msgs[i].buf == NULL ||
502 msgs[i].len == 0) {
503 err = IIC_ENOTSUPP;
504 break;
505 }
506 /*
507 * If next message have NOSTART flag, then they both
508 * should be same type (read/write) and same address.
509 */
510 if (i < nmsgs - 1) {
511 if ((msgs[i + 1].flags & IIC_M_NOSTART) &&
512 ((msgs[i].flags & IIC_M_RD) !=
513 (msgs[i + 1].flags & IIC_M_RD) ||
514 (msgs[i].slave != msgs[i + 1].slave))) {
515 err = IIC_ENOTSUPP;
516 break;
517 }
518 }
519 /*
520 * Detect simple register read case.
521 * The first message should be IIC_M_WR | IIC_M_NOSTOP,
522 * next pure IIC_M_RD (no other flags allowed). Both
523 * messages should have same slave address.
524 */
525
526 if (nmsgs - i >= 2 && msgs[i].len < 4 &&
527 msgs[i].flags == (IIC_M_WR | IIC_M_NOSTOP) &&
528 (msgs[i + 1].flags & IIC_M_RD) == IIC_M_RD &&
529 (msgs[i].slave & ~LSB) == (msgs[i + 1].slave & ~LSB)) {
530 sc->mode = RK_I2C_CON_MODE_RRX;
531
532 /* Write slave address */
533 reg = msgs[i].slave & ~LSB;
534 reg |= RK_I2C_MRXADDR_VALID(0);
535 RK_I2C_WRITE(sc, RK_I2C_MRXADDR, reg);
536
537 /* Write slave register address */
538 reg = 0;
539 for (j = 0; j < msgs[i].len ; j++) {
540 reg |= (uint32_t)msgs[i].buf[j] << (j * 8);
541 reg |= RK_I2C_MRXADDR_VALID(j);
542 }
543 RK_I2C_WRITE(sc, RK_I2C_MRXRADDR, reg);
544
545 i++;
546 } else {
547 if (msgs[i].flags & IIC_M_RD) {
548 if (msgs[i].flags & IIC_M_NOSTART) {
549 sc->mode = RK_I2C_CON_MODE_RX;
550 } else {
551 sc->mode = RK_I2C_CON_MODE_RRX;
552 reg = msgs[i].slave & ~LSB;
553 reg |= RK_I2C_MRXADDR_VALID(0);
554 RK_I2C_WRITE(sc, RK_I2C_MRXADDR, reg);
555 RK_I2C_WRITE(sc, RK_I2C_MRXRADDR, 0);
556 }
557 } else {
558 sc->mode = RK_I2C_CON_MODE_TX;
559 }
560 }
561 /* last message ? */
562 last_msg = (i >= nmsgs - 1) ||
563 !(msgs[i + 1].flags & IIC_M_NOSTART);
564 rk_i2c_start_xfer(sc, msgs + i, last_msg);
565
566 if (cold) {
567 for(timeout = 10000; timeout > 0; timeout--) {
568 rk_i2c_intr_locked(sc);
569 if (sc->transfer_done)
570 break;
571 DELAY(1000);
572 }
573 if (timeout <= 0)
574 err = IIC_ETIMEOUT;
575 } else {
576 while (err == 0 && !sc->transfer_done) {
577 err = msleep(sc, &sc->mtx, PZERO, "rk_i2c",
578 10 * hz);
579 }
580 }
581 }
582
583 /* Disable the module and interrupts */
584 RK_I2C_WRITE(sc, RK_I2C_CON, 0);
585 RK_I2C_WRITE(sc, RK_I2C_IEN, 0);
586
587 sc->busy = 0;
588
589 if (sc->nak_recv)
590 err = IIC_ENOACK;
591
592 RK_I2C_UNLOCK(sc);
593 return (err);
594 }
595
596 static int
rk_i2c_probe(device_t dev)597 rk_i2c_probe(device_t dev)
598 {
599
600 if (!ofw_bus_status_okay(dev))
601 return (ENXIO);
602 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
603 return (ENXIO);
604
605 device_set_desc(dev, "RockChip I2C");
606 return (BUS_PROBE_DEFAULT);
607 }
608
609 static int
rk_i2c_attach(device_t dev)610 rk_i2c_attach(device_t dev)
611 {
612 struct rk_i2c_softc *sc;
613 int error;
614
615 sc = device_get_softc(dev);
616 sc->dev = dev;
617
618 mtx_init(&sc->mtx, device_get_nameunit(dev), "rk_i2c", MTX_DEF);
619
620 if (bus_alloc_resources(dev, rk_i2c_spec, sc->res) != 0) {
621 device_printf(dev, "cannot allocate resources for device\n");
622 error = ENXIO;
623 goto fail;
624 }
625
626 if (bus_setup_intr(dev, sc->res[1],
627 INTR_TYPE_MISC | INTR_MPSAFE, NULL, rk_i2c_intr, sc,
628 &sc->intrhand)) {
629 bus_release_resources(dev, rk_i2c_spec, sc->res);
630 device_printf(dev, "cannot setup interrupt handler\n");
631 return (ENXIO);
632 }
633
634 clk_set_assigned(dev, ofw_bus_get_node(dev));
635
636 /* Activate the module clocks. */
637 error = clk_get_by_ofw_name(dev, 0, "i2c", &sc->sclk);
638 if (error != 0) {
639 device_printf(dev, "cannot get i2c clock\n");
640 goto fail;
641 }
642 error = clk_enable(sc->sclk);
643 if (error != 0) {
644 device_printf(dev, "cannot enable i2c clock\n");
645 goto fail;
646 }
647 /* pclk clock is optional. */
648 error = clk_get_by_ofw_name(dev, 0, "pclk", &sc->pclk);
649 if (error != 0 && error != ENOENT) {
650 device_printf(dev, "cannot get pclk clock\n");
651 goto fail;
652 }
653 if (sc->pclk != NULL) {
654 error = clk_enable(sc->pclk);
655 if (error != 0) {
656 device_printf(dev, "cannot enable pclk clock\n");
657 goto fail;
658 }
659 }
660
661 sc->iicbus = device_add_child(dev, "iicbus", DEVICE_UNIT_ANY);
662 if (sc->iicbus == NULL) {
663 device_printf(dev, "cannot add iicbus child device\n");
664 error = ENXIO;
665 goto fail;
666 }
667
668 bus_attach_children(dev);
669
670 return (0);
671
672 fail:
673 if (rk_i2c_detach(dev) != 0)
674 device_printf(dev, "Failed to detach\n");
675 return (error);
676 }
677
678 static int
rk_i2c_detach(device_t dev)679 rk_i2c_detach(device_t dev)
680 {
681 struct rk_i2c_softc *sc;
682 int error;
683
684 sc = device_get_softc(dev);
685
686 if ((error = bus_generic_detach(dev)) != 0)
687 return (error);
688
689 if (sc->iicbus != NULL)
690 if ((error = device_delete_child(dev, sc->iicbus)) != 0)
691 return (error);
692
693 if (sc->sclk != NULL)
694 clk_release(sc->sclk);
695 if (sc->pclk != NULL)
696 clk_release(sc->pclk);
697
698 if (sc->intrhand != NULL)
699 bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand);
700
701 bus_release_resources(dev, rk_i2c_spec, sc->res);
702
703 mtx_destroy(&sc->mtx);
704
705 return (0);
706 }
707
708 static phandle_t
rk_i2c_get_node(device_t bus,device_t dev)709 rk_i2c_get_node(device_t bus, device_t dev)
710 {
711
712 return ofw_bus_get_node(bus);
713 }
714
715 static device_method_t rk_i2c_methods[] = {
716 DEVMETHOD(device_probe, rk_i2c_probe),
717 DEVMETHOD(device_attach, rk_i2c_attach),
718 DEVMETHOD(device_detach, rk_i2c_detach),
719
720 /* OFW methods */
721 DEVMETHOD(ofw_bus_get_node, rk_i2c_get_node),
722
723 DEVMETHOD(iicbus_callback, iicbus_null_callback),
724 DEVMETHOD(iicbus_reset, rk_i2c_reset),
725 DEVMETHOD(iicbus_transfer, rk_i2c_transfer),
726
727 DEVMETHOD_END
728 };
729
730 static driver_t rk_i2c_driver = {
731 "rk_i2c",
732 rk_i2c_methods,
733 sizeof(struct rk_i2c_softc),
734 };
735
736 EARLY_DRIVER_MODULE(rk_i2c, simplebus, rk_i2c_driver, 0, 0,
737 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
738 EARLY_DRIVER_MODULE(ofw_iicbus, rk_i2c, ofw_iicbus_driver,
739 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
740 MODULE_DEPEND(rk_i2c, iicbus, 1, 1, 1);
741 MODULE_VERSION(rk_i2c, 1);
742