1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 #ifndef __SOC_RK3588_GRF_H 3 #define __SOC_RK3588_GRF_H 4 5 #define RK3588_PMUGRF_OS_REG2 0x208 6 #define RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13) 7 #define RK3588_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2) 8 #define RK3588_PMUGRF_OS_REG2_BW_CH1 GENMASK(19, 18) 9 #define RK3588_PMUGRF_OS_REG2_CH_INFO GENMASK(29, 28) 10 11 #define RK3588_PMUGRF_OS_REG3 0x20c 12 #define RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12) 13 #define RK3588_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28) 14 15 #define RK3588_PMUGRF_OS_REG4 0x210 16 #define RK3588_PMUGRF_OS_REG5 0x214 17 #define RK3588_PMUGRF_OS_REG6 0x218 18 #define RK3588_PMUGRF_OS_REG6_LP5_BANK_MODE GENMASK(2, 1) 19 /* Whether the LPDDR5 is in 2:1 (= 0) or 4:1 (= 1) CKR a.k.a. DQS mode */ 20 #define RK3588_PMUGRF_OS_REG6_LP5_CKR BIT(0) 21 22 #endif /* __SOC_RK3588_GRF_H */ 23