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Searched defs:RC (Results 1 – 25 of 311) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp92 const TargetRegisterClass &RC = *MRI.getRegClass(Reg); in mask() local
123 if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg)) in getPhysRegBitWidth() local
131 const TargetRegisterClass &RC, unsigned Idx) const { in composeWithSubRegIndex() argument
281 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
288 auto half = [this] (const BT::RegisterCell &RC, unsigned N) in evaluate()
289 -> BT::RegisterCell { in evaluate()
298 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate() local
333 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
349 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); in evaluate() local
356 RegisterCell RC = RegisterCell::self(Reg[0].Reg, RW); in evaluate() local
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H A DHexagonConstPropagation.cpp718 LatticeCell RC = Cells.get(DefR.Reg); in visitNonBranch() local
1080 LatticeCell &RC) { in getCell() argument
1390 LatticeCell RC; in evaluateANDrr() local
1406 LatticeCell RC; evaluateANDri() local
1457 LatticeCell RC; evaluateORrr() local
1473 LatticeCell RC; evaluateORri() local
1522 LatticeCell RC; evaluateXORrr() local
1941 LatticeCell RC; evaluate() local
1963 LatticeCell RC; evaluate() local
1997 LatticeCell RC = Outputs.get(DefR.Reg); evaluate() local
2006 LatticeCell RC = Outputs.get(DefR.Reg); evaluate() local
2040 LatticeCell RC = Outputs.get(DefR.Reg); evaluate() local
2052 LatticeCell RC = Outputs.get(DefR.Reg); evaluate() local
2101 LatticeCell RC = Outputs.get(DefR.Reg); evaluate() local
2133 LatticeCell RC = Outputs.get(DefR.Reg); evaluate() local
2155 LatticeCell RC = Outputs.get(DefR.Reg); evaluate() local
2208 const TargetRegisterClass *RC = MRI->getRegClass(R.Reg); evaluate() local
2360 const TargetRegisterClass *RC = MRI->getRegClass(Reg); getRegBitWidth() local
2636 LatticeCell RC; evaluateHexLogical() local
2693 LatticeCell RC = Outputs.get(DefR.Reg); evaluateHexCondMove() local
2752 LatticeCell RC = Outputs.get(DefR.Reg); evaluateHexExt() local
2767 LatticeCell RC = Outputs.get(DefR.Reg); evaluateHexVector1() local
2868 const TargetRegisterClass *RC = MRI->getRegClass(R); rewriteHexConstDefs() local
2995 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); rewriteHexConstUses() local
3024 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); rewriteHexConstUses() local
3061 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); rewriteHexConstUses() local
3093 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); rewriteHexConstUses() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h192 isSGPRClass(const TargetRegisterClass * RC) isSGPRClass() argument
204 isVGPRClass(const TargetRegisterClass * RC) isVGPRClass() argument
209 isAGPRClass(const TargetRegisterClass * RC) isAGPRClass() argument
214 isVectorSuperClass(const TargetRegisterClass * RC) isVectorSuperClass() argument
219 isVSSuperClass(const TargetRegisterClass * RC) isVSSuperClass() argument
224 hasVGPRs(const TargetRegisterClass * RC) hasVGPRs() argument
229 hasAGPRs(const TargetRegisterClass * RC) hasAGPRs() argument
234 hasSGPRs(const TargetRegisterClass * RC) hasSGPRs() argument
239 hasVectorRegisters(const TargetRegisterClass * RC) hasVectorRegisters() argument
299 isDivergentRegClass(const TargetRegisterClass * RC) isDivergentRegClass() argument
429 getRegClassAlignmentNumBits(const TargetRegisterClass * RC) getRegClassAlignmentNumBits() argument
434 isRegClassAligned(const TargetRegisterClass * RC,unsigned AlignNumBits) isRegClassAligned() argument
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H A DGCNRewritePartialRegUses.cpp81 const TargetRegisterClass *RC; member
187 GCNRewritePartialRegUses::getSuperRegClassMask(const TargetRegisterClass *RC, in getSuperRegClassMask()
210 auto *RC = TRI->getRegClass(ClassID); in getAllocatableAndAlignedRegClassMask() local
220 const TargetRegisterClass *RC, unsigned RShift, unsigned RegNumBits, in getRegClassWithShiftedSubregs()
271 auto *RC = TRI->getRegClass(ClassID); in getRegClassWithShiftedSubregs() local
294 GCNRewritePartialRegUses::getMinSizeReg(const TargetRegisterClass *RC, in getMinSizeReg()
418 auto *RC = MRI->getRegClass(Reg); in rewriteReg() local
H A DSILowerSGPRSpills.cpp105 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass( in insertCSRSaves() local
146 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass( in insertCSRRestores() local
235 const TargetRegisterClass *RC = in spillCalleeSavedRegs() local
430 const TargetRegisterClass *RC = TRI->getWaveMaskRegClass(); in runOnMachineFunction() local
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h78 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
94 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
101 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
111 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
131 uint8_t getMinCost(const TargetRegisterClass *RC) const { in getMinCost()
139 unsigned getLastCostChange(const TargetRegisterClass *RC) const { in getLastCostChange()
H A DTargetRegisterInfo.h126 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
131 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
138 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
143 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
297 TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits()
303 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize()
309 Align getSpillAlign(const TargetRegisterClass &RC) const { in getSpillAlign()
314 bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const { in isTypeLegalForClass()
322 bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const { in isTypeLegalForClass()
336 vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const { in legalclasstypes_begin()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyExplicitLocals.cpp88 static unsigned getDropOpcode(const TargetRegisterClass *RC) { in getDropOpcode()
109 static unsigned getLocalGetOpcode(const TargetRegisterClass *RC) { in getLocalGetOpcode()
130 static unsigned getLocalSetOpcode(const TargetRegisterClass *RC) { in getLocalSetOpcode()
151 static unsigned getLocalTeeOpcode(const TargetRegisterClass *RC) { in getLocalTeeOpcode()
172 static MVT typeForRegClass(const TargetRegisterClass *RC) { in typeForRegClass()
311 const TargetRegisterClass *RC = MRI.getRegClass(DefReg); in runOnMachineFunction() local
344 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
416 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp74 void addRegisterClass(const CodeGenRegisterClass *RC) { in addRegisterClass()
176 const CodeGenRegisterClass *RC, const Twine &Kind, in visitRegisterBankClasses()
227 for (const auto &RC : Bank.register_classes()) in emitBaseClassImplementation() local
235 for (const auto &RC : RCs) { in emitBaseClassImplementation() local
274 const CodeGenRegisterClass &RC = *Bank.getRCWithLargestRegSize(M); in emitBaseClassImplementation() local
305 for (const CodeGenRegisterClass *RC : in run() local
309 [&Bank](const CodeGenRegisterClass *RC, StringRef Kind) { in run()
H A DRegisterInfoEmitter.cpp148 for (const auto &RC : RegisterClasses) in runEnums() local
217 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure() local
1008 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1044 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1163 [](const auto &RC) { return RC.getBaseClassOrder(); })) { in runTargetHeader()
1174 for (const auto &RC : RegisterClasses) { in runTargetHeader() local
1210 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1223 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1281 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1325 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp45 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createLRSpillSlot() local
63 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createFPSpillSlot() local
76 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createEHSpillSlot() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMachineFunction.cpp78 const TargetRegisterClass *RC; initGlobalBaseReg() local
159 const TargetRegisterClass &RC = createEhDataRegsFI() local
174 const TargetRegisterClass &RC = Mips::GPR32RegClass; createISRRegFI() local
201 getMoveF64ViaSpillFI(MachineFunction & MF,const TargetRegisterClass * RC) getMoveF64ViaSpillFI() argument
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H A DMipsSEFrameLowering.cpp173 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
188 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
231 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC() local
264 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); in expandCopyACC() local
317 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64() local
383 const TargetRegisterClass *RC = in expandExtractElementF64() local
421 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? in emitPrologue() local
718 const TargetRegisterClass *RC = in emitEpilogue() local
833 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters() local
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H A DMipsInstrInfo.h139 const TargetRegisterClass *RC, in storeRegToStackSlot()
147 int FrameIndex, const TargetRegisterClass *RC, in loadRegFromStackSlot()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp449 const TargetRegisterClass *RC, in PPCEmitLoad()
606 const TargetRegisterClass *RC = in SelectLoad() local
623 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); in PPCEmitStore() local
987 auto RC = MRI.getRegClass(SrcReg); in SelectFPTrunc() local
1051 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in PPCMoveToFPReg() local
1130 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in SelectIToFP() local
1174 const TargetRegisterClass *RC = in PPCMoveToIntReg() local
1225 auto RC = MRI.getRegClass(SrcReg); in SelectFPToI() local
1280 const TargetRegisterClass *RC = in SelectBinaryIntOp() local
1440 const TargetRegisterClass *RC = in processCallArgs() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.cpp85 const TargetRegisterClass *RC = &Xtensa::ARRegClass; in adjustStackPtr() local
121 bool isKill, int FrameIdx, const TargetRegisterClass *RC, in storeRegToStackSlot()
134 const TargetRegisterClass *RC, in loadRegFromStackSlot()
143 void XtensaInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC, in getLoadStoreOpcodes()
159 const TargetRegisterClass *RC = &Xtensa::ARRegClass; in loadImmediate() local
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveStacks.cpp54 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval()
79 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print() local
H A DSwiftErrorValueTracking.cpp36 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVReg() local
58 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVRegDefAt() local
126 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in createEntriesInEntryBlock() local
240 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in propagateVRegs() local
H A DRegisterBank.cpp37 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); verify() local
107 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); print() local
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp59 for (const TargetRegisterClass *RC : TRI->regclasses()) in ResourcePriorityQueue() local
359 for (const TargetRegisterClass *RC : TRI->regclasses()) in regPressureDelta() local
363 for (const TargetRegisterClass *RC : TRI->regclasses()) { in regPressureDelta() local
477 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
488 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.cpp29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { in getNVPTXRegClassName()
67 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { in getNVPTXRegClassStr()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstantFolder.h46 auto *RC = dyn_cast<Constant>(RHS); in FoldBinOp() local
58 auto *RC = dyn_cast<Constant>(RHS); in FoldExactBinOp() local
71 auto *RC = dyn_cast<Constant>(RHS); in FoldNoWrapBinOp() local
100 auto *RC = dyn_cast<Constant>(RHS); in FoldCmp() local
/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DTargetFolder.h57 auto *RC = dyn_cast<Constant>(RHS); in FoldBinOp() local
69 auto *RC = dyn_cast<Constant>(RHS); in FoldExactBinOp() local
82 auto *RC = dyn_cast<Constant>(RHS); in FoldNoWrapBinOp() local
104 auto *RC = dyn_cast<Constant>(RHS); in FoldCmp() local
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h245 getLargestSuperClass(const TargetRegisterClass *RC) const override { in getLargestSuperClass()
258 const TargetRegisterClass *RC) const override { in doesRegClassHavePseudoInitUndef()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp1011 CodeGenRegisterClass &RC = *I; in computeSubClasses() local
1035 for (auto &RC : RegClasses) { in computeSubClasses() local
1051 for (auto &RC : RegClasses) in computeSubClasses() local
1079 for (auto &RC : RegClasses) in getMatchingSubClassWithSubRegs() local
1089 for (auto &RC : RegClasses) { in getMatchingSubClassWithSubRegs() local
1301 CodeGenRegisterClass &RC = RegClasses.back(); in CodeGenRegBank() local
1312 for (auto &RC : RegClasses) in CodeGenRegBank() local
1353 void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) { in addToMaps()
1365 CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC, in getOrCreateSubClass()
1381 if (CodeGenRegisterClass *RC = Def2RC.lookup(Def)) in getRegClass() local
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