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Searched defs:RC (Results 1 – 25 of 318) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp82 const TargetRegisterClass &RC = *MRI.getRegClass(Reg); in mask() local
114 if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg)) in getPhysRegBitWidth() local
122 const TargetRegisterClass &RC, unsigned Idx) const { in composeWithSubRegIndex() argument
273 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
280 auto half = [this] (const BT::RegisterCell &RC, unsigned N) in evaluate()
281 -> BT::RegisterCell { in evaluate()
290 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate() local
325 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
341 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); in evaluate() local
348 RegisterCell RC = RegisterCell::self(Reg[0].Reg, RW); in evaluate() local
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H A DHexagonConstPropagation.cpp699 LatticeCell RC = Cells.get(DefR.Reg); in visitNonBranch() local
1060 const CellMap &Inputs, LatticeCell &RC) { in getCell()
1376 LatticeCell RC; in evaluateANDrr() local
1394 LatticeCell RC; in evaluateANDri() local
1447 LatticeCell RC; in evaluateORrr() local
1464 LatticeCell RC; in evaluateORri() local
1515 LatticeCell RC; in evaluateXORrr() local
1938 LatticeCell RC; in evaluate() local
1960 LatticeCell RC; in evaluate() local
1994 LatticeCell RC = Outputs.get(DefR.Reg); in evaluate() local
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H A DHexagonBitSimplify.cpp336 bool HexagonBitSimplify::isZero(const BitTracker::RegisterCell &RC, in isZero()
345 bool HexagonBitSimplify::getConst(const BitTracker::RegisterCell &RC, in getConst()
415 const TargetRegisterClass *RC = MRI.getRegClass(RR.Reg); in getSubregMask() local
907 auto *RC = MRI.getRegClass(RR.Reg); in getFinalVRegClass() local
913 auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void { in getFinalVRegClass()
1268 const TargetRegisterClass *RC = HBS::getFinalVRegClass(RR, MRI); in computeUsedBits() local
1418 Register ConstGeneration::genTfrConst(const TargetRegisterClass *RC, int64_t C, in genTfrConst()
1564 const BitTracker::RegisterCell &RC = BT.lookup(R); in findMatch() local
1699 const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg); in propagateRegCopy() local
1709 const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg); in propagateRegCopy() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h226 static bool isSGPRClass(const TargetRegisterClass *RC) { in isSGPRClass()
245 static bool isVGPRClass(const TargetRegisterClass *RC) { in isVGPRClass()
250 static bool isAGPRClass(const TargetRegisterClass *RC) { in isAGPRClass()
255 bool isVectorSuperClass(const TargetRegisterClass *RC) const { in isVectorSuperClass()
260 bool isVSSuperClass(const TargetRegisterClass *RC) const { in isVSSuperClass()
265 static bool hasVGPRs(const TargetRegisterClass *RC) { in hasVGPRs()
270 static bool hasAGPRs(const TargetRegisterClass *RC) { in hasAGPRs()
275 static bool hasSGPRs(const TargetRegisterClass *RC) { in hasSGPRs()
280 static bool hasVectorRegisters(const TargetRegisterClass *RC) { in hasVectorRegisters()
335 bool isDivergentRegClass(const TargetRegisterClass *RC) const override { in isDivergentRegClass()
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H A DGCNRewritePartialRegUses.cpp174 const TargetRegisterClass *RC, unsigned SubRegIdx) const { in getSuperRegClassMask() argument
197 auto *RC = TRI->getRegClass(ClassID); in getAllocatableAndAlignedRegClassMask() local
207 const TargetRegisterClass *RC, unsigned RShift, unsigned CoverSubregIdx, in getRegClassWithShiftedSubregs()
259 auto *RC = TRI->getRegClass(ClassID); in getRegClassWithShiftedSubregs() local
280 GCNRewritePartialRegUsesImpl::getMinSizeReg(const TargetRegisterClass *RC, in getMinSizeReg()
401 auto *RC = MRI->getRegClass(Reg); in rewriteReg() local
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h81 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
99 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
106 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
116 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
136 uint8_t getMinCost(const TargetRegisterClass *RC) const { in getMinCost()
144 unsigned getLastCostChange(const TargetRegisterClass *RC) const { in getLastCostChange()
H A DTargetRegisterInfo.h126 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
131 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
138 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
143 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
296 TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits()
302 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize()
308 Align getSpillAlign(const TargetRegisterClass &RC) const { in getSpillAlign()
313 bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const { in isTypeLegalForClass()
321 bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const { in isTypeLegalForClass()
335 vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const { in legalclasstypes_begin()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyExplicitLocals.cpp88 static unsigned getDropOpcode(const TargetRegisterClass *RC) { in getDropOpcode()
109 static unsigned getLocalGetOpcode(const TargetRegisterClass *RC) { in getLocalGetOpcode()
130 static unsigned getLocalSetOpcode(const TargetRegisterClass *RC) { in getLocalSetOpcode()
151 static unsigned getLocalTeeOpcode(const TargetRegisterClass *RC) { in getLocalTeeOpcode()
172 static MVT typeForRegClass(const TargetRegisterClass *RC) { in typeForRegClass()
333 const TargetRegisterClass *RC = MRI.getRegClass(DefReg); in runOnMachineFunction() local
366 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
438 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp76 void addRegisterClass(const CodeGenRegisterClass *RC) { in addRegisterClass()
180 const CodeGenRegisterClass *RC, const Twine &Kind, in visitRegisterBankClasses()
231 for (const auto &RC : Bank.register_classes()) in emitBaseClassImplementation() local
239 for (const auto &RC : RCs) { in emitBaseClassImplementation() local
278 const CodeGenRegisterClass &RC = *Bank.getRCWithLargestRegSize(M); in emitBaseClassImplementation() local
307 for (const auto *RC : Bank.register_classes()) { in emitBaseClassImplementation() local
397 for (const CodeGenRegisterClass *RC : in run() local
401 [&Bank](const CodeGenRegisterClass *RC, StringRef Kind) { in run()
H A DRegisterInfoEmitter.cpp144 for (const auto &RC : RegisterClasses) in runEnums() local
211 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure() local
1045 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1081 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1202 [](const auto &RC) { return RC.getBaseClassOrder(); })) { in runTargetHeader()
1213 for (const auto &RC : RegisterClasses) { in runTargetHeader() local
1248 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1262 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1320 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1361 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp45 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createLRSpillSlot() local
63 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createFPSpillSlot() local
76 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createEHSpillSlot() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp171 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
186 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
204 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
229 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC() local
262 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); in expandCopyACC() local
315 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64() local
381 const TargetRegisterClass *RC = in expandExtractElementF64() local
418 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? in emitPrologue() local
682 const TargetRegisterClass *RC = in emitEpilogue() local
797 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters() local
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H A DMipsMachineFunction.cpp78 const TargetRegisterClass *RC; initGlobalBaseReg() local
159 const TargetRegisterClass &RC = createEhDataRegsFI() local
174 const TargetRegisterClass &RC = Mips::GPR32RegClass; createISRRegFI() local
201 getMoveF64ViaSpillFI(MachineFunction & MF,const TargetRegisterClass * RC) getMoveF64ViaSpillFI() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/DirectX/
H A DDXILPrettyPrinter.cpp22 static StringRef getRCName(dxil::ResourceClass RC) { in getRCName()
36 static StringRef getRCPrefix(dxil::ResourceClass RC) { in getRCPrefix()
181 dxil::ResourceClass RC; member
195 dxil::ResourceClass RC; member
240 dxil::ResourceClass RC = RTI.getResourceClass(); in prettyPrintResources() local
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp437 const TargetRegisterClass *RC, in PPCEmitLoad()
594 const TargetRegisterClass *RC = in SelectLoad() local
611 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); in PPCEmitStore() local
975 auto RC = MRI.getRegClass(SrcReg); in SelectFPTrunc() local
1039 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in PPCMoveToFPReg() local
1118 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in SelectIToFP() local
1162 const TargetRegisterClass *RC = in PPCMoveToIntReg() local
1213 auto RC = MRI.getRegClass(SrcReg); in SelectFPToI() local
1268 const TargetRegisterClass *RC = in SelectBinaryIntOp() local
1429 const TargetRegisterClass *RC = in processCallArgs() local
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DSwiftErrorValueTracking.cpp36 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVReg() local
58 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVRegDefAt() local
126 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in createEntriesInEntryBlock() local
240 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in propagateVRegs() local
H A DRegisterBank.cpp37 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); verify() local
107 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); print() local
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H A DLiveStacks.cpp53 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval()
105 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print() local
H A DRegAllocBase.cpp127 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg->reg()); in allocatePhysRegs() local
213 MCPhysReg RegAllocBase::getErrorAssignment(const TargetRegisterClass &RC, in getErrorAssignment()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp59 for (const TargetRegisterClass *RC : TRI->regclasses()) in ResourcePriorityQueue() local
359 for (const TargetRegisterClass *RC : TRI->regclasses()) in regPressureDelta() local
363 for (const TargetRegisterClass *RC : TRI->regclasses()) { in regPressureDelta() local
477 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
488 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstantFolder.h47 auto *RC = dyn_cast<Constant>(RHS); in FoldBinOp() local
59 auto *RC = dyn_cast<Constant>(RHS); in FoldExactBinOp() local
72 auto *RC = dyn_cast<Constant>(RHS); in FoldNoWrapBinOp() local
101 auto *RC = dyn_cast<Constant>(RHS); in FoldCmp() local
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp935 CodeGenRegisterClass &RC = *I; in computeSubClasses() local
959 for (auto &RC : RegClasses) { in computeSubClasses() local
1003 for (auto &RC : RegClasses) in getMatchingSubClassWithSubRegs() local
1013 for (auto &RC : RegClasses) { in getMatchingSubClassWithSubRegs() local
1145 const RecordKeeper &RC = Records; in CodeGenRegBank() local
1173 for (const Record *RC : TupRegs) in CodeGenRegBank() local
1243 CodeGenRegisterClass &RC = RegClasses.back(); in CodeGenRegBank() local
1292 void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) { in addToMaps()
1304 CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC, in getOrCreateSubClass()
1320 if (CodeGenRegisterClass *RC = Def2RC.lookup(Def)) in getRegClass() local
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/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DTargetFolder.h58 auto *RC = dyn_cast<Constant>(RHS); in FoldBinOp() local
70 auto *RC = dyn_cast<Constant>(RHS); in FoldExactBinOp() local
83 auto *RC = dyn_cast<Constant>(RHS); in FoldNoWrapBinOp() local
105 auto *RC = dyn_cast<Constant>(RHS); in FoldCmp() local
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVRegisterBankInfo.cpp29 SPIRVRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, in getRegBankFromRegClass()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.cpp27 StringRef getNVPTXRegClassName(TargetRegisterClass const *RC) { in getNVPTXRegClassName()
61 StringRef getNVPTXRegClassStr(TargetRegisterClass const *RC) { in getNVPTXRegClassStr()

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