1 /*-
2 * Copyright (c) 2017 Semihalf.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/param.h>
28 #include <sys/bus.h>
29 #include <sys/conf.h>
30 #include <sys/kernel.h>
31 #include <sys/sysctl.h>
32 #include <sys/systm.h>
33
34 #include <machine/bus.h>
35
36 #include <dev/ofw/ofw_bus_subr.h>
37 #include <dev/uart/uart.h>
38 #include <dev/uart/uart_bus.h>
39 #include <dev/uart/uart_cpu.h>
40 #include <dev/uart/uart_cpu_fdt.h>
41
42 #include "uart_if.h"
43
44 #define UART_RBR 0x00 /* Receiver Buffer */
45 #define RBR_BRK_DET (1 << 15) /* Break Detect */
46 #define RBR_FRM_ERR_DET (1 << 14) /* Frame Error Detect */
47 #define RBR_PAR_ERR_DET (1 << 13) /* Parity Error Detect */
48 #define RBR_OVR_ERR_DET (1 << 12) /* Overrun Error */
49
50 #define UART_TSH 0x04 /* Transmitter Holding Register */
51
52 #define UART_CTRL 0x08 /* Control Register */
53 #define CTRL_SOFT_RST (1 << 31) /* Soft Reset */
54 #define CTRL_TX_FIFO_RST (1 << 15) /* TX FIFO Reset */
55 #define CTRL_RX_FIFO_RST (1 << 14) /* RX FIFO Reset */
56 #define CTRL_ST_MIRR_EN (1 << 13) /* Status Mirror Enable */
57 #define CTRL_LPBK_EN (1 << 12) /* Loopback Mode Enable */
58 #define CTRL_SND_BRK_SEQ (1 << 11) /* Send Break Sequence */
59 #define CTRL_PAR_EN (1 << 10) /* Parity Enable */
60 #define CTRL_TWO_STOP (1 << 9) /* Two Stop Bits */
61 #define CTRL_TX_HALF_INT (1 << 8) /* TX Half-Full Interrupt Enable */
62 #define CTRL_RX_HALF_INT (1 << 7) /* RX Half-Full Interrupt Enable */
63 #define CTRL_TX_EMPT_INT (1 << 6) /* TX Empty Interrupt Enable */
64 #define CTRL_TX_RDY_INT (1 << 5) /* TX Ready Interrupt Enable */
65 #define CTRL_RX_RDY_INT (1 << 4) /* RX Ready Interrupt Enable */
66 #define CTRL_BRK_DET_INT (1 << 3) /* Break Detect Interrupt Enable */
67 #define CTRL_FRM_ERR_INT (1 << 2) /* Frame Error Interrupt Enable */
68 #define CTRL_PAR_ERR_INT (1 << 1) /* Parity Error Interrupt Enable */
69 #define CTRL_OVR_ERR_INT (1 << 0) /* Overrun Error Interrupt Enable */
70 #define CTRL_INTR_MASK 0x1ff
71 #define CTRL_TX_IDLE_INT CTRL_TX_RDY_INT
72 #define CTRL_IPEND_MASK (CTRL_OVR_ERR_INT | CTRL_BRK_DET_INT | \
73 CTRL_RX_RDY_INT)
74
75 #define UART_STAT 0x0c /* Status Register */
76 #define STAT_TX_FIFO_EMPT (1 << 13) /* TX FIFO Empty */
77 #define STAT_RX_FIFO_EMPT (1 << 12) /* RX FIFO Empty */
78 #define STAT_TX_FIFO_FULL (1 << 11) /* TX FIFO Full */
79 #define STAT_TX_FIFO_HALF (1 << 10) /* TX FIFO Half Full */
80 #define STAT_RX_TOGL (1 << 9) /* RX Toogled */
81 #define STAT_RX_FIFO_FULL (1 << 8) /* RX FIFO Full */
82 #define STAT_RX_FIFO_HALF (1 << 7) /* RX FIFO Half Full */
83 #define STAT_TX_EMPT (1 << 6) /* TX Empty */
84 #define STAT_TX_RDY (1 << 5) /* TX Ready */
85 #define STAT_RX_RDY (1 << 4) /* RX Ready */
86 #define STAT_BRK_DET (1 << 3) /* Break Detect */
87 #define STAT_FRM_ERR (1 << 2) /* Frame Error */
88 #define STAT_PAR_ERR (1 << 1) /* Parity Error */
89 #define STAT_OVR_ERR (1 << 0) /* Overrun Error */
90 #define STAT_TX_IDLE STAT_TX_RDY
91 #define STAT_TRANS_MASK (STAT_OVR_ERR | STAT_BRK_DET | STAT_RX_RDY)
92
93 #define UART_CCR 0x10 /* Clock Control Register */
94 #define CCR_BAUDRATE_DIV 0x3ff /* Baud Rate Divisor */
95
96 #define DEFAULT_RCLK 25804800
97 #define ONE_FRAME_TIME 87
98
99 #define stat_ipend_trans(i) ( \
100 (i & STAT_OVR_ERR) << 16 | \
101 (i & STAT_BRK_DET) << 14 | \
102 (i & STAT_RX_RDY) << 14)
103
104 /*
105 * For debugging purposes
106 */
107 #if CHECK_EARLY_PRINTF(mvebu)
108 static void
uart_mvebu_early_putc(int c)109 uart_mvebu_early_putc(int c)
110 {
111 volatile uint32_t *tsh;
112 volatile uint32_t *stat;
113
114 tsh = (uint32_t *)(socdev_va + UART_REG_OFFSET + UART_TSH);
115 stat = (uint32_t *)(socdev_va + UART_REG_OFFSET + UART_STAT);
116
117 while(!(*stat & STAT_TX_RDY))
118 ;
119
120 *tsh = c & 0xff;
121 }
122
123 early_putc_t *early_putc = uart_mvebu_early_putc;
124 #endif
125
126 /*
127 * Low-level UART interface.
128 */
129 static int uart_mvebu_probe(struct uart_bas *);
130 static void uart_mvebu_init(struct uart_bas *, int, int, int, int);
131 static void uart_mvebu_putc(struct uart_bas *, int);
132 static int uart_mvebu_rxready(struct uart_bas *);
133 static int uart_mvebu_getc(struct uart_bas *, struct mtx *);
134
135 static struct uart_ops uart_mvebu_ops = {
136 .probe = uart_mvebu_probe,
137 .init = uart_mvebu_init,
138 .term = NULL,
139 .putc = uart_mvebu_putc,
140 .rxready = uart_mvebu_rxready,
141 .getc = uart_mvebu_getc,
142 };
143
144 static int
uart_mvebu_probe(struct uart_bas * bas)145 uart_mvebu_probe(struct uart_bas *bas)
146 {
147
148 return (0);
149 }
150
151 static int
uart_mvebu_divisor(int rclk,int baudrate)152 uart_mvebu_divisor(int rclk, int baudrate)
153 {
154 int divisor;
155
156 if (baudrate == 0)
157 return (0);
158
159 divisor = (rclk >> 4) / baudrate;
160 if (divisor <= 1 || divisor >= 1024)
161 return (0);
162
163 return (divisor);
164 }
165
166 static int
uart_mvebu_param(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)167 uart_mvebu_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
168 int parity)
169 {
170 uint32_t ctrl = 0;
171 uint32_t ccr;
172 int divisor, ret = 0;
173
174 /* Reset UART */
175 ctrl = uart_getreg(bas, UART_CTRL);
176 uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST | CTRL_RX_FIFO_RST |
177 CTRL_LPBK_EN);
178 uart_barrier(bas);
179
180 switch (stopbits) {
181 case 2:
182 ctrl |= CTRL_TWO_STOP;
183 break;
184 case 1:
185 default:
186 ctrl &=~ CTRL_TWO_STOP;
187 }
188
189 switch (parity) {
190 case 3: /* Even parity bit */
191 ctrl |= CTRL_PAR_EN;
192 break;
193 default:
194 ctrl &=~ CTRL_PAR_EN;
195 }
196
197 /* Set baudrate. */
198 if (baudrate > 0) {
199 divisor = uart_mvebu_divisor(bas->rclk, baudrate);
200 if (divisor == 0) {
201 ret = EINVAL;
202 } else {
203 ccr = uart_getreg(bas, UART_CCR);
204 ccr &=~CCR_BAUDRATE_DIV;
205
206 uart_setreg(bas, UART_CCR, ccr | divisor);
207 uart_barrier(bas);
208 }
209 }
210
211 /* Set mirroring of status bits */
212 ctrl |= CTRL_ST_MIRR_EN;
213
214 uart_setreg(bas, UART_CTRL, ctrl);
215 uart_barrier(bas);
216
217 return (ret);
218 }
219
220 static void
uart_mvebu_init(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)221 uart_mvebu_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
222 int parity)
223 {
224 /* Set default frequency */
225 bas->rclk = DEFAULT_RCLK;
226
227 /* Mask interrupts */
228 uart_setreg(bas, UART_CTRL, uart_getreg(bas, UART_CTRL) &
229 ~CTRL_INTR_MASK);
230 uart_barrier(bas);
231
232 uart_mvebu_param(bas, baudrate, databits, stopbits, parity);
233 }
234
235 static void
uart_mvebu_putc(struct uart_bas * bas,int c)236 uart_mvebu_putc(struct uart_bas *bas, int c)
237 {
238 while (uart_getreg(bas, UART_STAT) & STAT_TX_FIFO_FULL)
239 ;
240 uart_setreg(bas, UART_TSH, c & 0xff);
241 }
242
243 static int
uart_mvebu_rxready(struct uart_bas * bas)244 uart_mvebu_rxready(struct uart_bas *bas)
245 {
246 if (uart_getreg(bas, UART_STAT) & STAT_RX_RDY)
247 return 1;
248 return 0;
249 }
250
251 static int
uart_mvebu_getc(struct uart_bas * bas,struct mtx * hwmtx)252 uart_mvebu_getc(struct uart_bas *bas, struct mtx *hwmtx)
253 {
254 int c;
255
256 uart_lock(hwmtx);
257 while (!(uart_getreg(bas, UART_STAT) & STAT_RX_RDY))
258 ;
259
260 c = uart_getreg(bas, UART_RBR) & 0xff;
261 uart_unlock(hwmtx);
262
263 return c;
264 }
265
266 /*
267 * UART driver methods implementation.
268 */
269 struct uart_mvebu_softc {
270 struct uart_softc base;
271 uint16_t intrm;
272 };
273
274 static int uart_mvebu_bus_attach(struct uart_softc *);
275 static int uart_mvebu_bus_detach(struct uart_softc *);
276 static int uart_mvebu_bus_flush(struct uart_softc *, int);
277 static int uart_mvebu_bus_getsig(struct uart_softc *);
278 static int uart_mvebu_bus_ioctl(struct uart_softc *, int, intptr_t);
279 static int uart_mvebu_bus_ipend(struct uart_softc *);
280 static int uart_mvebu_bus_param(struct uart_softc *, int, int, int, int);
281 static int uart_mvebu_bus_probe(struct uart_softc *);
282 static int uart_mvebu_bus_receive(struct uart_softc *);
283 static int uart_mvebu_bus_setsig(struct uart_softc *, int);
284 static int uart_mvebu_bus_transmit(struct uart_softc *);
285 static void uart_mvebu_bus_grab(struct uart_softc *);
286 static void uart_mvebu_bus_ungrab(struct uart_softc *);
287
288 static kobj_method_t uart_mvebu_methods[] = {
289 KOBJMETHOD(uart_attach, uart_mvebu_bus_attach),
290 KOBJMETHOD(uart_detach, uart_mvebu_bus_detach),
291 KOBJMETHOD(uart_flush, uart_mvebu_bus_flush),
292 KOBJMETHOD(uart_getsig, uart_mvebu_bus_getsig),
293 KOBJMETHOD(uart_ioctl, uart_mvebu_bus_ioctl),
294 KOBJMETHOD(uart_ipend, uart_mvebu_bus_ipend),
295 KOBJMETHOD(uart_param, uart_mvebu_bus_param),
296 KOBJMETHOD(uart_probe, uart_mvebu_bus_probe),
297 KOBJMETHOD(uart_receive, uart_mvebu_bus_receive),
298 KOBJMETHOD(uart_setsig, uart_mvebu_bus_setsig),
299 KOBJMETHOD(uart_transmit, uart_mvebu_bus_transmit),
300 KOBJMETHOD(uart_grab, uart_mvebu_bus_grab),
301 KOBJMETHOD(uart_ungrab, uart_mvebu_bus_ungrab),
302 { 0, 0 }
303 };
304
305 struct uart_class uart_mvebu_class = {
306 "mvebu-uart",
307 uart_mvebu_methods,
308 sizeof(struct uart_mvebu_softc),
309 .uc_ops = &uart_mvebu_ops,
310 .uc_range = 0x14,
311 .uc_rclk = DEFAULT_RCLK,
312 .uc_rshift = 0,
313 .uc_riowidth = 4
314 };
315
316 static struct ofw_compat_data compat_data[] = {
317 {"marvell,armada-3700-uart", (uintptr_t)&uart_mvebu_class},
318 {NULL, (uintptr_t)NULL},
319 };
320 UART_FDT_CLASS_AND_DEVICE(compat_data);
321
322 static int
uart_mvebu_bus_attach(struct uart_softc * sc)323 uart_mvebu_bus_attach(struct uart_softc *sc)
324 {
325 struct uart_bas *bas;
326 int ctrl;
327
328 bas = &sc->sc_bas;
329 uart_lock(sc->sc_hwmtx);
330
331 ctrl = uart_getreg(bas, UART_CTRL);
332
333 /* Enable interrupts */
334 ctrl &=~ CTRL_INTR_MASK;
335 ctrl |= CTRL_IPEND_MASK;
336
337 /* Set interrupts */
338 uart_setreg(bas, UART_CTRL, ctrl);
339 uart_barrier(bas);
340
341 uart_unlock(sc->sc_hwmtx);
342
343 return (0);
344 }
345
346 static int
uart_mvebu_bus_detach(struct uart_softc * sc)347 uart_mvebu_bus_detach(struct uart_softc *sc)
348 {
349
350 return (0);
351 }
352
353 static int
uart_mvebu_bus_flush(struct uart_softc * sc,int what)354 uart_mvebu_bus_flush(struct uart_softc *sc, int what)
355 {
356 struct uart_bas *bas;
357 int ctrl, ret = 0;
358
359 bas = &sc->sc_bas;
360 uart_lock(sc->sc_hwmtx);
361 ctrl = uart_getreg(bas, UART_CTRL);
362
363 switch (what) {
364 case UART_FLUSH_RECEIVER:
365 uart_setreg(bas, UART_CTRL, ctrl | CTRL_RX_FIFO_RST);
366 uart_barrier(bas);
367 break;
368
369 case UART_FLUSH_TRANSMITTER:
370 uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST);
371 uart_barrier(bas);
372 break;
373
374 default:
375 ret = EINVAL;
376 break;
377 }
378
379 /* Back to normal operation */
380 if (!ret) {
381 uart_setreg(bas, UART_CTRL, ctrl);
382 uart_barrier(bas);
383 }
384
385 uart_unlock(sc->sc_hwmtx);
386 return (ret);
387 }
388
389 static int
uart_mvebu_bus_getsig(struct uart_softc * sc)390 uart_mvebu_bus_getsig(struct uart_softc *sc)
391 {
392
393 return (0);
394 }
395
396 static int
uart_mvebu_bus_ioctl(struct uart_softc * sc,int request,intptr_t data)397 uart_mvebu_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
398 {
399 struct uart_bas *bas;
400 int ctrl, ret = 0;
401 int divisor, baudrate;
402
403 bas = &sc->sc_bas;
404 uart_lock(sc->sc_hwmtx);
405 switch (request) {
406 case UART_IOCTL_BREAK:
407 ctrl = uart_getreg(bas, UART_CTRL);
408 if (data)
409 ctrl |= CTRL_SND_BRK_SEQ;
410 else
411 ctrl &=~ CTRL_SND_BRK_SEQ;
412 uart_setreg(bas, UART_CTRL, ctrl);
413 uart_barrier(bas);
414 break;
415
416 case UART_IOCTL_BAUD:
417 divisor = uart_getreg(bas, UART_CCR) & CCR_BAUDRATE_DIV;
418 baudrate = bas->rclk/(divisor * 16);
419 *(int *)data = baudrate;
420 break;
421
422 default:
423 ret = ENOTTY;
424 break;
425 }
426 uart_unlock(sc->sc_hwmtx);
427
428 return (ret);
429 }
430
431 static int
uart_mvebu_bus_ipend(struct uart_softc * sc)432 uart_mvebu_bus_ipend(struct uart_softc *sc)
433 {
434 struct uart_bas *bas;
435 int ipend, ctrl, ret = 0;
436
437 bas = &sc->sc_bas;
438 uart_lock(sc->sc_hwmtx);
439 ipend = uart_getreg(bas, UART_STAT);
440 ctrl = uart_getreg(bas, UART_CTRL);
441
442 if (((ipend & STAT_TX_IDLE) == STAT_TX_IDLE) &&
443 (ctrl & CTRL_TX_IDLE_INT) == CTRL_TX_IDLE_INT) {
444 /* Disable TX IDLE Interrupt generation */
445 uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_TX_IDLE_INT);
446 uart_barrier(bas);
447
448 /* SER_INT_TXIDLE means empty TX FIFO. Wait until it cleans */
449 while(!(uart_getreg(bas, UART_STAT) & STAT_TX_FIFO_EMPT))
450 DELAY(ONE_FRAME_TIME/2);
451
452 ret |= SER_INT_TXIDLE;
453 }
454
455 ret |= stat_ipend_trans(ipend & STAT_TRANS_MASK);
456
457 uart_unlock(sc->sc_hwmtx);
458
459 return (ret);
460 }
461
462 static int
uart_mvebu_bus_param(struct uart_softc * sc,int baudrate,int databits,int stopbits,int parity)463 uart_mvebu_bus_param(struct uart_softc *sc, int baudrate, int databits,
464 int stopbits, int parity)
465 {
466 int ret;
467
468 uart_lock(sc->sc_hwmtx);
469 ret = uart_mvebu_param(&sc->sc_bas, baudrate, databits, stopbits, parity);
470 uart_unlock(sc->sc_hwmtx);
471
472 return (ret);
473 }
474
475 static int
uart_mvebu_bus_probe(struct uart_softc * sc)476 uart_mvebu_bus_probe(struct uart_softc *sc)
477 {
478 if (!ofw_bus_status_okay(sc->sc_dev))
479 return (ENXIO);
480
481 if (!ofw_bus_search_compatible(sc->sc_dev, compat_data)->ocd_data)
482 return (ENXIO);
483
484 device_set_desc(sc->sc_dev, "Marvell Armada 3700 UART");
485
486 sc->sc_txfifosz = 32;
487 sc->sc_rxfifosz = 64;
488 sc->sc_hwiflow = 0;
489 sc->sc_hwoflow = 0;
490
491 return (0);
492 }
493
494 int
uart_mvebu_bus_receive(struct uart_softc * sc)495 uart_mvebu_bus_receive(struct uart_softc *sc)
496 {
497 struct uart_bas *bas;
498 uint32_t xc;
499 int rx, er;
500
501 bas = &sc->sc_bas;
502 uart_lock(sc->sc_hwmtx);
503
504 while (!(uart_getreg(bas, UART_STAT) & STAT_RX_FIFO_EMPT)) {
505 if (uart_rx_full(sc)) {
506 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
507 break;
508 }
509
510 xc = uart_getreg(bas, UART_RBR);
511 rx = xc & 0xff;
512 er = xc & 0xf000;
513 /*
514 * Formula which translates marvell error bits
515 * Only valid when CTRL_ST_MIRR_EN is set
516 */
517 er = (er & RBR_BRK_DET) >> 7 |
518 (er & RBR_FRM_ERR_DET) >> 5 |
519 (er & RBR_PAR_ERR_DET) >> 2 |
520 (er & RBR_OVR_ERR_DET) >> 2;
521
522 uart_rx_put(sc, rx | er);
523 uart_barrier(bas);
524 }
525 /*
526 * uart_if.m says that receive interrupt
527 * should be cleared, so we need to reset
528 * RX FIFO
529 */
530
531 if (!(uart_getreg(bas, UART_STAT) & STAT_RX_FIFO_EMPT)) {
532 uart_mvebu_bus_flush(sc, UART_FLUSH_RECEIVER);
533 }
534
535 uart_unlock(sc->sc_hwmtx);
536 return (0);
537 }
538
539 static int
uart_mvebu_bus_setsig(struct uart_softc * sc,int sig)540 uart_mvebu_bus_setsig(struct uart_softc *sc, int sig)
541 {
542 /* Not supported by hardware */
543 return (0);
544 }
545
546 int
uart_mvebu_bus_transmit(struct uart_softc * sc)547 uart_mvebu_bus_transmit(struct uart_softc *sc)
548 {
549 struct uart_bas *bas;
550 int i, ctrl;
551
552 bas = &sc->sc_bas;
553 uart_lock(sc->sc_hwmtx);
554
555 /* Turn off all interrupts during send */
556 ctrl = uart_getreg(bas, UART_CTRL);
557 uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_INTR_MASK);
558 uart_barrier(bas);
559
560 for (i = 0; i < sc->sc_txdatasz; i++) {
561 uart_setreg(bas, UART_TSH, sc->sc_txbuf[i] & 0xff);
562 uart_barrier(bas);
563 }
564
565 /*
566 * Make sure that interrupt is generated
567 * when FIFO can get more data.
568 */
569 uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_IDLE_INT);
570 uart_barrier(bas);
571
572 /* Mark busy */
573 sc->sc_txbusy = 1;
574
575 uart_unlock(sc->sc_hwmtx);
576 return (0);
577 }
578
579 static void
uart_mvebu_bus_grab(struct uart_softc * sc)580 uart_mvebu_bus_grab(struct uart_softc *sc)
581 {
582 struct uart_mvebu_softc *msc = (struct uart_mvebu_softc *)sc;
583 struct uart_bas *bas = &sc->sc_bas;
584 uint32_t ctrl;
585
586 /* Mask all interrupts */
587 uart_lock(sc->sc_hwmtx);
588 ctrl = uart_getreg(bas, UART_CTRL);
589 msc->intrm = ctrl & CTRL_INTR_MASK;
590 uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_INTR_MASK);
591 uart_barrier(bas);
592 uart_unlock(sc->sc_hwmtx);
593 }
594
595 static void
uart_mvebu_bus_ungrab(struct uart_softc * sc)596 uart_mvebu_bus_ungrab(struct uart_softc *sc)
597 {
598 struct uart_mvebu_softc *msc = (struct uart_mvebu_softc *)sc;
599 struct uart_bas *bas = &sc->sc_bas;
600 uint32_t ctrl;
601
602 /* Restore interrupts */
603 uart_lock(sc->sc_hwmtx);
604 ctrl = uart_getreg(bas, UART_CTRL) & ~CTRL_INTR_MASK;
605 uart_setreg(bas, UART_CTRL, ctrl | msc->intrm);
606 uart_barrier(bas);
607 uart_unlock(sc->sc_hwmtx);
608 }
609