xref: /titanic_41/usr/src/uts/common/io/ural/ural_reg.h (revision 40db2e2b777b79f3dd0d6d9629593a07f86b9c0a)
1 /*
2  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
3  * Use is subject to license terms.
4  */
5 
6 /*
7  * Copyright (c) 2005, 2006
8  *	Damien Bergamini <damien.bergamini@free.fr>
9  *
10  * Permission to use, copy, modify, and distribute this software for any
11  * purpose with or without fee is hereby granted, provided that the above
12  * copyright notice and this permission notice appear in all copies.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
16  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
19  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
20  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21  */
22 #ifndef _URAL_REG_H
23 #define	_URAL_REG_H
24 
25 #pragma ident	"%Z%%M%	%I%	%E% SMI"
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
31 #define	RAL_RX_DESC_SIZE	(sizeof (struct ural_rx_desc))
32 #define	RAL_TX_DESC_SIZE	(sizeof (struct ural_tx_desc))
33 
34 #define	RAL_CONFIG_NO		1
35 #define	RAL_IFACE_INDEX		0
36 
37 #define	RAL_VENDOR_REQUEST	0x01
38 #define	RAL_WRITE_MAC		0x02
39 #define	RAL_READ_MAC		0x03
40 #define	RAL_WRITE_MULTI_MAC	0x06
41 #define	RAL_READ_MULTI_MAC	0x07
42 #define	RAL_READ_EEPROM		0x09
43 
44 /*
45  * MAC registers.
46  */
47 #define	RAL_MAC_CSR0	0x0400	/* ASIC Version */
48 #define	RAL_MAC_CSR1	0x0402	/* System control */
49 #define	RAL_MAC_CSR2	0x0404	/* MAC addr0 */
50 #define	RAL_MAC_CSR3	0x0406	/* MAC addr1 */
51 #define	RAL_MAC_CSR4	0x0408	/* MAC addr2 */
52 #define	RAL_MAC_CSR5	0x040a	/* BSSID0 */
53 #define	RAL_MAC_CSR6	0x040c	/* BSSID1 */
54 #define	RAL_MAC_CSR7	0x040e	/* BSSID2 */
55 #define	RAL_MAC_CSR8	0x0410	/* Max frame length */
56 #define	RAL_MAC_CSR9	0x0412	/* Timer control */
57 #define	RAL_MAC_CSR10	0x0414	/* Slot time */
58 #define	RAL_MAC_CSR11	0x0416	/* IFS */
59 #define	RAL_MAC_CSR12	0x0418	/* EIFS */
60 #define	RAL_MAC_CSR13	0x041a	/* Power mode0 */
61 #define	RAL_MAC_CSR14	0x041c	/* Power mode1 */
62 #define	RAL_MAC_CSR15	0x041e	/* Power saving transition0 */
63 #define	RAL_MAC_CSR16	0x0420	/* Power saving transition1 */
64 #define	RAL_MAC_CSR17	0x0422	/* Power state control */
65 #define	RAL_MAC_CSR18	0x0424	/* Auto wake-up control */
66 #define	RAL_MAC_CSR19	0x0426	/* GPIO control */
67 #define	RAL_MAC_CSR20	0x0428	/* LED control0 */
68 #define	RAL_MAC_CSR22	0x042c	/* Not documented */
69 
70 /*
71  * Tx/Rx Registers.
72  */
73 #define	RAL_TXRX_CSR0	0x0440	/* Security control */
74 #define	RAL_TXRX_CSR2	0x0444	/* Rx control */
75 #define	RAL_TXRX_CSR5	0x044a	/* CCK Tx BBP ID0 */
76 #define	RAL_TXRX_CSR6	0x044c	/* CCK Tx BBP ID1 */
77 #define	RAL_TXRX_CSR7	0x044e	/* OFDM Tx BBP ID0 */
78 #define	RAL_TXRX_CSR8	0x0450	/* OFDM Tx BBP ID1 */
79 #define	RAL_TXRX_CSR10	0x0454	/* Auto responder control */
80 #define	RAL_TXRX_CSR11	0x0456	/* Auto responder basic rate */
81 #define	RAL_TXRX_CSR18	0x0464	/* Beacon interval */
82 #define	RAL_TXRX_CSR19	0x0466	/* Beacon/sync control */
83 #define	RAL_TXRX_CSR20	0x0468	/* Beacon alignment */
84 #define	RAL_TXRX_CSR21	0x046a	/* Not documented */
85 
86 /*
87  * Security registers.
88  */
89 #define	RAL_SEC_CSR0	0x0480	/* Shared key 0, word 0 */
90 
91 /*
92  * PHY registers.
93  */
94 #define	RAL_PHY_CSR2	0x04c4	/* Tx MAC configuration */
95 #define	RAL_PHY_CSR4	0x04c8	/* Interface configuration */
96 #define	RAL_PHY_CSR5	0x04ca	/* BBP Pre-Tx CCK */
97 #define	RAL_PHY_CSR6	0x04cc	/* BBP Pre-Tx OFDM */
98 #define	RAL_PHY_CSR7	0x04ce	/* BBP serial control */
99 #define	RAL_PHY_CSR8	0x04d0	/* BBP serial status */
100 #define	RAL_PHY_CSR9	0x04d2	/* RF serial control0 */
101 #define	RAL_PHY_CSR10	0x04d4	/* RF serial control1 */
102 
103 /*
104  * Statistics registers.
105  */
106 #define	RAL_STA_CSR0	0x04e0	/* FCS error */
107 
108 
109 #define	RAL_DISABLE_RX		(1 << 0)
110 #define	RAL_DROP_CRC		(1 << 1)
111 #define	RAL_DROP_PHY		(1 << 2)
112 #define	RAL_DROP_CTL		(1 << 3)
113 #define	RAL_DROP_NOT_TO_ME	(1 << 4)
114 #define	RAL_DROP_TODS		(1 << 5)
115 #define	RAL_DROP_BAD_VERSION	(1 << 6)
116 #define	RAL_DROP_MULTICAST	(1 << 9)
117 #define	RAL_DROP_BROADCAST	(1 << 10)
118 
119 #define	RAL_SHORT_PREAMBLE	(1 << 2)
120 
121 #define	RAL_RESET_ASIC	(1 << 0)
122 #define	RAL_RESET_BBP	(1 << 1)
123 #define	RAL_HOST_READY	(1 << 2)
124 
125 #define	RAL_ENABLE_TSF			(1 << 0)
126 #define	RAL_ENABLE_TSF_SYNC(x)		(((x) & 0x3) << 1)
127 #define	RAL_ENABLE_TBCN			(1 << 3)
128 #define	RAL_ENABLE_BEACON_GENERATOR	(1 << 4)
129 
130 #define	RAL_RF_AWAKE	(3 << 7)
131 #define	RAL_BBP_AWAKE	(3 << 5)
132 
133 #define	RAL_BBP_WRITE	(1 << 15)
134 #define	RAL_BBP_BUSY	(1 << 0)
135 
136 #define	RAL_RF1_AUTOTUNE	0x08000
137 #define	RAL_RF3_AUTOTUNE	0x00040
138 
139 #define	RAL_RF_2522	0x00
140 #define	RAL_RF_2523	0x01
141 #define	RAL_RF_2524	0x02
142 #define	RAL_RF_2525	0x03
143 #define	RAL_RF_2525E	0x04
144 #define	RAL_RF_2526	0x05
145 /* dual-band RF */
146 #define	RAL_RF_5222	0x10
147 
148 #define	RAL_BBP_VERSION	0
149 #define	RAL_BBP_TX	2
150 #define	RAL_BBP_RX	14
151 
152 #define	RAL_BBP_ANTA		0x00
153 #define	RAL_BBP_DIVERSITY	0x01
154 #define	RAL_BBP_ANTB		0x02
155 #define	RAL_BBP_ANTMASK		0x03
156 #define	RAL_BBP_FLIPIQ		0x04
157 
158 #define	RAL_JAPAN_FILTER	0x08
159 
160 #pragma pack(1)
161 struct ural_tx_desc {
162 	uint32_t	flags;
163 #define	RAL_TX_RETRY(x)		((x) << 4)
164 #define	RAL_TX_MORE_FRAG	(1 << 8)
165 #define	RAL_TX_ACK		(1 << 9)
166 #define	RAL_TX_TIMESTAMP	(1 << 10)
167 #define	RAL_TX_OFDM		(1 << 11)
168 #define	RAL_TX_NEWSEQ		(1 << 12)
169 
170 #define	RAL_TX_IFS_MASK		0x00006000
171 #define	RAL_TX_IFS_BACKOFF	(0 << 13)
172 #define	RAL_TX_IFS_SIFS		(1 << 13)
173 #define	RAL_TX_IFS_NEWBACKOFF	(2 << 13)
174 #define	RAL_TX_IFS_NONE		(3 << 13)
175 
176 	uint16_t	wme;
177 #define	RAL_LOGCWMAX(x)		(((x) & 0xf) << 12)
178 #define	RAL_LOGCWMIN(x)		(((x) & 0xf) << 8)
179 #define	RAL_AIFSN(x)		(((x) & 0x3) << 6)
180 #define	RAL_IVOFFSET(x)		(((x) & 0x3f))
181 
182 	uint16_t	reserved1;
183 	uint8_t		plcp_signal;
184 	uint8_t		plcp_service;
185 #define	RAL_PLCP_LENGEXT	0x80
186 
187 	uint8_t		plcp_length_lo;
188 	uint8_t		plcp_length_hi;
189 	uint32_t	iv;
190 	uint32_t	eiv;
191 };
192 #pragma pack()
193 
194 #pragma pack(1)
195 struct ural_rx_desc {
196 	uint32_t	flags;
197 #define	RAL_RX_CRC_ERROR	(1 << 5)
198 #define	RAL_RX_OFDM		(1 << 6)
199 #define	RAL_RX_PHY_ERROR	(1 << 7)
200 
201 	uint8_t		rssi;
202 	uint8_t		rate;
203 	uint16_t	reserved;
204 
205 	uint32_t	iv;
206 	uint32_t	eiv;
207 };
208 #pragma pack()
209 
210 #define	RAL_RF_LOBUSY	(1 << 15)
211 #define	RAL_RF_BUSY	((uint32_t)1 << 31)
212 #define	RAL_RF_20BIT	(20 << 24)
213 
214 #define	RAL_RF1	0
215 #define	RAL_RF2	2
216 #define	RAL_RF3	1
217 #define	RAL_RF4	3
218 
219 #define	RAL_EEPROM_ADDRESS	0x0004
220 #define	RAL_EEPROM_TXPOWER	0x003c
221 #define	RAL_EEPROM_CONFIG0	0x0016
222 #define	RAL_EEPROM_BBP_BASE	0x001c
223 
224 #ifdef __cplusplus
225 }
226 #endif
227 
228 #endif /* _URAL_REG_H */
229