1 /* SPDX-License-Identifier: GPL-2.0+ 2 * Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2021 Microchip Technology Inc. 5 */ 6 7 /* This file is autogenerated by cml-utils 2023-02-10 11:18:53 +0100. 8 * Commit ID: c30fb4bf0281cd4a7133bdab6682f9e43c872ada 9 */ 10 11 #ifndef _SPARX5_MAIN_REGS_H_ 12 #define _SPARX5_MAIN_REGS_H_ 13 14 #include <linux/bitfield.h> 15 #include <linux/types.h> 16 #include <linux/bug.h> 17 18 enum sparx5_target { 19 TARGET_ANA_AC = 1, 20 TARGET_ANA_ACL = 2, 21 TARGET_ANA_AC_POL = 4, 22 TARGET_ANA_AC_SDLB = 5, 23 TARGET_ANA_CL = 6, 24 TARGET_ANA_L2 = 7, 25 TARGET_ANA_L3 = 8, 26 TARGET_ASM = 9, 27 TARGET_CLKGEN = 11, 28 TARGET_CPU = 12, 29 TARGET_DEV10G = 17, 30 TARGET_DEV25G = 29, 31 TARGET_DEV2G5 = 37, 32 TARGET_DEV5G = 102, 33 TARGET_DSM = 115, 34 TARGET_EACL = 116, 35 TARGET_FDMA = 117, 36 TARGET_GCB = 118, 37 TARGET_HSCH = 119, 38 TARGET_LRN = 122, 39 TARGET_PCEP = 129, 40 TARGET_PCS10G_BR = 132, 41 TARGET_PCS25G_BR = 144, 42 TARGET_PCS5G_BR = 160, 43 TARGET_PORT_CONF = 173, 44 TARGET_PTP = 174, 45 TARGET_QFWD = 175, 46 TARGET_QRES = 176, 47 TARGET_QS = 177, 48 TARGET_QSYS = 178, 49 TARGET_REW = 179, 50 TARGET_VCAP_ES0 = 323, 51 TARGET_VCAP_ES2 = 324, 52 TARGET_VCAP_SUPER = 326, 53 TARGET_VOP = 327, 54 TARGET_XQS = 331, 55 NUM_TARGETS = 332 56 }; 57 58 #define __REG(...) __VA_ARGS__ 59 60 /* ANA_AC:RAM_CTRL:RAM_INIT */ 61 #define ANA_AC_RAM_INIT __REG(TARGET_ANA_AC,\ 62 0, 1, 839108, 0, 1, 4, 0, 0, 1, 4) 63 64 #define ANA_AC_RAM_INIT_RAM_INIT BIT(1) 65 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\ 66 FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x) 67 #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\ 68 FIELD_GET(ANA_AC_RAM_INIT_RAM_INIT, x) 69 70 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK BIT(0) 71 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 72 FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x) 73 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 74 FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x) 75 76 /* ANA_AC:PS_COMMON:OWN_UPSID */ 77 #define ANA_AC_OWN_UPSID(r) __REG(TARGET_ANA_AC,\ 78 0, 1, 894472, 0, 1, 352, 52, r, 3, 4) 79 80 #define ANA_AC_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 81 #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\ 82 FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x) 83 #define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\ 84 FIELD_GET(ANA_AC_OWN_UPSID_OWN_UPSID, x) 85 86 /* ANA_AC:MIRROR_PROBE:PROBE_CFG */ 87 #define ANA_AC_PROBE_CFG(g) \ 88 __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 0, 0, 1, 4) 89 90 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD GENMASK(31, 27) 91 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_SET(x)\ 92 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x) 93 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_GET(x)\ 94 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x) 95 96 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET GENMASK(26, 19) 97 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_SET(x)\ 98 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x) 99 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_GET(x)\ 100 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x) 101 102 #define ANA_AC_PROBE_CFG_PROBE_VID GENMASK(18, 6) 103 #define ANA_AC_PROBE_CFG_PROBE_VID_SET(x)\ 104 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VID, x) 105 #define ANA_AC_PROBE_CFG_PROBE_VID_GET(x)\ 106 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VID, x) 107 108 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE GENMASK(5, 4) 109 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_SET(x)\ 110 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x) 111 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_GET(x)\ 112 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x) 113 114 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE GENMASK(3, 2) 115 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_SET(x)\ 116 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x) 117 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_GET(x)\ 118 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x) 119 120 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION GENMASK(1, 0) 121 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_SET(x)\ 122 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x) 123 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_GET(x)\ 124 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x) 125 126 /* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG */ 127 #define ANA_AC_PROBE_PORT_CFG(g) \ 128 __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 8, 0, 1, 4) 129 130 /* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG1 */ 131 #define ANA_AC_PROBE_PORT_CFG1(g) \ 132 __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 12, 0, 1, 4) 133 134 /* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG2 */ 135 #define ANA_AC_PROBE_PORT_CFG2(g) \ 136 __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 16, 0, 1, 4) 137 138 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2 BIT(0) 139 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_SET(x)\ 140 FIELD_PREP(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x) 141 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_GET(x)\ 142 FIELD_GET(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x) 143 144 /* ANA_AC:SRC:SRC_CFG */ 145 #define ANA_AC_SRC_CFG(g) __REG(TARGET_ANA_AC,\ 146 0, 1, 849920, g, 102, 16, 0, 0, 1, 4) 147 148 /* ANA_AC:SRC:SRC_CFG1 */ 149 #define ANA_AC_SRC_CFG1(g) __REG(TARGET_ANA_AC,\ 150 0, 1, 849920, g, 102, 16, 4, 0, 1, 4) 151 152 /* ANA_AC:SRC:SRC_CFG2 */ 153 #define ANA_AC_SRC_CFG2(g) __REG(TARGET_ANA_AC,\ 154 0, 1, 849920, g, 102, 16, 8, 0, 1, 4) 155 156 #define ANA_AC_SRC_CFG2_PORT_MASK2 BIT(0) 157 #define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\ 158 FIELD_PREP(ANA_AC_SRC_CFG2_PORT_MASK2, x) 159 #define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\ 160 FIELD_GET(ANA_AC_SRC_CFG2_PORT_MASK2, x) 161 162 /* ANA_AC:PGID:PGID_CFG */ 163 #define ANA_AC_PGID_CFG(g) __REG(TARGET_ANA_AC,\ 164 0, 1, 786432, g, 3290, 16, 0, 0, 1, 4) 165 166 /* ANA_AC:PGID:PGID_CFG1 */ 167 #define ANA_AC_PGID_CFG1(g) __REG(TARGET_ANA_AC,\ 168 0, 1, 786432, g, 3290, 16, 4, 0, 1, 4) 169 170 /* ANA_AC:PGID:PGID_CFG2 */ 171 #define ANA_AC_PGID_CFG2(g) __REG(TARGET_ANA_AC,\ 172 0, 1, 786432, g, 3290, 16, 8, 0, 1, 4) 173 174 #define ANA_AC_PGID_CFG2_PORT_MASK2 BIT(0) 175 #define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\ 176 FIELD_PREP(ANA_AC_PGID_CFG2_PORT_MASK2, x) 177 #define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\ 178 FIELD_GET(ANA_AC_PGID_CFG2_PORT_MASK2, x) 179 180 /* ANA_AC:PGID:PGID_MISC_CFG */ 181 #define ANA_AC_PGID_MISC_CFG(g) __REG(TARGET_ANA_AC,\ 182 0, 1, 786432, g, 3290, 16, 12, 0, 1, 4) 183 184 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU GENMASK(6, 4) 185 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\ 186 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x) 187 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_GET(x)\ 188 FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x) 189 190 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA BIT(1) 191 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_SET(x)\ 192 FIELD_PREP(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x) 193 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_GET(x)\ 194 FIELD_GET(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x) 195 196 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA BIT(0) 197 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(x)\ 198 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x) 199 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\ 200 FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x) 201 202 /* ANA_AC:TSN_SF:TSN_SF */ 203 #define ANA_AC_TSN_SF __REG(TARGET_ANA_AC,\ 204 0, 1, 839136, 0, 1, 4, 0, 0, 1, 4) 205 206 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY BIT(9) 207 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_SET(x)\ 208 FIELD_PREP(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x) 209 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_GET(x)\ 210 FIELD_GET(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x) 211 212 #define ANA_AC_TSN_SF_PORT_NUM GENMASK(8, 0) 213 #define ANA_AC_TSN_SF_PORT_NUM_SET(x)\ 214 FIELD_PREP(ANA_AC_TSN_SF_PORT_NUM, x) 215 #define ANA_AC_TSN_SF_PORT_NUM_GET(x)\ 216 FIELD_GET(ANA_AC_TSN_SF_PORT_NUM, x) 217 218 /* ANA_AC:TSN_SF_CFG:TSN_SF_CFG */ 219 #define ANA_AC_TSN_SF_CFG(g) __REG(TARGET_ANA_AC,\ 220 0, 1, 839680, g, 1024, 4, 0, 0, 1, 4) 221 222 #define ANA_AC_TSN_SF_CFG_TSN_SGID GENMASK(25, 16) 223 #define ANA_AC_TSN_SF_CFG_TSN_SGID_SET(x)\ 224 FIELD_PREP(ANA_AC_TSN_SF_CFG_TSN_SGID, x) 225 #define ANA_AC_TSN_SF_CFG_TSN_SGID_GET(x)\ 226 FIELD_GET(ANA_AC_TSN_SF_CFG_TSN_SGID, x) 227 228 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU GENMASK(15, 2) 229 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_SET(x)\ 230 FIELD_PREP(ANA_AC_TSN_SF_CFG_TSN_MAX_SDU, x) 231 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_GET(x)\ 232 FIELD_GET(ANA_AC_TSN_SF_CFG_TSN_MAX_SDU, x) 233 234 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA BIT(1) 235 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_SET(x)\ 236 FIELD_PREP(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA, x) 237 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_GET(x)\ 238 FIELD_GET(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA, x) 239 240 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE BIT(0) 241 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_SET(x)\ 242 FIELD_PREP(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE, x) 243 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_GET(x)\ 244 FIELD_GET(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE, x) 245 246 /* ANA_AC:TSN_SF_STATUS:TSN_SF_STATUS */ 247 #define ANA_AC_TSN_SF_STATUS __REG(TARGET_ANA_AC,\ 248 0, 1, 839072, 0, 1, 16, 0, 0, 1, 4) 249 250 #define ANA_AC_TSN_SF_STATUS_FRM_LEN GENMASK(25, 12) 251 #define ANA_AC_TSN_SF_STATUS_FRM_LEN_SET(x)\ 252 FIELD_PREP(ANA_AC_TSN_SF_STATUS_FRM_LEN, x) 253 #define ANA_AC_TSN_SF_STATUS_FRM_LEN_GET(x)\ 254 FIELD_GET(ANA_AC_TSN_SF_STATUS_FRM_LEN, x) 255 256 #define ANA_AC_TSN_SF_STATUS_DLB_DROP BIT(11) 257 #define ANA_AC_TSN_SF_STATUS_DLB_DROP_SET(x)\ 258 FIELD_PREP(ANA_AC_TSN_SF_STATUS_DLB_DROP, x) 259 #define ANA_AC_TSN_SF_STATUS_DLB_DROP_GET(x)\ 260 FIELD_GET(ANA_AC_TSN_SF_STATUS_DLB_DROP, x) 261 262 #define ANA_AC_TSN_SF_STATUS_TSN_SFID GENMASK(10, 1) 263 #define ANA_AC_TSN_SF_STATUS_TSN_SFID_SET(x)\ 264 FIELD_PREP(ANA_AC_TSN_SF_STATUS_TSN_SFID, x) 265 #define ANA_AC_TSN_SF_STATUS_TSN_SFID_GET(x)\ 266 FIELD_GET(ANA_AC_TSN_SF_STATUS_TSN_SFID, x) 267 268 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD BIT(0) 269 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_SET(x)\ 270 FIELD_PREP(ANA_AC_TSN_SF_STATUS_TSTAMP_VLD, x) 271 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_GET(x)\ 272 FIELD_GET(ANA_AC_TSN_SF_STATUS_TSTAMP_VLD, x) 273 274 /* ANA_AC:SG_ACCESS:SG_ACCESS_CTRL */ 275 #define ANA_AC_SG_ACCESS_CTRL __REG(TARGET_ANA_AC,\ 276 0, 1, 839140, 0, 1, 12, 0, 0, 1, 4) 277 278 #define ANA_AC_SG_ACCESS_CTRL_SGID GENMASK(9, 0) 279 #define ANA_AC_SG_ACCESS_CTRL_SGID_SET(x)\ 280 FIELD_PREP(ANA_AC_SG_ACCESS_CTRL_SGID, x) 281 #define ANA_AC_SG_ACCESS_CTRL_SGID_GET(x)\ 282 FIELD_GET(ANA_AC_SG_ACCESS_CTRL_SGID, x) 283 284 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE BIT(28) 285 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_SET(x)\ 286 FIELD_PREP(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE, x) 287 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_GET(x)\ 288 FIELD_GET(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE, x) 289 290 /* ANA_AC:SG_ACCESS:SG_CYCLETIME_UPDATE_PERIOD */ 291 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD __REG(TARGET_ANA_AC,\ 292 0, 1, 839140, 0, 1, 12, 8, 0, 1, 4) 293 294 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS GENMASK(15, 0) 295 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_SET(x)\ 296 FIELD_PREP(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS, x) 297 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_GET(x)\ 298 FIELD_GET(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS, x) 299 300 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA BIT(31) 301 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_SET(x)\ 302 FIELD_PREP(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA, x) 303 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_GET(x)\ 304 FIELD_GET(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA, x) 305 306 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_1 */ 307 #define ANA_AC_SG_CONFIG_REG_1 __REG(TARGET_ANA_AC,\ 308 0, 1, 851584, 0, 1, 128, 48, 0, 1, 4) 309 310 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_2 */ 311 #define ANA_AC_SG_CONFIG_REG_2 __REG(TARGET_ANA_AC,\ 312 0, 1, 851584, 0, 1, 128, 52, 0, 1, 4) 313 314 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_3 */ 315 #define ANA_AC_SG_CONFIG_REG_3 __REG(TARGET_ANA_AC,\ 316 0, 1, 851584, 0, 1, 128, 56, 0, 1, 4) 317 318 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB GENMASK(15, 0) 319 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_SET(x)\ 320 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB, x) 321 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_GET(x)\ 322 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB, x) 323 324 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH GENMASK(18, 16) 325 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_SET(x)\ 326 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH, x) 327 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_GET(x)\ 328 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH, x) 329 330 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE BIT(20) 331 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_SET(x)\ 332 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE, x) 333 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_GET(x)\ 334 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE, x) 335 336 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS GENMASK(24, 21) 337 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_SET(x)\ 338 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INIT_IPS, x) 339 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_GET(x)\ 340 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INIT_IPS, x) 341 342 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(25) 343 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_SET(x)\ 344 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE, x) 345 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_GET(x)\ 346 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE, x) 347 348 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA BIT(26) 349 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_SET(x)\ 350 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA, x) 351 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_GET(x)\ 352 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA, x) 353 354 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX BIT(27) 355 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_SET(x)\ 356 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INVALID_RX, x) 357 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_GET(x)\ 358 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INVALID_RX, x) 359 360 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA BIT(28) 361 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_SET(x)\ 362 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA, x) 363 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_GET(x)\ 364 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA, x) 365 366 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED BIT(29) 367 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_SET(x)\ 368 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED, x) 369 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_GET(x)\ 370 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED, x) 371 372 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_4 */ 373 #define ANA_AC_SG_CONFIG_REG_4 __REG(TARGET_ANA_AC,\ 374 0, 1, 851584, 0, 1, 128, 60, 0, 1, 4) 375 376 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_5 */ 377 #define ANA_AC_SG_CONFIG_REG_5 __REG(TARGET_ANA_AC,\ 378 0, 1, 851584, 0, 1, 128, 64, 0, 1, 4) 379 380 /* ANA_AC:SG_CONFIG:SG_GCL_GS_CONFIG */ 381 #define ANA_AC_SG_GCL_GS_CONFIG(r) __REG(TARGET_ANA_AC,\ 382 0, 1, 851584, 0, 1, 128, 0, r, 4, 4) 383 384 #define ANA_AC_SG_GCL_GS_CONFIG_IPS GENMASK(3, 0) 385 #define ANA_AC_SG_GCL_GS_CONFIG_IPS_SET(x)\ 386 FIELD_PREP(ANA_AC_SG_GCL_GS_CONFIG_IPS, x) 387 #define ANA_AC_SG_GCL_GS_CONFIG_IPS_GET(x)\ 388 FIELD_GET(ANA_AC_SG_GCL_GS_CONFIG_IPS, x) 389 390 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE BIT(4) 391 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_SET(x)\ 392 FIELD_PREP(ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE, x) 393 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_GET(x)\ 394 FIELD_GET(ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE, x) 395 396 /* ANA_AC:SG_CONFIG:SG_GCL_TI_CONFIG */ 397 #define ANA_AC_SG_GCL_TI_CONFIG(r) __REG(TARGET_ANA_AC,\ 398 0, 1, 851584, 0, 1, 128, 16, r, 4, 4) 399 400 /* ANA_AC:SG_CONFIG:SG_GCL_OCT_CONFIG */ 401 #define ANA_AC_SG_GCL_OCT_CONFIG(r) __REG(TARGET_ANA_AC,\ 402 0, 1, 851584, 0, 1, 128, 32, r, 4, 4) 403 404 /* ANA_AC:SG_STATUS:SG_STATUS_REG_1 */ 405 #define ANA_AC_SG_STATUS_REG_1 __REG(TARGET_ANA_AC,\ 406 0, 1, 839088, 0, 1, 16, 0, 0, 1, 4) 407 408 /* ANA_AC:SG_STATUS:SG_STATUS_REG_2 */ 409 #define ANA_AC_SG_STATUS_REG_2 __REG(TARGET_ANA_AC,\ 410 0, 1, 839088, 0, 1, 16, 4, 0, 1, 4) 411 412 /* ANA_AC:SG_STATUS:SG_STATUS_REG_3 */ 413 #define ANA_AC_SG_STATUS_REG_3 __REG(TARGET_ANA_AC,\ 414 0, 1, 839088, 0, 1, 16, 8, 0, 1, 4) 415 416 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB GENMASK(15, 0) 417 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_SET(x)\ 418 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB, x) 419 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_GET(x)\ 420 FIELD_GET(ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB, x) 421 422 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE BIT(16) 423 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE_SET(x)\ 424 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_GATE_STATE, x) 425 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE_GET(x)\ 426 FIELD_GET(ANA_AC_SG_STATUS_REG_3_GATE_STATE, x) 427 428 #define ANA_AC_SG_STATUS_REG_3_IPS GENMASK(23, 20) 429 #define ANA_AC_SG_STATUS_REG_3_IPS_SET(x)\ 430 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_IPS, x) 431 #define ANA_AC_SG_STATUS_REG_3_IPS_GET(x)\ 432 FIELD_GET(ANA_AC_SG_STATUS_REG_3_IPS, x) 433 434 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING BIT(24) 435 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_SET(x)\ 436 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING, x) 437 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_GET(x)\ 438 FIELD_GET(ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING, x) 439 440 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX GENMASK(27, 25) 441 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_SET(x)\ 442 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX, x) 443 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_GET(x)\ 444 FIELD_GET(ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX, x) 445 446 /* ANA_AC:SG_STATUS:SG_STATUS_REG_4 */ 447 #define ANA_AC_SG_STATUS_REG_4 __REG(TARGET_ANA_AC,\ 448 0, 1, 839088, 0, 1, 16, 12, 0, 1, 4) 449 450 /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_GLOBAL_EVENT_MASK */ 451 #define ANA_AC_PORT_SGE_CFG(r) __REG(TARGET_ANA_AC,\ 452 0, 1, 851552, 0, 1, 20, 0, r, 4, 4) 453 454 #define ANA_AC_PORT_SGE_CFG_MASK GENMASK(15, 0) 455 #define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\ 456 FIELD_PREP(ANA_AC_PORT_SGE_CFG_MASK, x) 457 #define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\ 458 FIELD_GET(ANA_AC_PORT_SGE_CFG_MASK, x) 459 460 /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_RESET */ 461 #define ANA_AC_STAT_RESET __REG(TARGET_ANA_AC,\ 462 0, 1, 851552, 0, 1, 20, 16, 0, 1, 4) 463 464 #define ANA_AC_STAT_RESET_RESET BIT(0) 465 #define ANA_AC_STAT_RESET_RESET_SET(x)\ 466 FIELD_PREP(ANA_AC_STAT_RESET_RESET, x) 467 #define ANA_AC_STAT_RESET_RESET_GET(x)\ 468 FIELD_GET(ANA_AC_STAT_RESET_RESET, x) 469 470 /* ANA_AC:STAT_CNT_CFG_PORT:STAT_CFG */ 471 #define ANA_AC_PORT_STAT_CFG(g, r) __REG(TARGET_ANA_AC,\ 472 0, 1, 843776, g, 70, 64, 4, r, 4, 4) 473 474 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK GENMASK(11, 4) 475 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\ 476 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x) 477 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_GET(x)\ 478 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x) 479 480 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE GENMASK(3, 1) 481 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(x)\ 482 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x) 483 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_GET(x)\ 484 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x) 485 486 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE BIT(0) 487 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_SET(x)\ 488 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x) 489 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\ 490 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x) 491 492 /* ANA_AC:STAT_CNT_CFG_PORT:STAT_LSB_CNT */ 493 #define ANA_AC_PORT_STAT_LSB_CNT(g, r) __REG(TARGET_ANA_AC,\ 494 0, 1, 843776, g, 70, 64, 20, r, 4, 4) 495 496 /* ANA_AC:STAT_GLOBAL_CFG_ACL:GLOBAL_CNT_FRM_TYPE_CFG */ 497 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG(r) __REG(TARGET_ANA_AC,\ 498 0, 1, 893792, 0, 1, 24, 0, r, 2, 4) 499 500 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE GENMASK(2, 0) 501 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_SET(x)\ 502 FIELD_PREP(ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE, x) 503 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_GET(x)\ 504 FIELD_GET(ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE, x) 505 506 /* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_CFG */ 507 #define ANA_AC_ACL_STAT_GLOBAL_CFG(r) __REG(TARGET_ANA_AC,\ 508 0, 1, 893792, 0, 1, 24, 8, r, 2, 4) 509 510 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE BIT(0) 511 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_SET(x)\ 512 FIELD_PREP(ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE, x) 513 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_GET(x)\ 514 FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE, x) 515 516 /* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_EVENT_MASK */ 517 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK(r) __REG(TARGET_ANA_AC,\ 518 0, 1, 893792, 0, 1, 24, 16, r, 2, 4) 519 520 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK GENMASK(3, 0) 521 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_SET(x)\ 522 FIELD_PREP(ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK, x) 523 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_GET(x)\ 524 FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK, x) 525 526 /* ANA_ACL:COMMON:VCAP_S2_CFG */ 527 #define ANA_ACL_VCAP_S2_CFG(r) __REG(TARGET_ANA_ACL,\ 528 0, 1, 32768, 0, 1, 592, 0, r, 70, 4) 529 530 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA BIT(28) 531 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_SET(x)\ 532 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA, x) 533 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_GET(x)\ 534 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA, x) 535 536 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA GENMASK(27, 26) 537 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_SET(x)\ 538 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA, x) 539 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_GET(x)\ 540 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA, x) 541 542 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA GENMASK(25, 24) 543 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_SET(x)\ 544 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA, x) 545 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_GET(x)\ 546 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA, x) 547 548 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA GENMASK(23, 22) 549 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_SET(x)\ 550 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA, x) 551 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_GET(x)\ 552 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA, x) 553 554 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA GENMASK(21, 20) 555 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_SET(x)\ 556 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA, x) 557 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_GET(x)\ 558 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA, x) 559 560 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA GENMASK(19, 18) 561 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_SET(x)\ 562 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA, x) 563 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_GET(x)\ 564 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA, x) 565 566 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA GENMASK(17, 16) 567 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_SET(x)\ 568 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA, x) 569 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_GET(x)\ 570 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA, x) 571 572 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA GENMASK(15, 14) 573 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_SET(x)\ 574 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA, x) 575 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_GET(x)\ 576 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA, x) 577 578 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA GENMASK(13, 12) 579 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_SET(x)\ 580 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA, x) 581 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_GET(x)\ 582 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA, x) 583 584 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA GENMASK(11, 10) 585 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_SET(x)\ 586 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA, x) 587 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_GET(x)\ 588 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA, x) 589 590 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA GENMASK(9, 8) 591 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_SET(x)\ 592 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA, x) 593 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_GET(x)\ 594 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA, x) 595 596 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA GENMASK(7, 6) 597 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_SET(x)\ 598 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA, x) 599 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_GET(x)\ 600 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA, x) 601 602 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA GENMASK(5, 4) 603 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_SET(x)\ 604 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA, x) 605 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_GET(x)\ 606 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA, x) 607 608 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA GENMASK(3, 0) 609 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_SET(x)\ 610 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x) 611 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_GET(x)\ 612 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x) 613 614 /* ANA_ACL:COMMON:SWAP_IP_CTRL */ 615 #define ANA_ACL_SWAP_IP_CTRL __REG(TARGET_ANA_ACL,\ 616 0, 1, 32768, 0, 1, 592, 412, 0, 1, 4) 617 618 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL GENMASK(23, 18) 619 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_SET(x)\ 620 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL, x) 621 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_GET(x)\ 622 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL, x) 623 624 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL GENMASK(17, 10) 625 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_SET(x)\ 626 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL, x) 627 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_GET(x)\ 628 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL, x) 629 630 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL GENMASK(9, 2) 631 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_SET(x)\ 632 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL, x) 633 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_GET(x)\ 634 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL, x) 635 636 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA BIT(1) 637 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_SET(x)\ 638 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA, x) 639 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_GET(x)\ 640 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA, x) 641 642 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA BIT(0) 643 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_SET(x)\ 644 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x) 645 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_GET(x)\ 646 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x) 647 648 /* ANA_ACL:COMMON:VCAP_S2_RLEG_STAT */ 649 #define ANA_ACL_VCAP_S2_RLEG_STAT(r) __REG(TARGET_ANA_ACL,\ 650 0, 1, 32768, 0, 1, 592, 424, r, 4, 4) 651 652 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK GENMASK(12, 6) 653 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_SET(x)\ 654 FIELD_PREP(ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK, x) 655 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_GET(x)\ 656 FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK, x) 657 658 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK GENMASK(5, 0) 659 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_SET(x)\ 660 FIELD_PREP(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x) 661 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_GET(x)\ 662 FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x) 663 664 /* ANA_ACL:COMMON:VCAP_S2_FRAGMENT_CFG */ 665 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG __REG(TARGET_ANA_ACL,\ 666 0, 1, 32768, 0, 1, 592, 440, 0, 1, 4) 667 668 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN GENMASK(9, 5) 669 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_SET(x)\ 670 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN, x) 671 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_GET(x)\ 672 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN, x) 673 674 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS BIT(4) 675 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_SET(x)\ 676 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS, x) 677 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_GET(x)\ 678 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS, x) 679 680 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES GENMASK(3, 0) 681 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_SET(x)\ 682 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x) 683 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_GET(x)\ 684 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x) 685 686 /* ANA_ACL:COMMON:OWN_UPSID */ 687 #define ANA_ACL_OWN_UPSID(r) __REG(TARGET_ANA_ACL,\ 688 0, 1, 32768, 0, 1, 592, 580, r, 3, 4) 689 690 #define ANA_ACL_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 691 #define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\ 692 FIELD_PREP(ANA_ACL_OWN_UPSID_OWN_UPSID, x) 693 #define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\ 694 FIELD_GET(ANA_ACL_OWN_UPSID_OWN_UPSID, x) 695 696 /* ANA_ACL:KEY_SEL:VCAP_S2_KEY_SEL */ 697 #define ANA_ACL_VCAP_S2_KEY_SEL(g, r) __REG(TARGET_ANA_ACL,\ 698 0, 1, 34200, g, 134, 16, 0, r, 4, 4) 699 700 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA BIT(13) 701 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_SET(x)\ 702 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA, x) 703 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_GET(x)\ 704 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA, x) 705 706 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL BIT(12) 707 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_SET(x)\ 708 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL, x) 709 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_GET(x)\ 710 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL, x) 711 712 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL GENMASK(11, 10) 713 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_SET(x)\ 714 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL, x) 715 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_GET(x)\ 716 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL, x) 717 718 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL GENMASK(9, 8) 719 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_SET(x)\ 720 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL, x) 721 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_GET(x)\ 722 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL, x) 723 724 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL GENMASK(7, 6) 725 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_SET(x)\ 726 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL, x) 727 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_GET(x)\ 728 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL, x) 729 730 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL GENMASK(5, 3) 731 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_SET(x)\ 732 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL, x) 733 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_GET(x)\ 734 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL, x) 735 736 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL GENMASK(2, 1) 737 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_SET(x)\ 738 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL, x) 739 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_GET(x)\ 740 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL, x) 741 742 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL BIT(0) 743 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_SET(x)\ 744 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x) 745 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_GET(x)\ 746 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x) 747 748 /* ANA_ACL:CNT_A:CNT_A */ 749 #define ANA_ACL_CNT_A(g) __REG(TARGET_ANA_ACL,\ 750 0, 1, 0, g, 4096, 4, 0, 0, 1, 4) 751 752 /* ANA_ACL:CNT_B:CNT_B */ 753 #define ANA_ACL_CNT_B(g) __REG(TARGET_ANA_ACL,\ 754 0, 1, 16384, g, 4096, 4, 0, 0, 1, 4) 755 756 /* ANA_ACL:STICKY:SEC_LOOKUP_STICKY */ 757 #define ANA_ACL_SEC_LOOKUP_STICKY(r) __REG(TARGET_ANA_ACL,\ 758 0, 1, 36408, 0, 1, 16, 0, r, 4, 4) 759 760 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY BIT(17) 761 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_SET(x)\ 762 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY, x) 763 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_GET(x)\ 764 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY, x) 765 766 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY BIT(16) 767 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_SET(x)\ 768 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY, x) 769 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_GET(x)\ 770 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY, x) 771 772 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY BIT(15) 773 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_SET(x)\ 774 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY, x) 775 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_GET(x)\ 776 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY, x) 777 778 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY BIT(14) 779 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_SET(x)\ 780 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY, x) 781 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_GET(x)\ 782 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY, x) 783 784 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY BIT(13) 785 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_SET(x)\ 786 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY, x) 787 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_GET(x)\ 788 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY, x) 789 790 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY BIT(12) 791 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_SET(x)\ 792 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY, x) 793 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_GET(x)\ 794 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY, x) 795 796 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY BIT(11) 797 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_SET(x)\ 798 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY, x) 799 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_GET(x)\ 800 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY, x) 801 802 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY BIT(10) 803 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\ 804 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x) 805 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\ 806 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x) 807 808 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY BIT(9) 809 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\ 810 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x) 811 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\ 812 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x) 813 814 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY BIT(8) 815 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_SET(x)\ 816 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY, x) 817 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_GET(x)\ 818 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY, x) 819 820 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY BIT(7) 821 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\ 822 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x) 823 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\ 824 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x) 825 826 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY BIT(6) 827 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\ 828 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x) 829 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\ 830 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x) 831 832 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY BIT(5) 833 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\ 834 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x) 835 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\ 836 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x) 837 838 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY BIT(4) 839 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\ 840 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x) 841 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\ 842 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x) 843 844 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY BIT(3) 845 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\ 846 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x) 847 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\ 848 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x) 849 850 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY BIT(2) 851 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_SET(x)\ 852 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY, x) 853 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_GET(x)\ 854 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY, x) 855 856 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY BIT(1) 857 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_SET(x)\ 858 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY, x) 859 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_GET(x)\ 860 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY, x) 861 862 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY BIT(0) 863 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\ 864 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) 865 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\ 866 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) 867 868 /* ANA_AC_POL:POL_ALL_CFG:POL_UPD_INT_CFG */ 869 #define ANA_AC_POL_POL_UPD_INT_CFG __REG(TARGET_ANA_AC_POL,\ 870 0, 1, 75968, 0, 1, 1160, 1148, 0, 1, 4) 871 872 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT GENMASK(9, 0) 873 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\ 874 FIELD_PREP(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x) 875 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\ 876 FIELD_GET(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x) 877 878 /* ANA_AC_POL:COMMON_BDLB:DLB_CTRL */ 879 #define ANA_AC_POL_BDLB_DLB_CTRL __REG(TARGET_ANA_AC_POL,\ 880 0, 1, 79048, 0, 1, 8, 0, 0, 1, 4) 881 882 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19) 883 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ 884 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x) 885 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\ 886 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x) 887 888 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT GENMASK(18, 4) 889 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\ 890 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x) 891 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\ 892 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x) 893 894 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA BIT(1) 895 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_SET(x)\ 896 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x) 897 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_GET(x)\ 898 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x) 899 900 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA BIT(0) 901 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\ 902 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x) 903 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ 904 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x) 905 906 /* ANA_AC_POL:COMMON_BUM_SLB:DLB_CTRL */ 907 #define ANA_AC_POL_SLB_DLB_CTRL __REG(TARGET_ANA_AC_POL,\ 908 0, 1, 79056, 0, 1, 20, 0, 0, 1, 4) 909 910 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19) 911 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ 912 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x) 913 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\ 914 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x) 915 916 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT GENMASK(18, 4) 917 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\ 918 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x) 919 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\ 920 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x) 921 922 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA BIT(1) 923 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_SET(x)\ 924 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x) 925 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_GET(x)\ 926 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x) 927 928 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA BIT(0) 929 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\ 930 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x) 931 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ 932 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x) 933 934 /* ANA_AC_SDLB:LBGRP_TBL:XLB_START */ 935 #define ANA_AC_SDLB_XLB_START(g) __REG(TARGET_ANA_AC_SDLB,\ 936 0, 1, 295468, g, 10, 24, 0, 0, 1, 4) 937 938 #define ANA_AC_SDLB_XLB_START_LBSET_START GENMASK(12, 0) 939 #define ANA_AC_SDLB_XLB_START_LBSET_START_SET(x)\ 940 FIELD_PREP(ANA_AC_SDLB_XLB_START_LBSET_START, x) 941 #define ANA_AC_SDLB_XLB_START_LBSET_START_GET(x)\ 942 FIELD_GET(ANA_AC_SDLB_XLB_START_LBSET_START, x) 943 944 /* ANA_AC_SDLB:LBGRP_TBL:PUP_INTERVAL */ 945 #define ANA_AC_SDLB_PUP_INTERVAL(g) __REG(TARGET_ANA_AC_SDLB,\ 946 0, 1, 295468, g, 10, 24, 4, 0, 1, 4) 947 948 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL GENMASK(19, 0) 949 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_SET(x)\ 950 FIELD_PREP(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL, x) 951 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_GET(x)\ 952 FIELD_GET(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL, x) 953 954 /* ANA_AC_SDLB:LBGRP_TBL:PUP_CTRL */ 955 #define ANA_AC_SDLB_PUP_CTRL(g) __REG(TARGET_ANA_AC_SDLB,\ 956 0, 1, 295468, g, 10, 24, 8, 0, 1, 4) 957 958 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT GENMASK(18, 0) 959 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_SET(x)\ 960 FIELD_PREP(ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT, x) 961 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_GET(x)\ 962 FIELD_GET(ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT, x) 963 964 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA BIT(24) 965 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(x)\ 966 FIELD_PREP(ANA_AC_SDLB_PUP_CTRL_PUP_ENA, x) 967 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_GET(x)\ 968 FIELD_GET(ANA_AC_SDLB_PUP_CTRL_PUP_ENA, x) 969 970 /* ANA_AC_SDLB:LBGRP_TBL:LBGRP_MISC */ 971 #define ANA_AC_SDLB_LBGRP_MISC(g) __REG(TARGET_ANA_AC_SDLB,\ 972 0, 1, 295468, g, 10, 24, 12, 0, 1, 4) 973 974 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT GENMASK(12, 8) 975 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_SET(x)\ 976 FIELD_PREP(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x) 977 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_GET(x)\ 978 FIELD_GET(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x) 979 980 /* ANA_AC_SDLB:LBGRP_TBL:FRM_RATE_TOKENS */ 981 #define ANA_AC_SDLB_FRM_RATE_TOKENS(g) __REG(TARGET_ANA_AC_SDLB,\ 982 0, 1, 295468, g, 10, 24, 16, 0, 1, 4) 983 984 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS GENMASK(12, 0) 985 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_SET(x)\ 986 FIELD_PREP(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS, x) 987 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_GET(x)\ 988 FIELD_GET(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS, x) 989 990 /* ANA_AC_SDLB:LBGRP_TBL:LBGRP_STATE_TBL */ 991 #define ANA_AC_SDLB_LBGRP_STATE_TBL(g) __REG(TARGET_ANA_AC_SDLB,\ 992 0, 1, 295468, g, 10, 24, 20, 0, 1, 4) 993 994 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING BIT(0) 995 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_SET(x)\ 996 FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING, x) 997 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_GET(x)\ 998 FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING, x) 999 1000 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK BIT(1) 1001 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_SET(x)\ 1002 FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK, x) 1003 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_GET(x)\ 1004 FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK, x) 1005 1006 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT GENMASK(28, 16) 1007 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_SET(x)\ 1008 FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x) 1009 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_GET(x)\ 1010 FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x) 1011 1012 /* ANA_AC_SDLB:LBSET_TBL:PUP_TOKENS */ 1013 #define ANA_AC_SDLB_PUP_TOKENS(g, r) __REG(TARGET_ANA_AC_SDLB,\ 1014 0, 1, 0, g, 4616, 64, 0, r, 2, 4) 1015 1016 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS GENMASK(12, 0) 1017 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_SET(x)\ 1018 FIELD_PREP(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS, x) 1019 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_GET(x)\ 1020 FIELD_GET(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS, x) 1021 1022 /* ANA_AC_SDLB:LBSET_TBL:THRES */ 1023 #define ANA_AC_SDLB_THRES(g, r) __REG(TARGET_ANA_AC_SDLB,\ 1024 0, 1, 0, g, 4616, 64, 8, r, 2, 4) 1025 1026 #define ANA_AC_SDLB_THRES_THRES GENMASK(9, 0) 1027 #define ANA_AC_SDLB_THRES_THRES_SET(x)\ 1028 FIELD_PREP(ANA_AC_SDLB_THRES_THRES, x) 1029 #define ANA_AC_SDLB_THRES_THRES_GET(x)\ 1030 FIELD_GET(ANA_AC_SDLB_THRES_THRES, x) 1031 1032 #define ANA_AC_SDLB_THRES_THRES_HYS GENMASK(25, 16) 1033 #define ANA_AC_SDLB_THRES_THRES_HYS_SET(x)\ 1034 FIELD_PREP(ANA_AC_SDLB_THRES_THRES_HYS, x) 1035 #define ANA_AC_SDLB_THRES_THRES_HYS_GET(x)\ 1036 FIELD_GET(ANA_AC_SDLB_THRES_THRES_HYS, x) 1037 1038 /* ANA_AC_SDLB:LBSET_TBL:XLB_NEXT */ 1039 #define ANA_AC_SDLB_XLB_NEXT(g) __REG(TARGET_ANA_AC_SDLB,\ 1040 0, 1, 0, g, 4616, 64, 16, 0, 1, 4) 1041 1042 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT GENMASK(12, 0) 1043 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_SET(x)\ 1044 FIELD_PREP(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x) 1045 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_GET(x)\ 1046 FIELD_GET(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x) 1047 1048 #define ANA_AC_SDLB_XLB_NEXT_LBGRP GENMASK(27, 24) 1049 #define ANA_AC_SDLB_XLB_NEXT_LBGRP_SET(x)\ 1050 FIELD_PREP(ANA_AC_SDLB_XLB_NEXT_LBGRP, x) 1051 #define ANA_AC_SDLB_XLB_NEXT_LBGRP_GET(x)\ 1052 FIELD_GET(ANA_AC_SDLB_XLB_NEXT_LBGRP, x) 1053 1054 /* ANA_AC_SDLB:LBSET_TBL:INH_CTRL */ 1055 #define ANA_AC_SDLB_INH_CTRL(g, r) __REG(TARGET_ANA_AC_SDLB,\ 1056 0, 1, 0, g, 4616, 64, 20, r, 2, 4) 1057 1058 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX GENMASK(12, 0) 1059 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_SET(x)\ 1060 FIELD_PREP(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX, x) 1061 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_GET(x)\ 1062 FIELD_GET(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX, x) 1063 1064 #define ANA_AC_SDLB_INH_CTRL_INH_MODE GENMASK(21, 20) 1065 #define ANA_AC_SDLB_INH_CTRL_INH_MODE_SET(x)\ 1066 FIELD_PREP(ANA_AC_SDLB_INH_CTRL_INH_MODE, x) 1067 #define ANA_AC_SDLB_INH_CTRL_INH_MODE_GET(x)\ 1068 FIELD_GET(ANA_AC_SDLB_INH_CTRL_INH_MODE, x) 1069 1070 #define ANA_AC_SDLB_INH_CTRL_INH_LB BIT(24) 1071 #define ANA_AC_SDLB_INH_CTRL_INH_LB_SET(x)\ 1072 FIELD_PREP(ANA_AC_SDLB_INH_CTRL_INH_LB, x) 1073 #define ANA_AC_SDLB_INH_CTRL_INH_LB_GET(x)\ 1074 FIELD_GET(ANA_AC_SDLB_INH_CTRL_INH_LB, x) 1075 1076 /* ANA_AC_SDLB:LBSET_TBL:INH_LBSET_ADDR */ 1077 #define ANA_AC_SDLB_INH_LBSET_ADDR(g) __REG(TARGET_ANA_AC_SDLB,\ 1078 0, 1, 0, g, 4616, 64, 28, 0, 1, 4) 1079 1080 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR GENMASK(12, 0) 1081 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_SET(x)\ 1082 FIELD_PREP(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x) 1083 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_GET(x)\ 1084 FIELD_GET(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x) 1085 1086 /* ANA_AC_SDLB:LBSET_TBL:DLB_MISC */ 1087 #define ANA_AC_SDLB_DLB_MISC(g) __REG(TARGET_ANA_AC_SDLB,\ 1088 0, 1, 0, g, 4616, 64, 32, 0, 1, 4) 1089 1090 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA BIT(0) 1091 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_SET(x)\ 1092 FIELD_PREP(ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA, x) 1093 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_GET(x)\ 1094 FIELD_GET(ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA, x) 1095 1096 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA BIT(6) 1097 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_SET(x)\ 1098 FIELD_PREP(ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA, x) 1099 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_GET(x)\ 1100 FIELD_GET(ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA, x) 1101 1102 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ GENMASK(14, 8) 1103 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_SET(x)\ 1104 FIELD_PREP(ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ, x) 1105 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_GET(x)\ 1106 FIELD_GET(ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ, x) 1107 1108 /* ANA_AC_SDLB:LBSET_TBL:DLB_CFG */ 1109 #define ANA_AC_SDLB_DLB_CFG(g) __REG(TARGET_ANA_AC_SDLB,\ 1110 0, 1, 0, g, 4616, 64, 36, 0, 1, 4) 1111 1112 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA BIT(11) 1113 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_SET(x)\ 1114 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA, x) 1115 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_GET(x)\ 1116 FIELD_GET(ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA, x) 1117 1118 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL GENMASK(10, 9) 1119 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_SET(x)\ 1120 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL, x) 1121 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_GET(x)\ 1122 FIELD_GET(ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL, x) 1123 1124 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS BIT(8) 1125 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_SET(x)\ 1126 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS, x) 1127 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_GET(x)\ 1128 FIELD_GET(ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS, x) 1129 1130 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS BIT(7) 1131 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_SET(x)\ 1132 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS, x) 1133 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_GET(x)\ 1134 FIELD_GET(ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS, x) 1135 1136 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL GENMASK(6, 5) 1137 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_SET(x)\ 1138 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL, x) 1139 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_GET(x)\ 1140 FIELD_GET(ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL, x) 1141 1142 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL GENMASK(4, 3) 1143 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_SET(x)\ 1144 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL, x) 1145 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_GET(x)\ 1146 FIELD_GET(ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL, x) 1147 1148 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE BIT(2) 1149 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE_SET(x)\ 1150 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DLB_MODE, x) 1151 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE_GET(x)\ 1152 FIELD_GET(ANA_AC_SDLB_DLB_CFG_DLB_MODE, x) 1153 1154 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK GENMASK(1, 0) 1155 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_SET(x)\ 1156 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK, x) 1157 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_GET(x)\ 1158 FIELD_GET(ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK, x) 1159 1160 /* ANA_CL:PORT:FILTER_CTRL */ 1161 #define ANA_CL_FILTER_CTRL(g) __REG(TARGET_ANA_CL,\ 1162 0, 1, 131072, g, 70, 512, 4, 0, 1, 4) 1163 1164 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS BIT(2) 1165 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\ 1166 FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x) 1167 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_GET(x)\ 1168 FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x) 1169 1170 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS BIT(1) 1171 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_SET(x)\ 1172 FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x) 1173 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_GET(x)\ 1174 FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x) 1175 1176 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA BIT(0) 1177 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x)\ 1178 FIELD_PREP(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x) 1179 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\ 1180 FIELD_GET(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x) 1181 1182 /* ANA_CL:PORT:VLAN_FILTER_CTRL */ 1183 #define ANA_CL_VLAN_FILTER_CTRL(g, r) __REG(TARGET_ANA_CL,\ 1184 0, 1, 131072, g, 70, 512, 8, r, 3, 4) 1185 1186 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA BIT(10) 1187 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\ 1188 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x) 1189 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_GET(x)\ 1190 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x) 1191 1192 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS BIT(9) 1193 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_SET(x)\ 1194 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x) 1195 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_GET(x)\ 1196 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x) 1197 1198 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS BIT(8) 1199 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_SET(x)\ 1200 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x) 1201 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_GET(x)\ 1202 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x) 1203 1204 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS BIT(7) 1205 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_SET(x)\ 1206 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x) 1207 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_GET(x)\ 1208 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x) 1209 1210 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS BIT(6) 1211 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_SET(x)\ 1212 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x) 1213 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_GET(x)\ 1214 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x) 1215 1216 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS BIT(5) 1217 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_SET(x)\ 1218 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x) 1219 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_GET(x)\ 1220 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x) 1221 1222 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS BIT(4) 1223 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_SET(x)\ 1224 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x) 1225 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_GET(x)\ 1226 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x) 1227 1228 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS BIT(3) 1229 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_SET(x)\ 1230 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x) 1231 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_GET(x)\ 1232 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x) 1233 1234 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS BIT(2) 1235 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_SET(x)\ 1236 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x) 1237 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_GET(x)\ 1238 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x) 1239 1240 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS BIT(1) 1241 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_SET(x)\ 1242 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x) 1243 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_GET(x)\ 1244 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x) 1245 1246 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS BIT(0) 1247 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_SET(x)\ 1248 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x) 1249 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\ 1250 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x) 1251 1252 /* ANA_CL:PORT:ETAG_FILTER_CTRL */ 1253 #define ANA_CL_ETAG_FILTER_CTRL(g) __REG(TARGET_ANA_CL,\ 1254 0, 1, 131072, g, 70, 512, 20, 0, 1, 4) 1255 1256 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA BIT(1) 1257 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\ 1258 FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x) 1259 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_GET(x)\ 1260 FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x) 1261 1262 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS BIT(0) 1263 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_SET(x)\ 1264 FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x) 1265 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\ 1266 FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x) 1267 1268 /* ANA_CL:PORT:VLAN_CTRL */ 1269 #define ANA_CL_VLAN_CTRL(g) __REG(TARGET_ANA_CL,\ 1270 0, 1, 131072, g, 70, 512, 32, 0, 1, 4) 1271 1272 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS GENMASK(30, 26) 1273 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\ 1274 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x) 1275 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_GET(x)\ 1276 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x) 1277 1278 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP GENMASK(25, 23) 1279 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_SET(x)\ 1280 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x) 1281 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_GET(x)\ 1282 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x) 1283 1284 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI BIT(22) 1285 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_SET(x)\ 1286 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x) 1287 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_GET(x)\ 1288 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x) 1289 1290 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA BIT(21) 1291 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_SET(x)\ 1292 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x) 1293 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_GET(x)\ 1294 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x) 1295 1296 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL BIT(20) 1297 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_SET(x)\ 1298 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x) 1299 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_GET(x)\ 1300 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x) 1301 1302 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA BIT(19) 1303 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x)\ 1304 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x) 1305 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x)\ 1306 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x) 1307 1308 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT GENMASK(18, 17) 1309 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x)\ 1310 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x) 1311 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x)\ 1312 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x) 1313 1314 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE BIT(16) 1315 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_SET(x)\ 1316 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x) 1317 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_GET(x)\ 1318 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x) 1319 1320 #define ANA_CL_VLAN_CTRL_PORT_PCP GENMASK(15, 13) 1321 #define ANA_CL_VLAN_CTRL_PORT_PCP_SET(x)\ 1322 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_PCP, x) 1323 #define ANA_CL_VLAN_CTRL_PORT_PCP_GET(x)\ 1324 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_PCP, x) 1325 1326 #define ANA_CL_VLAN_CTRL_PORT_DEI BIT(12) 1327 #define ANA_CL_VLAN_CTRL_PORT_DEI_SET(x)\ 1328 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_DEI, x) 1329 #define ANA_CL_VLAN_CTRL_PORT_DEI_GET(x)\ 1330 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_DEI, x) 1331 1332 #define ANA_CL_VLAN_CTRL_PORT_VID GENMASK(11, 0) 1333 #define ANA_CL_VLAN_CTRL_PORT_VID_SET(x)\ 1334 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VID, x) 1335 #define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\ 1336 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VID, x) 1337 1338 /* ANA_CL:PORT:VLAN_CTRL_2 */ 1339 #define ANA_CL_VLAN_CTRL_2(g) __REG(TARGET_ANA_CL,\ 1340 0, 1, 131072, g, 70, 512, 36, 0, 1, 4) 1341 1342 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT GENMASK(1, 0) 1343 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\ 1344 FIELD_PREP(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x) 1345 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\ 1346 FIELD_GET(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x) 1347 1348 /* ANA_CL:PORT:PCP_DEI_MAP_CFG */ 1349 #define ANA_CL_PCP_DEI_MAP_CFG(g, r) __REG(TARGET_ANA_CL,\ 1350 0, 1, 131072, g, 70, 512, 108, r, 16, 4) 1351 1352 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL GENMASK(4, 3) 1353 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_SET(x)\ 1354 FIELD_PREP(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL, x) 1355 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_GET(x)\ 1356 FIELD_GET(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL, x) 1357 1358 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL GENMASK(2, 0) 1359 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_SET(x)\ 1360 FIELD_PREP(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL, x) 1361 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_GET(x)\ 1362 FIELD_GET(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL, x) 1363 1364 /* ANA_CL:PORT:QOS_CFG */ 1365 #define ANA_CL_QOS_CFG(g) __REG(TARGET_ANA_CL,\ 1366 0, 1, 131072, g, 70, 512, 172, 0, 1, 4) 1367 1368 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA BIT(17) 1369 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_SET(x)\ 1370 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_COSID_ENA, x) 1371 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_GET(x)\ 1372 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_COSID_ENA, x) 1373 1374 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL GENMASK(16, 14) 1375 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_SET(x)\ 1376 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_COSID_VAL, x) 1377 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_GET(x)\ 1378 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_COSID_VAL, x) 1379 1380 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL GENMASK(13, 12) 1381 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_SET(x)\ 1382 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL, x) 1383 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_GET(x)\ 1384 FIELD_GET(ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL, x) 1385 1386 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA BIT(11) 1387 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_SET(x)\ 1388 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA, x) 1389 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_GET(x)\ 1390 FIELD_GET(ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA, x) 1391 1392 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA BIT(10) 1393 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_SET(x)\ 1394 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_KEEP_ENA, x) 1395 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_GET(x)\ 1396 FIELD_GET(ANA_CL_QOS_CFG_DSCP_KEEP_ENA, x) 1397 1398 #define ANA_CL_QOS_CFG_KEEP_ENA BIT(9) 1399 #define ANA_CL_QOS_CFG_KEEP_ENA_SET(x)\ 1400 FIELD_PREP(ANA_CL_QOS_CFG_KEEP_ENA, x) 1401 #define ANA_CL_QOS_CFG_KEEP_ENA_GET(x)\ 1402 FIELD_GET(ANA_CL_QOS_CFG_KEEP_ENA, x) 1403 1404 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA BIT(8) 1405 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_SET(x)\ 1406 FIELD_PREP(ANA_CL_QOS_CFG_PCP_DEI_DP_ENA, x) 1407 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_GET(x)\ 1408 FIELD_GET(ANA_CL_QOS_CFG_PCP_DEI_DP_ENA, x) 1409 1410 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA BIT(7) 1411 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_SET(x)\ 1412 FIELD_PREP(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA, x) 1413 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_GET(x)\ 1414 FIELD_GET(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA, x) 1415 1416 #define ANA_CL_QOS_CFG_DSCP_DP_ENA BIT(6) 1417 #define ANA_CL_QOS_CFG_DSCP_DP_ENA_SET(x)\ 1418 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_DP_ENA, x) 1419 #define ANA_CL_QOS_CFG_DSCP_DP_ENA_GET(x)\ 1420 FIELD_GET(ANA_CL_QOS_CFG_DSCP_DP_ENA, x) 1421 1422 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA BIT(5) 1423 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_SET(x)\ 1424 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_QOS_ENA, x) 1425 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_GET(x)\ 1426 FIELD_GET(ANA_CL_QOS_CFG_DSCP_QOS_ENA, x) 1427 1428 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL GENMASK(4, 3) 1429 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_SET(x)\ 1430 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_DP_VAL, x) 1431 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_GET(x)\ 1432 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_DP_VAL, x) 1433 1434 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL GENMASK(2, 0) 1435 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_SET(x)\ 1436 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL, x) 1437 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_GET(x)\ 1438 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL, x) 1439 1440 /* ANA_CL:PORT:CAPTURE_BPDU_CFG */ 1441 #define ANA_CL_CAPTURE_BPDU_CFG(g) __REG(TARGET_ANA_CL,\ 1442 0, 1, 131072, g, 70, 512, 196, 0, 1, 4) 1443 1444 /* ANA_CL:PORT:ADV_CL_CFG_2 */ 1445 #define ANA_CL_ADV_CL_CFG_2(g, r) __REG(TARGET_ANA_CL,\ 1446 0, 1, 131072, g, 70, 512, 200, r, 6, 4) 1447 1448 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA BIT(1) 1449 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_SET(x)\ 1450 FIELD_PREP(ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA, x) 1451 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_GET(x)\ 1452 FIELD_GET(ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA, x) 1453 1454 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA BIT(0) 1455 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_SET(x)\ 1456 FIELD_PREP(ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA, x) 1457 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_GET(x)\ 1458 FIELD_GET(ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA, x) 1459 1460 /* ANA_CL:PORT:ADV_CL_CFG */ 1461 #define ANA_CL_ADV_CL_CFG(g, r) __REG(TARGET_ANA_CL,\ 1462 0, 1, 131072, g, 70, 512, 224, r, 6, 4) 1463 1464 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL GENMASK(30, 26) 1465 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_SET(x)\ 1466 FIELD_PREP(ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL, x) 1467 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_GET(x)\ 1468 FIELD_GET(ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL, x) 1469 1470 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL GENMASK(25, 21) 1471 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_SET(x)\ 1472 FIELD_PREP(ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL, x) 1473 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_GET(x)\ 1474 FIELD_GET(ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL, x) 1475 1476 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL GENMASK(20, 16) 1477 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_SET(x)\ 1478 FIELD_PREP(ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL, x) 1479 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_GET(x)\ 1480 FIELD_GET(ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL, x) 1481 1482 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL GENMASK(15, 11) 1483 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_SET(x)\ 1484 FIELD_PREP(ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL, x) 1485 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_GET(x)\ 1486 FIELD_GET(ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL, x) 1487 1488 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL GENMASK(10, 6) 1489 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_SET(x)\ 1490 FIELD_PREP(ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL, x) 1491 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_GET(x)\ 1492 FIELD_GET(ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL, x) 1493 1494 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL GENMASK(5, 1) 1495 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_SET(x)\ 1496 FIELD_PREP(ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL, x) 1497 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_GET(x)\ 1498 FIELD_GET(ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL, x) 1499 1500 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA BIT(0) 1501 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_SET(x)\ 1502 FIELD_PREP(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, x) 1503 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_GET(x)\ 1504 FIELD_GET(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, x) 1505 1506 /* ANA_CL:COMMON:OWN_UPSID */ 1507 #define ANA_CL_OWN_UPSID(r) __REG(TARGET_ANA_CL,\ 1508 0, 1, 166912, 0, 1, 756, 0, r, 3, 4) 1509 1510 #define ANA_CL_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 1511 #define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x)\ 1512 FIELD_PREP(ANA_CL_OWN_UPSID_OWN_UPSID, x) 1513 #define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x)\ 1514 FIELD_GET(ANA_CL_OWN_UPSID_OWN_UPSID, x) 1515 1516 /* ANA_CL:COMMON:DSCP_CFG */ 1517 #define ANA_CL_DSCP_CFG(r) __REG(TARGET_ANA_CL,\ 1518 0, 1, 166912, 0, 1, 756, 256, r, 64, 4) 1519 1520 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL GENMASK(12, 7) 1521 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_SET(x)\ 1522 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL, x) 1523 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_GET(x)\ 1524 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL, x) 1525 1526 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL GENMASK(6, 4) 1527 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_SET(x)\ 1528 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_QOS_VAL, x) 1529 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_GET(x)\ 1530 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_QOS_VAL, x) 1531 1532 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL GENMASK(3, 2) 1533 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_SET(x)\ 1534 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_DP_VAL, x) 1535 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_GET(x)\ 1536 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_DP_VAL, x) 1537 1538 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA BIT(1) 1539 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_SET(x)\ 1540 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_REWR_ENA, x) 1541 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_GET(x)\ 1542 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_REWR_ENA, x) 1543 1544 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA BIT(0) 1545 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_SET(x)\ 1546 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, x) 1547 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_GET(x)\ 1548 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, x) 1549 1550 /* ANA_CL:COMMON:QOS_MAP_CFG */ 1551 #define ANA_CL_QOS_MAP_CFG(r) __REG(TARGET_ANA_CL,\ 1552 0, 1, 166912, 0, 1, 756, 512, r, 32, 4) 1553 1554 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL GENMASK(9, 4) 1555 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_SET(x)\ 1556 FIELD_PREP(ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL, x) 1557 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_GET(x)\ 1558 FIELD_GET(ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL, x) 1559 1560 /* ANA_L2:COMMON:FWD_CFG */ 1561 #define ANA_L2_FWD_CFG __REG(TARGET_ANA_L2,\ 1562 0, 1, 566024, 0, 1, 700, 0, 0, 1, 4) 1563 1564 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL GENMASK(21, 20) 1565 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_SET(x)\ 1566 FIELD_PREP(ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL, x) 1567 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_GET(x)\ 1568 FIELD_GET(ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL, x) 1569 1570 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA BIT(18) 1571 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_SET(x)\ 1572 FIELD_PREP(ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA, x) 1573 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_GET(x)\ 1574 FIELD_GET(ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA, x) 1575 1576 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA BIT(17) 1577 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_SET(x)\ 1578 FIELD_PREP(ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA, x) 1579 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_GET(x)\ 1580 FIELD_GET(ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA, x) 1581 1582 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA BIT(16) 1583 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_SET(x)\ 1584 FIELD_PREP(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA, x) 1585 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_GET(x)\ 1586 FIELD_GET(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA, x) 1587 1588 #define ANA_L2_FWD_CFG_CPU_DMAC_QU GENMASK(10, 8) 1589 #define ANA_L2_FWD_CFG_CPU_DMAC_QU_SET(x)\ 1590 FIELD_PREP(ANA_L2_FWD_CFG_CPU_DMAC_QU, x) 1591 #define ANA_L2_FWD_CFG_CPU_DMAC_QU_GET(x)\ 1592 FIELD_GET(ANA_L2_FWD_CFG_CPU_DMAC_QU, x) 1593 1594 #define ANA_L2_FWD_CFG_LOOPBACK_ENA BIT(7) 1595 #define ANA_L2_FWD_CFG_LOOPBACK_ENA_SET(x)\ 1596 FIELD_PREP(ANA_L2_FWD_CFG_LOOPBACK_ENA, x) 1597 #define ANA_L2_FWD_CFG_LOOPBACK_ENA_GET(x)\ 1598 FIELD_GET(ANA_L2_FWD_CFG_LOOPBACK_ENA, x) 1599 1600 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA BIT(6) 1601 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_SET(x)\ 1602 FIELD_PREP(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA, x) 1603 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_GET(x)\ 1604 FIELD_GET(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA, x) 1605 1606 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL BIT(4) 1607 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL_SET(x)\ 1608 FIELD_PREP(ANA_L2_FWD_CFG_FILTER_MODE_SEL, x) 1609 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL_GET(x)\ 1610 FIELD_GET(ANA_L2_FWD_CFG_FILTER_MODE_SEL, x) 1611 1612 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA BIT(3) 1613 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_SET(x)\ 1614 FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA, x) 1615 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_GET(x)\ 1616 FIELD_GET(ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA, x) 1617 1618 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA BIT(2) 1619 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_SET(x)\ 1620 FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA, x) 1621 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_GET(x)\ 1622 FIELD_GET(ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA, x) 1623 1624 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA BIT(1) 1625 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_SET(x)\ 1626 FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA, x) 1627 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_GET(x)\ 1628 FIELD_GET(ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA, x) 1629 1630 #define ANA_L2_FWD_CFG_FWD_ENA BIT(0) 1631 #define ANA_L2_FWD_CFG_FWD_ENA_SET(x)\ 1632 FIELD_PREP(ANA_L2_FWD_CFG_FWD_ENA, x) 1633 #define ANA_L2_FWD_CFG_FWD_ENA_GET(x)\ 1634 FIELD_GET(ANA_L2_FWD_CFG_FWD_ENA, x) 1635 1636 /* ANA_L2:COMMON:AUTO_LRN_CFG */ 1637 #define ANA_L2_AUTO_LRN_CFG __REG(TARGET_ANA_L2,\ 1638 0, 1, 566024, 0, 1, 700, 24, 0, 1, 4) 1639 1640 /* ANA_L2:COMMON:AUTO_LRN_CFG1 */ 1641 #define ANA_L2_AUTO_LRN_CFG1 __REG(TARGET_ANA_L2,\ 1642 0, 1, 566024, 0, 1, 700, 28, 0, 1, 4) 1643 1644 /* ANA_L2:COMMON:AUTO_LRN_CFG2 */ 1645 #define ANA_L2_AUTO_LRN_CFG2 __REG(TARGET_ANA_L2,\ 1646 0, 1, 566024, 0, 1, 700, 32, 0, 1, 4) 1647 1648 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2 BIT(0) 1649 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x)\ 1650 FIELD_PREP(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x) 1651 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x)\ 1652 FIELD_GET(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x) 1653 1654 /* ANA_L2:COMMON:OWN_UPSID */ 1655 #define ANA_L2_OWN_UPSID(r) __REG(TARGET_ANA_L2,\ 1656 0, 1, 566024, 0, 1, 700, 672, r, 3, 4) 1657 1658 #define ANA_L2_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 1659 #define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x)\ 1660 FIELD_PREP(ANA_L2_OWN_UPSID_OWN_UPSID, x) 1661 #define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x)\ 1662 FIELD_GET(ANA_L2_OWN_UPSID_OWN_UPSID, x) 1663 1664 /* ANA_L2:ISDX:DLB_CFG */ 1665 #define ANA_L2_DLB_CFG(g) __REG(TARGET_ANA_L2,\ 1666 0, 1, 0, g, 4096, 128, 56, 0, 1, 4) 1667 1668 #define ANA_L2_DLB_CFG_DLB_IDX GENMASK(12, 0) 1669 #define ANA_L2_DLB_CFG_DLB_IDX_SET(x)\ 1670 FIELD_PREP(ANA_L2_DLB_CFG_DLB_IDX, x) 1671 #define ANA_L2_DLB_CFG_DLB_IDX_GET(x)\ 1672 FIELD_GET(ANA_L2_DLB_CFG_DLB_IDX, x) 1673 1674 /* ANA_L2:ISDX:TSN_CFG */ 1675 #define ANA_L2_TSN_CFG(g) __REG(TARGET_ANA_L2,\ 1676 0, 1, 0, g, 4096, 128, 100, 0, 1, 4) 1677 1678 #define ANA_L2_TSN_CFG_TSN_SFID GENMASK(9, 0) 1679 #define ANA_L2_TSN_CFG_TSN_SFID_SET(x)\ 1680 FIELD_PREP(ANA_L2_TSN_CFG_TSN_SFID, x) 1681 #define ANA_L2_TSN_CFG_TSN_SFID_GET(x)\ 1682 FIELD_GET(ANA_L2_TSN_CFG_TSN_SFID, x) 1683 1684 /* ANA_L3:COMMON:VLAN_CTRL */ 1685 #define ANA_L3_VLAN_CTRL __REG(TARGET_ANA_L3,\ 1686 0, 1, 493632, 0, 1, 184, 4, 0, 1, 4) 1687 1688 #define ANA_L3_VLAN_CTRL_VLAN_ENA BIT(0) 1689 #define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x)\ 1690 FIELD_PREP(ANA_L3_VLAN_CTRL_VLAN_ENA, x) 1691 #define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x)\ 1692 FIELD_GET(ANA_L3_VLAN_CTRL_VLAN_ENA, x) 1693 1694 /* ANA_L3:VLAN:VLAN_CFG */ 1695 #define ANA_L3_VLAN_CFG(g) __REG(TARGET_ANA_L3,\ 1696 0, 1, 0, g, 5120, 64, 8, 0, 1, 4) 1697 1698 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR GENMASK(30, 24) 1699 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x)\ 1700 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x) 1701 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_GET(x)\ 1702 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x) 1703 1704 #define ANA_L3_VLAN_CFG_VLAN_FID GENMASK(20, 8) 1705 #define ANA_L3_VLAN_CFG_VLAN_FID_SET(x)\ 1706 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FID, x) 1707 #define ANA_L3_VLAN_CFG_VLAN_FID_GET(x)\ 1708 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FID, x) 1709 1710 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA BIT(6) 1711 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_SET(x)\ 1712 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x) 1713 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_GET(x)\ 1714 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x) 1715 1716 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA BIT(5) 1717 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_SET(x)\ 1718 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x) 1719 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_GET(x)\ 1720 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x) 1721 1722 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS BIT(4) 1723 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_SET(x)\ 1724 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x) 1725 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_GET(x)\ 1726 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x) 1727 1728 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS BIT(3) 1729 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(x)\ 1730 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x) 1731 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_GET(x)\ 1732 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x) 1733 1734 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA BIT(2) 1735 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_SET(x)\ 1736 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x) 1737 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_GET(x)\ 1738 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x) 1739 1740 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA BIT(1) 1741 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_SET(x)\ 1742 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x) 1743 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_GET(x)\ 1744 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x) 1745 1746 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA BIT(0) 1747 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_SET(x)\ 1748 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x) 1749 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x)\ 1750 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x) 1751 1752 /* ANA_L3:VLAN:VLAN_MASK_CFG */ 1753 #define ANA_L3_VLAN_MASK_CFG(g) __REG(TARGET_ANA_L3,\ 1754 0, 1, 0, g, 5120, 64, 16, 0, 1, 4) 1755 1756 /* ANA_L3:VLAN:VLAN_MASK_CFG1 */ 1757 #define ANA_L3_VLAN_MASK_CFG1(g) __REG(TARGET_ANA_L3,\ 1758 0, 1, 0, g, 5120, 64, 20, 0, 1, 4) 1759 1760 /* ANA_L3:VLAN:VLAN_MASK_CFG2 */ 1761 #define ANA_L3_VLAN_MASK_CFG2(g) __REG(TARGET_ANA_L3,\ 1762 0, 1, 0, g, 5120, 64, 24, 0, 1, 4) 1763 1764 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2 BIT(0) 1765 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x)\ 1766 FIELD_PREP(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x) 1767 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x)\ 1768 FIELD_GET(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x) 1769 1770 /* ASM:DEV_STATISTICS:RX_IN_BYTES_CNT */ 1771 #define ASM_RX_IN_BYTES_CNT(g) __REG(TARGET_ASM,\ 1772 0, 1, 0, g, 65, 512, 0, 0, 1, 4) 1773 1774 /* ASM:DEV_STATISTICS:RX_SYMBOL_ERR_CNT */ 1775 #define ASM_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM,\ 1776 0, 1, 0, g, 65, 512, 4, 0, 1, 4) 1777 1778 /* ASM:DEV_STATISTICS:RX_PAUSE_CNT */ 1779 #define ASM_RX_PAUSE_CNT(g) __REG(TARGET_ASM,\ 1780 0, 1, 0, g, 65, 512, 8, 0, 1, 4) 1781 1782 /* ASM:DEV_STATISTICS:RX_UNSUP_OPCODE_CNT */ 1783 #define ASM_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM,\ 1784 0, 1, 0, g, 65, 512, 12, 0, 1, 4) 1785 1786 /* ASM:DEV_STATISTICS:RX_OK_BYTES_CNT */ 1787 #define ASM_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ 1788 0, 1, 0, g, 65, 512, 16, 0, 1, 4) 1789 1790 /* ASM:DEV_STATISTICS:RX_BAD_BYTES_CNT */ 1791 #define ASM_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM,\ 1792 0, 1, 0, g, 65, 512, 20, 0, 1, 4) 1793 1794 /* ASM:DEV_STATISTICS:RX_UC_CNT */ 1795 #define ASM_RX_UC_CNT(g) __REG(TARGET_ASM,\ 1796 0, 1, 0, g, 65, 512, 24, 0, 1, 4) 1797 1798 /* ASM:DEV_STATISTICS:RX_MC_CNT */ 1799 #define ASM_RX_MC_CNT(g) __REG(TARGET_ASM,\ 1800 0, 1, 0, g, 65, 512, 28, 0, 1, 4) 1801 1802 /* ASM:DEV_STATISTICS:RX_BC_CNT */ 1803 #define ASM_RX_BC_CNT(g) __REG(TARGET_ASM,\ 1804 0, 1, 0, g, 65, 512, 32, 0, 1, 4) 1805 1806 /* ASM:DEV_STATISTICS:RX_CRC_ERR_CNT */ 1807 #define ASM_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM,\ 1808 0, 1, 0, g, 65, 512, 36, 0, 1, 4) 1809 1810 /* ASM:DEV_STATISTICS:RX_UNDERSIZE_CNT */ 1811 #define ASM_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM,\ 1812 0, 1, 0, g, 65, 512, 40, 0, 1, 4) 1813 1814 /* ASM:DEV_STATISTICS:RX_FRAGMENTS_CNT */ 1815 #define ASM_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM,\ 1816 0, 1, 0, g, 65, 512, 44, 0, 1, 4) 1817 1818 /* ASM:DEV_STATISTICS:RX_IN_RANGE_LEN_ERR_CNT */ 1819 #define ASM_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ 1820 0, 1, 0, g, 65, 512, 48, 0, 1, 4) 1821 1822 /* ASM:DEV_STATISTICS:RX_OUT_OF_RANGE_LEN_ERR_CNT */ 1823 #define ASM_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ 1824 0, 1, 0, g, 65, 512, 52, 0, 1, 4) 1825 1826 /* ASM:DEV_STATISTICS:RX_OVERSIZE_CNT */ 1827 #define ASM_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM,\ 1828 0, 1, 0, g, 65, 512, 56, 0, 1, 4) 1829 1830 /* ASM:DEV_STATISTICS:RX_JABBERS_CNT */ 1831 #define ASM_RX_JABBERS_CNT(g) __REG(TARGET_ASM,\ 1832 0, 1, 0, g, 65, 512, 60, 0, 1, 4) 1833 1834 /* ASM:DEV_STATISTICS:RX_SIZE64_CNT */ 1835 #define ASM_RX_SIZE64_CNT(g) __REG(TARGET_ASM,\ 1836 0, 1, 0, g, 65, 512, 64, 0, 1, 4) 1837 1838 /* ASM:DEV_STATISTICS:RX_SIZE65TO127_CNT */ 1839 #define ASM_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ 1840 0, 1, 0, g, 65, 512, 68, 0, 1, 4) 1841 1842 /* ASM:DEV_STATISTICS:RX_SIZE128TO255_CNT */ 1843 #define ASM_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ 1844 0, 1, 0, g, 65, 512, 72, 0, 1, 4) 1845 1846 /* ASM:DEV_STATISTICS:RX_SIZE256TO511_CNT */ 1847 #define ASM_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ 1848 0, 1, 0, g, 65, 512, 76, 0, 1, 4) 1849 1850 /* ASM:DEV_STATISTICS:RX_SIZE512TO1023_CNT */ 1851 #define ASM_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ 1852 0, 1, 0, g, 65, 512, 80, 0, 1, 4) 1853 1854 /* ASM:DEV_STATISTICS:RX_SIZE1024TO1518_CNT */ 1855 #define ASM_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ 1856 0, 1, 0, g, 65, 512, 84, 0, 1, 4) 1857 1858 /* ASM:DEV_STATISTICS:RX_SIZE1519TOMAX_CNT */ 1859 #define ASM_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ 1860 0, 1, 0, g, 65, 512, 88, 0, 1, 4) 1861 1862 /* ASM:DEV_STATISTICS:RX_IPG_SHRINK_CNT */ 1863 #define ASM_RX_IPG_SHRINK_CNT(g) __REG(TARGET_ASM,\ 1864 0, 1, 0, g, 65, 512, 92, 0, 1, 4) 1865 1866 /* ASM:DEV_STATISTICS:TX_OUT_BYTES_CNT */ 1867 #define ASM_TX_OUT_BYTES_CNT(g) __REG(TARGET_ASM,\ 1868 0, 1, 0, g, 65, 512, 96, 0, 1, 4) 1869 1870 /* ASM:DEV_STATISTICS:TX_PAUSE_CNT */ 1871 #define ASM_TX_PAUSE_CNT(g) __REG(TARGET_ASM,\ 1872 0, 1, 0, g, 65, 512, 100, 0, 1, 4) 1873 1874 /* ASM:DEV_STATISTICS:TX_OK_BYTES_CNT */ 1875 #define ASM_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ 1876 0, 1, 0, g, 65, 512, 104, 0, 1, 4) 1877 1878 /* ASM:DEV_STATISTICS:TX_UC_CNT */ 1879 #define ASM_TX_UC_CNT(g) __REG(TARGET_ASM,\ 1880 0, 1, 0, g, 65, 512, 108, 0, 1, 4) 1881 1882 /* ASM:DEV_STATISTICS:TX_MC_CNT */ 1883 #define ASM_TX_MC_CNT(g) __REG(TARGET_ASM,\ 1884 0, 1, 0, g, 65, 512, 112, 0, 1, 4) 1885 1886 /* ASM:DEV_STATISTICS:TX_BC_CNT */ 1887 #define ASM_TX_BC_CNT(g) __REG(TARGET_ASM,\ 1888 0, 1, 0, g, 65, 512, 116, 0, 1, 4) 1889 1890 /* ASM:DEV_STATISTICS:TX_SIZE64_CNT */ 1891 #define ASM_TX_SIZE64_CNT(g) __REG(TARGET_ASM,\ 1892 0, 1, 0, g, 65, 512, 120, 0, 1, 4) 1893 1894 /* ASM:DEV_STATISTICS:TX_SIZE65TO127_CNT */ 1895 #define ASM_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ 1896 0, 1, 0, g, 65, 512, 124, 0, 1, 4) 1897 1898 /* ASM:DEV_STATISTICS:TX_SIZE128TO255_CNT */ 1899 #define ASM_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ 1900 0, 1, 0, g, 65, 512, 128, 0, 1, 4) 1901 1902 /* ASM:DEV_STATISTICS:TX_SIZE256TO511_CNT */ 1903 #define ASM_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ 1904 0, 1, 0, g, 65, 512, 132, 0, 1, 4) 1905 1906 /* ASM:DEV_STATISTICS:TX_SIZE512TO1023_CNT */ 1907 #define ASM_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ 1908 0, 1, 0, g, 65, 512, 136, 0, 1, 4) 1909 1910 /* ASM:DEV_STATISTICS:TX_SIZE1024TO1518_CNT */ 1911 #define ASM_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ 1912 0, 1, 0, g, 65, 512, 140, 0, 1, 4) 1913 1914 /* ASM:DEV_STATISTICS:TX_SIZE1519TOMAX_CNT */ 1915 #define ASM_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ 1916 0, 1, 0, g, 65, 512, 144, 0, 1, 4) 1917 1918 /* ASM:DEV_STATISTICS:RX_ALIGNMENT_LOST_CNT */ 1919 #define ASM_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM,\ 1920 0, 1, 0, g, 65, 512, 148, 0, 1, 4) 1921 1922 /* ASM:DEV_STATISTICS:RX_TAGGED_FRMS_CNT */ 1923 #define ASM_RX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ 1924 0, 1, 0, g, 65, 512, 152, 0, 1, 4) 1925 1926 /* ASM:DEV_STATISTICS:RX_UNTAGGED_FRMS_CNT */ 1927 #define ASM_RX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ 1928 0, 1, 0, g, 65, 512, 156, 0, 1, 4) 1929 1930 /* ASM:DEV_STATISTICS:TX_TAGGED_FRMS_CNT */ 1931 #define ASM_TX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ 1932 0, 1, 0, g, 65, 512, 160, 0, 1, 4) 1933 1934 /* ASM:DEV_STATISTICS:TX_UNTAGGED_FRMS_CNT */ 1935 #define ASM_TX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ 1936 0, 1, 0, g, 65, 512, 164, 0, 1, 4) 1937 1938 /* ASM:DEV_STATISTICS:PMAC_RX_SYMBOL_ERR_CNT */ 1939 #define ASM_PMAC_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM,\ 1940 0, 1, 0, g, 65, 512, 168, 0, 1, 4) 1941 1942 /* ASM:DEV_STATISTICS:PMAC_RX_PAUSE_CNT */ 1943 #define ASM_PMAC_RX_PAUSE_CNT(g) __REG(TARGET_ASM,\ 1944 0, 1, 0, g, 65, 512, 172, 0, 1, 4) 1945 1946 /* ASM:DEV_STATISTICS:PMAC_RX_UNSUP_OPCODE_CNT */ 1947 #define ASM_PMAC_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM,\ 1948 0, 1, 0, g, 65, 512, 176, 0, 1, 4) 1949 1950 /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_CNT */ 1951 #define ASM_PMAC_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ 1952 0, 1, 0, g, 65, 512, 180, 0, 1, 4) 1953 1954 /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_CNT */ 1955 #define ASM_PMAC_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM,\ 1956 0, 1, 0, g, 65, 512, 184, 0, 1, 4) 1957 1958 /* ASM:DEV_STATISTICS:PMAC_RX_UC_CNT */ 1959 #define ASM_PMAC_RX_UC_CNT(g) __REG(TARGET_ASM,\ 1960 0, 1, 0, g, 65, 512, 188, 0, 1, 4) 1961 1962 /* ASM:DEV_STATISTICS:PMAC_RX_MC_CNT */ 1963 #define ASM_PMAC_RX_MC_CNT(g) __REG(TARGET_ASM,\ 1964 0, 1, 0, g, 65, 512, 192, 0, 1, 4) 1965 1966 /* ASM:DEV_STATISTICS:PMAC_RX_BC_CNT */ 1967 #define ASM_PMAC_RX_BC_CNT(g) __REG(TARGET_ASM,\ 1968 0, 1, 0, g, 65, 512, 196, 0, 1, 4) 1969 1970 /* ASM:DEV_STATISTICS:PMAC_RX_CRC_ERR_CNT */ 1971 #define ASM_PMAC_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM,\ 1972 0, 1, 0, g, 65, 512, 200, 0, 1, 4) 1973 1974 /* ASM:DEV_STATISTICS:PMAC_RX_UNDERSIZE_CNT */ 1975 #define ASM_PMAC_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM,\ 1976 0, 1, 0, g, 65, 512, 204, 0, 1, 4) 1977 1978 /* ASM:DEV_STATISTICS:PMAC_RX_FRAGMENTS_CNT */ 1979 #define ASM_PMAC_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM,\ 1980 0, 1, 0, g, 65, 512, 208, 0, 1, 4) 1981 1982 /* ASM:DEV_STATISTICS:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ 1983 #define ASM_PMAC_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ 1984 0, 1, 0, g, 65, 512, 212, 0, 1, 4) 1985 1986 /* ASM:DEV_STATISTICS:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ 1987 #define ASM_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ 1988 0, 1, 0, g, 65, 512, 216, 0, 1, 4) 1989 1990 /* ASM:DEV_STATISTICS:PMAC_RX_OVERSIZE_CNT */ 1991 #define ASM_PMAC_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM,\ 1992 0, 1, 0, g, 65, 512, 220, 0, 1, 4) 1993 1994 /* ASM:DEV_STATISTICS:PMAC_RX_JABBERS_CNT */ 1995 #define ASM_PMAC_RX_JABBERS_CNT(g) __REG(TARGET_ASM,\ 1996 0, 1, 0, g, 65, 512, 224, 0, 1, 4) 1997 1998 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE64_CNT */ 1999 #define ASM_PMAC_RX_SIZE64_CNT(g) __REG(TARGET_ASM,\ 2000 0, 1, 0, g, 65, 512, 228, 0, 1, 4) 2001 2002 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE65TO127_CNT */ 2003 #define ASM_PMAC_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ 2004 0, 1, 0, g, 65, 512, 232, 0, 1, 4) 2005 2006 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE128TO255_CNT */ 2007 #define ASM_PMAC_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ 2008 0, 1, 0, g, 65, 512, 236, 0, 1, 4) 2009 2010 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE256TO511_CNT */ 2011 #define ASM_PMAC_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ 2012 0, 1, 0, g, 65, 512, 240, 0, 1, 4) 2013 2014 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE512TO1023_CNT */ 2015 #define ASM_PMAC_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ 2016 0, 1, 0, g, 65, 512, 244, 0, 1, 4) 2017 2018 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1024TO1518_CNT */ 2019 #define ASM_PMAC_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ 2020 0, 1, 0, g, 65, 512, 248, 0, 1, 4) 2021 2022 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1519TOMAX_CNT */ 2023 #define ASM_PMAC_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ 2024 0, 1, 0, g, 65, 512, 252, 0, 1, 4) 2025 2026 /* ASM:DEV_STATISTICS:PMAC_TX_PAUSE_CNT */ 2027 #define ASM_PMAC_TX_PAUSE_CNT(g) __REG(TARGET_ASM,\ 2028 0, 1, 0, g, 65, 512, 256, 0, 1, 4) 2029 2030 /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_CNT */ 2031 #define ASM_PMAC_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ 2032 0, 1, 0, g, 65, 512, 260, 0, 1, 4) 2033 2034 /* ASM:DEV_STATISTICS:PMAC_TX_UC_CNT */ 2035 #define ASM_PMAC_TX_UC_CNT(g) __REG(TARGET_ASM,\ 2036 0, 1, 0, g, 65, 512, 264, 0, 1, 4) 2037 2038 /* ASM:DEV_STATISTICS:PMAC_TX_MC_CNT */ 2039 #define ASM_PMAC_TX_MC_CNT(g) __REG(TARGET_ASM,\ 2040 0, 1, 0, g, 65, 512, 268, 0, 1, 4) 2041 2042 /* ASM:DEV_STATISTICS:PMAC_TX_BC_CNT */ 2043 #define ASM_PMAC_TX_BC_CNT(g) __REG(TARGET_ASM,\ 2044 0, 1, 0, g, 65, 512, 272, 0, 1, 4) 2045 2046 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE64_CNT */ 2047 #define ASM_PMAC_TX_SIZE64_CNT(g) __REG(TARGET_ASM,\ 2048 0, 1, 0, g, 65, 512, 276, 0, 1, 4) 2049 2050 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE65TO127_CNT */ 2051 #define ASM_PMAC_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ 2052 0, 1, 0, g, 65, 512, 280, 0, 1, 4) 2053 2054 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE128TO255_CNT */ 2055 #define ASM_PMAC_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ 2056 0, 1, 0, g, 65, 512, 284, 0, 1, 4) 2057 2058 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE256TO511_CNT */ 2059 #define ASM_PMAC_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ 2060 0, 1, 0, g, 65, 512, 288, 0, 1, 4) 2061 2062 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE512TO1023_CNT */ 2063 #define ASM_PMAC_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ 2064 0, 1, 0, g, 65, 512, 292, 0, 1, 4) 2065 2066 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1024TO1518_CNT */ 2067 #define ASM_PMAC_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ 2068 0, 1, 0, g, 65, 512, 296, 0, 1, 4) 2069 2070 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1519TOMAX_CNT */ 2071 #define ASM_PMAC_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ 2072 0, 1, 0, g, 65, 512, 300, 0, 1, 4) 2073 2074 /* ASM:DEV_STATISTICS:PMAC_RX_ALIGNMENT_LOST_CNT */ 2075 #define ASM_PMAC_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM,\ 2076 0, 1, 0, g, 65, 512, 304, 0, 1, 4) 2077 2078 /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_ERR_CNT */ 2079 #define ASM_MM_RX_ASSEMBLY_ERR_CNT(g) __REG(TARGET_ASM,\ 2080 0, 1, 0, g, 65, 512, 308, 0, 1, 4) 2081 2082 /* ASM:DEV_STATISTICS:MM_RX_SMD_ERR_CNT */ 2083 #define ASM_MM_RX_SMD_ERR_CNT(g) __REG(TARGET_ASM,\ 2084 0, 1, 0, g, 65, 512, 312, 0, 1, 4) 2085 2086 /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_OK_CNT */ 2087 #define ASM_MM_RX_ASSEMBLY_OK_CNT(g) __REG(TARGET_ASM,\ 2088 0, 1, 0, g, 65, 512, 316, 0, 1, 4) 2089 2090 /* ASM:DEV_STATISTICS:MM_RX_MERGE_FRAG_CNT */ 2091 #define ASM_MM_RX_MERGE_FRAG_CNT(g) __REG(TARGET_ASM,\ 2092 0, 1, 0, g, 65, 512, 320, 0, 1, 4) 2093 2094 /* ASM:DEV_STATISTICS:MM_TX_PFRAGMENT_CNT */ 2095 #define ASM_MM_TX_PFRAGMENT_CNT(g) __REG(TARGET_ASM,\ 2096 0, 1, 0, g, 65, 512, 324, 0, 1, 4) 2097 2098 /* ASM:DEV_STATISTICS:TX_MULTI_COLL_CNT */ 2099 #define ASM_TX_MULTI_COLL_CNT(g) __REG(TARGET_ASM,\ 2100 0, 1, 0, g, 65, 512, 328, 0, 1, 4) 2101 2102 /* ASM:DEV_STATISTICS:TX_LATE_COLL_CNT */ 2103 #define ASM_TX_LATE_COLL_CNT(g) __REG(TARGET_ASM,\ 2104 0, 1, 0, g, 65, 512, 332, 0, 1, 4) 2105 2106 /* ASM:DEV_STATISTICS:TX_XCOLL_CNT */ 2107 #define ASM_TX_XCOLL_CNT(g) __REG(TARGET_ASM,\ 2108 0, 1, 0, g, 65, 512, 336, 0, 1, 4) 2109 2110 /* ASM:DEV_STATISTICS:TX_DEFER_CNT */ 2111 #define ASM_TX_DEFER_CNT(g) __REG(TARGET_ASM,\ 2112 0, 1, 0, g, 65, 512, 340, 0, 1, 4) 2113 2114 /* ASM:DEV_STATISTICS:TX_XDEFER_CNT */ 2115 #define ASM_TX_XDEFER_CNT(g) __REG(TARGET_ASM,\ 2116 0, 1, 0, g, 65, 512, 344, 0, 1, 4) 2117 2118 /* ASM:DEV_STATISTICS:TX_BACKOFF1_CNT */ 2119 #define ASM_TX_BACKOFF1_CNT(g) __REG(TARGET_ASM,\ 2120 0, 1, 0, g, 65, 512, 348, 0, 1, 4) 2121 2122 /* ASM:DEV_STATISTICS:TX_CSENSE_CNT */ 2123 #define ASM_TX_CSENSE_CNT(g) __REG(TARGET_ASM,\ 2124 0, 1, 0, g, 65, 512, 352, 0, 1, 4) 2125 2126 /* ASM:DEV_STATISTICS:RX_IN_BYTES_MSB_CNT */ 2127 #define ASM_RX_IN_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ 2128 0, 1, 0, g, 65, 512, 356, 0, 1, 4) 2129 2130 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(3, 0) 2131 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ 2132 FIELD_PREP(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 2133 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ 2134 FIELD_GET(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 2135 2136 /* ASM:DEV_STATISTICS:RX_OK_BYTES_MSB_CNT */ 2137 #define ASM_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ 2138 0, 1, 0, g, 65, 512, 360, 0, 1, 4) 2139 2140 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(3, 0) 2141 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ 2142 FIELD_PREP(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 2143 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ 2144 FIELD_GET(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 2145 2146 /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_MSB_CNT */ 2147 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ 2148 0, 1, 0, g, 65, 512, 364, 0, 1, 4) 2149 2150 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(3, 0) 2151 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ 2152 FIELD_PREP(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 2153 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ 2154 FIELD_GET(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 2155 2156 /* ASM:DEV_STATISTICS:RX_BAD_BYTES_MSB_CNT */ 2157 #define ASM_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ 2158 0, 1, 0, g, 65, 512, 368, 0, 1, 4) 2159 2160 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0) 2161 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ 2162 FIELD_PREP(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 2163 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ 2164 FIELD_GET(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 2165 2166 /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_MSB_CNT */ 2167 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ 2168 0, 1, 0, g, 65, 512, 372, 0, 1, 4) 2169 2170 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0) 2171 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ 2172 FIELD_PREP(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 2173 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ 2174 FIELD_GET(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 2175 2176 /* ASM:DEV_STATISTICS:TX_OUT_BYTES_MSB_CNT */ 2177 #define ASM_TX_OUT_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ 2178 0, 1, 0, g, 65, 512, 376, 0, 1, 4) 2179 2180 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(3, 0) 2181 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ 2182 FIELD_PREP(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 2183 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ 2184 FIELD_GET(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 2185 2186 /* ASM:DEV_STATISTICS:TX_OK_BYTES_MSB_CNT */ 2187 #define ASM_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ 2188 0, 1, 0, g, 65, 512, 380, 0, 1, 4) 2189 2190 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(3, 0) 2191 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ 2192 FIELD_PREP(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 2193 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ 2194 FIELD_GET(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 2195 2196 /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_MSB_CNT */ 2197 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ 2198 0, 1, 0, g, 65, 512, 384, 0, 1, 4) 2199 2200 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(3, 0) 2201 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ 2202 FIELD_PREP(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 2203 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ 2204 FIELD_GET(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 2205 2206 /* ASM:DEV_STATISTICS:RX_SYNC_LOST_ERR_CNT */ 2207 #define ASM_RX_SYNC_LOST_ERR_CNT(g) __REG(TARGET_ASM,\ 2208 0, 1, 0, g, 65, 512, 388, 0, 1, 4) 2209 2210 /* ASM:CFG:STAT_CFG */ 2211 #define ASM_STAT_CFG __REG(TARGET_ASM,\ 2212 0, 1, 33280, 0, 1, 1088, 0, 0, 1, 4) 2213 2214 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT BIT(0) 2215 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x)\ 2216 FIELD_PREP(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x) 2217 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x)\ 2218 FIELD_GET(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x) 2219 2220 /* ASM:CFG:PORT_CFG */ 2221 #define ASM_PORT_CFG(r) __REG(TARGET_ASM,\ 2222 0, 1, 33280, 0, 1, 1088, 540, r, 67, 4) 2223 2224 #define ASM_PORT_CFG_CSC_STAT_DIS BIT(12) 2225 #define ASM_PORT_CFG_CSC_STAT_DIS_SET(x)\ 2226 FIELD_PREP(ASM_PORT_CFG_CSC_STAT_DIS, x) 2227 #define ASM_PORT_CFG_CSC_STAT_DIS_GET(x)\ 2228 FIELD_GET(ASM_PORT_CFG_CSC_STAT_DIS, x) 2229 2230 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA BIT(11) 2231 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_SET(x)\ 2232 FIELD_PREP(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x) 2233 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_GET(x)\ 2234 FIELD_GET(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x) 2235 2236 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA BIT(10) 2237 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_SET(x)\ 2238 FIELD_PREP(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x) 2239 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_GET(x)\ 2240 FIELD_GET(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x) 2241 2242 #define ASM_PORT_CFG_NO_PREAMBLE_ENA BIT(9) 2243 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(x)\ 2244 FIELD_PREP(ASM_PORT_CFG_NO_PREAMBLE_ENA, x) 2245 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_GET(x)\ 2246 FIELD_GET(ASM_PORT_CFG_NO_PREAMBLE_ENA, x) 2247 2248 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA BIT(8) 2249 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_SET(x)\ 2250 FIELD_PREP(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x) 2251 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_GET(x)\ 2252 FIELD_GET(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x) 2253 2254 #define ASM_PORT_CFG_FRM_AGING_DIS BIT(7) 2255 #define ASM_PORT_CFG_FRM_AGING_DIS_SET(x)\ 2256 FIELD_PREP(ASM_PORT_CFG_FRM_AGING_DIS, x) 2257 #define ASM_PORT_CFG_FRM_AGING_DIS_GET(x)\ 2258 FIELD_GET(ASM_PORT_CFG_FRM_AGING_DIS, x) 2259 2260 #define ASM_PORT_CFG_PAD_ENA BIT(6) 2261 #define ASM_PORT_CFG_PAD_ENA_SET(x)\ 2262 FIELD_PREP(ASM_PORT_CFG_PAD_ENA, x) 2263 #define ASM_PORT_CFG_PAD_ENA_GET(x)\ 2264 FIELD_GET(ASM_PORT_CFG_PAD_ENA, x) 2265 2266 #define ASM_PORT_CFG_INJ_DISCARD_CFG GENMASK(5, 4) 2267 #define ASM_PORT_CFG_INJ_DISCARD_CFG_SET(x)\ 2268 FIELD_PREP(ASM_PORT_CFG_INJ_DISCARD_CFG, x) 2269 #define ASM_PORT_CFG_INJ_DISCARD_CFG_GET(x)\ 2270 FIELD_GET(ASM_PORT_CFG_INJ_DISCARD_CFG, x) 2271 2272 #define ASM_PORT_CFG_INJ_FORMAT_CFG GENMASK(3, 2) 2273 #define ASM_PORT_CFG_INJ_FORMAT_CFG_SET(x)\ 2274 FIELD_PREP(ASM_PORT_CFG_INJ_FORMAT_CFG, x) 2275 #define ASM_PORT_CFG_INJ_FORMAT_CFG_GET(x)\ 2276 FIELD_GET(ASM_PORT_CFG_INJ_FORMAT_CFG, x) 2277 2278 #define ASM_PORT_CFG_VSTAX2_AWR_ENA BIT(1) 2279 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_SET(x)\ 2280 FIELD_PREP(ASM_PORT_CFG_VSTAX2_AWR_ENA, x) 2281 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_GET(x)\ 2282 FIELD_GET(ASM_PORT_CFG_VSTAX2_AWR_ENA, x) 2283 2284 #define ASM_PORT_CFG_PFRM_FLUSH BIT(0) 2285 #define ASM_PORT_CFG_PFRM_FLUSH_SET(x)\ 2286 FIELD_PREP(ASM_PORT_CFG_PFRM_FLUSH, x) 2287 #define ASM_PORT_CFG_PFRM_FLUSH_GET(x)\ 2288 FIELD_GET(ASM_PORT_CFG_PFRM_FLUSH, x) 2289 2290 /* ASM:RAM_CTRL:RAM_INIT */ 2291 #define ASM_RAM_INIT __REG(TARGET_ASM,\ 2292 0, 1, 34832, 0, 1, 4, 0, 0, 1, 4) 2293 2294 #define ASM_RAM_INIT_RAM_INIT BIT(1) 2295 #define ASM_RAM_INIT_RAM_INIT_SET(x)\ 2296 FIELD_PREP(ASM_RAM_INIT_RAM_INIT, x) 2297 #define ASM_RAM_INIT_RAM_INIT_GET(x)\ 2298 FIELD_GET(ASM_RAM_INIT_RAM_INIT, x) 2299 2300 #define ASM_RAM_INIT_RAM_CFG_HOOK BIT(0) 2301 #define ASM_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 2302 FIELD_PREP(ASM_RAM_INIT_RAM_CFG_HOOK, x) 2303 #define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 2304 FIELD_GET(ASM_RAM_INIT_RAM_CFG_HOOK, x) 2305 2306 /* CLKGEN:LCPLL1:LCPLL1_CORE_CLK_CFG */ 2307 #define CLKGEN_LCPLL1_CORE_CLK_CFG __REG(TARGET_CLKGEN,\ 2308 0, 1, 12, 0, 1, 36, 0, 0, 1, 4) 2309 2310 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV GENMASK(7, 0) 2311 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x)\ 2312 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x) 2313 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_GET(x)\ 2314 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x) 2315 2316 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV GENMASK(10, 8) 2317 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(x)\ 2318 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x) 2319 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_GET(x)\ 2320 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x) 2321 2322 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR BIT(11) 2323 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(x)\ 2324 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x) 2325 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_GET(x)\ 2326 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x) 2327 2328 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL GENMASK(13, 12) 2329 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(x)\ 2330 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x) 2331 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_GET(x)\ 2332 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x) 2333 2334 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA BIT(14) 2335 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(x)\ 2336 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x) 2337 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_GET(x)\ 2338 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x) 2339 2340 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA BIT(15) 2341 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(x)\ 2342 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x) 2343 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x)\ 2344 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x) 2345 2346 /* CPU:CPU_REGS:PROC_CTRL */ 2347 #define CPU_PROC_CTRL __REG(TARGET_CPU,\ 2348 0, 1, 0, 0, 1, 204, 176, 0, 1, 4) 2349 2350 #define CPU_PROC_CTRL_AARCH64_MODE_ENA BIT(12) 2351 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x)\ 2352 FIELD_PREP(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) 2353 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x)\ 2354 FIELD_GET(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) 2355 2356 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS BIT(11) 2357 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x)\ 2358 FIELD_PREP(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) 2359 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x)\ 2360 FIELD_GET(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) 2361 2362 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS BIT(10) 2363 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x)\ 2364 FIELD_PREP(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) 2365 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x)\ 2366 FIELD_GET(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) 2367 2368 #define CPU_PROC_CTRL_BE_EXCEP_MODE BIT(9) 2369 #define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x)\ 2370 FIELD_PREP(CPU_PROC_CTRL_BE_EXCEP_MODE, x) 2371 #define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x)\ 2372 FIELD_GET(CPU_PROC_CTRL_BE_EXCEP_MODE, x) 2373 2374 #define CPU_PROC_CTRL_VINITHI BIT(8) 2375 #define CPU_PROC_CTRL_VINITHI_SET(x)\ 2376 FIELD_PREP(CPU_PROC_CTRL_VINITHI, x) 2377 #define CPU_PROC_CTRL_VINITHI_GET(x)\ 2378 FIELD_GET(CPU_PROC_CTRL_VINITHI, x) 2379 2380 #define CPU_PROC_CTRL_CFGTE BIT(7) 2381 #define CPU_PROC_CTRL_CFGTE_SET(x)\ 2382 FIELD_PREP(CPU_PROC_CTRL_CFGTE, x) 2383 #define CPU_PROC_CTRL_CFGTE_GET(x)\ 2384 FIELD_GET(CPU_PROC_CTRL_CFGTE, x) 2385 2386 #define CPU_PROC_CTRL_CP15S_DISABLE BIT(6) 2387 #define CPU_PROC_CTRL_CP15S_DISABLE_SET(x)\ 2388 FIELD_PREP(CPU_PROC_CTRL_CP15S_DISABLE, x) 2389 #define CPU_PROC_CTRL_CP15S_DISABLE_GET(x)\ 2390 FIELD_GET(CPU_PROC_CTRL_CP15S_DISABLE, x) 2391 2392 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE BIT(5) 2393 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x)\ 2394 FIELD_PREP(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) 2395 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x)\ 2396 FIELD_GET(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) 2397 2398 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA BIT(4) 2399 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x)\ 2400 FIELD_PREP(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x) 2401 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x)\ 2402 FIELD_GET(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x) 2403 2404 #define CPU_PROC_CTRL_ACP_AWCACHE BIT(3) 2405 #define CPU_PROC_CTRL_ACP_AWCACHE_SET(x)\ 2406 FIELD_PREP(CPU_PROC_CTRL_ACP_AWCACHE, x) 2407 #define CPU_PROC_CTRL_ACP_AWCACHE_GET(x)\ 2408 FIELD_GET(CPU_PROC_CTRL_ACP_AWCACHE, x) 2409 2410 #define CPU_PROC_CTRL_ACP_ARCACHE BIT(2) 2411 #define CPU_PROC_CTRL_ACP_ARCACHE_SET(x)\ 2412 FIELD_PREP(CPU_PROC_CTRL_ACP_ARCACHE, x) 2413 #define CPU_PROC_CTRL_ACP_ARCACHE_GET(x)\ 2414 FIELD_GET(CPU_PROC_CTRL_ACP_ARCACHE, x) 2415 2416 #define CPU_PROC_CTRL_L2_FLUSH_REQ BIT(1) 2417 #define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x)\ 2418 FIELD_PREP(CPU_PROC_CTRL_L2_FLUSH_REQ, x) 2419 #define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x)\ 2420 FIELD_GET(CPU_PROC_CTRL_L2_FLUSH_REQ, x) 2421 2422 #define CPU_PROC_CTRL_ACP_DISABLE BIT(0) 2423 #define CPU_PROC_CTRL_ACP_DISABLE_SET(x)\ 2424 FIELD_PREP(CPU_PROC_CTRL_ACP_DISABLE, x) 2425 #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\ 2426 FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x) 2427 2428 /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ 2429 #define DEV10G_MAC_ENA_CFG(t) __REG(TARGET_DEV10G,\ 2430 t, 12, 0, 0, 1, 60, 0, 0, 1, 4) 2431 2432 #define DEV10G_MAC_ENA_CFG_RX_ENA BIT(4) 2433 #define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x)\ 2434 FIELD_PREP(DEV10G_MAC_ENA_CFG_RX_ENA, x) 2435 #define DEV10G_MAC_ENA_CFG_RX_ENA_GET(x)\ 2436 FIELD_GET(DEV10G_MAC_ENA_CFG_RX_ENA, x) 2437 2438 #define DEV10G_MAC_ENA_CFG_TX_ENA BIT(0) 2439 #define DEV10G_MAC_ENA_CFG_TX_ENA_SET(x)\ 2440 FIELD_PREP(DEV10G_MAC_ENA_CFG_TX_ENA, x) 2441 #define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x)\ 2442 FIELD_GET(DEV10G_MAC_ENA_CFG_TX_ENA, x) 2443 2444 /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 2445 #define DEV10G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV10G,\ 2446 t, 12, 0, 0, 1, 60, 8, 0, 1, 4) 2447 2448 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) 2449 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ 2450 FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 2451 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ 2452 FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 2453 2454 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 2455 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 2456 FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x) 2457 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 2458 FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x) 2459 2460 /* DEV10G:MAC_CFG_STATUS:MAC_NUM_TAGS_CFG */ 2461 #define DEV10G_MAC_NUM_TAGS_CFG(t) __REG(TARGET_DEV10G,\ 2462 t, 12, 0, 0, 1, 60, 12, 0, 1, 4) 2463 2464 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS GENMASK(1, 0) 2465 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x)\ 2466 FIELD_PREP(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x) 2467 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x)\ 2468 FIELD_GET(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x) 2469 2470 /* DEV10G:MAC_CFG_STATUS:MAC_TAGS_CFG */ 2471 #define DEV10G_MAC_TAGS_CFG(t, r) __REG(TARGET_DEV10G,\ 2472 t, 12, 0, 0, 1, 60, 16, r, 3, 4) 2473 2474 #define DEV10G_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) 2475 #define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x)\ 2476 FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ID, x) 2477 #define DEV10G_MAC_TAGS_CFG_TAG_ID_GET(x)\ 2478 FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ID, x) 2479 2480 #define DEV10G_MAC_TAGS_CFG_TAG_ENA BIT(4) 2481 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_SET(x)\ 2482 FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ENA, x) 2483 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x)\ 2484 FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ENA, x) 2485 2486 /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 2487 #define DEV10G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV10G,\ 2488 t, 12, 0, 0, 1, 60, 28, 0, 1, 4) 2489 2490 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) 2491 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ 2492 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 2493 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ 2494 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 2495 2496 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20) 2497 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ 2498 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 2499 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ 2500 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 2501 2502 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16) 2503 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ 2504 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 2505 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ 2506 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 2507 2508 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12) 2509 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ 2510 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 2511 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ 2512 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 2513 2514 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8) 2515 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ 2516 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 2517 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ 2518 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 2519 2520 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4) 2521 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ 2522 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 2523 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ 2524 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 2525 2526 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0) 2527 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ 2528 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 2529 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ 2530 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 2531 2532 /* DEV10G:MAC_CFG_STATUS:MAC_TX_MONITOR_STICKY */ 2533 #define DEV10G_MAC_TX_MONITOR_STICKY(t) __REG(TARGET_DEV10G,\ 2534 t, 12, 0, 0, 1, 60, 48, 0, 1, 4) 2535 2536 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY BIT(4) 2537 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x)\ 2538 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x) 2539 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_GET(x)\ 2540 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x) 2541 2542 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY BIT(3) 2543 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_SET(x)\ 2544 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x) 2545 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_GET(x)\ 2546 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x) 2547 2548 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY BIT(2) 2549 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_SET(x)\ 2550 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x) 2551 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_GET(x)\ 2552 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x) 2553 2554 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY BIT(1) 2555 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_SET(x)\ 2556 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x) 2557 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_GET(x)\ 2558 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x) 2559 2560 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY BIT(0) 2561 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_SET(x)\ 2562 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x) 2563 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x)\ 2564 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x) 2565 2566 /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ 2567 #define DEV10G_DEV_RST_CTRL(t) __REG(TARGET_DEV10G,\ 2568 t, 12, 436, 0, 1, 52, 0, 0, 1, 4) 2569 2570 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) 2571 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ 2572 FIELD_PREP(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 2573 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ 2574 FIELD_GET(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 2575 2576 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27) 2577 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ 2578 FIELD_PREP(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 2579 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ 2580 FIELD_GET(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 2581 2582 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25) 2583 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ 2584 FIELD_PREP(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 2585 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ 2586 FIELD_GET(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 2587 2588 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23) 2589 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ 2590 FIELD_PREP(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 2591 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ 2592 FIELD_GET(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 2593 2594 #define DEV10G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) 2595 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ 2596 FIELD_PREP(DEV10G_DEV_RST_CTRL_SPEED_SEL, x) 2597 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ 2598 FIELD_GET(DEV10G_DEV_RST_CTRL_SPEED_SEL, x) 2599 2600 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST BIT(12) 2601 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ 2602 FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x) 2603 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ 2604 FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x) 2605 2606 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST BIT(8) 2607 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ 2608 FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x) 2609 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ 2610 FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x) 2611 2612 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST BIT(4) 2613 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ 2614 FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x) 2615 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ 2616 FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x) 2617 2618 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST BIT(0) 2619 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ 2620 FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x) 2621 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 2622 FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x) 2623 2624 /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ 2625 #define DEV10G_PCS25G_CFG(t) __REG(TARGET_DEV10G,\ 2626 t, 12, 488, 0, 1, 32, 0, 0, 1, 4) 2627 2628 #define DEV10G_PCS25G_CFG_PCS25G_ENA BIT(0) 2629 #define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x)\ 2630 FIELD_PREP(DEV10G_PCS25G_CFG_PCS25G_ENA, x) 2631 #define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x)\ 2632 FIELD_GET(DEV10G_PCS25G_CFG_PCS25G_ENA, x) 2633 2634 /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ 2635 #define DEV25G_MAC_ENA_CFG(t) __REG(TARGET_DEV25G,\ 2636 t, 8, 0, 0, 1, 60, 0, 0, 1, 4) 2637 2638 #define DEV25G_MAC_ENA_CFG_RX_ENA BIT(4) 2639 #define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x)\ 2640 FIELD_PREP(DEV25G_MAC_ENA_CFG_RX_ENA, x) 2641 #define DEV25G_MAC_ENA_CFG_RX_ENA_GET(x)\ 2642 FIELD_GET(DEV25G_MAC_ENA_CFG_RX_ENA, x) 2643 2644 #define DEV25G_MAC_ENA_CFG_TX_ENA BIT(0) 2645 #define DEV25G_MAC_ENA_CFG_TX_ENA_SET(x)\ 2646 FIELD_PREP(DEV25G_MAC_ENA_CFG_TX_ENA, x) 2647 #define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x)\ 2648 FIELD_GET(DEV25G_MAC_ENA_CFG_TX_ENA, x) 2649 2650 /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 2651 #define DEV25G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV25G,\ 2652 t, 8, 0, 0, 1, 60, 8, 0, 1, 4) 2653 2654 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) 2655 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ 2656 FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 2657 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ 2658 FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 2659 2660 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 2661 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 2662 FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x) 2663 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 2664 FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x) 2665 2666 /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 2667 #define DEV25G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV25G,\ 2668 t, 8, 0, 0, 1, 60, 28, 0, 1, 4) 2669 2670 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) 2671 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ 2672 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 2673 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ 2674 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 2675 2676 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20) 2677 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ 2678 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 2679 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ 2680 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 2681 2682 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16) 2683 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ 2684 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 2685 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ 2686 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 2687 2688 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12) 2689 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ 2690 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 2691 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ 2692 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 2693 2694 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8) 2695 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ 2696 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 2697 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ 2698 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 2699 2700 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4) 2701 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ 2702 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 2703 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ 2704 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 2705 2706 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0) 2707 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ 2708 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 2709 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ 2710 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 2711 2712 /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ 2713 #define DEV25G_DEV_RST_CTRL(t) __REG(TARGET_DEV25G,\ 2714 t, 8, 436, 0, 1, 52, 0, 0, 1, 4) 2715 2716 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) 2717 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ 2718 FIELD_PREP(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 2719 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ 2720 FIELD_GET(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 2721 2722 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27) 2723 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ 2724 FIELD_PREP(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 2725 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ 2726 FIELD_GET(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 2727 2728 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25) 2729 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ 2730 FIELD_PREP(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 2731 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ 2732 FIELD_GET(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 2733 2734 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23) 2735 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ 2736 FIELD_PREP(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 2737 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ 2738 FIELD_GET(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 2739 2740 #define DEV25G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) 2741 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ 2742 FIELD_PREP(DEV25G_DEV_RST_CTRL_SPEED_SEL, x) 2743 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ 2744 FIELD_GET(DEV25G_DEV_RST_CTRL_SPEED_SEL, x) 2745 2746 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST BIT(12) 2747 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ 2748 FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x) 2749 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ 2750 FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x) 2751 2752 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST BIT(8) 2753 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ 2754 FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x) 2755 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ 2756 FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x) 2757 2758 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST BIT(4) 2759 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ 2760 FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x) 2761 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ 2762 FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x) 2763 2764 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST BIT(0) 2765 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ 2766 FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x) 2767 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 2768 FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x) 2769 2770 /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ 2771 #define DEV25G_PCS25G_CFG(t) __REG(TARGET_DEV25G,\ 2772 t, 8, 488, 0, 1, 32, 0, 0, 1, 4) 2773 2774 #define DEV25G_PCS25G_CFG_PCS25G_ENA BIT(0) 2775 #define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x)\ 2776 FIELD_PREP(DEV25G_PCS25G_CFG_PCS25G_ENA, x) 2777 #define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x)\ 2778 FIELD_GET(DEV25G_PCS25G_CFG_PCS25G_ENA, x) 2779 2780 /* DEV10G:PCS25G_CFG_STATUS:PCS25G_SD_CFG */ 2781 #define DEV25G_PCS25G_SD_CFG(t) __REG(TARGET_DEV25G,\ 2782 t, 8, 488, 0, 1, 32, 4, 0, 1, 4) 2783 2784 #define DEV25G_PCS25G_SD_CFG_SD_SEL BIT(8) 2785 #define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x)\ 2786 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_SEL, x) 2787 #define DEV25G_PCS25G_SD_CFG_SD_SEL_GET(x)\ 2788 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_SEL, x) 2789 2790 #define DEV25G_PCS25G_SD_CFG_SD_POL BIT(4) 2791 #define DEV25G_PCS25G_SD_CFG_SD_POL_SET(x)\ 2792 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_POL, x) 2793 #define DEV25G_PCS25G_SD_CFG_SD_POL_GET(x)\ 2794 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_POL, x) 2795 2796 #define DEV25G_PCS25G_SD_CFG_SD_ENA BIT(0) 2797 #define DEV25G_PCS25G_SD_CFG_SD_ENA_SET(x)\ 2798 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_ENA, x) 2799 #define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x)\ 2800 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_ENA, x) 2801 2802 /* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */ 2803 #define DEV2G5_DEV_RST_CTRL(t) __REG(TARGET_DEV2G5,\ 2804 t, 65, 0, 0, 1, 36, 0, 0, 1, 4) 2805 2806 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(23) 2807 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ 2808 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 2809 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ 2810 FIELD_GET(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 2811 2812 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) 2813 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(x)\ 2814 FIELD_PREP(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x) 2815 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_GET(x)\ 2816 FIELD_GET(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x) 2817 2818 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST BIT(17) 2819 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(x)\ 2820 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x) 2821 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_GET(x)\ 2822 FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x) 2823 2824 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST BIT(16) 2825 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(x)\ 2826 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x) 2827 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_GET(x)\ 2828 FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x) 2829 2830 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST BIT(12) 2831 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ 2832 FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x) 2833 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ 2834 FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x) 2835 2836 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST BIT(8) 2837 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ 2838 FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x) 2839 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ 2840 FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x) 2841 2842 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST BIT(4) 2843 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ 2844 FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x) 2845 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ 2846 FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x) 2847 2848 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST BIT(0) 2849 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ 2850 FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x) 2851 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 2852 FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x) 2853 2854 /* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */ 2855 #define DEV2G5_MAC_ENA_CFG(t) __REG(TARGET_DEV2G5,\ 2856 t, 65, 52, 0, 1, 36, 0, 0, 1, 4) 2857 2858 #define DEV2G5_MAC_ENA_CFG_RX_ENA BIT(4) 2859 #define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x)\ 2860 FIELD_PREP(DEV2G5_MAC_ENA_CFG_RX_ENA, x) 2861 #define DEV2G5_MAC_ENA_CFG_RX_ENA_GET(x)\ 2862 FIELD_GET(DEV2G5_MAC_ENA_CFG_RX_ENA, x) 2863 2864 #define DEV2G5_MAC_ENA_CFG_TX_ENA BIT(0) 2865 #define DEV2G5_MAC_ENA_CFG_TX_ENA_SET(x)\ 2866 FIELD_PREP(DEV2G5_MAC_ENA_CFG_TX_ENA, x) 2867 #define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x)\ 2868 FIELD_GET(DEV2G5_MAC_ENA_CFG_TX_ENA, x) 2869 2870 /* DEV1G:MAC_CFG_STATUS:MAC_MODE_CFG */ 2871 #define DEV2G5_MAC_MODE_CFG(t) __REG(TARGET_DEV2G5,\ 2872 t, 65, 52, 0, 1, 36, 4, 0, 1, 4) 2873 2874 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8) 2875 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x)\ 2876 FIELD_PREP(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x) 2877 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_GET(x)\ 2878 FIELD_GET(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x) 2879 2880 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4) 2881 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\ 2882 FIELD_PREP(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x) 2883 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\ 2884 FIELD_GET(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x) 2885 2886 #define DEV2G5_MAC_MODE_CFG_FDX_ENA BIT(0) 2887 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_SET(x)\ 2888 FIELD_PREP(DEV2G5_MAC_MODE_CFG_FDX_ENA, x) 2889 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x)\ 2890 FIELD_GET(DEV2G5_MAC_MODE_CFG_FDX_ENA, x) 2891 2892 /* DEV1G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 2893 #define DEV2G5_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV2G5,\ 2894 t, 65, 52, 0, 1, 36, 8, 0, 1, 4) 2895 2896 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 2897 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 2898 FIELD_PREP(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x) 2899 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 2900 FIELD_GET(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x) 2901 2902 /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */ 2903 #define DEV2G5_MAC_TAGS_CFG(t) __REG(TARGET_DEV2G5,\ 2904 t, 65, 52, 0, 1, 36, 12, 0, 1, 4) 2905 2906 #define DEV2G5_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) 2907 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x)\ 2908 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_TAG_ID, x) 2909 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_GET(x)\ 2910 FIELD_GET(DEV2G5_MAC_TAGS_CFG_TAG_ID, x) 2911 2912 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(3) 2913 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\ 2914 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x) 2915 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\ 2916 FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x) 2917 2918 #define DEV2G5_MAC_TAGS_CFG_PB_ENA GENMASK(2, 1) 2919 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_SET(x)\ 2920 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_PB_ENA, x) 2921 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_GET(x)\ 2922 FIELD_GET(DEV2G5_MAC_TAGS_CFG_PB_ENA, x) 2923 2924 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0) 2925 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\ 2926 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x) 2927 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\ 2928 FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x) 2929 2930 /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG2 */ 2931 #define DEV2G5_MAC_TAGS_CFG2(t) __REG(TARGET_DEV2G5,\ 2932 t, 65, 52, 0, 1, 36, 16, 0, 1, 4) 2933 2934 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3 GENMASK(31, 16) 2935 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x)\ 2936 FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x) 2937 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_GET(x)\ 2938 FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x) 2939 2940 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2 GENMASK(15, 0) 2941 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_SET(x)\ 2942 FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x) 2943 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x)\ 2944 FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x) 2945 2946 /* DEV1G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 2947 #define DEV2G5_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV2G5,\ 2948 t, 65, 52, 0, 1, 36, 20, 0, 1, 4) 2949 2950 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0) 2951 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x)\ 2952 FIELD_PREP(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x) 2953 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x)\ 2954 FIELD_GET(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x) 2955 2956 /* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */ 2957 #define DEV2G5_MAC_IFG_CFG(t) __REG(TARGET_DEV2G5,\ 2958 t, 65, 52, 0, 1, 36, 24, 0, 1, 4) 2959 2960 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17) 2961 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x)\ 2962 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x) 2963 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_GET(x)\ 2964 FIELD_GET(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x) 2965 2966 #define DEV2G5_MAC_IFG_CFG_TX_IFG GENMASK(12, 8) 2967 #define DEV2G5_MAC_IFG_CFG_TX_IFG_SET(x)\ 2968 FIELD_PREP(DEV2G5_MAC_IFG_CFG_TX_IFG, x) 2969 #define DEV2G5_MAC_IFG_CFG_TX_IFG_GET(x)\ 2970 FIELD_GET(DEV2G5_MAC_IFG_CFG_TX_IFG, x) 2971 2972 #define DEV2G5_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4) 2973 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(x)\ 2974 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG2, x) 2975 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_GET(x)\ 2976 FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG2, x) 2977 2978 #define DEV2G5_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0) 2979 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(x)\ 2980 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG1, x) 2981 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x)\ 2982 FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG1, x) 2983 2984 /* DEV1G:MAC_CFG_STATUS:MAC_HDX_CFG */ 2985 #define DEV2G5_MAC_HDX_CFG(t) __REG(TARGET_DEV2G5,\ 2986 t, 65, 52, 0, 1, 36, 28, 0, 1, 4) 2987 2988 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26) 2989 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x)\ 2990 FIELD_PREP(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x) 2991 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_GET(x)\ 2992 FIELD_GET(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x) 2993 2994 #define DEV2G5_MAC_HDX_CFG_SEED GENMASK(23, 16) 2995 #define DEV2G5_MAC_HDX_CFG_SEED_SET(x)\ 2996 FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED, x) 2997 #define DEV2G5_MAC_HDX_CFG_SEED_GET(x)\ 2998 FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED, x) 2999 3000 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD BIT(12) 3001 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_SET(x)\ 3002 FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x) 3003 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_GET(x)\ 3004 FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x) 3005 3006 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8) 3007 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_SET(x)\ 3008 FIELD_PREP(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x) 3009 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_GET(x)\ 3010 FIELD_GET(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x) 3011 3012 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS GENMASK(6, 0) 3013 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_SET(x)\ 3014 FIELD_PREP(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x) 3015 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x)\ 3016 FIELD_GET(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x) 3017 3018 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_CFG */ 3019 #define DEV2G5_PCS1G_CFG(t) __REG(TARGET_DEV2G5,\ 3020 t, 65, 88, 0, 1, 68, 0, 0, 1, 4) 3021 3022 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE BIT(4) 3023 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x)\ 3024 FIELD_PREP(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x) 3025 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_GET(x)\ 3026 FIELD_GET(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x) 3027 3028 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1) 3029 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_SET(x)\ 3030 FIELD_PREP(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x) 3031 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_GET(x)\ 3032 FIELD_GET(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x) 3033 3034 #define DEV2G5_PCS1G_CFG_PCS_ENA BIT(0) 3035 #define DEV2G5_PCS1G_CFG_PCS_ENA_SET(x)\ 3036 FIELD_PREP(DEV2G5_PCS1G_CFG_PCS_ENA, x) 3037 #define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x)\ 3038 FIELD_GET(DEV2G5_PCS1G_CFG_PCS_ENA, x) 3039 3040 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ 3041 #define DEV2G5_PCS1G_MODE_CFG(t) __REG(TARGET_DEV2G5,\ 3042 t, 65, 88, 0, 1, 68, 4, 0, 1, 4) 3043 3044 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4) 3045 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x)\ 3046 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x) 3047 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_GET(x)\ 3048 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x) 3049 3050 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA BIT(1) 3051 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\ 3052 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) 3053 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\ 3054 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) 3055 3056 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0) 3057 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\ 3058 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 3059 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ 3060 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 3061 3062 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ 3063 #define DEV2G5_PCS1G_SD_CFG(t) __REG(TARGET_DEV2G5,\ 3064 t, 65, 88, 0, 1, 68, 8, 0, 1, 4) 3065 3066 #define DEV2G5_PCS1G_SD_CFG_SD_SEL BIT(8) 3067 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x)\ 3068 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_SEL, x) 3069 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_GET(x)\ 3070 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_SEL, x) 3071 3072 #define DEV2G5_PCS1G_SD_CFG_SD_POL BIT(4) 3073 #define DEV2G5_PCS1G_SD_CFG_SD_POL_SET(x)\ 3074 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_POL, x) 3075 #define DEV2G5_PCS1G_SD_CFG_SD_POL_GET(x)\ 3076 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_POL, x) 3077 3078 #define DEV2G5_PCS1G_SD_CFG_SD_ENA BIT(0) 3079 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(x)\ 3080 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_ENA, x) 3081 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x)\ 3082 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_ENA, x) 3083 3084 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ 3085 #define DEV2G5_PCS1G_ANEG_CFG(t) __REG(TARGET_DEV2G5,\ 3086 t, 65, 88, 0, 1, 68, 12, 0, 1, 4) 3087 3088 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16) 3089 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\ 3090 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x) 3091 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\ 3092 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x) 3093 3094 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8) 3095 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\ 3096 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 3097 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\ 3098 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 3099 3100 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1) 3101 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(x)\ 3102 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x) 3103 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_GET(x)\ 3104 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x) 3105 3106 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA BIT(0) 3107 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(x)\ 3108 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x) 3109 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x)\ 3110 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x) 3111 3112 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LB_CFG */ 3113 #define DEV2G5_PCS1G_LB_CFG(t) __REG(TARGET_DEV2G5,\ 3114 t, 65, 88, 0, 1, 68, 20, 0, 1, 4) 3115 3116 #define DEV2G5_PCS1G_LB_CFG_RA_ENA BIT(4) 3117 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x)\ 3118 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_RA_ENA, x) 3119 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_GET(x)\ 3120 FIELD_GET(DEV2G5_PCS1G_LB_CFG_RA_ENA, x) 3121 3122 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA BIT(1) 3123 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_SET(x)\ 3124 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x) 3125 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_GET(x)\ 3126 FIELD_GET(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x) 3127 3128 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA BIT(0) 3129 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_SET(x)\ 3130 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x) 3131 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x)\ 3132 FIELD_GET(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x) 3133 3134 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ 3135 #define DEV2G5_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV2G5,\ 3136 t, 65, 88, 0, 1, 68, 32, 0, 1, 4) 3137 3138 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY GENMASK(31, 16) 3139 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x)\ 3140 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x) 3141 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_GET(x)\ 3142 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x) 3143 3144 #define DEV2G5_PCS1G_ANEG_STATUS_PR BIT(4) 3145 #define DEV2G5_PCS1G_ANEG_STATUS_PR_SET(x)\ 3146 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PR, x) 3147 #define DEV2G5_PCS1G_ANEG_STATUS_PR_GET(x)\ 3148 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PR, x) 3149 3150 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY BIT(3) 3151 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_SET(x)\ 3152 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x) 3153 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_GET(x)\ 3154 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x) 3155 3156 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0) 3157 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\ 3158 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 3159 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\ 3160 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 3161 3162 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ 3163 #define DEV2G5_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV2G5,\ 3164 t, 65, 88, 0, 1, 68, 40, 0, 1, 4) 3165 3166 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR GENMASK(15, 12) 3167 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x)\ 3168 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x) 3169 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_GET(x)\ 3170 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x) 3171 3172 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT BIT(8) 3173 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_SET(x)\ 3174 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x) 3175 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_GET(x)\ 3176 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x) 3177 3178 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS BIT(4) 3179 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\ 3180 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x) 3181 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\ 3182 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x) 3183 3184 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS BIT(0) 3185 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\ 3186 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x) 3187 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\ 3188 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x) 3189 3190 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_STICKY */ 3191 #define DEV2G5_PCS1G_STICKY(t) __REG(TARGET_DEV2G5,\ 3192 t, 65, 88, 0, 1, 68, 48, 0, 1, 4) 3193 3194 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4) 3195 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\ 3196 FIELD_PREP(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x) 3197 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\ 3198 FIELD_GET(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x) 3199 3200 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY BIT(0) 3201 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_SET(x)\ 3202 FIELD_PREP(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x) 3203 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x)\ 3204 FIELD_GET(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x) 3205 3206 /* DEV1G:PCS_FX100_CONFIGURATION:PCS_FX100_CFG */ 3207 #define DEV2G5_PCS_FX100_CFG(t) __REG(TARGET_DEV2G5,\ 3208 t, 65, 164, 0, 1, 4, 0, 0, 1, 4) 3209 3210 #define DEV2G5_PCS_FX100_CFG_SD_SEL BIT(26) 3211 #define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x)\ 3212 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_SEL, x) 3213 #define DEV2G5_PCS_FX100_CFG_SD_SEL_GET(x)\ 3214 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_SEL, x) 3215 3216 #define DEV2G5_PCS_FX100_CFG_SD_POL BIT(25) 3217 #define DEV2G5_PCS_FX100_CFG_SD_POL_SET(x)\ 3218 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_POL, x) 3219 #define DEV2G5_PCS_FX100_CFG_SD_POL_GET(x)\ 3220 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_POL, x) 3221 3222 #define DEV2G5_PCS_FX100_CFG_SD_ENA BIT(24) 3223 #define DEV2G5_PCS_FX100_CFG_SD_ENA_SET(x)\ 3224 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_ENA, x) 3225 #define DEV2G5_PCS_FX100_CFG_SD_ENA_GET(x)\ 3226 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_ENA, x) 3227 3228 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA BIT(20) 3229 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_SET(x)\ 3230 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x) 3231 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_GET(x)\ 3232 FIELD_GET(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x) 3233 3234 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA BIT(16) 3235 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_SET(x)\ 3236 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x) 3237 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_GET(x)\ 3238 FIELD_GET(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x) 3239 3240 #define DEV2G5_PCS_FX100_CFG_RXBITSEL GENMASK(15, 12) 3241 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_SET(x)\ 3242 FIELD_PREP(DEV2G5_PCS_FX100_CFG_RXBITSEL, x) 3243 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_GET(x)\ 3244 FIELD_GET(DEV2G5_PCS_FX100_CFG_RXBITSEL, x) 3245 3246 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG GENMASK(10, 9) 3247 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_SET(x)\ 3248 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x) 3249 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_GET(x)\ 3250 FIELD_GET(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x) 3251 3252 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA BIT(8) 3253 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_SET(x)\ 3254 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x) 3255 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_GET(x)\ 3256 FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x) 3257 3258 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER GENMASK(7, 4) 3259 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_SET(x)\ 3260 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x) 3261 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_GET(x)\ 3262 FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x) 3263 3264 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA BIT(3) 3265 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_SET(x)\ 3266 FIELD_PREP(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x) 3267 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_GET(x)\ 3268 FIELD_GET(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x) 3269 3270 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA BIT(2) 3271 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_SET(x)\ 3272 FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x) 3273 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_GET(x)\ 3274 FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x) 3275 3276 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA BIT(1) 3277 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_SET(x)\ 3278 FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x) 3279 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_GET(x)\ 3280 FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x) 3281 3282 #define DEV2G5_PCS_FX100_CFG_PCS_ENA BIT(0) 3283 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_SET(x)\ 3284 FIELD_PREP(DEV2G5_PCS_FX100_CFG_PCS_ENA, x) 3285 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x)\ 3286 FIELD_GET(DEV2G5_PCS_FX100_CFG_PCS_ENA, x) 3287 3288 /* DEV1G:PCS_FX100_STATUS:PCS_FX100_STATUS */ 3289 #define DEV2G5_PCS_FX100_STATUS(t) __REG(TARGET_DEV2G5,\ 3290 t, 65, 168, 0, 1, 4, 0, 0, 1, 4) 3291 3292 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP GENMASK(11, 8) 3293 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x)\ 3294 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x) 3295 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_GET(x)\ 3296 FIELD_GET(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x) 3297 3298 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY BIT(7) 3299 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_SET(x)\ 3300 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x) 3301 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_GET(x)\ 3302 FIELD_GET(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x) 3303 3304 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY BIT(6) 3305 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_SET(x)\ 3306 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x) 3307 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_GET(x)\ 3308 FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x) 3309 3310 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY BIT(5) 3311 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_SET(x)\ 3312 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x) 3313 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_GET(x)\ 3314 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x) 3315 3316 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4) 3317 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_SET(x)\ 3318 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x) 3319 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_GET(x)\ 3320 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x) 3321 3322 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS BIT(2) 3323 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_SET(x)\ 3324 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x) 3325 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_GET(x)\ 3326 FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x) 3327 3328 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT BIT(1) 3329 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_SET(x)\ 3330 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x) 3331 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_GET(x)\ 3332 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x) 3333 3334 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS BIT(0) 3335 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_SET(x)\ 3336 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x) 3337 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x)\ 3338 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x) 3339 3340 /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ 3341 #define DEV5G_MAC_ENA_CFG(t) __REG(TARGET_DEV5G,\ 3342 t, 13, 0, 0, 1, 60, 0, 0, 1, 4) 3343 3344 #define DEV5G_MAC_ENA_CFG_RX_ENA BIT(4) 3345 #define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x)\ 3346 FIELD_PREP(DEV5G_MAC_ENA_CFG_RX_ENA, x) 3347 #define DEV5G_MAC_ENA_CFG_RX_ENA_GET(x)\ 3348 FIELD_GET(DEV5G_MAC_ENA_CFG_RX_ENA, x) 3349 3350 #define DEV5G_MAC_ENA_CFG_TX_ENA BIT(0) 3351 #define DEV5G_MAC_ENA_CFG_TX_ENA_SET(x)\ 3352 FIELD_PREP(DEV5G_MAC_ENA_CFG_TX_ENA, x) 3353 #define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x)\ 3354 FIELD_GET(DEV5G_MAC_ENA_CFG_TX_ENA, x) 3355 3356 /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 3357 #define DEV5G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV5G,\ 3358 t, 13, 0, 0, 1, 60, 8, 0, 1, 4) 3359 3360 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) 3361 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ 3362 FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 3363 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ 3364 FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 3365 3366 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 3367 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 3368 FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x) 3369 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 3370 FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x) 3371 3372 /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 3373 #define DEV5G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV5G,\ 3374 t, 13, 0, 0, 1, 60, 28, 0, 1, 4) 3375 3376 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) 3377 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ 3378 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 3379 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ 3380 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 3381 3382 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20) 3383 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ 3384 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 3385 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ 3386 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 3387 3388 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16) 3389 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ 3390 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 3391 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ 3392 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 3393 3394 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12) 3395 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ 3396 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 3397 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ 3398 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 3399 3400 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8) 3401 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ 3402 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 3403 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ 3404 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 3405 3406 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4) 3407 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ 3408 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 3409 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ 3410 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 3411 3412 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0) 3413 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ 3414 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 3415 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ 3416 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 3417 3418 /* DEV10G:DEV_STATISTICS_32BIT:RX_SYMBOL_ERR_CNT */ 3419 #define DEV5G_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3420 t, 13, 60, 0, 1, 312, 0, 0, 1, 4) 3421 3422 /* DEV10G:DEV_STATISTICS_32BIT:RX_PAUSE_CNT */ 3423 #define DEV5G_RX_PAUSE_CNT(t) __REG(TARGET_DEV5G,\ 3424 t, 13, 60, 0, 1, 312, 4, 0, 1, 4) 3425 3426 /* DEV10G:DEV_STATISTICS_32BIT:RX_UNSUP_OPCODE_CNT */ 3427 #define DEV5G_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G,\ 3428 t, 13, 60, 0, 1, 312, 8, 0, 1, 4) 3429 3430 /* DEV10G:DEV_STATISTICS_32BIT:RX_UC_CNT */ 3431 #define DEV5G_RX_UC_CNT(t) __REG(TARGET_DEV5G,\ 3432 t, 13, 60, 0, 1, 312, 12, 0, 1, 4) 3433 3434 /* DEV10G:DEV_STATISTICS_32BIT:RX_MC_CNT */ 3435 #define DEV5G_RX_MC_CNT(t) __REG(TARGET_DEV5G,\ 3436 t, 13, 60, 0, 1, 312, 16, 0, 1, 4) 3437 3438 /* DEV10G:DEV_STATISTICS_32BIT:RX_BC_CNT */ 3439 #define DEV5G_RX_BC_CNT(t) __REG(TARGET_DEV5G,\ 3440 t, 13, 60, 0, 1, 312, 20, 0, 1, 4) 3441 3442 /* DEV10G:DEV_STATISTICS_32BIT:RX_CRC_ERR_CNT */ 3443 #define DEV5G_RX_CRC_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3444 t, 13, 60, 0, 1, 312, 24, 0, 1, 4) 3445 3446 /* DEV10G:DEV_STATISTICS_32BIT:RX_UNDERSIZE_CNT */ 3447 #define DEV5G_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G,\ 3448 t, 13, 60, 0, 1, 312, 28, 0, 1, 4) 3449 3450 /* DEV10G:DEV_STATISTICS_32BIT:RX_FRAGMENTS_CNT */ 3451 #define DEV5G_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G,\ 3452 t, 13, 60, 0, 1, 312, 32, 0, 1, 4) 3453 3454 /* DEV10G:DEV_STATISTICS_32BIT:RX_IN_RANGE_LEN_ERR_CNT */ 3455 #define DEV5G_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3456 t, 13, 60, 0, 1, 312, 36, 0, 1, 4) 3457 3458 /* DEV10G:DEV_STATISTICS_32BIT:RX_OUT_OF_RANGE_LEN_ERR_CNT */ 3459 #define DEV5G_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3460 t, 13, 60, 0, 1, 312, 40, 0, 1, 4) 3461 3462 /* DEV10G:DEV_STATISTICS_32BIT:RX_OVERSIZE_CNT */ 3463 #define DEV5G_RX_OVERSIZE_CNT(t) __REG(TARGET_DEV5G,\ 3464 t, 13, 60, 0, 1, 312, 44, 0, 1, 4) 3465 3466 /* DEV10G:DEV_STATISTICS_32BIT:RX_JABBERS_CNT */ 3467 #define DEV5G_RX_JABBERS_CNT(t) __REG(TARGET_DEV5G,\ 3468 t, 13, 60, 0, 1, 312, 48, 0, 1, 4) 3469 3470 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE64_CNT */ 3471 #define DEV5G_RX_SIZE64_CNT(t) __REG(TARGET_DEV5G,\ 3472 t, 13, 60, 0, 1, 312, 52, 0, 1, 4) 3473 3474 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE65TO127_CNT */ 3475 #define DEV5G_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G,\ 3476 t, 13, 60, 0, 1, 312, 56, 0, 1, 4) 3477 3478 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE128TO255_CNT */ 3479 #define DEV5G_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G,\ 3480 t, 13, 60, 0, 1, 312, 60, 0, 1, 4) 3481 3482 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE256TO511_CNT */ 3483 #define DEV5G_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G,\ 3484 t, 13, 60, 0, 1, 312, 64, 0, 1, 4) 3485 3486 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE512TO1023_CNT */ 3487 #define DEV5G_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G,\ 3488 t, 13, 60, 0, 1, 312, 68, 0, 1, 4) 3489 3490 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1024TO1518_CNT */ 3491 #define DEV5G_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G,\ 3492 t, 13, 60, 0, 1, 312, 72, 0, 1, 4) 3493 3494 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1519TOMAX_CNT */ 3495 #define DEV5G_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G,\ 3496 t, 13, 60, 0, 1, 312, 76, 0, 1, 4) 3497 3498 /* DEV10G:DEV_STATISTICS_32BIT:RX_IPG_SHRINK_CNT */ 3499 #define DEV5G_RX_IPG_SHRINK_CNT(t) __REG(TARGET_DEV5G,\ 3500 t, 13, 60, 0, 1, 312, 80, 0, 1, 4) 3501 3502 /* DEV10G:DEV_STATISTICS_32BIT:TX_PAUSE_CNT */ 3503 #define DEV5G_TX_PAUSE_CNT(t) __REG(TARGET_DEV5G,\ 3504 t, 13, 60, 0, 1, 312, 84, 0, 1, 4) 3505 3506 /* DEV10G:DEV_STATISTICS_32BIT:TX_UC_CNT */ 3507 #define DEV5G_TX_UC_CNT(t) __REG(TARGET_DEV5G,\ 3508 t, 13, 60, 0, 1, 312, 88, 0, 1, 4) 3509 3510 /* DEV10G:DEV_STATISTICS_32BIT:TX_MC_CNT */ 3511 #define DEV5G_TX_MC_CNT(t) __REG(TARGET_DEV5G,\ 3512 t, 13, 60, 0, 1, 312, 92, 0, 1, 4) 3513 3514 /* DEV10G:DEV_STATISTICS_32BIT:TX_BC_CNT */ 3515 #define DEV5G_TX_BC_CNT(t) __REG(TARGET_DEV5G,\ 3516 t, 13, 60, 0, 1, 312, 96, 0, 1, 4) 3517 3518 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE64_CNT */ 3519 #define DEV5G_TX_SIZE64_CNT(t) __REG(TARGET_DEV5G,\ 3520 t, 13, 60, 0, 1, 312, 100, 0, 1, 4) 3521 3522 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE65TO127_CNT */ 3523 #define DEV5G_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G,\ 3524 t, 13, 60, 0, 1, 312, 104, 0, 1, 4) 3525 3526 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE128TO255_CNT */ 3527 #define DEV5G_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G,\ 3528 t, 13, 60, 0, 1, 312, 108, 0, 1, 4) 3529 3530 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE256TO511_CNT */ 3531 #define DEV5G_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G,\ 3532 t, 13, 60, 0, 1, 312, 112, 0, 1, 4) 3533 3534 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE512TO1023_CNT */ 3535 #define DEV5G_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G,\ 3536 t, 13, 60, 0, 1, 312, 116, 0, 1, 4) 3537 3538 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1024TO1518_CNT */ 3539 #define DEV5G_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G,\ 3540 t, 13, 60, 0, 1, 312, 120, 0, 1, 4) 3541 3542 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1519TOMAX_CNT */ 3543 #define DEV5G_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G,\ 3544 t, 13, 60, 0, 1, 312, 124, 0, 1, 4) 3545 3546 /* DEV10G:DEV_STATISTICS_32BIT:RX_ALIGNMENT_LOST_CNT */ 3547 #define DEV5G_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G,\ 3548 t, 13, 60, 0, 1, 312, 128, 0, 1, 4) 3549 3550 /* DEV10G:DEV_STATISTICS_32BIT:RX_TAGGED_FRMS_CNT */ 3551 #define DEV5G_RX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G,\ 3552 t, 13, 60, 0, 1, 312, 132, 0, 1, 4) 3553 3554 /* DEV10G:DEV_STATISTICS_32BIT:RX_UNTAGGED_FRMS_CNT */ 3555 #define DEV5G_RX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G,\ 3556 t, 13, 60, 0, 1, 312, 136, 0, 1, 4) 3557 3558 /* DEV10G:DEV_STATISTICS_32BIT:TX_TAGGED_FRMS_CNT */ 3559 #define DEV5G_TX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G,\ 3560 t, 13, 60, 0, 1, 312, 140, 0, 1, 4) 3561 3562 /* DEV10G:DEV_STATISTICS_32BIT:TX_UNTAGGED_FRMS_CNT */ 3563 #define DEV5G_TX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G,\ 3564 t, 13, 60, 0, 1, 312, 144, 0, 1, 4) 3565 3566 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SYMBOL_ERR_CNT */ 3567 #define DEV5G_PMAC_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3568 t, 13, 60, 0, 1, 312, 148, 0, 1, 4) 3569 3570 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_PAUSE_CNT */ 3571 #define DEV5G_PMAC_RX_PAUSE_CNT(t) __REG(TARGET_DEV5G,\ 3572 t, 13, 60, 0, 1, 312, 152, 0, 1, 4) 3573 3574 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNSUP_OPCODE_CNT */ 3575 #define DEV5G_PMAC_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G,\ 3576 t, 13, 60, 0, 1, 312, 156, 0, 1, 4) 3577 3578 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UC_CNT */ 3579 #define DEV5G_PMAC_RX_UC_CNT(t) __REG(TARGET_DEV5G,\ 3580 t, 13, 60, 0, 1, 312, 160, 0, 1, 4) 3581 3582 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_MC_CNT */ 3583 #define DEV5G_PMAC_RX_MC_CNT(t) __REG(TARGET_DEV5G,\ 3584 t, 13, 60, 0, 1, 312, 164, 0, 1, 4) 3585 3586 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_BC_CNT */ 3587 #define DEV5G_PMAC_RX_BC_CNT(t) __REG(TARGET_DEV5G,\ 3588 t, 13, 60, 0, 1, 312, 168, 0, 1, 4) 3589 3590 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_CRC_ERR_CNT */ 3591 #define DEV5G_PMAC_RX_CRC_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3592 t, 13, 60, 0, 1, 312, 172, 0, 1, 4) 3593 3594 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNDERSIZE_CNT */ 3595 #define DEV5G_PMAC_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G,\ 3596 t, 13, 60, 0, 1, 312, 176, 0, 1, 4) 3597 3598 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_FRAGMENTS_CNT */ 3599 #define DEV5G_PMAC_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G,\ 3600 t, 13, 60, 0, 1, 312, 180, 0, 1, 4) 3601 3602 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ 3603 #define DEV5G_PMAC_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3604 t, 13, 60, 0, 1, 312, 184, 0, 1, 4) 3605 3606 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ 3607 #define DEV5G_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3608 t, 13, 60, 0, 1, 312, 188, 0, 1, 4) 3609 3610 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OVERSIZE_CNT */ 3611 #define DEV5G_PMAC_RX_OVERSIZE_CNT(t) __REG(TARGET_DEV5G,\ 3612 t, 13, 60, 0, 1, 312, 192, 0, 1, 4) 3613 3614 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_JABBERS_CNT */ 3615 #define DEV5G_PMAC_RX_JABBERS_CNT(t) __REG(TARGET_DEV5G,\ 3616 t, 13, 60, 0, 1, 312, 196, 0, 1, 4) 3617 3618 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE64_CNT */ 3619 #define DEV5G_PMAC_RX_SIZE64_CNT(t) __REG(TARGET_DEV5G,\ 3620 t, 13, 60, 0, 1, 312, 200, 0, 1, 4) 3621 3622 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE65TO127_CNT */ 3623 #define DEV5G_PMAC_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G,\ 3624 t, 13, 60, 0, 1, 312, 204, 0, 1, 4) 3625 3626 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE128TO255_CNT */ 3627 #define DEV5G_PMAC_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G,\ 3628 t, 13, 60, 0, 1, 312, 208, 0, 1, 4) 3629 3630 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE256TO511_CNT */ 3631 #define DEV5G_PMAC_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G,\ 3632 t, 13, 60, 0, 1, 312, 212, 0, 1, 4) 3633 3634 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE512TO1023_CNT */ 3635 #define DEV5G_PMAC_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G,\ 3636 t, 13, 60, 0, 1, 312, 216, 0, 1, 4) 3637 3638 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1024TO1518_CNT */ 3639 #define DEV5G_PMAC_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G,\ 3640 t, 13, 60, 0, 1, 312, 220, 0, 1, 4) 3641 3642 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1519TOMAX_CNT */ 3643 #define DEV5G_PMAC_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G,\ 3644 t, 13, 60, 0, 1, 312, 224, 0, 1, 4) 3645 3646 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_PAUSE_CNT */ 3647 #define DEV5G_PMAC_TX_PAUSE_CNT(t) __REG(TARGET_DEV5G,\ 3648 t, 13, 60, 0, 1, 312, 228, 0, 1, 4) 3649 3650 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_UC_CNT */ 3651 #define DEV5G_PMAC_TX_UC_CNT(t) __REG(TARGET_DEV5G,\ 3652 t, 13, 60, 0, 1, 312, 232, 0, 1, 4) 3653 3654 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_MC_CNT */ 3655 #define DEV5G_PMAC_TX_MC_CNT(t) __REG(TARGET_DEV5G,\ 3656 t, 13, 60, 0, 1, 312, 236, 0, 1, 4) 3657 3658 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_BC_CNT */ 3659 #define DEV5G_PMAC_TX_BC_CNT(t) __REG(TARGET_DEV5G,\ 3660 t, 13, 60, 0, 1, 312, 240, 0, 1, 4) 3661 3662 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE64_CNT */ 3663 #define DEV5G_PMAC_TX_SIZE64_CNT(t) __REG(TARGET_DEV5G,\ 3664 t, 13, 60, 0, 1, 312, 244, 0, 1, 4) 3665 3666 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE65TO127_CNT */ 3667 #define DEV5G_PMAC_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G,\ 3668 t, 13, 60, 0, 1, 312, 248, 0, 1, 4) 3669 3670 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE128TO255_CNT */ 3671 #define DEV5G_PMAC_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G,\ 3672 t, 13, 60, 0, 1, 312, 252, 0, 1, 4) 3673 3674 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE256TO511_CNT */ 3675 #define DEV5G_PMAC_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G,\ 3676 t, 13, 60, 0, 1, 312, 256, 0, 1, 4) 3677 3678 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE512TO1023_CNT */ 3679 #define DEV5G_PMAC_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G,\ 3680 t, 13, 60, 0, 1, 312, 260, 0, 1, 4) 3681 3682 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1024TO1518_CNT */ 3683 #define DEV5G_PMAC_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G,\ 3684 t, 13, 60, 0, 1, 312, 264, 0, 1, 4) 3685 3686 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1519TOMAX_CNT */ 3687 #define DEV5G_PMAC_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G,\ 3688 t, 13, 60, 0, 1, 312, 268, 0, 1, 4) 3689 3690 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_ALIGNMENT_LOST_CNT */ 3691 #define DEV5G_PMAC_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G,\ 3692 t, 13, 60, 0, 1, 312, 272, 0, 1, 4) 3693 3694 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_ERR_CNT */ 3695 #define DEV5G_MM_RX_ASSEMBLY_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3696 t, 13, 60, 0, 1, 312, 276, 0, 1, 4) 3697 3698 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_SMD_ERR_CNT */ 3699 #define DEV5G_MM_RX_SMD_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3700 t, 13, 60, 0, 1, 312, 280, 0, 1, 4) 3701 3702 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_OK_CNT */ 3703 #define DEV5G_MM_RX_ASSEMBLY_OK_CNT(t) __REG(TARGET_DEV5G,\ 3704 t, 13, 60, 0, 1, 312, 284, 0, 1, 4) 3705 3706 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_MERGE_FRAG_CNT */ 3707 #define DEV5G_MM_RX_MERGE_FRAG_CNT(t) __REG(TARGET_DEV5G,\ 3708 t, 13, 60, 0, 1, 312, 288, 0, 1, 4) 3709 3710 /* DEV10G:DEV_STATISTICS_32BIT:MM_TX_PFRAGMENT_CNT */ 3711 #define DEV5G_MM_TX_PFRAGMENT_CNT(t) __REG(TARGET_DEV5G,\ 3712 t, 13, 60, 0, 1, 312, 292, 0, 1, 4) 3713 3714 /* DEV10G:DEV_STATISTICS_32BIT:RX_HIH_CKSM_ERR_CNT */ 3715 #define DEV5G_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3716 t, 13, 60, 0, 1, 312, 296, 0, 1, 4) 3717 3718 /* DEV10G:DEV_STATISTICS_32BIT:RX_XGMII_PROT_ERR_CNT */ 3719 #define DEV5G_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3720 t, 13, 60, 0, 1, 312, 300, 0, 1, 4) 3721 3722 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_HIH_CKSM_ERR_CNT */ 3723 #define DEV5G_PMAC_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3724 t, 13, 60, 0, 1, 312, 304, 0, 1, 4) 3725 3726 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_XGMII_PROT_ERR_CNT */ 3727 #define DEV5G_PMAC_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3728 t, 13, 60, 0, 1, 312, 308, 0, 1, 4) 3729 3730 /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_CNT */ 3731 #define DEV5G_RX_IN_BYTES_CNT(t) __REG(TARGET_DEV5G,\ 3732 t, 13, 372, 0, 1, 64, 0, 0, 1, 4) 3733 3734 /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_MSB_CNT */ 3735 #define DEV5G_RX_IN_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ 3736 t, 13, 372, 0, 1, 64, 4, 0, 1, 4) 3737 3738 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(7, 0) 3739 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ 3740 FIELD_PREP(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 3741 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ 3742 FIELD_GET(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 3743 3744 /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_CNT */ 3745 #define DEV5G_RX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G,\ 3746 t, 13, 372, 0, 1, 64, 8, 0, 1, 4) 3747 3748 /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_MSB_CNT */ 3749 #define DEV5G_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ 3750 t, 13, 372, 0, 1, 64, 12, 0, 1, 4) 3751 3752 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(7, 0) 3753 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ 3754 FIELD_PREP(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 3755 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ 3756 FIELD_GET(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 3757 3758 /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_CNT */ 3759 #define DEV5G_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G,\ 3760 t, 13, 372, 0, 1, 64, 16, 0, 1, 4) 3761 3762 /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_MSB_CNT */ 3763 #define DEV5G_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ 3764 t, 13, 372, 0, 1, 64, 20, 0, 1, 4) 3765 3766 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0) 3767 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ 3768 FIELD_PREP(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 3769 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ 3770 FIELD_GET(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 3771 3772 /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_CNT */ 3773 #define DEV5G_TX_OUT_BYTES_CNT(t) __REG(TARGET_DEV5G,\ 3774 t, 13, 372, 0, 1, 64, 24, 0, 1, 4) 3775 3776 /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_MSB_CNT */ 3777 #define DEV5G_TX_OUT_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ 3778 t, 13, 372, 0, 1, 64, 28, 0, 1, 4) 3779 3780 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(7, 0) 3781 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ 3782 FIELD_PREP(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 3783 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ 3784 FIELD_GET(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 3785 3786 /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_CNT */ 3787 #define DEV5G_TX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G,\ 3788 t, 13, 372, 0, 1, 64, 32, 0, 1, 4) 3789 3790 /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_MSB_CNT */ 3791 #define DEV5G_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ 3792 t, 13, 372, 0, 1, 64, 36, 0, 1, 4) 3793 3794 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(7, 0) 3795 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ 3796 FIELD_PREP(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 3797 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ 3798 FIELD_GET(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 3799 3800 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_CNT */ 3801 #define DEV5G_PMAC_RX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G,\ 3802 t, 13, 372, 0, 1, 64, 40, 0, 1, 4) 3803 3804 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_MSB_CNT */ 3805 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ 3806 t, 13, 372, 0, 1, 64, 44, 0, 1, 4) 3807 3808 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(7, 0) 3809 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ 3810 FIELD_PREP(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 3811 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ 3812 FIELD_GET(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 3813 3814 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_CNT */ 3815 #define DEV5G_PMAC_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G,\ 3816 t, 13, 372, 0, 1, 64, 48, 0, 1, 4) 3817 3818 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_MSB_CNT */ 3819 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ 3820 t, 13, 372, 0, 1, 64, 52, 0, 1, 4) 3821 3822 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0) 3823 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ 3824 FIELD_PREP(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 3825 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ 3826 FIELD_GET(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 3827 3828 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_CNT */ 3829 #define DEV5G_PMAC_TX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G,\ 3830 t, 13, 372, 0, 1, 64, 56, 0, 1, 4) 3831 3832 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_MSB_CNT */ 3833 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ 3834 t, 13, 372, 0, 1, 64, 60, 0, 1, 4) 3835 3836 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(7, 0) 3837 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ 3838 FIELD_PREP(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 3839 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ 3840 FIELD_GET(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 3841 3842 /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ 3843 #define DEV5G_DEV_RST_CTRL(t) __REG(TARGET_DEV5G,\ 3844 t, 13, 436, 0, 1, 52, 0, 0, 1, 4) 3845 3846 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) 3847 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ 3848 FIELD_PREP(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 3849 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ 3850 FIELD_GET(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 3851 3852 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27) 3853 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ 3854 FIELD_PREP(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 3855 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ 3856 FIELD_GET(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 3857 3858 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25) 3859 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ 3860 FIELD_PREP(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 3861 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ 3862 FIELD_GET(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 3863 3864 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23) 3865 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ 3866 FIELD_PREP(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 3867 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ 3868 FIELD_GET(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 3869 3870 #define DEV5G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) 3871 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ 3872 FIELD_PREP(DEV5G_DEV_RST_CTRL_SPEED_SEL, x) 3873 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ 3874 FIELD_GET(DEV5G_DEV_RST_CTRL_SPEED_SEL, x) 3875 3876 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST BIT(12) 3877 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ 3878 FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x) 3879 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ 3880 FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x) 3881 3882 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST BIT(8) 3883 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ 3884 FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x) 3885 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ 3886 FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x) 3887 3888 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST BIT(4) 3889 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ 3890 FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x) 3891 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ 3892 FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x) 3893 3894 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST BIT(0) 3895 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ 3896 FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x) 3897 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 3898 FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x) 3899 3900 /* DSM:RAM_CTRL:RAM_INIT */ 3901 #define DSM_RAM_INIT __REG(TARGET_DSM,\ 3902 0, 1, 0, 0, 1, 4, 0, 0, 1, 4) 3903 3904 #define DSM_RAM_INIT_RAM_INIT BIT(1) 3905 #define DSM_RAM_INIT_RAM_INIT_SET(x)\ 3906 FIELD_PREP(DSM_RAM_INIT_RAM_INIT, x) 3907 #define DSM_RAM_INIT_RAM_INIT_GET(x)\ 3908 FIELD_GET(DSM_RAM_INIT_RAM_INIT, x) 3909 3910 #define DSM_RAM_INIT_RAM_CFG_HOOK BIT(0) 3911 #define DSM_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 3912 FIELD_PREP(DSM_RAM_INIT_RAM_CFG_HOOK, x) 3913 #define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 3914 FIELD_GET(DSM_RAM_INIT_RAM_CFG_HOOK, x) 3915 3916 /* DSM:CFG:BUF_CFG */ 3917 #define DSM_BUF_CFG(r) __REG(TARGET_DSM,\ 3918 0, 1, 20, 0, 1, 3528, 0, r, 67, 4) 3919 3920 #define DSM_BUF_CFG_CSC_STAT_DIS BIT(13) 3921 #define DSM_BUF_CFG_CSC_STAT_DIS_SET(x)\ 3922 FIELD_PREP(DSM_BUF_CFG_CSC_STAT_DIS, x) 3923 #define DSM_BUF_CFG_CSC_STAT_DIS_GET(x)\ 3924 FIELD_GET(DSM_BUF_CFG_CSC_STAT_DIS, x) 3925 3926 #define DSM_BUF_CFG_AGING_ENA BIT(12) 3927 #define DSM_BUF_CFG_AGING_ENA_SET(x)\ 3928 FIELD_PREP(DSM_BUF_CFG_AGING_ENA, x) 3929 #define DSM_BUF_CFG_AGING_ENA_GET(x)\ 3930 FIELD_GET(DSM_BUF_CFG_AGING_ENA, x) 3931 3932 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS BIT(11) 3933 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(x)\ 3934 FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x) 3935 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_GET(x)\ 3936 FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x) 3937 3938 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT GENMASK(10, 0) 3939 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_SET(x)\ 3940 FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x) 3941 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x)\ 3942 FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x) 3943 3944 /* DSM:CFG:DEV_TX_STOP_WM_CFG */ 3945 #define DSM_DEV_TX_STOP_WM_CFG(r) __REG(TARGET_DSM,\ 3946 0, 1, 20, 0, 1, 3528, 1360, r, 67, 4) 3947 3948 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA BIT(9) 3949 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x)\ 3950 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x) 3951 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_GET(x)\ 3952 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x) 3953 3954 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA BIT(8) 3955 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(x)\ 3956 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x) 3957 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_GET(x)\ 3958 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x) 3959 3960 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM GENMASK(7, 1) 3961 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(x)\ 3962 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x) 3963 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_GET(x)\ 3964 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x) 3965 3966 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR BIT(0) 3967 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(x)\ 3968 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x) 3969 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_GET(x)\ 3970 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x) 3971 3972 /* DSM:CFG:RX_PAUSE_CFG */ 3973 #define DSM_RX_PAUSE_CFG(r) __REG(TARGET_DSM,\ 3974 0, 1, 20, 0, 1, 3528, 1628, r, 67, 4) 3975 3976 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN BIT(1) 3977 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(x)\ 3978 FIELD_PREP(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x) 3979 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_GET(x)\ 3980 FIELD_GET(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x) 3981 3982 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL BIT(0) 3983 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_SET(x)\ 3984 FIELD_PREP(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x) 3985 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_GET(x)\ 3986 FIELD_GET(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x) 3987 3988 /* DSM:CFG:MAC_CFG */ 3989 #define DSM_MAC_CFG(r) __REG(TARGET_DSM,\ 3990 0, 1, 20, 0, 1, 3528, 2432, r, 67, 4) 3991 3992 #define DSM_MAC_CFG_TX_PAUSE_VAL GENMASK(31, 16) 3993 #define DSM_MAC_CFG_TX_PAUSE_VAL_SET(x)\ 3994 FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_VAL, x) 3995 #define DSM_MAC_CFG_TX_PAUSE_VAL_GET(x)\ 3996 FIELD_GET(DSM_MAC_CFG_TX_PAUSE_VAL, x) 3997 3998 #define DSM_MAC_CFG_HDX_BACKPREASSURE BIT(2) 3999 #define DSM_MAC_CFG_HDX_BACKPREASSURE_SET(x)\ 4000 FIELD_PREP(DSM_MAC_CFG_HDX_BACKPREASSURE, x) 4001 #define DSM_MAC_CFG_HDX_BACKPREASSURE_GET(x)\ 4002 FIELD_GET(DSM_MAC_CFG_HDX_BACKPREASSURE, x) 4003 4004 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE BIT(1) 4005 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_SET(x)\ 4006 FIELD_PREP(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x) 4007 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_GET(x)\ 4008 FIELD_GET(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x) 4009 4010 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF BIT(0) 4011 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_SET(x)\ 4012 FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x) 4013 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_GET(x)\ 4014 FIELD_GET(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x) 4015 4016 /* DSM:CFG:MAC_ADDR_BASE_HIGH_CFG */ 4017 #define DSM_MAC_ADDR_BASE_HIGH_CFG(r) __REG(TARGET_DSM,\ 4018 0, 1, 20, 0, 1, 3528, 2700, r, 65, 4) 4019 4020 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH GENMASK(23, 0) 4021 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_SET(x)\ 4022 FIELD_PREP(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x) 4023 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_GET(x)\ 4024 FIELD_GET(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x) 4025 4026 /* DSM:CFG:MAC_ADDR_BASE_LOW_CFG */ 4027 #define DSM_MAC_ADDR_BASE_LOW_CFG(r) __REG(TARGET_DSM,\ 4028 0, 1, 20, 0, 1, 3528, 2960, r, 65, 4) 4029 4030 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW GENMASK(23, 0) 4031 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_SET(x)\ 4032 FIELD_PREP(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x) 4033 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_GET(x)\ 4034 FIELD_GET(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x) 4035 4036 /* DSM:CFG:TAXI_CAL_CFG */ 4037 #define DSM_TAXI_CAL_CFG(r) __REG(TARGET_DSM,\ 4038 0, 1, 20, 0, 1, 3528, 3224, r, 9, 4) 4039 4040 #define DSM_TAXI_CAL_CFG_CAL_IDX GENMASK(20, 15) 4041 #define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\ 4042 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_IDX, x) 4043 #define DSM_TAXI_CAL_CFG_CAL_IDX_GET(x)\ 4044 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_IDX, x) 4045 4046 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN GENMASK(14, 9) 4047 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_SET(x)\ 4048 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x) 4049 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(x)\ 4050 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x) 4051 4052 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL GENMASK(8, 5) 4053 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_SET(x)\ 4054 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x) 4055 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_GET(x)\ 4056 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x) 4057 4058 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL GENMASK(4, 1) 4059 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(x)\ 4060 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x) 4061 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_GET(x)\ 4062 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x) 4063 4064 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA BIT(0) 4065 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(x)\ 4066 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x) 4067 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\ 4068 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x) 4069 4070 /* EACL:ES2_KEY_SELECT_PROFILE:VCAP_ES2_KEY_SEL */ 4071 #define EACL_VCAP_ES2_KEY_SEL(g, r) __REG(TARGET_EACL,\ 4072 0, 1, 149504, g, 138, 8, 0, r, 2, 4) 4073 4074 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL GENMASK(7, 5) 4075 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_SET(x)\ 4076 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL, x) 4077 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_GET(x)\ 4078 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL, x) 4079 4080 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL GENMASK(4, 2) 4081 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_SET(x)\ 4082 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL, x) 4083 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_GET(x)\ 4084 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL, x) 4085 4086 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL BIT(1) 4087 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_SET(x)\ 4088 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL, x) 4089 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_GET(x)\ 4090 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL, x) 4091 4092 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA BIT(0) 4093 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_SET(x)\ 4094 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_KEY_ENA, x) 4095 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_GET(x)\ 4096 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_KEY_ENA, x) 4097 4098 /* EACL:CNT_TBL:ES2_CNT */ 4099 #define EACL_ES2_CNT(g) __REG(TARGET_EACL,\ 4100 0, 1, 122880, g, 2048, 4, 0, 0, 1, 4) 4101 4102 /* EACL:POL_CFG:POL_EACL_CFG */ 4103 #define EACL_POL_EACL_CFG __REG(TARGET_EACL,\ 4104 0, 1, 150608, 0, 1, 780, 768, 0, 1, 4) 4105 4106 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED BIT(5) 4107 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_SET(x)\ 4108 FIELD_PREP(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x) 4109 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_GET(x)\ 4110 FIELD_GET(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x) 4111 4112 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY BIT(4) 4113 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_SET(x)\ 4114 FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x) 4115 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_GET(x)\ 4116 FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x) 4117 4118 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY BIT(3) 4119 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_SET(x)\ 4120 FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x) 4121 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_GET(x)\ 4122 FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x) 4123 4124 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE BIT(2) 4125 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_SET(x)\ 4126 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x) 4127 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_GET(x)\ 4128 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x) 4129 4130 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN BIT(1) 4131 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_SET(x)\ 4132 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x) 4133 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_GET(x)\ 4134 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x) 4135 4136 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT BIT(0) 4137 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(x)\ 4138 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x) 4139 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_GET(x)\ 4140 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x) 4141 4142 /* EACL:ES2_STICKY:SEC_LOOKUP_STICKY */ 4143 #define EACL_SEC_LOOKUP_STICKY(r) __REG(TARGET_EACL,\ 4144 0, 1, 118696, 0, 1, 8, 0, r, 2, 4) 4145 4146 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY BIT(7) 4147 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\ 4148 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x) 4149 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\ 4150 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x) 4151 4152 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY BIT(6) 4153 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\ 4154 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x) 4155 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\ 4156 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x) 4157 4158 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY BIT(5) 4159 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\ 4160 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x) 4161 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\ 4162 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x) 4163 4164 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY BIT(4) 4165 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\ 4166 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x) 4167 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\ 4168 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x) 4169 4170 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY BIT(3) 4171 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\ 4172 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x) 4173 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\ 4174 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x) 4175 4176 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY BIT(2) 4177 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\ 4178 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x) 4179 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\ 4180 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x) 4181 4182 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY BIT(1) 4183 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\ 4184 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x) 4185 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\ 4186 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x) 4187 4188 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY BIT(0) 4189 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\ 4190 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) 4191 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\ 4192 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) 4193 4194 /* EACL:RAM_CTRL:RAM_INIT */ 4195 #define EACL_RAM_INIT __REG(TARGET_EACL,\ 4196 0, 1, 118736, 0, 1, 4, 0, 0, 1, 4) 4197 4198 #define EACL_RAM_INIT_RAM_INIT BIT(1) 4199 #define EACL_RAM_INIT_RAM_INIT_SET(x)\ 4200 FIELD_PREP(EACL_RAM_INIT_RAM_INIT, x) 4201 #define EACL_RAM_INIT_RAM_INIT_GET(x)\ 4202 FIELD_GET(EACL_RAM_INIT_RAM_INIT, x) 4203 4204 #define EACL_RAM_INIT_RAM_CFG_HOOK BIT(0) 4205 #define EACL_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 4206 FIELD_PREP(EACL_RAM_INIT_RAM_CFG_HOOK, x) 4207 #define EACL_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 4208 FIELD_GET(EACL_RAM_INIT_RAM_CFG_HOOK, x) 4209 4210 /* FDMA:FDMA:FDMA_CH_ACTIVATE */ 4211 #define FDMA_CH_ACTIVATE __REG(TARGET_FDMA,\ 4212 0, 1, 8, 0, 1, 428, 0, 0, 1, 4) 4213 4214 #define FDMA_CH_ACTIVATE_CH_ACTIVATE GENMASK(7, 0) 4215 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\ 4216 FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 4217 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\ 4218 FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 4219 4220 /* FDMA:FDMA:FDMA_CH_RELOAD */ 4221 #define FDMA_CH_RELOAD __REG(TARGET_FDMA,\ 4222 0, 1, 8, 0, 1, 428, 4, 0, 1, 4) 4223 4224 #define FDMA_CH_RELOAD_CH_RELOAD GENMASK(7, 0) 4225 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\ 4226 FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x) 4227 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\ 4228 FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x) 4229 4230 /* FDMA:FDMA:FDMA_CH_DISABLE */ 4231 #define FDMA_CH_DISABLE __REG(TARGET_FDMA,\ 4232 0, 1, 8, 0, 1, 428, 8, 0, 1, 4) 4233 4234 #define FDMA_CH_DISABLE_CH_DISABLE GENMASK(7, 0) 4235 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\ 4236 FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x) 4237 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\ 4238 FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x) 4239 4240 /* FDMA:FDMA:FDMA_DCB_LLP */ 4241 #define FDMA_DCB_LLP(r) __REG(TARGET_FDMA,\ 4242 0, 1, 8, 0, 1, 428, 52, r, 8, 4) 4243 4244 /* FDMA:FDMA:FDMA_DCB_LLP1 */ 4245 #define FDMA_DCB_LLP1(r) __REG(TARGET_FDMA,\ 4246 0, 1, 8, 0, 1, 428, 84, r, 8, 4) 4247 4248 /* FDMA:FDMA:FDMA_DCB_LLP_PREV */ 4249 #define FDMA_DCB_LLP_PREV(r) __REG(TARGET_FDMA,\ 4250 0, 1, 8, 0, 1, 428, 116, r, 8, 4) 4251 4252 /* FDMA:FDMA:FDMA_DCB_LLP_PREV1 */ 4253 #define FDMA_DCB_LLP_PREV1(r) __REG(TARGET_FDMA,\ 4254 0, 1, 8, 0, 1, 428, 148, r, 8, 4) 4255 4256 /* FDMA:FDMA:FDMA_CH_CFG */ 4257 #define FDMA_CH_CFG(r) __REG(TARGET_FDMA,\ 4258 0, 1, 8, 0, 1, 428, 224, r, 8, 4) 4259 4260 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE BIT(7) 4261 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_SET(x)\ 4262 FIELD_PREP(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) 4263 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_GET(x)\ 4264 FIELD_GET(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) 4265 4266 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY BIT(6) 4267 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\ 4268 FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 4269 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\ 4270 FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 4271 4272 #define FDMA_CH_CFG_CH_INJ_PORT BIT(5) 4273 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\ 4274 FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x) 4275 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\ 4276 FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x) 4277 4278 #define FDMA_CH_CFG_CH_DCB_DB_CNT GENMASK(4, 1) 4279 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\ 4280 FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 4281 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\ 4282 FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 4283 4284 #define FDMA_CH_CFG_CH_MEM BIT(0) 4285 #define FDMA_CH_CFG_CH_MEM_SET(x)\ 4286 FIELD_PREP(FDMA_CH_CFG_CH_MEM, x) 4287 #define FDMA_CH_CFG_CH_MEM_GET(x)\ 4288 FIELD_GET(FDMA_CH_CFG_CH_MEM, x) 4289 4290 /* FDMA:FDMA:FDMA_CH_TRANSLATE */ 4291 #define FDMA_CH_TRANSLATE(r) __REG(TARGET_FDMA,\ 4292 0, 1, 8, 0, 1, 428, 256, r, 8, 4) 4293 4294 #define FDMA_CH_TRANSLATE_OFFSET GENMASK(15, 0) 4295 #define FDMA_CH_TRANSLATE_OFFSET_SET(x)\ 4296 FIELD_PREP(FDMA_CH_TRANSLATE_OFFSET, x) 4297 #define FDMA_CH_TRANSLATE_OFFSET_GET(x)\ 4298 FIELD_GET(FDMA_CH_TRANSLATE_OFFSET, x) 4299 4300 /* FDMA:FDMA:FDMA_XTR_CFG */ 4301 #define FDMA_XTR_CFG __REG(TARGET_FDMA,\ 4302 0, 1, 8, 0, 1, 428, 364, 0, 1, 4) 4303 4304 #define FDMA_XTR_CFG_XTR_FIFO_WM GENMASK(15, 11) 4305 #define FDMA_XTR_CFG_XTR_FIFO_WM_SET(x)\ 4306 FIELD_PREP(FDMA_XTR_CFG_XTR_FIFO_WM, x) 4307 #define FDMA_XTR_CFG_XTR_FIFO_WM_GET(x)\ 4308 FIELD_GET(FDMA_XTR_CFG_XTR_FIFO_WM, x) 4309 4310 #define FDMA_XTR_CFG_XTR_ARB_SAT GENMASK(10, 0) 4311 #define FDMA_XTR_CFG_XTR_ARB_SAT_SET(x)\ 4312 FIELD_PREP(FDMA_XTR_CFG_XTR_ARB_SAT, x) 4313 #define FDMA_XTR_CFG_XTR_ARB_SAT_GET(x)\ 4314 FIELD_GET(FDMA_XTR_CFG_XTR_ARB_SAT, x) 4315 4316 /* FDMA:FDMA:FDMA_PORT_CTRL */ 4317 #define FDMA_PORT_CTRL(r) __REG(TARGET_FDMA,\ 4318 0, 1, 8, 0, 1, 428, 376, r, 2, 4) 4319 4320 #define FDMA_PORT_CTRL_INJ_STOP BIT(4) 4321 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\ 4322 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x) 4323 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\ 4324 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x) 4325 4326 #define FDMA_PORT_CTRL_INJ_STOP_FORCE BIT(3) 4327 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_SET(x)\ 4328 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP_FORCE, x) 4329 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_GET(x)\ 4330 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP_FORCE, x) 4331 4332 #define FDMA_PORT_CTRL_XTR_STOP BIT(2) 4333 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\ 4334 FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x) 4335 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\ 4336 FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x) 4337 4338 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY BIT(1) 4339 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_SET(x)\ 4340 FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x) 4341 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(x)\ 4342 FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x) 4343 4344 #define FDMA_PORT_CTRL_XTR_BUF_RST BIT(0) 4345 #define FDMA_PORT_CTRL_XTR_BUF_RST_SET(x)\ 4346 FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_RST, x) 4347 #define FDMA_PORT_CTRL_XTR_BUF_RST_GET(x)\ 4348 FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_RST, x) 4349 4350 /* FDMA:FDMA:FDMA_INTR_DCB */ 4351 #define FDMA_INTR_DCB __REG(TARGET_FDMA,\ 4352 0, 1, 8, 0, 1, 428, 384, 0, 1, 4) 4353 4354 #define FDMA_INTR_DCB_INTR_DCB GENMASK(7, 0) 4355 #define FDMA_INTR_DCB_INTR_DCB_SET(x)\ 4356 FIELD_PREP(FDMA_INTR_DCB_INTR_DCB, x) 4357 #define FDMA_INTR_DCB_INTR_DCB_GET(x)\ 4358 FIELD_GET(FDMA_INTR_DCB_INTR_DCB, x) 4359 4360 /* FDMA:FDMA:FDMA_INTR_DCB_ENA */ 4361 #define FDMA_INTR_DCB_ENA __REG(TARGET_FDMA,\ 4362 0, 1, 8, 0, 1, 428, 388, 0, 1, 4) 4363 4364 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA GENMASK(7, 0) 4365 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_SET(x)\ 4366 FIELD_PREP(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x) 4367 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_GET(x)\ 4368 FIELD_GET(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x) 4369 4370 /* FDMA:FDMA:FDMA_INTR_DB */ 4371 #define FDMA_INTR_DB __REG(TARGET_FDMA,\ 4372 0, 1, 8, 0, 1, 428, 392, 0, 1, 4) 4373 4374 #define FDMA_INTR_DB_INTR_DB GENMASK(7, 0) 4375 #define FDMA_INTR_DB_INTR_DB_SET(x)\ 4376 FIELD_PREP(FDMA_INTR_DB_INTR_DB, x) 4377 #define FDMA_INTR_DB_INTR_DB_GET(x)\ 4378 FIELD_GET(FDMA_INTR_DB_INTR_DB, x) 4379 4380 /* FDMA:FDMA:FDMA_INTR_DB_ENA */ 4381 #define FDMA_INTR_DB_ENA __REG(TARGET_FDMA,\ 4382 0, 1, 8, 0, 1, 428, 396, 0, 1, 4) 4383 4384 #define FDMA_INTR_DB_ENA_INTR_DB_ENA GENMASK(7, 0) 4385 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\ 4386 FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 4387 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\ 4388 FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 4389 4390 /* FDMA:FDMA:FDMA_INTR_ERR */ 4391 #define FDMA_INTR_ERR __REG(TARGET_FDMA,\ 4392 0, 1, 8, 0, 1, 428, 400, 0, 1, 4) 4393 4394 #define FDMA_INTR_ERR_INTR_PORT_ERR GENMASK(9, 8) 4395 #define FDMA_INTR_ERR_INTR_PORT_ERR_SET(x)\ 4396 FIELD_PREP(FDMA_INTR_ERR_INTR_PORT_ERR, x) 4397 #define FDMA_INTR_ERR_INTR_PORT_ERR_GET(x)\ 4398 FIELD_GET(FDMA_INTR_ERR_INTR_PORT_ERR, x) 4399 4400 #define FDMA_INTR_ERR_INTR_CH_ERR GENMASK(7, 0) 4401 #define FDMA_INTR_ERR_INTR_CH_ERR_SET(x)\ 4402 FIELD_PREP(FDMA_INTR_ERR_INTR_CH_ERR, x) 4403 #define FDMA_INTR_ERR_INTR_CH_ERR_GET(x)\ 4404 FIELD_GET(FDMA_INTR_ERR_INTR_CH_ERR, x) 4405 4406 /* FDMA:FDMA:FDMA_ERRORS */ 4407 #define FDMA_ERRORS __REG(TARGET_FDMA,\ 4408 0, 1, 8, 0, 1, 428, 412, 0, 1, 4) 4409 4410 #define FDMA_ERRORS_ERR_XTR_WR GENMASK(31, 30) 4411 #define FDMA_ERRORS_ERR_XTR_WR_SET(x)\ 4412 FIELD_PREP(FDMA_ERRORS_ERR_XTR_WR, x) 4413 #define FDMA_ERRORS_ERR_XTR_WR_GET(x)\ 4414 FIELD_GET(FDMA_ERRORS_ERR_XTR_WR, x) 4415 4416 #define FDMA_ERRORS_ERR_XTR_OVF GENMASK(29, 28) 4417 #define FDMA_ERRORS_ERR_XTR_OVF_SET(x)\ 4418 FIELD_PREP(FDMA_ERRORS_ERR_XTR_OVF, x) 4419 #define FDMA_ERRORS_ERR_XTR_OVF_GET(x)\ 4420 FIELD_GET(FDMA_ERRORS_ERR_XTR_OVF, x) 4421 4422 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF GENMASK(27, 26) 4423 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_SET(x)\ 4424 FIELD_PREP(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x) 4425 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_GET(x)\ 4426 FIELD_GET(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x) 4427 4428 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL GENMASK(25, 24) 4429 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_SET(x)\ 4430 FIELD_PREP(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x) 4431 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_GET(x)\ 4432 FIELD_GET(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x) 4433 4434 #define FDMA_ERRORS_ERR_DCB_RD GENMASK(23, 16) 4435 #define FDMA_ERRORS_ERR_DCB_RD_SET(x)\ 4436 FIELD_PREP(FDMA_ERRORS_ERR_DCB_RD, x) 4437 #define FDMA_ERRORS_ERR_DCB_RD_GET(x)\ 4438 FIELD_GET(FDMA_ERRORS_ERR_DCB_RD, x) 4439 4440 #define FDMA_ERRORS_ERR_INJ_RD GENMASK(15, 10) 4441 #define FDMA_ERRORS_ERR_INJ_RD_SET(x)\ 4442 FIELD_PREP(FDMA_ERRORS_ERR_INJ_RD, x) 4443 #define FDMA_ERRORS_ERR_INJ_RD_GET(x)\ 4444 FIELD_GET(FDMA_ERRORS_ERR_INJ_RD, x) 4445 4446 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC GENMASK(9, 8) 4447 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_SET(x)\ 4448 FIELD_PREP(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x) 4449 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_GET(x)\ 4450 FIELD_GET(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x) 4451 4452 #define FDMA_ERRORS_ERR_CH_WR GENMASK(7, 0) 4453 #define FDMA_ERRORS_ERR_CH_WR_SET(x)\ 4454 FIELD_PREP(FDMA_ERRORS_ERR_CH_WR, x) 4455 #define FDMA_ERRORS_ERR_CH_WR_GET(x)\ 4456 FIELD_GET(FDMA_ERRORS_ERR_CH_WR, x) 4457 4458 /* FDMA:FDMA:FDMA_ERRORS_2 */ 4459 #define FDMA_ERRORS_2 __REG(TARGET_FDMA,\ 4460 0, 1, 8, 0, 1, 428, 416, 0, 1, 4) 4461 4462 #define FDMA_ERRORS_2_ERR_XTR_FRAG GENMASK(1, 0) 4463 #define FDMA_ERRORS_2_ERR_XTR_FRAG_SET(x)\ 4464 FIELD_PREP(FDMA_ERRORS_2_ERR_XTR_FRAG, x) 4465 #define FDMA_ERRORS_2_ERR_XTR_FRAG_GET(x)\ 4466 FIELD_GET(FDMA_ERRORS_2_ERR_XTR_FRAG, x) 4467 4468 /* FDMA:FDMA:FDMA_CTRL */ 4469 #define FDMA_CTRL __REG(TARGET_FDMA,\ 4470 0, 1, 8, 0, 1, 428, 424, 0, 1, 4) 4471 4472 #define FDMA_CTRL_NRESET BIT(0) 4473 #define FDMA_CTRL_NRESET_SET(x)\ 4474 FIELD_PREP(FDMA_CTRL_NRESET, x) 4475 #define FDMA_CTRL_NRESET_GET(x)\ 4476 FIELD_GET(FDMA_CTRL_NRESET, x) 4477 4478 /* DEVCPU_GCB:CHIP_REGS:CHIP_ID */ 4479 #define GCB_CHIP_ID __REG(TARGET_GCB,\ 4480 0, 1, 0, 0, 1, 424, 0, 0, 1, 4) 4481 4482 #define GCB_CHIP_ID_REV_ID GENMASK(31, 28) 4483 #define GCB_CHIP_ID_REV_ID_SET(x)\ 4484 FIELD_PREP(GCB_CHIP_ID_REV_ID, x) 4485 #define GCB_CHIP_ID_REV_ID_GET(x)\ 4486 FIELD_GET(GCB_CHIP_ID_REV_ID, x) 4487 4488 #define GCB_CHIP_ID_PART_ID GENMASK(27, 12) 4489 #define GCB_CHIP_ID_PART_ID_SET(x)\ 4490 FIELD_PREP(GCB_CHIP_ID_PART_ID, x) 4491 #define GCB_CHIP_ID_PART_ID_GET(x)\ 4492 FIELD_GET(GCB_CHIP_ID_PART_ID, x) 4493 4494 #define GCB_CHIP_ID_MFG_ID GENMASK(11, 1) 4495 #define GCB_CHIP_ID_MFG_ID_SET(x)\ 4496 FIELD_PREP(GCB_CHIP_ID_MFG_ID, x) 4497 #define GCB_CHIP_ID_MFG_ID_GET(x)\ 4498 FIELD_GET(GCB_CHIP_ID_MFG_ID, x) 4499 4500 #define GCB_CHIP_ID_ONE BIT(0) 4501 #define GCB_CHIP_ID_ONE_SET(x)\ 4502 FIELD_PREP(GCB_CHIP_ID_ONE, x) 4503 #define GCB_CHIP_ID_ONE_GET(x)\ 4504 FIELD_GET(GCB_CHIP_ID_ONE, x) 4505 4506 /* DEVCPU_GCB:CHIP_REGS:SOFT_RST */ 4507 #define GCB_SOFT_RST __REG(TARGET_GCB,\ 4508 0, 1, 0, 0, 1, 424, 8, 0, 1, 4) 4509 4510 #define GCB_SOFT_RST_SOFT_NON_CFG_RST BIT(2) 4511 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_SET(x)\ 4512 FIELD_PREP(GCB_SOFT_RST_SOFT_NON_CFG_RST, x) 4513 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_GET(x)\ 4514 FIELD_GET(GCB_SOFT_RST_SOFT_NON_CFG_RST, x) 4515 4516 #define GCB_SOFT_RST_SOFT_SWC_RST BIT(1) 4517 #define GCB_SOFT_RST_SOFT_SWC_RST_SET(x)\ 4518 FIELD_PREP(GCB_SOFT_RST_SOFT_SWC_RST, x) 4519 #define GCB_SOFT_RST_SOFT_SWC_RST_GET(x)\ 4520 FIELD_GET(GCB_SOFT_RST_SOFT_SWC_RST, x) 4521 4522 #define GCB_SOFT_RST_SOFT_CHIP_RST BIT(0) 4523 #define GCB_SOFT_RST_SOFT_CHIP_RST_SET(x)\ 4524 FIELD_PREP(GCB_SOFT_RST_SOFT_CHIP_RST, x) 4525 #define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\ 4526 FIELD_GET(GCB_SOFT_RST_SOFT_CHIP_RST, x) 4527 4528 /* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_SD_CFG */ 4529 #define GCB_HW_SGPIO_SD_CFG __REG(TARGET_GCB,\ 4530 0, 1, 0, 0, 1, 424, 20, 0, 1, 4) 4531 4532 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA BIT(1) 4533 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_SET(x)\ 4534 FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x) 4535 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_GET(x)\ 4536 FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x) 4537 4538 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL BIT(0) 4539 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_SET(x)\ 4540 FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x) 4541 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_GET(x)\ 4542 FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x) 4543 4544 /* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_TO_SD_MAP_CFG */ 4545 #define GCB_HW_SGPIO_TO_SD_MAP_CFG(r) __REG(TARGET_GCB,\ 4546 0, 1, 0, 0, 1, 424, 24, r, 65, 4) 4547 4548 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL GENMASK(8, 0) 4549 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_SET(x)\ 4550 FIELD_PREP(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) 4551 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_GET(x)\ 4552 FIELD_GET(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) 4553 4554 /* DEVCPU_GCB:SIO_CTRL:SIO_CLOCK */ 4555 #define GCB_SIO_CLOCK(g) __REG(TARGET_GCB,\ 4556 0, 1, 876, g, 3, 280, 20, 0, 1, 4) 4557 4558 #define GCB_SIO_CLOCK_SIO_CLK_FREQ GENMASK(19, 8) 4559 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_SET(x)\ 4560 FIELD_PREP(GCB_SIO_CLOCK_SIO_CLK_FREQ, x) 4561 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_GET(x)\ 4562 FIELD_GET(GCB_SIO_CLOCK_SIO_CLK_FREQ, x) 4563 4564 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD GENMASK(7, 0) 4565 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(x)\ 4566 FIELD_PREP(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x) 4567 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_GET(x)\ 4568 FIELD_GET(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x) 4569 4570 /* HSCH:HSCH_CFG:CIR_CFG */ 4571 #define HSCH_CIR_CFG(g) __REG(TARGET_HSCH,\ 4572 0, 1, 0, g, 5040, 32, 0, 0, 1, 4) 4573 4574 #define HSCH_CIR_CFG_CIR_RATE GENMASK(22, 6) 4575 #define HSCH_CIR_CFG_CIR_RATE_SET(x)\ 4576 FIELD_PREP(HSCH_CIR_CFG_CIR_RATE, x) 4577 #define HSCH_CIR_CFG_CIR_RATE_GET(x)\ 4578 FIELD_GET(HSCH_CIR_CFG_CIR_RATE, x) 4579 4580 #define HSCH_CIR_CFG_CIR_BURST GENMASK(5, 0) 4581 #define HSCH_CIR_CFG_CIR_BURST_SET(x)\ 4582 FIELD_PREP(HSCH_CIR_CFG_CIR_BURST, x) 4583 #define HSCH_CIR_CFG_CIR_BURST_GET(x)\ 4584 FIELD_GET(HSCH_CIR_CFG_CIR_BURST, x) 4585 4586 /* HSCH:HSCH_CFG:EIR_CFG */ 4587 #define HSCH_EIR_CFG(g) __REG(TARGET_HSCH,\ 4588 0, 1, 0, g, 5040, 32, 4, 0, 1, 4) 4589 4590 #define HSCH_EIR_CFG_EIR_RATE GENMASK(22, 6) 4591 #define HSCH_EIR_CFG_EIR_RATE_SET(x)\ 4592 FIELD_PREP(HSCH_EIR_CFG_EIR_RATE, x) 4593 #define HSCH_EIR_CFG_EIR_RATE_GET(x)\ 4594 FIELD_GET(HSCH_EIR_CFG_EIR_RATE, x) 4595 4596 #define HSCH_EIR_CFG_EIR_BURST GENMASK(5, 0) 4597 #define HSCH_EIR_CFG_EIR_BURST_SET(x)\ 4598 FIELD_PREP(HSCH_EIR_CFG_EIR_BURST, x) 4599 #define HSCH_EIR_CFG_EIR_BURST_GET(x)\ 4600 FIELD_GET(HSCH_EIR_CFG_EIR_BURST, x) 4601 4602 /* HSCH:HSCH_CFG:SE_CFG */ 4603 #define HSCH_SE_CFG(g) __REG(TARGET_HSCH,\ 4604 0, 1, 0, g, 5040, 32, 8, 0, 1, 4) 4605 4606 #define HSCH_SE_CFG_SE_DWRR_CNT GENMASK(12, 6) 4607 #define HSCH_SE_CFG_SE_DWRR_CNT_SET(x)\ 4608 FIELD_PREP(HSCH_SE_CFG_SE_DWRR_CNT, x) 4609 #define HSCH_SE_CFG_SE_DWRR_CNT_GET(x)\ 4610 FIELD_GET(HSCH_SE_CFG_SE_DWRR_CNT, x) 4611 4612 #define HSCH_SE_CFG_SE_AVB_ENA BIT(5) 4613 #define HSCH_SE_CFG_SE_AVB_ENA_SET(x)\ 4614 FIELD_PREP(HSCH_SE_CFG_SE_AVB_ENA, x) 4615 #define HSCH_SE_CFG_SE_AVB_ENA_GET(x)\ 4616 FIELD_GET(HSCH_SE_CFG_SE_AVB_ENA, x) 4617 4618 #define HSCH_SE_CFG_SE_FRM_MODE GENMASK(4, 3) 4619 #define HSCH_SE_CFG_SE_FRM_MODE_SET(x)\ 4620 FIELD_PREP(HSCH_SE_CFG_SE_FRM_MODE, x) 4621 #define HSCH_SE_CFG_SE_FRM_MODE_GET(x)\ 4622 FIELD_GET(HSCH_SE_CFG_SE_FRM_MODE, x) 4623 4624 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE GENMASK(2, 1) 4625 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_SET(x)\ 4626 FIELD_PREP(HSCH_SE_CFG_SE_DWRR_FRM_MODE, x) 4627 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_GET(x)\ 4628 FIELD_GET(HSCH_SE_CFG_SE_DWRR_FRM_MODE, x) 4629 4630 #define HSCH_SE_CFG_SE_STOP BIT(0) 4631 #define HSCH_SE_CFG_SE_STOP_SET(x)\ 4632 FIELD_PREP(HSCH_SE_CFG_SE_STOP, x) 4633 #define HSCH_SE_CFG_SE_STOP_GET(x)\ 4634 FIELD_GET(HSCH_SE_CFG_SE_STOP, x) 4635 4636 /* HSCH:HSCH_CFG:SE_CONNECT */ 4637 #define HSCH_SE_CONNECT(g) __REG(TARGET_HSCH,\ 4638 0, 1, 0, g, 5040, 32, 12, 0, 1, 4) 4639 4640 #define HSCH_SE_CONNECT_SE_LEAK_LINK GENMASK(15, 0) 4641 #define HSCH_SE_CONNECT_SE_LEAK_LINK_SET(x)\ 4642 FIELD_PREP(HSCH_SE_CONNECT_SE_LEAK_LINK, x) 4643 #define HSCH_SE_CONNECT_SE_LEAK_LINK_GET(x)\ 4644 FIELD_GET(HSCH_SE_CONNECT_SE_LEAK_LINK, x) 4645 4646 /* HSCH:HSCH_CFG:SE_DLB_SENSE */ 4647 #define HSCH_SE_DLB_SENSE(g) __REG(TARGET_HSCH,\ 4648 0, 1, 0, g, 5040, 32, 16, 0, 1, 4) 4649 4650 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO GENMASK(12, 10) 4651 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_SET(x)\ 4652 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x) 4653 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_GET(x)\ 4654 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x) 4655 4656 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT GENMASK(9, 3) 4657 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_SET(x)\ 4658 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) 4659 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_GET(x)\ 4660 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) 4661 4662 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA BIT(2) 4663 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_SET(x)\ 4664 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA, x) 4665 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_GET(x)\ 4666 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA, x) 4667 4668 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA BIT(1) 4669 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_SET(x)\ 4670 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA, x) 4671 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_GET(x)\ 4672 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA, x) 4673 4674 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA BIT(0) 4675 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_SET(x)\ 4676 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x) 4677 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_GET(x)\ 4678 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x) 4679 4680 /* HSCH:HSCH_DWRR:DWRR_ENTRY */ 4681 #define HSCH_DWRR_ENTRY(g) __REG(TARGET_HSCH,\ 4682 0, 1, 162816, g, 72, 4, 0, 0, 1, 4) 4683 4684 #define HSCH_DWRR_ENTRY_DWRR_COST GENMASK(24, 20) 4685 #define HSCH_DWRR_ENTRY_DWRR_COST_SET(x)\ 4686 FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_COST, x) 4687 #define HSCH_DWRR_ENTRY_DWRR_COST_GET(x)\ 4688 FIELD_GET(HSCH_DWRR_ENTRY_DWRR_COST, x) 4689 4690 #define HSCH_DWRR_ENTRY_DWRR_BALANCE GENMASK(19, 0) 4691 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_SET(x)\ 4692 FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_BALANCE, x) 4693 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_GET(x)\ 4694 FIELD_GET(HSCH_DWRR_ENTRY_DWRR_BALANCE, x) 4695 4696 /* HSCH:HSCH_MISC:HSCH_CFG_CFG */ 4697 #define HSCH_HSCH_CFG_CFG __REG(TARGET_HSCH,\ 4698 0, 1, 163104, 0, 1, 648, 284, 0, 1, 4) 4699 4700 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX GENMASK(26, 14) 4701 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(x)\ 4702 FIELD_PREP(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) 4703 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_GET(x)\ 4704 FIELD_GET(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) 4705 4706 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER GENMASK(13, 12) 4707 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(x)\ 4708 FIELD_PREP(HSCH_HSCH_CFG_CFG_HSCH_LAYER, x) 4709 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_GET(x)\ 4710 FIELD_GET(HSCH_HSCH_CFG_CFG_HSCH_LAYER, x) 4711 4712 #define HSCH_HSCH_CFG_CFG_CSR_GRANT GENMASK(11, 0) 4713 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_SET(x)\ 4714 FIELD_PREP(HSCH_HSCH_CFG_CFG_CSR_GRANT, x) 4715 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_GET(x)\ 4716 FIELD_GET(HSCH_HSCH_CFG_CFG_CSR_GRANT, x) 4717 4718 /* HSCH:HSCH_MISC:SYS_CLK_PER */ 4719 #define HSCH_SYS_CLK_PER __REG(TARGET_HSCH,\ 4720 0, 1, 163104, 0, 1, 648, 640, 0, 1, 4) 4721 4722 #define HSCH_SYS_CLK_PER_100PS GENMASK(7, 0) 4723 #define HSCH_SYS_CLK_PER_100PS_SET(x)\ 4724 FIELD_PREP(HSCH_SYS_CLK_PER_100PS, x) 4725 #define HSCH_SYS_CLK_PER_100PS_GET(x)\ 4726 FIELD_GET(HSCH_SYS_CLK_PER_100PS, x) 4727 4728 /* HSCH:HSCH_LEAK_LISTS:HSCH_TIMER_CFG */ 4729 #define HSCH_HSCH_TIMER_CFG(g, r) __REG(TARGET_HSCH,\ 4730 0, 1, 161664, g, 4, 32, 0, r, 4, 4) 4731 4732 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME GENMASK(17, 0) 4733 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(x)\ 4734 FIELD_PREP(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x) 4735 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_GET(x)\ 4736 FIELD_GET(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x) 4737 4738 /* HSCH:HSCH_LEAK_LISTS:HSCH_LEAK_CFG */ 4739 #define HSCH_HSCH_LEAK_CFG(g, r) __REG(TARGET_HSCH,\ 4740 0, 1, 161664, g, 4, 32, 16, r, 4, 4) 4741 4742 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST GENMASK(16, 1) 4743 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(x)\ 4744 FIELD_PREP(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) 4745 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_GET(x)\ 4746 FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) 4747 4748 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR BIT(0) 4749 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_SET(x)\ 4750 FIELD_PREP(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x) 4751 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_GET(x)\ 4752 FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x) 4753 4754 /* HSCH:SYSTEM:FLUSH_CTRL */ 4755 #define HSCH_FLUSH_CTRL __REG(TARGET_HSCH,\ 4756 0, 1, 184000, 0, 1, 312, 4, 0, 1, 4) 4757 4758 #define HSCH_FLUSH_CTRL_FLUSH_ENA BIT(27) 4759 #define HSCH_FLUSH_CTRL_FLUSH_ENA_SET(x)\ 4760 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_ENA, x) 4761 #define HSCH_FLUSH_CTRL_FLUSH_ENA_GET(x)\ 4762 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_ENA, x) 4763 4764 #define HSCH_FLUSH_CTRL_FLUSH_SRC BIT(26) 4765 #define HSCH_FLUSH_CTRL_FLUSH_SRC_SET(x)\ 4766 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SRC, x) 4767 #define HSCH_FLUSH_CTRL_FLUSH_SRC_GET(x)\ 4768 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SRC, x) 4769 4770 #define HSCH_FLUSH_CTRL_FLUSH_DST BIT(25) 4771 #define HSCH_FLUSH_CTRL_FLUSH_DST_SET(x)\ 4772 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_DST, x) 4773 #define HSCH_FLUSH_CTRL_FLUSH_DST_GET(x)\ 4774 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_DST, x) 4775 4776 #define HSCH_FLUSH_CTRL_FLUSH_PORT GENMASK(24, 18) 4777 #define HSCH_FLUSH_CTRL_FLUSH_PORT_SET(x)\ 4778 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_PORT, x) 4779 #define HSCH_FLUSH_CTRL_FLUSH_PORT_GET(x)\ 4780 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_PORT, x) 4781 4782 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE BIT(17) 4783 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_SET(x)\ 4784 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x) 4785 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_GET(x)\ 4786 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x) 4787 4788 #define HSCH_FLUSH_CTRL_FLUSH_SE BIT(16) 4789 #define HSCH_FLUSH_CTRL_FLUSH_SE_SET(x)\ 4790 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SE, x) 4791 #define HSCH_FLUSH_CTRL_FLUSH_SE_GET(x)\ 4792 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SE, x) 4793 4794 #define HSCH_FLUSH_CTRL_FLUSH_HIER GENMASK(15, 0) 4795 #define HSCH_FLUSH_CTRL_FLUSH_HIER_SET(x)\ 4796 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_HIER, x) 4797 #define HSCH_FLUSH_CTRL_FLUSH_HIER_GET(x)\ 4798 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_HIER, x) 4799 4800 /* HSCH:SYSTEM:PORT_MODE */ 4801 #define HSCH_PORT_MODE(r) __REG(TARGET_HSCH,\ 4802 0, 1, 184000, 0, 1, 312, 8, r, 70, 4) 4803 4804 #define HSCH_PORT_MODE_DEQUEUE_DIS BIT(4) 4805 #define HSCH_PORT_MODE_DEQUEUE_DIS_SET(x)\ 4806 FIELD_PREP(HSCH_PORT_MODE_DEQUEUE_DIS, x) 4807 #define HSCH_PORT_MODE_DEQUEUE_DIS_GET(x)\ 4808 FIELD_GET(HSCH_PORT_MODE_DEQUEUE_DIS, x) 4809 4810 #define HSCH_PORT_MODE_AGE_DIS BIT(3) 4811 #define HSCH_PORT_MODE_AGE_DIS_SET(x)\ 4812 FIELD_PREP(HSCH_PORT_MODE_AGE_DIS, x) 4813 #define HSCH_PORT_MODE_AGE_DIS_GET(x)\ 4814 FIELD_GET(HSCH_PORT_MODE_AGE_DIS, x) 4815 4816 #define HSCH_PORT_MODE_TRUNC_ENA BIT(2) 4817 #define HSCH_PORT_MODE_TRUNC_ENA_SET(x)\ 4818 FIELD_PREP(HSCH_PORT_MODE_TRUNC_ENA, x) 4819 #define HSCH_PORT_MODE_TRUNC_ENA_GET(x)\ 4820 FIELD_GET(HSCH_PORT_MODE_TRUNC_ENA, x) 4821 4822 #define HSCH_PORT_MODE_EIR_REMARK_ENA BIT(1) 4823 #define HSCH_PORT_MODE_EIR_REMARK_ENA_SET(x)\ 4824 FIELD_PREP(HSCH_PORT_MODE_EIR_REMARK_ENA, x) 4825 #define HSCH_PORT_MODE_EIR_REMARK_ENA_GET(x)\ 4826 FIELD_GET(HSCH_PORT_MODE_EIR_REMARK_ENA, x) 4827 4828 #define HSCH_PORT_MODE_CPU_PRIO_MODE BIT(0) 4829 #define HSCH_PORT_MODE_CPU_PRIO_MODE_SET(x)\ 4830 FIELD_PREP(HSCH_PORT_MODE_CPU_PRIO_MODE, x) 4831 #define HSCH_PORT_MODE_CPU_PRIO_MODE_GET(x)\ 4832 FIELD_GET(HSCH_PORT_MODE_CPU_PRIO_MODE, x) 4833 4834 /* HSCH:SYSTEM:OUTB_SHARE_ENA */ 4835 #define HSCH_OUTB_SHARE_ENA(r) __REG(TARGET_HSCH,\ 4836 0, 1, 184000, 0, 1, 312, 288, r, 5, 4) 4837 4838 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA GENMASK(7, 0) 4839 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(x)\ 4840 FIELD_PREP(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x) 4841 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_GET(x)\ 4842 FIELD_GET(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x) 4843 4844 /* HSCH:MMGT:RESET_CFG */ 4845 #define HSCH_RESET_CFG __REG(TARGET_HSCH,\ 4846 0, 1, 162368, 0, 1, 16, 8, 0, 1, 4) 4847 4848 #define HSCH_RESET_CFG_CORE_ENA BIT(0) 4849 #define HSCH_RESET_CFG_CORE_ENA_SET(x)\ 4850 FIELD_PREP(HSCH_RESET_CFG_CORE_ENA, x) 4851 #define HSCH_RESET_CFG_CORE_ENA_GET(x)\ 4852 FIELD_GET(HSCH_RESET_CFG_CORE_ENA, x) 4853 4854 /* HSCH:TAS_CONFIG:TAS_STATEMACHINE_CFG */ 4855 #define HSCH_TAS_STATEMACHINE_CFG __REG(TARGET_HSCH,\ 4856 0, 1, 162384, 0, 1, 12, 8, 0, 1, 4) 4857 4858 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY GENMASK(7, 0) 4859 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET(x)\ 4860 FIELD_PREP(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x) 4861 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\ 4862 FIELD_GET(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x) 4863 4864 /* LRN:COMMON:COMMON_ACCESS_CTRL */ 4865 #define LRN_COMMON_ACCESS_CTRL __REG(TARGET_LRN,\ 4866 0, 1, 0, 0, 1, 72, 0, 0, 1, 4) 4867 4868 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL GENMASK(21, 20) 4869 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_SET(x)\ 4870 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x) 4871 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_GET(x)\ 4872 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x) 4873 4874 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE BIT(19) 4875 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_SET(x)\ 4876 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x) 4877 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_GET(x)\ 4878 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x) 4879 4880 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW GENMASK(18, 5) 4881 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_SET(x)\ 4882 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) 4883 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_GET(x)\ 4884 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) 4885 4886 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD GENMASK(4, 1) 4887 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x)\ 4888 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x) 4889 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_GET(x)\ 4890 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x) 4891 4892 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT BIT(0) 4893 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(x)\ 4894 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x) 4895 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x)\ 4896 FIELD_GET(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x) 4897 4898 /* LRN:COMMON:MAC_ACCESS_CFG_0 */ 4899 #define LRN_MAC_ACCESS_CFG_0 __REG(TARGET_LRN,\ 4900 0, 1, 0, 0, 1, 72, 4, 0, 1, 4) 4901 4902 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID GENMASK(28, 16) 4903 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_SET(x)\ 4904 FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x) 4905 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_GET(x)\ 4906 FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x) 4907 4908 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB GENMASK(15, 0) 4909 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_SET(x)\ 4910 FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x) 4911 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_GET(x)\ 4912 FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x) 4913 4914 /* LRN:COMMON:MAC_ACCESS_CFG_1 */ 4915 #define LRN_MAC_ACCESS_CFG_1 __REG(TARGET_LRN,\ 4916 0, 1, 0, 0, 1, 72, 8, 0, 1, 4) 4917 4918 /* LRN:COMMON:MAC_ACCESS_CFG_2 */ 4919 #define LRN_MAC_ACCESS_CFG_2 __REG(TARGET_LRN,\ 4920 0, 1, 0, 0, 1, 72, 12, 0, 1, 4) 4921 4922 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD BIT(28) 4923 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_SET(x)\ 4924 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x) 4925 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_GET(x)\ 4926 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x) 4927 4928 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL BIT(27) 4929 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_SET(x)\ 4930 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x) 4931 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_GET(x)\ 4932 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x) 4933 4934 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU GENMASK(26, 24) 4935 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(x)\ 4936 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x) 4937 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_GET(x)\ 4938 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x) 4939 4940 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY BIT(23) 4941 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(x)\ 4942 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x) 4943 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_GET(x)\ 4944 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x) 4945 4946 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE BIT(22) 4947 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_SET(x)\ 4948 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x) 4949 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_GET(x)\ 4950 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x) 4951 4952 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR BIT(21) 4953 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_SET(x)\ 4954 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x) 4955 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_GET(x)\ 4956 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x) 4957 4958 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG GENMASK(20, 19) 4959 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_SET(x)\ 4960 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x) 4961 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_GET(x)\ 4962 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x) 4963 4964 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL GENMASK(18, 17) 4965 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_SET(x)\ 4966 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x) 4967 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_GET(x)\ 4968 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x) 4969 4970 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED BIT(16) 4971 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(x)\ 4972 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x) 4973 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_GET(x)\ 4974 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x) 4975 4976 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD BIT(15) 4977 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(x)\ 4978 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x) 4979 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(x)\ 4980 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x) 4981 4982 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE GENMASK(14, 12) 4983 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(x)\ 4984 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x) 4985 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_GET(x)\ 4986 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x) 4987 4988 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR GENMASK(11, 0) 4989 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(x)\ 4990 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x) 4991 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x)\ 4992 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x) 4993 4994 /* LRN:COMMON:MAC_ACCESS_CFG_3 */ 4995 #define LRN_MAC_ACCESS_CFG_3 __REG(TARGET_LRN,\ 4996 0, 1, 0, 0, 1, 72, 16, 0, 1, 4) 4997 4998 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX GENMASK(10, 0) 4999 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x)\ 5000 FIELD_PREP(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) 5001 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x)\ 5002 FIELD_GET(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) 5003 5004 /* LRN:COMMON:SCAN_NEXT_CFG */ 5005 #define LRN_SCAN_NEXT_CFG __REG(TARGET_LRN,\ 5006 0, 1, 0, 0, 1, 72, 20, 0, 1, 4) 5007 5008 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL GENMASK(21, 19) 5009 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_SET(x)\ 5010 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x) 5011 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_GET(x)\ 5012 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x) 5013 5014 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL GENMASK(18, 17) 5015 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_SET(x)\ 5016 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x) 5017 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_GET(x)\ 5018 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x) 5019 5020 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL GENMASK(16, 15) 5021 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_SET(x)\ 5022 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x) 5023 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_GET(x)\ 5024 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x) 5025 5026 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA BIT(14) 5027 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_SET(x)\ 5028 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x) 5029 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_GET(x)\ 5030 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x) 5031 5032 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA BIT(13) 5033 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_SET(x)\ 5034 FIELD_PREP(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x) 5035 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_GET(x)\ 5036 FIELD_GET(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x) 5037 5038 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA BIT(12) 5039 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_SET(x)\ 5040 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x) 5041 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_GET(x)\ 5042 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x) 5043 5044 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA BIT(11) 5045 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_SET(x)\ 5046 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x) 5047 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_GET(x)\ 5048 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x) 5049 5050 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA BIT(10) 5051 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(x)\ 5052 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x) 5053 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_GET(x)\ 5054 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x) 5055 5056 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA BIT(9) 5057 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_SET(x)\ 5058 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x) 5059 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_GET(x)\ 5060 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x) 5061 5062 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA BIT(8) 5063 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_SET(x)\ 5064 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x) 5065 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_GET(x)\ 5066 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x) 5067 5068 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA BIT(7) 5069 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(x)\ 5070 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x) 5071 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_GET(x)\ 5072 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x) 5073 5074 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK GENMASK(6, 3) 5075 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_SET(x)\ 5076 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x) 5077 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_GET(x)\ 5078 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x) 5079 5080 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA BIT(2) 5081 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_SET(x)\ 5082 FIELD_PREP(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x) 5083 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_GET(x)\ 5084 FIELD_GET(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x) 5085 5086 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA BIT(1) 5087 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_SET(x)\ 5088 FIELD_PREP(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x) 5089 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_GET(x)\ 5090 FIELD_GET(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x) 5091 5092 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA BIT(0) 5093 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_SET(x)\ 5094 FIELD_PREP(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x) 5095 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_GET(x)\ 5096 FIELD_GET(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x) 5097 5098 /* LRN:COMMON:SCAN_NEXT_CFG_1 */ 5099 #define LRN_SCAN_NEXT_CFG_1 __REG(TARGET_LRN,\ 5100 0, 1, 0, 0, 1, 72, 24, 0, 1, 4) 5101 5102 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR GENMASK(30, 16) 5103 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_SET(x)\ 5104 FIELD_PREP(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x) 5105 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_GET(x)\ 5106 FIELD_GET(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x) 5107 5108 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK GENMASK(14, 0) 5109 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_SET(x)\ 5110 FIELD_PREP(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x) 5111 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_GET(x)\ 5112 FIELD_GET(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x) 5113 5114 /* LRN:COMMON:AUTOAGE_CFG */ 5115 #define LRN_AUTOAGE_CFG(r) __REG(TARGET_LRN,\ 5116 0, 1, 0, 0, 1, 72, 36, r, 4, 4) 5117 5118 #define LRN_AUTOAGE_CFG_UNIT_SIZE GENMASK(29, 28) 5119 #define LRN_AUTOAGE_CFG_UNIT_SIZE_SET(x)\ 5120 FIELD_PREP(LRN_AUTOAGE_CFG_UNIT_SIZE, x) 5121 #define LRN_AUTOAGE_CFG_UNIT_SIZE_GET(x)\ 5122 FIELD_GET(LRN_AUTOAGE_CFG_UNIT_SIZE, x) 5123 5124 #define LRN_AUTOAGE_CFG_PERIOD_VAL GENMASK(27, 0) 5125 #define LRN_AUTOAGE_CFG_PERIOD_VAL_SET(x)\ 5126 FIELD_PREP(LRN_AUTOAGE_CFG_PERIOD_VAL, x) 5127 #define LRN_AUTOAGE_CFG_PERIOD_VAL_GET(x)\ 5128 FIELD_GET(LRN_AUTOAGE_CFG_PERIOD_VAL, x) 5129 5130 /* LRN:COMMON:AUTOAGE_CFG_1 */ 5131 #define LRN_AUTOAGE_CFG_1 __REG(TARGET_LRN,\ 5132 0, 1, 0, 0, 1, 72, 52, 0, 1, 4) 5133 5134 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA BIT(25) 5135 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_SET(x)\ 5136 FIELD_PREP(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x) 5137 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_GET(x)\ 5138 FIELD_GET(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x) 5139 5140 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN GENMASK(24, 15) 5141 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_SET(x)\ 5142 FIELD_PREP(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x) 5143 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_GET(x)\ 5144 FIELD_GET(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x) 5145 5146 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS GENMASK(14, 7) 5147 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(x)\ 5148 FIELD_PREP(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x) 5149 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_GET(x)\ 5150 FIELD_GET(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x) 5151 5152 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA BIT(6) 5153 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_SET(x)\ 5154 FIELD_PREP(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x) 5155 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_GET(x)\ 5156 FIELD_GET(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x) 5157 5158 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT GENMASK(5, 2) 5159 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_SET(x)\ 5160 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x) 5161 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_GET(x)\ 5162 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x) 5163 5164 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT BIT(1) 5165 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_SET(x)\ 5166 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x) 5167 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_GET(x)\ 5168 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x) 5169 5170 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA BIT(0) 5171 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_SET(x)\ 5172 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x) 5173 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_GET(x)\ 5174 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x) 5175 5176 /* LRN:COMMON:AUTOAGE_CFG_2 */ 5177 #define LRN_AUTOAGE_CFG_2 __REG(TARGET_LRN,\ 5178 0, 1, 0, 0, 1, 72, 56, 0, 1, 4) 5179 5180 #define LRN_AUTOAGE_CFG_2_NEXT_ROW GENMASK(17, 4) 5181 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_SET(x)\ 5182 FIELD_PREP(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) 5183 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_GET(x)\ 5184 FIELD_GET(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) 5185 5186 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS GENMASK(3, 0) 5187 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_SET(x)\ 5188 FIELD_PREP(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x) 5189 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_GET(x)\ 5190 FIELD_GET(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x) 5191 5192 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_OUTBOUND_0 */ 5193 #define PCEP_RCTRL_2_OUT_0 __REG(TARGET_PCEP,\ 5194 0, 1, 3145728, 0, 1, 130852, 4, 0, 1, 4) 5195 5196 #define PCEP_RCTRL_2_OUT_0_MSG_CODE GENMASK(7, 0) 5197 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_SET(x)\ 5198 FIELD_PREP(PCEP_RCTRL_2_OUT_0_MSG_CODE, x) 5199 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_GET(x)\ 5200 FIELD_GET(PCEP_RCTRL_2_OUT_0_MSG_CODE, x) 5201 5202 #define PCEP_RCTRL_2_OUT_0_TAG GENMASK(15, 8) 5203 #define PCEP_RCTRL_2_OUT_0_TAG_SET(x)\ 5204 FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG, x) 5205 #define PCEP_RCTRL_2_OUT_0_TAG_GET(x)\ 5206 FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG, x) 5207 5208 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN BIT(16) 5209 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_SET(x)\ 5210 FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x) 5211 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_GET(x)\ 5212 FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x) 5213 5214 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS BIT(19) 5215 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_SET(x)\ 5216 FIELD_PREP(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x) 5217 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_GET(x)\ 5218 FIELD_GET(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x) 5219 5220 #define PCEP_RCTRL_2_OUT_0_SNP BIT(20) 5221 #define PCEP_RCTRL_2_OUT_0_SNP_SET(x)\ 5222 FIELD_PREP(PCEP_RCTRL_2_OUT_0_SNP, x) 5223 #define PCEP_RCTRL_2_OUT_0_SNP_GET(x)\ 5224 FIELD_GET(PCEP_RCTRL_2_OUT_0_SNP, x) 5225 5226 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD BIT(22) 5227 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_SET(x)\ 5228 FIELD_PREP(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x) 5229 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_GET(x)\ 5230 FIELD_GET(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x) 5231 5232 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN BIT(23) 5233 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_SET(x)\ 5234 FIELD_PREP(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x) 5235 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_GET(x)\ 5236 FIELD_GET(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x) 5237 5238 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE BIT(28) 5239 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_SET(x)\ 5240 FIELD_PREP(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x) 5241 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_GET(x)\ 5242 FIELD_GET(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x) 5243 5244 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE BIT(29) 5245 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_SET(x)\ 5246 FIELD_PREP(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x) 5247 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_GET(x)\ 5248 FIELD_GET(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x) 5249 5250 #define PCEP_RCTRL_2_OUT_0_REGION_EN BIT(31) 5251 #define PCEP_RCTRL_2_OUT_0_REGION_EN_SET(x)\ 5252 FIELD_PREP(PCEP_RCTRL_2_OUT_0_REGION_EN, x) 5253 #define PCEP_RCTRL_2_OUT_0_REGION_EN_GET(x)\ 5254 FIELD_GET(PCEP_RCTRL_2_OUT_0_REGION_EN, x) 5255 5256 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 */ 5257 #define PCEP_ADDR_LWR_OUT_0 __REG(TARGET_PCEP,\ 5258 0, 1, 3145728, 0, 1, 130852, 8, 0, 1, 4) 5259 5260 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW GENMASK(15, 0) 5261 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_SET(x)\ 5262 FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x) 5263 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_GET(x)\ 5264 FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x) 5265 5266 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW GENMASK(31, 16) 5267 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_SET(x)\ 5268 FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x) 5269 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_GET(x)\ 5270 FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x) 5271 5272 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 */ 5273 #define PCEP_ADDR_UPR_OUT_0 __REG(TARGET_PCEP,\ 5274 0, 1, 3145728, 0, 1, 130852, 12, 0, 1, 4) 5275 5276 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LIMIT_ADDR_OFF_OUTBOUND_0 */ 5277 #define PCEP_ADDR_LIM_OUT_0 __REG(TARGET_PCEP,\ 5278 0, 1, 3145728, 0, 1, 130852, 16, 0, 1, 4) 5279 5280 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW GENMASK(15, 0) 5281 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_SET(x)\ 5282 FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x) 5283 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_GET(x)\ 5284 FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x) 5285 5286 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW GENMASK(31, 16) 5287 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_SET(x)\ 5288 FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x) 5289 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_GET(x)\ 5290 FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x) 5291 5292 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 */ 5293 #define PCEP_ADDR_LWR_TGT_OUT_0 __REG(TARGET_PCEP,\ 5294 0, 1, 3145728, 0, 1, 130852, 20, 0, 1, 4) 5295 5296 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 */ 5297 #define PCEP_ADDR_UPR_TGT_OUT_0 __REG(TARGET_PCEP,\ 5298 0, 1, 3145728, 0, 1, 130852, 24, 0, 1, 4) 5299 5300 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0 */ 5301 #define PCEP_ADDR_UPR_LIM_OUT_0 __REG(TARGET_PCEP,\ 5302 0, 1, 3145728, 0, 1, 130852, 32, 0, 1, 4) 5303 5304 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW GENMASK(1, 0) 5305 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_SET(x)\ 5306 FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x) 5307 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_GET(x)\ 5308 FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x) 5309 5310 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW GENMASK(31, 2) 5311 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_SET(x)\ 5312 FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x) 5313 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_GET(x)\ 5314 FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x) 5315 5316 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ 5317 #define PCS10G_BR_PCS_CFG(t) __REG(TARGET_PCS10G_BR,\ 5318 t, 12, 0, 0, 1, 56, 0, 0, 1, 4) 5319 5320 #define PCS10G_BR_PCS_CFG_PCS_ENA BIT(31) 5321 #define PCS10G_BR_PCS_CFG_PCS_ENA_SET(x)\ 5322 FIELD_PREP(PCS10G_BR_PCS_CFG_PCS_ENA, x) 5323 #define PCS10G_BR_PCS_CFG_PCS_ENA_GET(x)\ 5324 FIELD_GET(PCS10G_BR_PCS_CFG_PCS_ENA, x) 5325 5326 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA BIT(30) 5327 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\ 5328 FIELD_PREP(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 5329 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\ 5330 FIELD_GET(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 5331 5332 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24) 5333 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\ 5334 FIELD_PREP(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x) 5335 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\ 5336 FIELD_GET(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x) 5337 5338 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP BIT(18) 5339 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\ 5340 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x) 5341 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\ 5342 FIELD_GET(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x) 5343 5344 #define PCS10G_BR_PCS_CFG_RESYNC_ENA BIT(15) 5345 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_SET(x)\ 5346 FIELD_PREP(PCS10G_BR_PCS_CFG_RESYNC_ENA, x) 5347 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_GET(x)\ 5348 FIELD_GET(PCS10G_BR_PCS_CFG_RESYNC_ENA, x) 5349 5350 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS BIT(14) 5351 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\ 5352 FIELD_PREP(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x) 5353 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\ 5354 FIELD_GET(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x) 5355 5356 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE BIT(13) 5357 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\ 5358 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x) 5359 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\ 5360 FIELD_GET(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x) 5361 5362 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE BIT(12) 5363 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\ 5364 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x) 5365 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\ 5366 FIELD_GET(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x) 5367 5368 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP BIT(7) 5369 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\ 5370 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x) 5371 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\ 5372 FIELD_GET(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x) 5373 5374 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA BIT(6) 5375 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\ 5376 FIELD_PREP(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 5377 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\ 5378 FIELD_GET(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 5379 5380 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE BIT(4) 5381 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\ 5382 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x) 5383 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\ 5384 FIELD_GET(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x) 5385 5386 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE BIT(3) 5387 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\ 5388 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x) 5389 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ 5390 FIELD_GET(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x) 5391 5392 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ 5393 #define PCS10G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS10G_BR,\ 5394 t, 12, 0, 0, 1, 56, 4, 0, 1, 4) 5395 5396 #define PCS10G_BR_PCS_SD_CFG_SD_SEL BIT(8) 5397 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ 5398 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_SEL, x) 5399 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_GET(x)\ 5400 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_SEL, x) 5401 5402 #define PCS10G_BR_PCS_SD_CFG_SD_POL BIT(4) 5403 #define PCS10G_BR_PCS_SD_CFG_SD_POL_SET(x)\ 5404 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_POL, x) 5405 #define PCS10G_BR_PCS_SD_CFG_SD_POL_GET(x)\ 5406 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_POL, x) 5407 5408 #define PCS10G_BR_PCS_SD_CFG_SD_ENA BIT(0) 5409 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_SET(x)\ 5410 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_ENA, x) 5411 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ 5412 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_ENA, x) 5413 5414 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ 5415 #define PCS25G_BR_PCS_CFG(t) __REG(TARGET_PCS25G_BR,\ 5416 t, 8, 0, 0, 1, 56, 0, 0, 1, 4) 5417 5418 #define PCS25G_BR_PCS_CFG_PCS_ENA BIT(31) 5419 #define PCS25G_BR_PCS_CFG_PCS_ENA_SET(x)\ 5420 FIELD_PREP(PCS25G_BR_PCS_CFG_PCS_ENA, x) 5421 #define PCS25G_BR_PCS_CFG_PCS_ENA_GET(x)\ 5422 FIELD_GET(PCS25G_BR_PCS_CFG_PCS_ENA, x) 5423 5424 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA BIT(30) 5425 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\ 5426 FIELD_PREP(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 5427 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\ 5428 FIELD_GET(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 5429 5430 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24) 5431 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\ 5432 FIELD_PREP(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x) 5433 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\ 5434 FIELD_GET(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x) 5435 5436 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP BIT(18) 5437 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\ 5438 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x) 5439 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\ 5440 FIELD_GET(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x) 5441 5442 #define PCS25G_BR_PCS_CFG_RESYNC_ENA BIT(15) 5443 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_SET(x)\ 5444 FIELD_PREP(PCS25G_BR_PCS_CFG_RESYNC_ENA, x) 5445 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_GET(x)\ 5446 FIELD_GET(PCS25G_BR_PCS_CFG_RESYNC_ENA, x) 5447 5448 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS BIT(14) 5449 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\ 5450 FIELD_PREP(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x) 5451 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\ 5452 FIELD_GET(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x) 5453 5454 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE BIT(13) 5455 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\ 5456 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x) 5457 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\ 5458 FIELD_GET(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x) 5459 5460 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE BIT(12) 5461 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\ 5462 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x) 5463 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\ 5464 FIELD_GET(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x) 5465 5466 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP BIT(7) 5467 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\ 5468 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x) 5469 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\ 5470 FIELD_GET(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x) 5471 5472 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA BIT(6) 5473 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\ 5474 FIELD_PREP(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 5475 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\ 5476 FIELD_GET(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 5477 5478 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE BIT(4) 5479 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\ 5480 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x) 5481 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\ 5482 FIELD_GET(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x) 5483 5484 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE BIT(3) 5485 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\ 5486 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x) 5487 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ 5488 FIELD_GET(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x) 5489 5490 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ 5491 #define PCS25G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS25G_BR,\ 5492 t, 8, 0, 0, 1, 56, 4, 0, 1, 4) 5493 5494 #define PCS25G_BR_PCS_SD_CFG_SD_SEL BIT(8) 5495 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ 5496 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_SEL, x) 5497 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_GET(x)\ 5498 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_SEL, x) 5499 5500 #define PCS25G_BR_PCS_SD_CFG_SD_POL BIT(4) 5501 #define PCS25G_BR_PCS_SD_CFG_SD_POL_SET(x)\ 5502 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_POL, x) 5503 #define PCS25G_BR_PCS_SD_CFG_SD_POL_GET(x)\ 5504 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_POL, x) 5505 5506 #define PCS25G_BR_PCS_SD_CFG_SD_ENA BIT(0) 5507 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_SET(x)\ 5508 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_ENA, x) 5509 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ 5510 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_ENA, x) 5511 5512 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ 5513 #define PCS5G_BR_PCS_CFG(t) __REG(TARGET_PCS5G_BR,\ 5514 t, 13, 0, 0, 1, 56, 0, 0, 1, 4) 5515 5516 #define PCS5G_BR_PCS_CFG_PCS_ENA BIT(31) 5517 #define PCS5G_BR_PCS_CFG_PCS_ENA_SET(x)\ 5518 FIELD_PREP(PCS5G_BR_PCS_CFG_PCS_ENA, x) 5519 #define PCS5G_BR_PCS_CFG_PCS_ENA_GET(x)\ 5520 FIELD_GET(PCS5G_BR_PCS_CFG_PCS_ENA, x) 5521 5522 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA BIT(30) 5523 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\ 5524 FIELD_PREP(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 5525 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\ 5526 FIELD_GET(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 5527 5528 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24) 5529 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\ 5530 FIELD_PREP(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x) 5531 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\ 5532 FIELD_GET(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x) 5533 5534 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP BIT(18) 5535 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\ 5536 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x) 5537 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\ 5538 FIELD_GET(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x) 5539 5540 #define PCS5G_BR_PCS_CFG_RESYNC_ENA BIT(15) 5541 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_SET(x)\ 5542 FIELD_PREP(PCS5G_BR_PCS_CFG_RESYNC_ENA, x) 5543 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_GET(x)\ 5544 FIELD_GET(PCS5G_BR_PCS_CFG_RESYNC_ENA, x) 5545 5546 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS BIT(14) 5547 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\ 5548 FIELD_PREP(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x) 5549 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\ 5550 FIELD_GET(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x) 5551 5552 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE BIT(13) 5553 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\ 5554 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x) 5555 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\ 5556 FIELD_GET(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x) 5557 5558 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE BIT(12) 5559 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\ 5560 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x) 5561 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\ 5562 FIELD_GET(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x) 5563 5564 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP BIT(7) 5565 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\ 5566 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x) 5567 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\ 5568 FIELD_GET(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x) 5569 5570 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA BIT(6) 5571 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\ 5572 FIELD_PREP(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 5573 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\ 5574 FIELD_GET(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 5575 5576 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE BIT(4) 5577 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\ 5578 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x) 5579 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\ 5580 FIELD_GET(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x) 5581 5582 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE BIT(3) 5583 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\ 5584 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x) 5585 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ 5586 FIELD_GET(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x) 5587 5588 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ 5589 #define PCS5G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS5G_BR,\ 5590 t, 13, 0, 0, 1, 56, 4, 0, 1, 4) 5591 5592 #define PCS5G_BR_PCS_SD_CFG_SD_SEL BIT(8) 5593 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ 5594 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_SEL, x) 5595 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_GET(x)\ 5596 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_SEL, x) 5597 5598 #define PCS5G_BR_PCS_SD_CFG_SD_POL BIT(4) 5599 #define PCS5G_BR_PCS_SD_CFG_SD_POL_SET(x)\ 5600 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_POL, x) 5601 #define PCS5G_BR_PCS_SD_CFG_SD_POL_GET(x)\ 5602 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_POL, x) 5603 5604 #define PCS5G_BR_PCS_SD_CFG_SD_ENA BIT(0) 5605 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_SET(x)\ 5606 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_ENA, x) 5607 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ 5608 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_ENA, x) 5609 5610 /* PORT_CONF:HW_CFG:DEV5G_MODES */ 5611 #define PORT_CONF_DEV5G_MODES __REG(TARGET_PORT_CONF,\ 5612 0, 1, 0, 0, 1, 24, 0, 0, 1, 4) 5613 5614 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE BIT(0) 5615 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_SET(x)\ 5616 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x) 5617 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_GET(x)\ 5618 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x) 5619 5620 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE BIT(1) 5621 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_SET(x)\ 5622 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x) 5623 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_GET(x)\ 5624 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x) 5625 5626 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE BIT(2) 5627 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_SET(x)\ 5628 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x) 5629 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_GET(x)\ 5630 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x) 5631 5632 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE BIT(3) 5633 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_SET(x)\ 5634 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x) 5635 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_GET(x)\ 5636 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x) 5637 5638 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE BIT(4) 5639 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_SET(x)\ 5640 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x) 5641 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_GET(x)\ 5642 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x) 5643 5644 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE BIT(5) 5645 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_SET(x)\ 5646 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x) 5647 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_GET(x)\ 5648 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x) 5649 5650 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE BIT(6) 5651 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_SET(x)\ 5652 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x) 5653 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_GET(x)\ 5654 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x) 5655 5656 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE BIT(7) 5657 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_SET(x)\ 5658 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x) 5659 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_GET(x)\ 5660 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x) 5661 5662 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE BIT(8) 5663 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_SET(x)\ 5664 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x) 5665 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_GET(x)\ 5666 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x) 5667 5668 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE BIT(9) 5669 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_SET(x)\ 5670 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x) 5671 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_GET(x)\ 5672 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x) 5673 5674 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE BIT(10) 5675 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_SET(x)\ 5676 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x) 5677 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_GET(x)\ 5678 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x) 5679 5680 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE BIT(11) 5681 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_SET(x)\ 5682 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x) 5683 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_GET(x)\ 5684 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x) 5685 5686 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE BIT(12) 5687 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x)\ 5688 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x) 5689 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x)\ 5690 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x) 5691 5692 /* PORT_CONF:HW_CFG:DEV10G_MODES */ 5693 #define PORT_CONF_DEV10G_MODES __REG(TARGET_PORT_CONF,\ 5694 0, 1, 0, 0, 1, 24, 4, 0, 1, 4) 5695 5696 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE BIT(0) 5697 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_SET(x)\ 5698 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x) 5699 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_GET(x)\ 5700 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x) 5701 5702 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE BIT(1) 5703 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_SET(x)\ 5704 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x) 5705 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_GET(x)\ 5706 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x) 5707 5708 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE BIT(2) 5709 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_SET(x)\ 5710 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x) 5711 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_GET(x)\ 5712 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x) 5713 5714 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE BIT(3) 5715 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_SET(x)\ 5716 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x) 5717 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_GET(x)\ 5718 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x) 5719 5720 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE BIT(4) 5721 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_SET(x)\ 5722 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x) 5723 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_GET(x)\ 5724 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x) 5725 5726 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE BIT(5) 5727 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_SET(x)\ 5728 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x) 5729 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_GET(x)\ 5730 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x) 5731 5732 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE BIT(6) 5733 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_SET(x)\ 5734 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x) 5735 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_GET(x)\ 5736 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x) 5737 5738 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE BIT(7) 5739 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_SET(x)\ 5740 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x) 5741 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_GET(x)\ 5742 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x) 5743 5744 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE BIT(8) 5745 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_SET(x)\ 5746 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x) 5747 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_GET(x)\ 5748 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x) 5749 5750 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE BIT(9) 5751 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_SET(x)\ 5752 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x) 5753 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_GET(x)\ 5754 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x) 5755 5756 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE BIT(10) 5757 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_SET(x)\ 5758 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x) 5759 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_GET(x)\ 5760 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x) 5761 5762 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE BIT(11) 5763 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_SET(x)\ 5764 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x) 5765 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_GET(x)\ 5766 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x) 5767 5768 /* PORT_CONF:HW_CFG:DEV25G_MODES */ 5769 #define PORT_CONF_DEV25G_MODES __REG(TARGET_PORT_CONF,\ 5770 0, 1, 0, 0, 1, 24, 8, 0, 1, 4) 5771 5772 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE BIT(0) 5773 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_SET(x)\ 5774 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x) 5775 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_GET(x)\ 5776 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x) 5777 5778 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE BIT(1) 5779 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_SET(x)\ 5780 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x) 5781 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_GET(x)\ 5782 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x) 5783 5784 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE BIT(2) 5785 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_SET(x)\ 5786 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x) 5787 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_GET(x)\ 5788 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x) 5789 5790 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE BIT(3) 5791 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_SET(x)\ 5792 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x) 5793 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_GET(x)\ 5794 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x) 5795 5796 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE BIT(4) 5797 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_SET(x)\ 5798 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x) 5799 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_GET(x)\ 5800 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x) 5801 5802 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE BIT(5) 5803 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_SET(x)\ 5804 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x) 5805 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_GET(x)\ 5806 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x) 5807 5808 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE BIT(6) 5809 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_SET(x)\ 5810 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x) 5811 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_GET(x)\ 5812 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x) 5813 5814 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE BIT(7) 5815 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_SET(x)\ 5816 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x) 5817 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_GET(x)\ 5818 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x) 5819 5820 /* PORT_CONF:HW_CFG:QSGMII_ENA */ 5821 #define PORT_CONF_QSGMII_ENA __REG(TARGET_PORT_CONF,\ 5822 0, 1, 0, 0, 1, 24, 12, 0, 1, 4) 5823 5824 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0 BIT(0) 5825 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_SET(x)\ 5826 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x) 5827 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_GET(x)\ 5828 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x) 5829 5830 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1 BIT(1) 5831 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_SET(x)\ 5832 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x) 5833 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_GET(x)\ 5834 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x) 5835 5836 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2 BIT(2) 5837 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_SET(x)\ 5838 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x) 5839 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_GET(x)\ 5840 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x) 5841 5842 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3 BIT(3) 5843 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_SET(x)\ 5844 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x) 5845 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_GET(x)\ 5846 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x) 5847 5848 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4 BIT(4) 5849 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_SET(x)\ 5850 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x) 5851 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_GET(x)\ 5852 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x) 5853 5854 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5 BIT(5) 5855 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_SET(x)\ 5856 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x) 5857 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_GET(x)\ 5858 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x) 5859 5860 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6 BIT(6) 5861 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_SET(x)\ 5862 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x) 5863 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_GET(x)\ 5864 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x) 5865 5866 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7 BIT(7) 5867 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_SET(x)\ 5868 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x) 5869 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_GET(x)\ 5870 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x) 5871 5872 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8 BIT(8) 5873 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_SET(x)\ 5874 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x) 5875 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_GET(x)\ 5876 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x) 5877 5878 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9 BIT(9) 5879 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_SET(x)\ 5880 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x) 5881 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_GET(x)\ 5882 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x) 5883 5884 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10 BIT(10) 5885 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_SET(x)\ 5886 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x) 5887 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_GET(x)\ 5888 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x) 5889 5890 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11 BIT(11) 5891 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_SET(x)\ 5892 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x) 5893 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_GET(x)\ 5894 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x) 5895 5896 /* PORT_CONF:USGMII_CFG_STAT:USGMII_CFG */ 5897 #define PORT_CONF_USGMII_CFG(g) __REG(TARGET_PORT_CONF,\ 5898 0, 1, 72, g, 6, 8, 0, 0, 1, 4) 5899 5900 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM BIT(9) 5901 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(x)\ 5902 FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x) 5903 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_GET(x)\ 5904 FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x) 5905 5906 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM BIT(8) 5907 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_SET(x)\ 5908 FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x) 5909 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_GET(x)\ 5910 FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x) 5911 5912 #define PORT_CONF_USGMII_CFG_FLIP_LANES BIT(7) 5913 #define PORT_CONF_USGMII_CFG_FLIP_LANES_SET(x)\ 5914 FIELD_PREP(PORT_CONF_USGMII_CFG_FLIP_LANES, x) 5915 #define PORT_CONF_USGMII_CFG_FLIP_LANES_GET(x)\ 5916 FIELD_GET(PORT_CONF_USGMII_CFG_FLIP_LANES, x) 5917 5918 #define PORT_CONF_USGMII_CFG_SHYST_DIS BIT(6) 5919 #define PORT_CONF_USGMII_CFG_SHYST_DIS_SET(x)\ 5920 FIELD_PREP(PORT_CONF_USGMII_CFG_SHYST_DIS, x) 5921 #define PORT_CONF_USGMII_CFG_SHYST_DIS_GET(x)\ 5922 FIELD_GET(PORT_CONF_USGMII_CFG_SHYST_DIS, x) 5923 5924 #define PORT_CONF_USGMII_CFG_E_DET_ENA BIT(5) 5925 #define PORT_CONF_USGMII_CFG_E_DET_ENA_SET(x)\ 5926 FIELD_PREP(PORT_CONF_USGMII_CFG_E_DET_ENA, x) 5927 #define PORT_CONF_USGMII_CFG_E_DET_ENA_GET(x)\ 5928 FIELD_GET(PORT_CONF_USGMII_CFG_E_DET_ENA, x) 5929 5930 #define PORT_CONF_USGMII_CFG_USE_I1_ENA BIT(4) 5931 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_SET(x)\ 5932 FIELD_PREP(PORT_CONF_USGMII_CFG_USE_I1_ENA, x) 5933 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_GET(x)\ 5934 FIELD_GET(PORT_CONF_USGMII_CFG_USE_I1_ENA, x) 5935 5936 #define PORT_CONF_USGMII_CFG_QUAD_MODE BIT(1) 5937 #define PORT_CONF_USGMII_CFG_QUAD_MODE_SET(x)\ 5938 FIELD_PREP(PORT_CONF_USGMII_CFG_QUAD_MODE, x) 5939 #define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x)\ 5940 FIELD_GET(PORT_CONF_USGMII_CFG_QUAD_MODE, x) 5941 5942 /* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR */ 5943 #define PTP_PTP_PIN_INTR __REG(TARGET_PTP,\ 5944 0, 1, 320, 0, 1, 16, 0, 0, 1, 4) 5945 5946 #define PTP_PTP_PIN_INTR_INTR_PTP GENMASK(4, 0) 5947 #define PTP_PTP_PIN_INTR_INTR_PTP_SET(x)\ 5948 FIELD_PREP(PTP_PTP_PIN_INTR_INTR_PTP, x) 5949 #define PTP_PTP_PIN_INTR_INTR_PTP_GET(x)\ 5950 FIELD_GET(PTP_PTP_PIN_INTR_INTR_PTP, x) 5951 5952 /* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR_ENA */ 5953 #define PTP_PTP_PIN_INTR_ENA __REG(TARGET_PTP,\ 5954 0, 1, 320, 0, 1, 16, 4, 0, 1, 4) 5955 5956 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA GENMASK(4, 0) 5957 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_SET(x)\ 5958 FIELD_PREP(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) 5959 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_GET(x)\ 5960 FIELD_GET(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) 5961 5962 /* DEVCPU_PTP:PTP_CFG:PTP_INTR_IDENT */ 5963 #define PTP_PTP_INTR_IDENT __REG(TARGET_PTP,\ 5964 0, 1, 320, 0, 1, 16, 8, 0, 1, 4) 5965 5966 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT GENMASK(4, 0) 5967 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_SET(x)\ 5968 FIELD_PREP(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) 5969 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_GET(x)\ 5970 FIELD_GET(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) 5971 5972 /* DEVCPU_PTP:PTP_CFG:PTP_DOM_CFG */ 5973 #define PTP_PTP_DOM_CFG __REG(TARGET_PTP,\ 5974 0, 1, 320, 0, 1, 16, 12, 0, 1, 4) 5975 5976 #define PTP_PTP_DOM_CFG_PTP_ENA GENMASK(11, 9) 5977 #define PTP_PTP_DOM_CFG_PTP_ENA_SET(x)\ 5978 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_ENA, x) 5979 #define PTP_PTP_DOM_CFG_PTP_ENA_GET(x)\ 5980 FIELD_GET(PTP_PTP_DOM_CFG_PTP_ENA, x) 5981 5982 #define PTP_PTP_DOM_CFG_PTP_HOLD GENMASK(8, 6) 5983 #define PTP_PTP_DOM_CFG_PTP_HOLD_SET(x)\ 5984 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_HOLD, x) 5985 #define PTP_PTP_DOM_CFG_PTP_HOLD_GET(x)\ 5986 FIELD_GET(PTP_PTP_DOM_CFG_PTP_HOLD, x) 5987 5988 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE GENMASK(5, 3) 5989 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_SET(x)\ 5990 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x) 5991 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_GET(x)\ 5992 FIELD_GET(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x) 5993 5994 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS GENMASK(2, 0) 5995 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(x)\ 5996 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x) 5997 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_GET(x)\ 5998 FIELD_GET(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x) 5999 6000 /* DEVCPU_PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */ 6001 #define PTP_CLK_PER_CFG(g, r) __REG(TARGET_PTP,\ 6002 0, 1, 336, g, 3, 28, 0, r, 2, 4) 6003 6004 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC */ 6005 #define PTP_PTP_CUR_NSEC(g) __REG(TARGET_PTP,\ 6006 0, 1, 336, g, 3, 28, 8, 0, 1, 4) 6007 6008 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC GENMASK(29, 0) 6009 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_SET(x)\ 6010 FIELD_PREP(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x) 6011 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_GET(x)\ 6012 FIELD_GET(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x) 6013 6014 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC_FRAC */ 6015 #define PTP_PTP_CUR_NSEC_FRAC(g) __REG(TARGET_PTP,\ 6016 0, 1, 336, g, 3, 28, 12, 0, 1, 4) 6017 6018 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC GENMASK(7, 0) 6019 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_SET(x)\ 6020 FIELD_PREP(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x) 6021 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_GET(x)\ 6022 FIELD_GET(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x) 6023 6024 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_LSB */ 6025 #define PTP_PTP_CUR_SEC_LSB(g) __REG(TARGET_PTP,\ 6026 0, 1, 336, g, 3, 28, 16, 0, 1, 4) 6027 6028 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_MSB */ 6029 #define PTP_PTP_CUR_SEC_MSB(g) __REG(TARGET_PTP,\ 6030 0, 1, 336, g, 3, 28, 20, 0, 1, 4) 6031 6032 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB GENMASK(15, 0) 6033 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_SET(x)\ 6034 FIELD_PREP(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x) 6035 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_GET(x)\ 6036 FIELD_GET(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x) 6037 6038 /* DEVCPU_PTP:PTP_TOD_DOMAINS:NTP_CUR_NSEC */ 6039 #define PTP_NTP_CUR_NSEC(g) __REG(TARGET_PTP,\ 6040 0, 1, 336, g, 3, 28, 24, 0, 1, 4) 6041 6042 /* DEVCPU_PTP:PTP_PINS:PTP_PIN_CFG */ 6043 #define PTP_PTP_PIN_CFG(g) __REG(TARGET_PTP,\ 6044 0, 1, 0, g, 5, 64, 0, 0, 1, 4) 6045 6046 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION GENMASK(28, 26) 6047 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(x)\ 6048 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) 6049 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_GET(x)\ 6050 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) 6051 6052 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC GENMASK(25, 24) 6053 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(x)\ 6054 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) 6055 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_GET(x)\ 6056 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) 6057 6058 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL BIT(23) 6059 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_SET(x)\ 6060 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) 6061 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_GET(x)\ 6062 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) 6063 6064 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT GENMASK(22, 21) 6065 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_SET(x)\ 6066 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) 6067 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_GET(x)\ 6068 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) 6069 6070 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT GENMASK(20, 18) 6071 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_SET(x)\ 6072 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x) 6073 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_GET(x)\ 6074 FIELD_GET(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x) 6075 6076 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM GENMASK(17, 16) 6077 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(x)\ 6078 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x) 6079 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_GET(x)\ 6080 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x) 6081 6082 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT GENMASK(15, 14) 6083 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_SET(x)\ 6084 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x) 6085 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_GET(x)\ 6086 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x) 6087 6088 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK BIT(13) 6089 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_SET(x)\ 6090 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x) 6091 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_GET(x)\ 6092 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x) 6093 6094 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS GENMASK(12, 0) 6095 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_SET(x)\ 6096 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x) 6097 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_GET(x)\ 6098 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x) 6099 6100 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_MSB */ 6101 #define PTP_PTP_TOD_SEC_MSB(g) __REG(TARGET_PTP,\ 6102 0, 1, 0, g, 5, 64, 4, 0, 1, 4) 6103 6104 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB GENMASK(15, 0) 6105 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(x)\ 6106 FIELD_PREP(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x) 6107 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_GET(x)\ 6108 FIELD_GET(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x) 6109 6110 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_LSB */ 6111 #define PTP_PTP_TOD_SEC_LSB(g) __REG(TARGET_PTP,\ 6112 0, 1, 0, g, 5, 64, 8, 0, 1, 4) 6113 6114 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC */ 6115 #define PTP_PTP_TOD_NSEC(g) __REG(TARGET_PTP,\ 6116 0, 1, 0, g, 5, 64, 12, 0, 1, 4) 6117 6118 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC GENMASK(29, 0) 6119 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(x)\ 6120 FIELD_PREP(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x) 6121 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_GET(x)\ 6122 FIELD_GET(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x) 6123 6124 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC_FRAC */ 6125 #define PTP_PTP_TOD_NSEC_FRAC(g) __REG(TARGET_PTP,\ 6126 0, 1, 0, g, 5, 64, 16, 0, 1, 4) 6127 6128 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC GENMASK(7, 0) 6129 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_SET(x)\ 6130 FIELD_PREP(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x) 6131 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_GET(x)\ 6132 FIELD_GET(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x) 6133 6134 /* DEVCPU_PTP:PTP_PINS:NTP_NSEC */ 6135 #define PTP_NTP_NSEC(g) __REG(TARGET_PTP,\ 6136 0, 1, 0, g, 5, 64, 20, 0, 1, 4) 6137 6138 /* DEVCPU_PTP:PTP_PINS:PIN_WF_HIGH_PERIOD */ 6139 #define PTP_PIN_WF_HIGH_PERIOD(g) __REG(TARGET_PTP,\ 6140 0, 1, 0, g, 5, 64, 24, 0, 1, 4) 6141 6142 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH GENMASK(29, 0) 6143 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_SET(x)\ 6144 FIELD_PREP(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x) 6145 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_GET(x)\ 6146 FIELD_GET(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x) 6147 6148 /* DEVCPU_PTP:PTP_PINS:PIN_WF_LOW_PERIOD */ 6149 #define PTP_PIN_WF_LOW_PERIOD(g) __REG(TARGET_PTP,\ 6150 0, 1, 0, g, 5, 64, 28, 0, 1, 4) 6151 6152 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL GENMASK(29, 0) 6153 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_SET(x)\ 6154 FIELD_PREP(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x) 6155 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_GET(x)\ 6156 FIELD_GET(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x) 6157 6158 /* DEVCPU_PTP:PTP_PINS:PIN_IOBOUNCH_DELAY */ 6159 #define PTP_PIN_IOBOUNCH_DELAY(g) __REG(TARGET_PTP,\ 6160 0, 1, 0, g, 5, 64, 32, 0, 1, 4) 6161 6162 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL GENMASK(18, 3) 6163 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_SET(x)\ 6164 FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x) 6165 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_GET(x)\ 6166 FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x) 6167 6168 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG GENMASK(2, 0) 6169 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_SET(x)\ 6170 FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x) 6171 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_GET(x)\ 6172 FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x) 6173 6174 /* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CTRL */ 6175 #define PTP_PHAD_CTRL(g) __REG(TARGET_PTP,\ 6176 0, 1, 420, g, 5, 8, 0, 0, 1, 4) 6177 6178 #define PTP_PHAD_CTRL_PHAD_ENA BIT(7) 6179 #define PTP_PHAD_CTRL_PHAD_ENA_SET(x)\ 6180 FIELD_PREP(PTP_PHAD_CTRL_PHAD_ENA, x) 6181 #define PTP_PHAD_CTRL_PHAD_ENA_GET(x)\ 6182 FIELD_GET(PTP_PHAD_CTRL_PHAD_ENA, x) 6183 6184 #define PTP_PHAD_CTRL_PHAD_FAILED BIT(6) 6185 #define PTP_PHAD_CTRL_PHAD_FAILED_SET(x)\ 6186 FIELD_PREP(PTP_PHAD_CTRL_PHAD_FAILED, x) 6187 #define PTP_PHAD_CTRL_PHAD_FAILED_GET(x)\ 6188 FIELD_GET(PTP_PHAD_CTRL_PHAD_FAILED, x) 6189 6190 #define PTP_PHAD_CTRL_REDUCED_RES GENMASK(5, 3) 6191 #define PTP_PHAD_CTRL_REDUCED_RES_SET(x)\ 6192 FIELD_PREP(PTP_PHAD_CTRL_REDUCED_RES, x) 6193 #define PTP_PHAD_CTRL_REDUCED_RES_GET(x)\ 6194 FIELD_GET(PTP_PHAD_CTRL_REDUCED_RES, x) 6195 6196 #define PTP_PHAD_CTRL_LOCK_ACC GENMASK(2, 0) 6197 #define PTP_PHAD_CTRL_LOCK_ACC_SET(x)\ 6198 FIELD_PREP(PTP_PHAD_CTRL_LOCK_ACC, x) 6199 #define PTP_PHAD_CTRL_LOCK_ACC_GET(x)\ 6200 FIELD_GET(PTP_PHAD_CTRL_LOCK_ACC, x) 6201 6202 /* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CYC_STAT */ 6203 #define PTP_PHAD_CYC_STAT(g) __REG(TARGET_PTP,\ 6204 0, 1, 420, g, 5, 8, 4, 0, 1, 4) 6205 6206 /* QFWD:SYSTEM:SWITCH_PORT_MODE */ 6207 #define QFWD_SWITCH_PORT_MODE(r) __REG(TARGET_QFWD,\ 6208 0, 1, 0, 0, 1, 340, 0, r, 70, 4) 6209 6210 #define QFWD_SWITCH_PORT_MODE_PORT_ENA BIT(19) 6211 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x)\ 6212 FIELD_PREP(QFWD_SWITCH_PORT_MODE_PORT_ENA, x) 6213 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_GET(x)\ 6214 FIELD_GET(QFWD_SWITCH_PORT_MODE_PORT_ENA, x) 6215 6216 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY GENMASK(18, 10) 6217 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_SET(x)\ 6218 FIELD_PREP(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x) 6219 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_GET(x)\ 6220 FIELD_GET(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x) 6221 6222 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD GENMASK(9, 6) 6223 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_SET(x)\ 6224 FIELD_PREP(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x) 6225 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_GET(x)\ 6226 FIELD_GET(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x) 6227 6228 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE BIT(5) 6229 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_SET(x)\ 6230 FIELD_PREP(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x) 6231 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_GET(x)\ 6232 FIELD_GET(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x) 6233 6234 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING BIT(4) 6235 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_SET(x)\ 6236 FIELD_PREP(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x) 6237 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_GET(x)\ 6238 FIELD_GET(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x) 6239 6240 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING BIT(3) 6241 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_SET(x)\ 6242 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x) 6243 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_GET(x)\ 6244 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x) 6245 6246 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE BIT(2) 6247 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_SET(x)\ 6248 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x) 6249 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_GET(x)\ 6250 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x) 6251 6252 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS BIT(1) 6253 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_SET(x)\ 6254 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x) 6255 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_GET(x)\ 6256 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x) 6257 6258 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE BIT(0) 6259 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_SET(x)\ 6260 FIELD_PREP(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x) 6261 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x)\ 6262 FIELD_GET(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x) 6263 6264 /* QFWD:SYSTEM:FRAME_COPY_CFG */ 6265 #define QFWD_FRAME_COPY_CFG(r)\ 6266 __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 284, r, 12, 4) 6267 6268 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL GENMASK(12, 6) 6269 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_SET(x)\ 6270 FIELD_PREP(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x) 6271 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_GET(x)\ 6272 FIELD_GET(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x) 6273 6274 /* QRES:RES_CTRL:RES_CFG */ 6275 #define QRES_RES_CFG(g) __REG(TARGET_QRES,\ 6276 0, 1, 0, g, 5120, 16, 0, 0, 1, 4) 6277 6278 #define QRES_RES_CFG_WM_HIGH GENMASK(11, 0) 6279 #define QRES_RES_CFG_WM_HIGH_SET(x)\ 6280 FIELD_PREP(QRES_RES_CFG_WM_HIGH, x) 6281 #define QRES_RES_CFG_WM_HIGH_GET(x)\ 6282 FIELD_GET(QRES_RES_CFG_WM_HIGH, x) 6283 6284 /* QRES:RES_CTRL:RES_STAT */ 6285 #define QRES_RES_STAT(g) __REG(TARGET_QRES,\ 6286 0, 1, 0, g, 5120, 16, 4, 0, 1, 4) 6287 6288 #define QRES_RES_STAT_MAXUSE GENMASK(20, 0) 6289 #define QRES_RES_STAT_MAXUSE_SET(x)\ 6290 FIELD_PREP(QRES_RES_STAT_MAXUSE, x) 6291 #define QRES_RES_STAT_MAXUSE_GET(x)\ 6292 FIELD_GET(QRES_RES_STAT_MAXUSE, x) 6293 6294 /* QRES:RES_CTRL:RES_STAT_CUR */ 6295 #define QRES_RES_STAT_CUR(g) __REG(TARGET_QRES,\ 6296 0, 1, 0, g, 5120, 16, 8, 0, 1, 4) 6297 6298 #define QRES_RES_STAT_CUR_INUSE GENMASK(20, 0) 6299 #define QRES_RES_STAT_CUR_INUSE_SET(x)\ 6300 FIELD_PREP(QRES_RES_STAT_CUR_INUSE, x) 6301 #define QRES_RES_STAT_CUR_INUSE_GET(x)\ 6302 FIELD_GET(QRES_RES_STAT_CUR_INUSE, x) 6303 6304 /* DEVCPU_QS:XTR:XTR_GRP_CFG */ 6305 #define QS_XTR_GRP_CFG(r) __REG(TARGET_QS,\ 6306 0, 1, 0, 0, 1, 36, 0, r, 2, 4) 6307 6308 #define QS_XTR_GRP_CFG_MODE GENMASK(3, 2) 6309 #define QS_XTR_GRP_CFG_MODE_SET(x)\ 6310 FIELD_PREP(QS_XTR_GRP_CFG_MODE, x) 6311 #define QS_XTR_GRP_CFG_MODE_GET(x)\ 6312 FIELD_GET(QS_XTR_GRP_CFG_MODE, x) 6313 6314 #define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1) 6315 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(x)\ 6316 FIELD_PREP(QS_XTR_GRP_CFG_STATUS_WORD_POS, x) 6317 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_GET(x)\ 6318 FIELD_GET(QS_XTR_GRP_CFG_STATUS_WORD_POS, x) 6319 6320 #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0) 6321 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\ 6322 FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x) 6323 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\ 6324 FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x) 6325 6326 /* DEVCPU_QS:XTR:XTR_RD */ 6327 #define QS_XTR_RD(r) __REG(TARGET_QS,\ 6328 0, 1, 0, 0, 1, 36, 8, r, 2, 4) 6329 6330 /* DEVCPU_QS:XTR:XTR_FLUSH */ 6331 #define QS_XTR_FLUSH __REG(TARGET_QS,\ 6332 0, 1, 0, 0, 1, 36, 24, 0, 1, 4) 6333 6334 #define QS_XTR_FLUSH_FLUSH GENMASK(1, 0) 6335 #define QS_XTR_FLUSH_FLUSH_SET(x)\ 6336 FIELD_PREP(QS_XTR_FLUSH_FLUSH, x) 6337 #define QS_XTR_FLUSH_FLUSH_GET(x)\ 6338 FIELD_GET(QS_XTR_FLUSH_FLUSH, x) 6339 6340 /* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ 6341 #define QS_XTR_DATA_PRESENT __REG(TARGET_QS,\ 6342 0, 1, 0, 0, 1, 36, 28, 0, 1, 4) 6343 6344 #define QS_XTR_DATA_PRESENT_DATA_PRESENT GENMASK(1, 0) 6345 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_SET(x)\ 6346 FIELD_PREP(QS_XTR_DATA_PRESENT_DATA_PRESENT, x) 6347 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_GET(x)\ 6348 FIELD_GET(QS_XTR_DATA_PRESENT_DATA_PRESENT, x) 6349 6350 /* DEVCPU_QS:INJ:INJ_GRP_CFG */ 6351 #define QS_INJ_GRP_CFG(r) __REG(TARGET_QS,\ 6352 0, 1, 36, 0, 1, 40, 0, r, 2, 4) 6353 6354 #define QS_INJ_GRP_CFG_MODE GENMASK(3, 2) 6355 #define QS_INJ_GRP_CFG_MODE_SET(x)\ 6356 FIELD_PREP(QS_INJ_GRP_CFG_MODE, x) 6357 #define QS_INJ_GRP_CFG_MODE_GET(x)\ 6358 FIELD_GET(QS_INJ_GRP_CFG_MODE, x) 6359 6360 #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) 6361 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\ 6362 FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x) 6363 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\ 6364 FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x) 6365 6366 /* DEVCPU_QS:INJ:INJ_WR */ 6367 #define QS_INJ_WR(r) __REG(TARGET_QS,\ 6368 0, 1, 36, 0, 1, 40, 8, r, 2, 4) 6369 6370 /* DEVCPU_QS:INJ:INJ_CTRL */ 6371 #define QS_INJ_CTRL(r) __REG(TARGET_QS,\ 6372 0, 1, 36, 0, 1, 40, 16, r, 2, 4) 6373 6374 #define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21) 6375 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\ 6376 FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x) 6377 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\ 6378 FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x) 6379 6380 #define QS_INJ_CTRL_ABORT BIT(20) 6381 #define QS_INJ_CTRL_ABORT_SET(x)\ 6382 FIELD_PREP(QS_INJ_CTRL_ABORT, x) 6383 #define QS_INJ_CTRL_ABORT_GET(x)\ 6384 FIELD_GET(QS_INJ_CTRL_ABORT, x) 6385 6386 #define QS_INJ_CTRL_EOF BIT(19) 6387 #define QS_INJ_CTRL_EOF_SET(x)\ 6388 FIELD_PREP(QS_INJ_CTRL_EOF, x) 6389 #define QS_INJ_CTRL_EOF_GET(x)\ 6390 FIELD_GET(QS_INJ_CTRL_EOF, x) 6391 6392 #define QS_INJ_CTRL_SOF BIT(18) 6393 #define QS_INJ_CTRL_SOF_SET(x)\ 6394 FIELD_PREP(QS_INJ_CTRL_SOF, x) 6395 #define QS_INJ_CTRL_SOF_GET(x)\ 6396 FIELD_GET(QS_INJ_CTRL_SOF, x) 6397 6398 #define QS_INJ_CTRL_VLD_BYTES GENMASK(17, 16) 6399 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\ 6400 FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x) 6401 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\ 6402 FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x) 6403 6404 /* DEVCPU_QS:INJ:INJ_STATUS */ 6405 #define QS_INJ_STATUS __REG(TARGET_QS,\ 6406 0, 1, 36, 0, 1, 40, 24, 0, 1, 4) 6407 6408 #define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4) 6409 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\ 6410 FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x) 6411 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\ 6412 FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x) 6413 6414 #define QS_INJ_STATUS_FIFO_RDY GENMASK(3, 2) 6415 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\ 6416 FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x) 6417 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\ 6418 FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x) 6419 6420 #define QS_INJ_STATUS_INJ_IN_PROGRESS GENMASK(1, 0) 6421 #define QS_INJ_STATUS_INJ_IN_PROGRESS_SET(x)\ 6422 FIELD_PREP(QS_INJ_STATUS_INJ_IN_PROGRESS, x) 6423 #define QS_INJ_STATUS_INJ_IN_PROGRESS_GET(x)\ 6424 FIELD_GET(QS_INJ_STATUS_INJ_IN_PROGRESS, x) 6425 6426 /* QSYS:PAUSE_CFG:PAUSE_CFG */ 6427 #define QSYS_PAUSE_CFG(r) __REG(TARGET_QSYS,\ 6428 0, 1, 544, 0, 1, 1128, 0, r, 70, 4) 6429 6430 #define QSYS_PAUSE_CFG_PAUSE_START GENMASK(25, 14) 6431 #define QSYS_PAUSE_CFG_PAUSE_START_SET(x)\ 6432 FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_START, x) 6433 #define QSYS_PAUSE_CFG_PAUSE_START_GET(x)\ 6434 FIELD_GET(QSYS_PAUSE_CFG_PAUSE_START, x) 6435 6436 #define QSYS_PAUSE_CFG_PAUSE_STOP GENMASK(13, 2) 6437 #define QSYS_PAUSE_CFG_PAUSE_STOP_SET(x)\ 6438 FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_STOP, x) 6439 #define QSYS_PAUSE_CFG_PAUSE_STOP_GET(x)\ 6440 FIELD_GET(QSYS_PAUSE_CFG_PAUSE_STOP, x) 6441 6442 #define QSYS_PAUSE_CFG_PAUSE_ENA BIT(1) 6443 #define QSYS_PAUSE_CFG_PAUSE_ENA_SET(x)\ 6444 FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_ENA, x) 6445 #define QSYS_PAUSE_CFG_PAUSE_ENA_GET(x)\ 6446 FIELD_GET(QSYS_PAUSE_CFG_PAUSE_ENA, x) 6447 6448 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA BIT(0) 6449 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_SET(x)\ 6450 FIELD_PREP(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x) 6451 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_GET(x)\ 6452 FIELD_GET(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x) 6453 6454 /* QSYS:PAUSE_CFG:ATOP */ 6455 #define QSYS_ATOP(r) __REG(TARGET_QSYS,\ 6456 0, 1, 544, 0, 1, 1128, 284, r, 70, 4) 6457 6458 #define QSYS_ATOP_ATOP GENMASK(11, 0) 6459 #define QSYS_ATOP_ATOP_SET(x)\ 6460 FIELD_PREP(QSYS_ATOP_ATOP, x) 6461 #define QSYS_ATOP_ATOP_GET(x)\ 6462 FIELD_GET(QSYS_ATOP_ATOP, x) 6463 6464 /* QSYS:PAUSE_CFG:FWD_PRESSURE */ 6465 #define QSYS_FWD_PRESSURE(r) __REG(TARGET_QSYS,\ 6466 0, 1, 544, 0, 1, 1128, 564, r, 70, 4) 6467 6468 #define QSYS_FWD_PRESSURE_FWD_PRESSURE GENMASK(11, 1) 6469 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_SET(x)\ 6470 FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE, x) 6471 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_GET(x)\ 6472 FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE, x) 6473 6474 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS BIT(0) 6475 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_SET(x)\ 6476 FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x) 6477 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_GET(x)\ 6478 FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x) 6479 6480 /* QSYS:PAUSE_CFG:ATOP_TOT_CFG */ 6481 #define QSYS_ATOP_TOT_CFG __REG(TARGET_QSYS,\ 6482 0, 1, 544, 0, 1, 1128, 844, 0, 1, 4) 6483 6484 #define QSYS_ATOP_TOT_CFG_ATOP_TOT GENMASK(11, 0) 6485 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_SET(x)\ 6486 FIELD_PREP(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) 6487 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_GET(x)\ 6488 FIELD_GET(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) 6489 6490 /* QSYS:CALCFG:CAL_AUTO */ 6491 #define QSYS_CAL_AUTO(r) __REG(TARGET_QSYS,\ 6492 0, 1, 2304, 0, 1, 40, 0, r, 7, 4) 6493 6494 #define QSYS_CAL_AUTO_CAL_AUTO GENMASK(29, 0) 6495 #define QSYS_CAL_AUTO_CAL_AUTO_SET(x)\ 6496 FIELD_PREP(QSYS_CAL_AUTO_CAL_AUTO, x) 6497 #define QSYS_CAL_AUTO_CAL_AUTO_GET(x)\ 6498 FIELD_GET(QSYS_CAL_AUTO_CAL_AUTO, x) 6499 6500 /* QSYS:CALCFG:CAL_CTRL */ 6501 #define QSYS_CAL_CTRL __REG(TARGET_QSYS,\ 6502 0, 1, 2304, 0, 1, 40, 36, 0, 1, 4) 6503 6504 #define QSYS_CAL_CTRL_CAL_MODE GENMASK(14, 11) 6505 #define QSYS_CAL_CTRL_CAL_MODE_SET(x)\ 6506 FIELD_PREP(QSYS_CAL_CTRL_CAL_MODE, x) 6507 #define QSYS_CAL_CTRL_CAL_MODE_GET(x)\ 6508 FIELD_GET(QSYS_CAL_CTRL_CAL_MODE, x) 6509 6510 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE GENMASK(10, 1) 6511 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(x)\ 6512 FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x) 6513 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_GET(x)\ 6514 FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x) 6515 6516 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR BIT(0) 6517 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_SET(x)\ 6518 FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x) 6519 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(x)\ 6520 FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x) 6521 6522 /* QSYS:RAM_CTRL:RAM_INIT */ 6523 #define QSYS_RAM_INIT __REG(TARGET_QSYS,\ 6524 0, 1, 2344, 0, 1, 4, 0, 0, 1, 4) 6525 6526 #define QSYS_RAM_INIT_RAM_INIT BIT(1) 6527 #define QSYS_RAM_INIT_RAM_INIT_SET(x)\ 6528 FIELD_PREP(QSYS_RAM_INIT_RAM_INIT, x) 6529 #define QSYS_RAM_INIT_RAM_INIT_GET(x)\ 6530 FIELD_GET(QSYS_RAM_INIT_RAM_INIT, x) 6531 6532 #define QSYS_RAM_INIT_RAM_CFG_HOOK BIT(0) 6533 #define QSYS_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 6534 FIELD_PREP(QSYS_RAM_INIT_RAM_CFG_HOOK, x) 6535 #define QSYS_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 6536 FIELD_GET(QSYS_RAM_INIT_RAM_CFG_HOOK, x) 6537 6538 /* REW:COMMON:OWN_UPSID */ 6539 #define REW_OWN_UPSID(r) __REG(TARGET_REW,\ 6540 0, 1, 387264, 0, 1, 1232, 0, r, 3, 4) 6541 6542 #define REW_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 6543 #define REW_OWN_UPSID_OWN_UPSID_SET(x)\ 6544 FIELD_PREP(REW_OWN_UPSID_OWN_UPSID, x) 6545 #define REW_OWN_UPSID_OWN_UPSID_GET(x)\ 6546 FIELD_GET(REW_OWN_UPSID_OWN_UPSID, x) 6547 6548 /* REW:COMMON:RTAG_ETAG_CTRL */ 6549 #define REW_RTAG_ETAG_CTRL(r) __REG(TARGET_REW,\ 6550 0, 1, 387264, 0, 1, 1232, 560, r, 70, 4) 6551 6552 #define REW_RTAG_ETAG_CTRL_IPE_TBL GENMASK(9, 3) 6553 #define REW_RTAG_ETAG_CTRL_IPE_TBL_SET(x)\ 6554 FIELD_PREP(REW_RTAG_ETAG_CTRL_IPE_TBL, x) 6555 #define REW_RTAG_ETAG_CTRL_IPE_TBL_GET(x)\ 6556 FIELD_GET(REW_RTAG_ETAG_CTRL_IPE_TBL, x) 6557 6558 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA GENMASK(2, 1) 6559 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_SET(x)\ 6560 FIELD_PREP(REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA, x) 6561 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_GET(x)\ 6562 FIELD_GET(REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA, x) 6563 6564 #define REW_RTAG_ETAG_CTRL_KEEP_ETAG BIT(0) 6565 #define REW_RTAG_ETAG_CTRL_KEEP_ETAG_SET(x)\ 6566 FIELD_PREP(REW_RTAG_ETAG_CTRL_KEEP_ETAG, x) 6567 #define REW_RTAG_ETAG_CTRL_KEEP_ETAG_GET(x)\ 6568 FIELD_GET(REW_RTAG_ETAG_CTRL_KEEP_ETAG, x) 6569 6570 /* REW:COMMON:ES0_CTRL */ 6571 #define REW_ES0_CTRL __REG(TARGET_REW,\ 6572 0, 1, 387264, 0, 1, 1232, 852, 0, 1, 4) 6573 6574 #define REW_ES0_CTRL_ES0_BY_RT_FWD BIT(5) 6575 #define REW_ES0_CTRL_ES0_BY_RT_FWD_SET(x)\ 6576 FIELD_PREP(REW_ES0_CTRL_ES0_BY_RT_FWD, x) 6577 #define REW_ES0_CTRL_ES0_BY_RT_FWD_GET(x)\ 6578 FIELD_GET(REW_ES0_CTRL_ES0_BY_RT_FWD, x) 6579 6580 #define REW_ES0_CTRL_ES0_BY_RLEG BIT(4) 6581 #define REW_ES0_CTRL_ES0_BY_RLEG_SET(x)\ 6582 FIELD_PREP(REW_ES0_CTRL_ES0_BY_RLEG, x) 6583 #define REW_ES0_CTRL_ES0_BY_RLEG_GET(x)\ 6584 FIELD_GET(REW_ES0_CTRL_ES0_BY_RLEG, x) 6585 6586 #define REW_ES0_CTRL_ES0_DPORT_ENA BIT(3) 6587 #define REW_ES0_CTRL_ES0_DPORT_ENA_SET(x)\ 6588 FIELD_PREP(REW_ES0_CTRL_ES0_DPORT_ENA, x) 6589 #define REW_ES0_CTRL_ES0_DPORT_ENA_GET(x)\ 6590 FIELD_GET(REW_ES0_CTRL_ES0_DPORT_ENA, x) 6591 6592 #define REW_ES0_CTRL_ES0_FRM_LBK_CFG BIT(2) 6593 #define REW_ES0_CTRL_ES0_FRM_LBK_CFG_SET(x)\ 6594 FIELD_PREP(REW_ES0_CTRL_ES0_FRM_LBK_CFG, x) 6595 #define REW_ES0_CTRL_ES0_FRM_LBK_CFG_GET(x)\ 6596 FIELD_GET(REW_ES0_CTRL_ES0_FRM_LBK_CFG, x) 6597 6598 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA BIT(1) 6599 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA_SET(x)\ 6600 FIELD_PREP(REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA, x) 6601 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA_GET(x)\ 6602 FIELD_GET(REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA, x) 6603 6604 #define REW_ES0_CTRL_ES0_LU_ENA BIT(0) 6605 #define REW_ES0_CTRL_ES0_LU_ENA_SET(x)\ 6606 FIELD_PREP(REW_ES0_CTRL_ES0_LU_ENA, x) 6607 #define REW_ES0_CTRL_ES0_LU_ENA_GET(x)\ 6608 FIELD_GET(REW_ES0_CTRL_ES0_LU_ENA, x) 6609 6610 /* REW:PORT:PORT_VLAN_CFG */ 6611 #define REW_PORT_VLAN_CFG(g) __REG(TARGET_REW,\ 6612 0, 1, 360448, g, 70, 256, 0, 0, 1, 4) 6613 6614 #define REW_PORT_VLAN_CFG_PORT_PCP GENMASK(15, 13) 6615 #define REW_PORT_VLAN_CFG_PORT_PCP_SET(x)\ 6616 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_PCP, x) 6617 #define REW_PORT_VLAN_CFG_PORT_PCP_GET(x)\ 6618 FIELD_GET(REW_PORT_VLAN_CFG_PORT_PCP, x) 6619 6620 #define REW_PORT_VLAN_CFG_PORT_DEI BIT(12) 6621 #define REW_PORT_VLAN_CFG_PORT_DEI_SET(x)\ 6622 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_DEI, x) 6623 #define REW_PORT_VLAN_CFG_PORT_DEI_GET(x)\ 6624 FIELD_GET(REW_PORT_VLAN_CFG_PORT_DEI, x) 6625 6626 #define REW_PORT_VLAN_CFG_PORT_VID GENMASK(11, 0) 6627 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\ 6628 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x) 6629 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\ 6630 FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x) 6631 6632 /* REW:PORT:PCP_MAP_DE0 */ 6633 #define REW_PCP_MAP_DE0(g, r) __REG(TARGET_REW,\ 6634 0, 1, 360448, g, 70, 256, 4, r, 8, 4) 6635 6636 #define REW_PCP_MAP_DE0_PCP_DE0 GENMASK(2, 0) 6637 #define REW_PCP_MAP_DE0_PCP_DE0_SET(x)\ 6638 FIELD_PREP(REW_PCP_MAP_DE0_PCP_DE0, x) 6639 #define REW_PCP_MAP_DE0_PCP_DE0_GET(x)\ 6640 FIELD_GET(REW_PCP_MAP_DE0_PCP_DE0, x) 6641 6642 /* REW:PORT:PCP_MAP_DE1 */ 6643 #define REW_PCP_MAP_DE1(g, r) __REG(TARGET_REW,\ 6644 0, 1, 360448, g, 70, 256, 36, r, 8, 4) 6645 6646 #define REW_PCP_MAP_DE1_PCP_DE1 GENMASK(2, 0) 6647 #define REW_PCP_MAP_DE1_PCP_DE1_SET(x)\ 6648 FIELD_PREP(REW_PCP_MAP_DE1_PCP_DE1, x) 6649 #define REW_PCP_MAP_DE1_PCP_DE1_GET(x)\ 6650 FIELD_GET(REW_PCP_MAP_DE1_PCP_DE1, x) 6651 6652 /* REW:PORT:DEI_MAP_DE0 */ 6653 #define REW_DEI_MAP_DE0(g, r) __REG(TARGET_REW,\ 6654 0, 1, 360448, g, 70, 256, 68, r, 8, 4) 6655 6656 #define REW_DEI_MAP_DE0_DEI_DE0 BIT(0) 6657 #define REW_DEI_MAP_DE0_DEI_DE0_SET(x)\ 6658 FIELD_PREP(REW_DEI_MAP_DE0_DEI_DE0, x) 6659 #define REW_DEI_MAP_DE0_DEI_DE0_GET(x)\ 6660 FIELD_GET(REW_DEI_MAP_DE0_DEI_DE0, x) 6661 6662 /* REW:PORT:DEI_MAP_DE1 */ 6663 #define REW_DEI_MAP_DE1(g, r) __REG(TARGET_REW,\ 6664 0, 1, 360448, g, 70, 256, 100, r, 8, 4) 6665 6666 #define REW_DEI_MAP_DE1_DEI_DE1 BIT(0) 6667 #define REW_DEI_MAP_DE1_DEI_DE1_SET(x)\ 6668 FIELD_PREP(REW_DEI_MAP_DE1_DEI_DE1, x) 6669 #define REW_DEI_MAP_DE1_DEI_DE1_GET(x)\ 6670 FIELD_GET(REW_DEI_MAP_DE1_DEI_DE1, x) 6671 6672 /* REW:PORT:TAG_CTRL */ 6673 #define REW_TAG_CTRL(g) __REG(TARGET_REW,\ 6674 0, 1, 360448, g, 70, 256, 132, 0, 1, 4) 6675 6676 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED BIT(13) 6677 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_SET(x)\ 6678 FIELD_PREP(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x) 6679 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_GET(x)\ 6680 FIELD_GET(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x) 6681 6682 #define REW_TAG_CTRL_TAG_CFG GENMASK(12, 11) 6683 #define REW_TAG_CTRL_TAG_CFG_SET(x)\ 6684 FIELD_PREP(REW_TAG_CTRL_TAG_CFG, x) 6685 #define REW_TAG_CTRL_TAG_CFG_GET(x)\ 6686 FIELD_GET(REW_TAG_CTRL_TAG_CFG, x) 6687 6688 #define REW_TAG_CTRL_TAG_TPID_CFG GENMASK(10, 8) 6689 #define REW_TAG_CTRL_TAG_TPID_CFG_SET(x)\ 6690 FIELD_PREP(REW_TAG_CTRL_TAG_TPID_CFG, x) 6691 #define REW_TAG_CTRL_TAG_TPID_CFG_GET(x)\ 6692 FIELD_GET(REW_TAG_CTRL_TAG_TPID_CFG, x) 6693 6694 #define REW_TAG_CTRL_TAG_VID_CFG GENMASK(7, 6) 6695 #define REW_TAG_CTRL_TAG_VID_CFG_SET(x)\ 6696 FIELD_PREP(REW_TAG_CTRL_TAG_VID_CFG, x) 6697 #define REW_TAG_CTRL_TAG_VID_CFG_GET(x)\ 6698 FIELD_GET(REW_TAG_CTRL_TAG_VID_CFG, x) 6699 6700 #define REW_TAG_CTRL_TAG_PCP_CFG GENMASK(5, 3) 6701 #define REW_TAG_CTRL_TAG_PCP_CFG_SET(x)\ 6702 FIELD_PREP(REW_TAG_CTRL_TAG_PCP_CFG, x) 6703 #define REW_TAG_CTRL_TAG_PCP_CFG_GET(x)\ 6704 FIELD_GET(REW_TAG_CTRL_TAG_PCP_CFG, x) 6705 6706 #define REW_TAG_CTRL_TAG_DEI_CFG GENMASK(2, 0) 6707 #define REW_TAG_CTRL_TAG_DEI_CFG_SET(x)\ 6708 FIELD_PREP(REW_TAG_CTRL_TAG_DEI_CFG, x) 6709 #define REW_TAG_CTRL_TAG_DEI_CFG_GET(x)\ 6710 FIELD_GET(REW_TAG_CTRL_TAG_DEI_CFG, x) 6711 6712 /* REW:PORT:DSCP_MAP */ 6713 #define REW_DSCP_MAP(g) __REG(TARGET_REW,\ 6714 0, 1, 360448, g, 70, 256, 136, 0, 1, 4) 6715 6716 #define REW_DSCP_MAP_DSCP_UPDATE_ENA BIT(1) 6717 #define REW_DSCP_MAP_DSCP_UPDATE_ENA_SET(x)\ 6718 FIELD_PREP(REW_DSCP_MAP_DSCP_UPDATE_ENA, x) 6719 #define REW_DSCP_MAP_DSCP_UPDATE_ENA_GET(x)\ 6720 FIELD_GET(REW_DSCP_MAP_DSCP_UPDATE_ENA, x) 6721 6722 #define REW_DSCP_MAP_DSCP_REMAP_ENA BIT(0) 6723 #define REW_DSCP_MAP_DSCP_REMAP_ENA_SET(x)\ 6724 FIELD_PREP(REW_DSCP_MAP_DSCP_REMAP_ENA, x) 6725 #define REW_DSCP_MAP_DSCP_REMAP_ENA_GET(x)\ 6726 FIELD_GET(REW_DSCP_MAP_DSCP_REMAP_ENA, x) 6727 6728 /* REW:PTP_CTRL:PTP_TWOSTEP_CTRL */ 6729 #define REW_PTP_TWOSTEP_CTRL __REG(TARGET_REW,\ 6730 0, 1, 378368, 0, 1, 40, 0, 0, 1, 4) 6731 6732 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA BIT(12) 6733 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\ 6734 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x) 6735 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\ 6736 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x) 6737 6738 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT BIT(11) 6739 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\ 6740 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x) 6741 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\ 6742 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x) 6743 6744 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD BIT(10) 6745 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\ 6746 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x) 6747 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\ 6748 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x) 6749 6750 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX BIT(9) 6751 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\ 6752 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x) 6753 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\ 6754 FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x) 6755 6756 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1) 6757 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\ 6758 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x) 6759 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\ 6760 FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x) 6761 6762 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL BIT(0) 6763 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\ 6764 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x) 6765 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\ 6766 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x) 6767 6768 /* REW:PTP_CTRL:PTP_TWOSTEP_STAMP */ 6769 #define REW_PTP_TWOSTEP_STAMP __REG(TARGET_REW,\ 6770 0, 1, 378368, 0, 1, 40, 4, 0, 1, 4) 6771 6772 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC GENMASK(29, 0) 6773 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\ 6774 FIELD_PREP(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 6775 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\ 6776 FIELD_GET(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 6777 6778 /* REW:PTP_CTRL:PTP_TWOSTEP_STAMP_SUBNS */ 6779 #define REW_PTP_TWOSTEP_STAMP_SUBNS __REG(TARGET_REW,\ 6780 0, 1, 378368, 0, 1, 40, 8, 0, 1, 4) 6781 6782 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC GENMASK(7, 0) 6783 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_SET(x)\ 6784 FIELD_PREP(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x) 6785 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_GET(x)\ 6786 FIELD_GET(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x) 6787 6788 /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO */ 6789 #define REW_PTP_RSRV_NOT_ZERO __REG(TARGET_REW,\ 6790 0, 1, 378368, 0, 1, 40, 12, 0, 1, 4) 6791 6792 /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO1 */ 6793 #define REW_PTP_RSRV_NOT_ZERO1 __REG(TARGET_REW,\ 6794 0, 1, 378368, 0, 1, 40, 16, 0, 1, 4) 6795 6796 /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO2 */ 6797 #define REW_PTP_RSRV_NOT_ZERO2 __REG(TARGET_REW,\ 6798 0, 1, 378368, 0, 1, 40, 20, 0, 1, 4) 6799 6800 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2 GENMASK(5, 0) 6801 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_SET(x)\ 6802 FIELD_PREP(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x) 6803 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_GET(x)\ 6804 FIELD_GET(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x) 6805 6806 /* REW:PTP_CTRL:PTP_GEN_STAMP_FMT */ 6807 #define REW_PTP_GEN_STAMP_FMT(r) __REG(TARGET_REW,\ 6808 0, 1, 378368, 0, 1, 40, 24, r, 4, 4) 6809 6810 #define REW_PTP_GEN_STAMP_FMT_RT_OFS GENMASK(6, 2) 6811 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_SET(x)\ 6812 FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_OFS, x) 6813 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_GET(x)\ 6814 FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_OFS, x) 6815 6816 #define REW_PTP_GEN_STAMP_FMT_RT_FMT GENMASK(1, 0) 6817 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_SET(x)\ 6818 FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_FMT, x) 6819 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_GET(x)\ 6820 FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_FMT, x) 6821 6822 /* REW:RAM_CTRL:RAM_INIT */ 6823 #define REW_RAM_INIT __REG(TARGET_REW,\ 6824 0, 1, 378696, 0, 1, 4, 0, 0, 1, 4) 6825 6826 #define REW_RAM_INIT_RAM_INIT BIT(1) 6827 #define REW_RAM_INIT_RAM_INIT_SET(x)\ 6828 FIELD_PREP(REW_RAM_INIT_RAM_INIT, x) 6829 #define REW_RAM_INIT_RAM_INIT_GET(x)\ 6830 FIELD_GET(REW_RAM_INIT_RAM_INIT, x) 6831 6832 #define REW_RAM_INIT_RAM_CFG_HOOK BIT(0) 6833 #define REW_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 6834 FIELD_PREP(REW_RAM_INIT_RAM_CFG_HOOK, x) 6835 #define REW_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 6836 FIELD_GET(REW_RAM_INIT_RAM_CFG_HOOK, x) 6837 6838 /* VCAP_ES0:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ 6839 #define VCAP_ES0_CTRL __REG(TARGET_VCAP_ES0,\ 6840 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) 6841 6842 #define VCAP_ES0_CTRL_UPDATE_CMD GENMASK(24, 22) 6843 #define VCAP_ES0_CTRL_UPDATE_CMD_SET(x)\ 6844 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_CMD, x) 6845 #define VCAP_ES0_CTRL_UPDATE_CMD_GET(x)\ 6846 FIELD_GET(VCAP_ES0_CTRL_UPDATE_CMD, x) 6847 6848 #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS BIT(21) 6849 #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS_SET(x)\ 6850 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_ENTRY_DIS, x) 6851 #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS_GET(x)\ 6852 FIELD_GET(VCAP_ES0_CTRL_UPDATE_ENTRY_DIS, x) 6853 6854 #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS BIT(20) 6855 #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS_SET(x)\ 6856 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_ACTION_DIS, x) 6857 #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS_GET(x)\ 6858 FIELD_GET(VCAP_ES0_CTRL_UPDATE_ACTION_DIS, x) 6859 6860 #define VCAP_ES0_CTRL_UPDATE_CNT_DIS BIT(19) 6861 #define VCAP_ES0_CTRL_UPDATE_CNT_DIS_SET(x)\ 6862 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_CNT_DIS, x) 6863 #define VCAP_ES0_CTRL_UPDATE_CNT_DIS_GET(x)\ 6864 FIELD_GET(VCAP_ES0_CTRL_UPDATE_CNT_DIS, x) 6865 6866 #define VCAP_ES0_CTRL_UPDATE_ADDR GENMASK(18, 3) 6867 #define VCAP_ES0_CTRL_UPDATE_ADDR_SET(x)\ 6868 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_ADDR, x) 6869 #define VCAP_ES0_CTRL_UPDATE_ADDR_GET(x)\ 6870 FIELD_GET(VCAP_ES0_CTRL_UPDATE_ADDR, x) 6871 6872 #define VCAP_ES0_CTRL_UPDATE_SHOT BIT(2) 6873 #define VCAP_ES0_CTRL_UPDATE_SHOT_SET(x)\ 6874 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_SHOT, x) 6875 #define VCAP_ES0_CTRL_UPDATE_SHOT_GET(x)\ 6876 FIELD_GET(VCAP_ES0_CTRL_UPDATE_SHOT, x) 6877 6878 #define VCAP_ES0_CTRL_CLEAR_CACHE BIT(1) 6879 #define VCAP_ES0_CTRL_CLEAR_CACHE_SET(x)\ 6880 FIELD_PREP(VCAP_ES0_CTRL_CLEAR_CACHE, x) 6881 #define VCAP_ES0_CTRL_CLEAR_CACHE_GET(x)\ 6882 FIELD_GET(VCAP_ES0_CTRL_CLEAR_CACHE, x) 6883 6884 #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN BIT(0) 6885 #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_SET(x)\ 6886 FIELD_PREP(VCAP_ES0_CTRL_MV_TRAFFIC_IGN, x) 6887 #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_GET(x)\ 6888 FIELD_GET(VCAP_ES0_CTRL_MV_TRAFFIC_IGN, x) 6889 6890 /* VCAP_ES0:VCAP_CORE_CFG:VCAP_MV_CFG */ 6891 #define VCAP_ES0_CFG __REG(TARGET_VCAP_ES0,\ 6892 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) 6893 6894 #define VCAP_ES0_CFG_MV_NUM_POS GENMASK(31, 16) 6895 #define VCAP_ES0_CFG_MV_NUM_POS_SET(x)\ 6896 FIELD_PREP(VCAP_ES0_CFG_MV_NUM_POS, x) 6897 #define VCAP_ES0_CFG_MV_NUM_POS_GET(x)\ 6898 FIELD_GET(VCAP_ES0_CFG_MV_NUM_POS, x) 6899 6900 #define VCAP_ES0_CFG_MV_SIZE GENMASK(15, 0) 6901 #define VCAP_ES0_CFG_MV_SIZE_SET(x)\ 6902 FIELD_PREP(VCAP_ES0_CFG_MV_SIZE, x) 6903 #define VCAP_ES0_CFG_MV_SIZE_GET(x)\ 6904 FIELD_GET(VCAP_ES0_CFG_MV_SIZE, x) 6905 6906 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ 6907 #define VCAP_ES0_VCAP_ENTRY_DAT(r) __REG(TARGET_VCAP_ES0,\ 6908 0, 1, 8, 0, 1, 904, 0, r, 64, 4) 6909 6910 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_MASK_DAT */ 6911 #define VCAP_ES0_VCAP_MASK_DAT(r) __REG(TARGET_VCAP_ES0,\ 6912 0, 1, 8, 0, 1, 904, 256, r, 64, 4) 6913 6914 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ 6915 #define VCAP_ES0_VCAP_ACTION_DAT(r) __REG(TARGET_VCAP_ES0,\ 6916 0, 1, 8, 0, 1, 904, 512, r, 64, 4) 6917 6918 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_DAT */ 6919 #define VCAP_ES0_VCAP_CNT_DAT(r) __REG(TARGET_VCAP_ES0,\ 6920 0, 1, 8, 0, 1, 904, 768, r, 32, 4) 6921 6922 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ 6923 #define VCAP_ES0_VCAP_CNT_FW_DAT __REG(TARGET_VCAP_ES0,\ 6924 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) 6925 6926 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_TG_DAT */ 6927 #define VCAP_ES0_VCAP_TG_DAT __REG(TARGET_VCAP_ES0,\ 6928 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) 6929 6930 /* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_IDX */ 6931 #define VCAP_ES0_IDX __REG(TARGET_VCAP_ES0,\ 6932 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) 6933 6934 #define VCAP_ES0_IDX_CORE_IDX GENMASK(3, 0) 6935 #define VCAP_ES0_IDX_CORE_IDX_SET(x)\ 6936 FIELD_PREP(VCAP_ES0_IDX_CORE_IDX, x) 6937 #define VCAP_ES0_IDX_CORE_IDX_GET(x)\ 6938 FIELD_GET(VCAP_ES0_IDX_CORE_IDX, x) 6939 6940 /* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_MAP */ 6941 #define VCAP_ES0_MAP __REG(TARGET_VCAP_ES0,\ 6942 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) 6943 6944 #define VCAP_ES0_MAP_CORE_MAP GENMASK(2, 0) 6945 #define VCAP_ES0_MAP_CORE_MAP_SET(x)\ 6946 FIELD_PREP(VCAP_ES0_MAP_CORE_MAP, x) 6947 #define VCAP_ES0_MAP_CORE_MAP_GET(x)\ 6948 FIELD_GET(VCAP_ES0_MAP_CORE_MAP, x) 6949 6950 /* VCAP_ES0:VCAP_CORE_STICKY:VCAP_STICKY */ 6951 #define VCAP_ES0_VCAP_STICKY __REG(TARGET_VCAP_ES0,\ 6952 0, 1, 920, 0, 1, 4, 0, 0, 1, 4) 6953 6954 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0) 6955 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\ 6956 FIELD_PREP(VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x) 6957 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\ 6958 FIELD_GET(VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x) 6959 6960 /* VCAP_ES0:VCAP_CONST:VCAP_VER */ 6961 #define VCAP_ES0_VCAP_VER __REG(TARGET_VCAP_ES0,\ 6962 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) 6963 6964 /* VCAP_ES0:VCAP_CONST:ENTRY_WIDTH */ 6965 #define VCAP_ES0_ENTRY_WIDTH __REG(TARGET_VCAP_ES0,\ 6966 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) 6967 6968 /* VCAP_ES0:VCAP_CONST:ENTRY_CNT */ 6969 #define VCAP_ES0_ENTRY_CNT __REG(TARGET_VCAP_ES0,\ 6970 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) 6971 6972 /* VCAP_ES0:VCAP_CONST:ENTRY_SWCNT */ 6973 #define VCAP_ES0_ENTRY_SWCNT __REG(TARGET_VCAP_ES0,\ 6974 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) 6975 6976 /* VCAP_ES0:VCAP_CONST:ENTRY_TG_WIDTH */ 6977 #define VCAP_ES0_ENTRY_TG_WIDTH __REG(TARGET_VCAP_ES0,\ 6978 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) 6979 6980 /* VCAP_ES0:VCAP_CONST:ACTION_DEF_CNT */ 6981 #define VCAP_ES0_ACTION_DEF_CNT __REG(TARGET_VCAP_ES0,\ 6982 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) 6983 6984 /* VCAP_ES0:VCAP_CONST:ACTION_WIDTH */ 6985 #define VCAP_ES0_ACTION_WIDTH __REG(TARGET_VCAP_ES0,\ 6986 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) 6987 6988 /* VCAP_ES0:VCAP_CONST:CNT_WIDTH */ 6989 #define VCAP_ES0_CNT_WIDTH __REG(TARGET_VCAP_ES0,\ 6990 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) 6991 6992 /* VCAP_ES0:VCAP_CONST:CORE_CNT */ 6993 #define VCAP_ES0_CORE_CNT __REG(TARGET_VCAP_ES0,\ 6994 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) 6995 6996 /* VCAP_ES0:VCAP_CONST:IF_CNT */ 6997 #define VCAP_ES0_IF_CNT __REG(TARGET_VCAP_ES0,\ 6998 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) 6999 7000 /* VCAP_ES2:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ 7001 #define VCAP_ES2_CTRL __REG(TARGET_VCAP_ES2,\ 7002 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) 7003 7004 #define VCAP_ES2_CTRL_UPDATE_CMD GENMASK(24, 22) 7005 #define VCAP_ES2_CTRL_UPDATE_CMD_SET(x)\ 7006 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_CMD, x) 7007 #define VCAP_ES2_CTRL_UPDATE_CMD_GET(x)\ 7008 FIELD_GET(VCAP_ES2_CTRL_UPDATE_CMD, x) 7009 7010 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS BIT(21) 7011 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_SET(x)\ 7012 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ENTRY_DIS, x) 7013 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_GET(x)\ 7014 FIELD_GET(VCAP_ES2_CTRL_UPDATE_ENTRY_DIS, x) 7015 7016 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS BIT(20) 7017 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_SET(x)\ 7018 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ACTION_DIS, x) 7019 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_GET(x)\ 7020 FIELD_GET(VCAP_ES2_CTRL_UPDATE_ACTION_DIS, x) 7021 7022 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS BIT(19) 7023 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS_SET(x)\ 7024 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_CNT_DIS, x) 7025 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS_GET(x)\ 7026 FIELD_GET(VCAP_ES2_CTRL_UPDATE_CNT_DIS, x) 7027 7028 #define VCAP_ES2_CTRL_UPDATE_ADDR GENMASK(18, 3) 7029 #define VCAP_ES2_CTRL_UPDATE_ADDR_SET(x)\ 7030 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ADDR, x) 7031 #define VCAP_ES2_CTRL_UPDATE_ADDR_GET(x)\ 7032 FIELD_GET(VCAP_ES2_CTRL_UPDATE_ADDR, x) 7033 7034 #define VCAP_ES2_CTRL_UPDATE_SHOT BIT(2) 7035 #define VCAP_ES2_CTRL_UPDATE_SHOT_SET(x)\ 7036 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_SHOT, x) 7037 #define VCAP_ES2_CTRL_UPDATE_SHOT_GET(x)\ 7038 FIELD_GET(VCAP_ES2_CTRL_UPDATE_SHOT, x) 7039 7040 #define VCAP_ES2_CTRL_CLEAR_CACHE BIT(1) 7041 #define VCAP_ES2_CTRL_CLEAR_CACHE_SET(x)\ 7042 FIELD_PREP(VCAP_ES2_CTRL_CLEAR_CACHE, x) 7043 #define VCAP_ES2_CTRL_CLEAR_CACHE_GET(x)\ 7044 FIELD_GET(VCAP_ES2_CTRL_CLEAR_CACHE, x) 7045 7046 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN BIT(0) 7047 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_SET(x)\ 7048 FIELD_PREP(VCAP_ES2_CTRL_MV_TRAFFIC_IGN, x) 7049 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_GET(x)\ 7050 FIELD_GET(VCAP_ES2_CTRL_MV_TRAFFIC_IGN, x) 7051 7052 /* VCAP_ES2:VCAP_CORE_CFG:VCAP_MV_CFG */ 7053 #define VCAP_ES2_CFG __REG(TARGET_VCAP_ES2,\ 7054 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) 7055 7056 #define VCAP_ES2_CFG_MV_NUM_POS GENMASK(31, 16) 7057 #define VCAP_ES2_CFG_MV_NUM_POS_SET(x)\ 7058 FIELD_PREP(VCAP_ES2_CFG_MV_NUM_POS, x) 7059 #define VCAP_ES2_CFG_MV_NUM_POS_GET(x)\ 7060 FIELD_GET(VCAP_ES2_CFG_MV_NUM_POS, x) 7061 7062 #define VCAP_ES2_CFG_MV_SIZE GENMASK(15, 0) 7063 #define VCAP_ES2_CFG_MV_SIZE_SET(x)\ 7064 FIELD_PREP(VCAP_ES2_CFG_MV_SIZE, x) 7065 #define VCAP_ES2_CFG_MV_SIZE_GET(x)\ 7066 FIELD_GET(VCAP_ES2_CFG_MV_SIZE, x) 7067 7068 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ 7069 #define VCAP_ES2_VCAP_ENTRY_DAT(r) __REG(TARGET_VCAP_ES2,\ 7070 0, 1, 8, 0, 1, 904, 0, r, 64, 4) 7071 7072 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_MASK_DAT */ 7073 #define VCAP_ES2_VCAP_MASK_DAT(r) __REG(TARGET_VCAP_ES2,\ 7074 0, 1, 8, 0, 1, 904, 256, r, 64, 4) 7075 7076 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ 7077 #define VCAP_ES2_VCAP_ACTION_DAT(r) __REG(TARGET_VCAP_ES2,\ 7078 0, 1, 8, 0, 1, 904, 512, r, 64, 4) 7079 7080 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_DAT */ 7081 #define VCAP_ES2_VCAP_CNT_DAT(r) __REG(TARGET_VCAP_ES2,\ 7082 0, 1, 8, 0, 1, 904, 768, r, 32, 4) 7083 7084 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ 7085 #define VCAP_ES2_VCAP_CNT_FW_DAT __REG(TARGET_VCAP_ES2,\ 7086 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) 7087 7088 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_TG_DAT */ 7089 #define VCAP_ES2_VCAP_TG_DAT __REG(TARGET_VCAP_ES2,\ 7090 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) 7091 7092 /* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_IDX */ 7093 #define VCAP_ES2_IDX __REG(TARGET_VCAP_ES2,\ 7094 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) 7095 7096 #define VCAP_ES2_IDX_CORE_IDX GENMASK(3, 0) 7097 #define VCAP_ES2_IDX_CORE_IDX_SET(x)\ 7098 FIELD_PREP(VCAP_ES2_IDX_CORE_IDX, x) 7099 #define VCAP_ES2_IDX_CORE_IDX_GET(x)\ 7100 FIELD_GET(VCAP_ES2_IDX_CORE_IDX, x) 7101 7102 /* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_MAP */ 7103 #define VCAP_ES2_MAP __REG(TARGET_VCAP_ES2,\ 7104 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) 7105 7106 #define VCAP_ES2_MAP_CORE_MAP GENMASK(2, 0) 7107 #define VCAP_ES2_MAP_CORE_MAP_SET(x)\ 7108 FIELD_PREP(VCAP_ES2_MAP_CORE_MAP, x) 7109 #define VCAP_ES2_MAP_CORE_MAP_GET(x)\ 7110 FIELD_GET(VCAP_ES2_MAP_CORE_MAP, x) 7111 7112 /* VCAP_ES2:VCAP_CORE_STICKY:VCAP_STICKY */ 7113 #define VCAP_ES2_VCAP_STICKY __REG(TARGET_VCAP_ES2,\ 7114 0, 1, 920, 0, 1, 4, 0, 0, 1, 4) 7115 7116 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0) 7117 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\ 7118 FIELD_PREP(VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x) 7119 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\ 7120 FIELD_GET(VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x) 7121 7122 /* VCAP_ES2:VCAP_CONST:VCAP_VER */ 7123 #define VCAP_ES2_VCAP_VER __REG(TARGET_VCAP_ES2,\ 7124 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) 7125 7126 /* VCAP_ES2:VCAP_CONST:ENTRY_WIDTH */ 7127 #define VCAP_ES2_ENTRY_WIDTH __REG(TARGET_VCAP_ES2,\ 7128 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) 7129 7130 /* VCAP_ES2:VCAP_CONST:ENTRY_CNT */ 7131 #define VCAP_ES2_ENTRY_CNT __REG(TARGET_VCAP_ES2,\ 7132 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) 7133 7134 /* VCAP_ES2:VCAP_CONST:ENTRY_SWCNT */ 7135 #define VCAP_ES2_ENTRY_SWCNT __REG(TARGET_VCAP_ES2,\ 7136 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) 7137 7138 /* VCAP_ES2:VCAP_CONST:ENTRY_TG_WIDTH */ 7139 #define VCAP_ES2_ENTRY_TG_WIDTH __REG(TARGET_VCAP_ES2,\ 7140 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) 7141 7142 /* VCAP_ES2:VCAP_CONST:ACTION_DEF_CNT */ 7143 #define VCAP_ES2_ACTION_DEF_CNT __REG(TARGET_VCAP_ES2,\ 7144 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) 7145 7146 /* VCAP_ES2:VCAP_CONST:ACTION_WIDTH */ 7147 #define VCAP_ES2_ACTION_WIDTH __REG(TARGET_VCAP_ES2,\ 7148 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) 7149 7150 /* VCAP_ES2:VCAP_CONST:CNT_WIDTH */ 7151 #define VCAP_ES2_CNT_WIDTH __REG(TARGET_VCAP_ES2,\ 7152 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) 7153 7154 /* VCAP_ES2:VCAP_CONST:CORE_CNT */ 7155 #define VCAP_ES2_CORE_CNT __REG(TARGET_VCAP_ES2,\ 7156 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) 7157 7158 /* VCAP_ES2:VCAP_CONST:IF_CNT */ 7159 #define VCAP_ES2_IF_CNT __REG(TARGET_VCAP_ES2,\ 7160 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) 7161 7162 /* VCAP_SUPER:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ 7163 #define VCAP_SUPER_CTRL __REG(TARGET_VCAP_SUPER,\ 7164 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) 7165 7166 #define VCAP_SUPER_CTRL_UPDATE_CMD GENMASK(24, 22) 7167 #define VCAP_SUPER_CTRL_UPDATE_CMD_SET(x)\ 7168 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_CMD, x) 7169 #define VCAP_SUPER_CTRL_UPDATE_CMD_GET(x)\ 7170 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_CMD, x) 7171 7172 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS BIT(21) 7173 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_SET(x)\ 7174 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS, x) 7175 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_GET(x)\ 7176 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS, x) 7177 7178 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS BIT(20) 7179 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_SET(x)\ 7180 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ACTION_DIS, x) 7181 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_GET(x)\ 7182 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ACTION_DIS, x) 7183 7184 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS BIT(19) 7185 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_SET(x)\ 7186 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_CNT_DIS, x) 7187 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_GET(x)\ 7188 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_CNT_DIS, x) 7189 7190 #define VCAP_SUPER_CTRL_UPDATE_ADDR GENMASK(18, 3) 7191 #define VCAP_SUPER_CTRL_UPDATE_ADDR_SET(x)\ 7192 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ADDR, x) 7193 #define VCAP_SUPER_CTRL_UPDATE_ADDR_GET(x)\ 7194 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ADDR, x) 7195 7196 #define VCAP_SUPER_CTRL_UPDATE_SHOT BIT(2) 7197 #define VCAP_SUPER_CTRL_UPDATE_SHOT_SET(x)\ 7198 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_SHOT, x) 7199 #define VCAP_SUPER_CTRL_UPDATE_SHOT_GET(x)\ 7200 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_SHOT, x) 7201 7202 #define VCAP_SUPER_CTRL_CLEAR_CACHE BIT(1) 7203 #define VCAP_SUPER_CTRL_CLEAR_CACHE_SET(x)\ 7204 FIELD_PREP(VCAP_SUPER_CTRL_CLEAR_CACHE, x) 7205 #define VCAP_SUPER_CTRL_CLEAR_CACHE_GET(x)\ 7206 FIELD_GET(VCAP_SUPER_CTRL_CLEAR_CACHE, x) 7207 7208 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN BIT(0) 7209 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_SET(x)\ 7210 FIELD_PREP(VCAP_SUPER_CTRL_MV_TRAFFIC_IGN, x) 7211 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_GET(x)\ 7212 FIELD_GET(VCAP_SUPER_CTRL_MV_TRAFFIC_IGN, x) 7213 7214 /* VCAP_SUPER:VCAP_CORE_CFG:VCAP_MV_CFG */ 7215 #define VCAP_SUPER_CFG __REG(TARGET_VCAP_SUPER,\ 7216 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) 7217 7218 #define VCAP_SUPER_CFG_MV_NUM_POS GENMASK(31, 16) 7219 #define VCAP_SUPER_CFG_MV_NUM_POS_SET(x)\ 7220 FIELD_PREP(VCAP_SUPER_CFG_MV_NUM_POS, x) 7221 #define VCAP_SUPER_CFG_MV_NUM_POS_GET(x)\ 7222 FIELD_GET(VCAP_SUPER_CFG_MV_NUM_POS, x) 7223 7224 #define VCAP_SUPER_CFG_MV_SIZE GENMASK(15, 0) 7225 #define VCAP_SUPER_CFG_MV_SIZE_SET(x)\ 7226 FIELD_PREP(VCAP_SUPER_CFG_MV_SIZE, x) 7227 #define VCAP_SUPER_CFG_MV_SIZE_GET(x)\ 7228 FIELD_GET(VCAP_SUPER_CFG_MV_SIZE, x) 7229 7230 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ 7231 #define VCAP_SUPER_VCAP_ENTRY_DAT(r) __REG(TARGET_VCAP_SUPER,\ 7232 0, 1, 8, 0, 1, 904, 0, r, 64, 4) 7233 7234 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_MASK_DAT */ 7235 #define VCAP_SUPER_VCAP_MASK_DAT(r) __REG(TARGET_VCAP_SUPER,\ 7236 0, 1, 8, 0, 1, 904, 256, r, 64, 4) 7237 7238 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ 7239 #define VCAP_SUPER_VCAP_ACTION_DAT(r) __REG(TARGET_VCAP_SUPER,\ 7240 0, 1, 8, 0, 1, 904, 512, r, 64, 4) 7241 7242 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_DAT */ 7243 #define VCAP_SUPER_VCAP_CNT_DAT(r) __REG(TARGET_VCAP_SUPER,\ 7244 0, 1, 8, 0, 1, 904, 768, r, 32, 4) 7245 7246 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ 7247 #define VCAP_SUPER_VCAP_CNT_FW_DAT __REG(TARGET_VCAP_SUPER,\ 7248 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) 7249 7250 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_TG_DAT */ 7251 #define VCAP_SUPER_VCAP_TG_DAT __REG(TARGET_VCAP_SUPER,\ 7252 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) 7253 7254 /* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_IDX */ 7255 #define VCAP_SUPER_IDX __REG(TARGET_VCAP_SUPER,\ 7256 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) 7257 7258 #define VCAP_SUPER_IDX_CORE_IDX GENMASK(3, 0) 7259 #define VCAP_SUPER_IDX_CORE_IDX_SET(x)\ 7260 FIELD_PREP(VCAP_SUPER_IDX_CORE_IDX, x) 7261 #define VCAP_SUPER_IDX_CORE_IDX_GET(x)\ 7262 FIELD_GET(VCAP_SUPER_IDX_CORE_IDX, x) 7263 7264 /* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_MAP */ 7265 #define VCAP_SUPER_MAP __REG(TARGET_VCAP_SUPER,\ 7266 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) 7267 7268 #define VCAP_SUPER_MAP_CORE_MAP GENMASK(2, 0) 7269 #define VCAP_SUPER_MAP_CORE_MAP_SET(x)\ 7270 FIELD_PREP(VCAP_SUPER_MAP_CORE_MAP, x) 7271 #define VCAP_SUPER_MAP_CORE_MAP_GET(x)\ 7272 FIELD_GET(VCAP_SUPER_MAP_CORE_MAP, x) 7273 7274 /* VCAP_SUPER:VCAP_CONST:VCAP_VER */ 7275 #define VCAP_SUPER_VCAP_VER __REG(TARGET_VCAP_SUPER,\ 7276 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) 7277 7278 /* VCAP_SUPER:VCAP_CONST:ENTRY_WIDTH */ 7279 #define VCAP_SUPER_ENTRY_WIDTH __REG(TARGET_VCAP_SUPER,\ 7280 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) 7281 7282 /* VCAP_SUPER:VCAP_CONST:ENTRY_CNT */ 7283 #define VCAP_SUPER_ENTRY_CNT __REG(TARGET_VCAP_SUPER,\ 7284 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) 7285 7286 /* VCAP_SUPER:VCAP_CONST:ENTRY_SWCNT */ 7287 #define VCAP_SUPER_ENTRY_SWCNT __REG(TARGET_VCAP_SUPER,\ 7288 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) 7289 7290 /* VCAP_SUPER:VCAP_CONST:ENTRY_TG_WIDTH */ 7291 #define VCAP_SUPER_ENTRY_TG_WIDTH __REG(TARGET_VCAP_SUPER,\ 7292 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) 7293 7294 /* VCAP_SUPER:VCAP_CONST:ACTION_DEF_CNT */ 7295 #define VCAP_SUPER_ACTION_DEF_CNT __REG(TARGET_VCAP_SUPER,\ 7296 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) 7297 7298 /* VCAP_SUPER:VCAP_CONST:ACTION_WIDTH */ 7299 #define VCAP_SUPER_ACTION_WIDTH __REG(TARGET_VCAP_SUPER,\ 7300 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) 7301 7302 /* VCAP_SUPER:VCAP_CONST:CNT_WIDTH */ 7303 #define VCAP_SUPER_CNT_WIDTH __REG(TARGET_VCAP_SUPER,\ 7304 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) 7305 7306 /* VCAP_SUPER:VCAP_CONST:CORE_CNT */ 7307 #define VCAP_SUPER_CORE_CNT __REG(TARGET_VCAP_SUPER,\ 7308 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) 7309 7310 /* VCAP_SUPER:VCAP_CONST:IF_CNT */ 7311 #define VCAP_SUPER_IF_CNT __REG(TARGET_VCAP_SUPER,\ 7312 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) 7313 7314 /* VCAP_SUPER:RAM_CTRL:RAM_INIT */ 7315 #define VCAP_SUPER_RAM_INIT __REG(TARGET_VCAP_SUPER,\ 7316 0, 1, 1120, 0, 1, 4, 0, 0, 1, 4) 7317 7318 #define VCAP_SUPER_RAM_INIT_RAM_INIT BIT(1) 7319 #define VCAP_SUPER_RAM_INIT_RAM_INIT_SET(x)\ 7320 FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_INIT, x) 7321 #define VCAP_SUPER_RAM_INIT_RAM_INIT_GET(x)\ 7322 FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_INIT, x) 7323 7324 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK BIT(0) 7325 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 7326 FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x) 7327 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 7328 FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x) 7329 7330 /* VOP:RAM_CTRL:RAM_INIT */ 7331 #define VOP_RAM_INIT __REG(TARGET_VOP,\ 7332 0, 1, 279176, 0, 1, 4, 0, 0, 1, 4) 7333 7334 #define VOP_RAM_INIT_RAM_INIT BIT(1) 7335 #define VOP_RAM_INIT_RAM_INIT_SET(x)\ 7336 FIELD_PREP(VOP_RAM_INIT_RAM_INIT, x) 7337 #define VOP_RAM_INIT_RAM_INIT_GET(x)\ 7338 FIELD_GET(VOP_RAM_INIT_RAM_INIT, x) 7339 7340 #define VOP_RAM_INIT_RAM_CFG_HOOK BIT(0) 7341 #define VOP_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 7342 FIELD_PREP(VOP_RAM_INIT_RAM_CFG_HOOK, x) 7343 #define VOP_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 7344 FIELD_GET(VOP_RAM_INIT_RAM_CFG_HOOK, x) 7345 7346 /* XQS:SYSTEM:STAT_CFG */ 7347 #define XQS_STAT_CFG __REG(TARGET_XQS,\ 7348 0, 1, 6768, 0, 1, 872, 860, 0, 1, 4) 7349 7350 #define XQS_STAT_CFG_STAT_CLEAR_SHOT GENMASK(21, 18) 7351 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_SET(x)\ 7352 FIELD_PREP(XQS_STAT_CFG_STAT_CLEAR_SHOT, x) 7353 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_GET(x)\ 7354 FIELD_GET(XQS_STAT_CFG_STAT_CLEAR_SHOT, x) 7355 7356 #define XQS_STAT_CFG_STAT_VIEW GENMASK(17, 5) 7357 #define XQS_STAT_CFG_STAT_VIEW_SET(x)\ 7358 FIELD_PREP(XQS_STAT_CFG_STAT_VIEW, x) 7359 #define XQS_STAT_CFG_STAT_VIEW_GET(x)\ 7360 FIELD_GET(XQS_STAT_CFG_STAT_VIEW, x) 7361 7362 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY BIT(4) 7363 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_SET(x)\ 7364 FIELD_PREP(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x) 7365 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_GET(x)\ 7366 FIELD_GET(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x) 7367 7368 #define XQS_STAT_CFG_STAT_WRAP_DIS GENMASK(3, 0) 7369 #define XQS_STAT_CFG_STAT_WRAP_DIS_SET(x)\ 7370 FIELD_PREP(XQS_STAT_CFG_STAT_WRAP_DIS, x) 7371 #define XQS_STAT_CFG_STAT_WRAP_DIS_GET(x)\ 7372 FIELD_GET(XQS_STAT_CFG_STAT_WRAP_DIS, x) 7373 7374 /* XQS:QLIMIT_SHR:QLIMIT_SHR_TOP_CFG */ 7375 #define XQS_QLIMIT_SHR_TOP_CFG(g) __REG(TARGET_XQS,\ 7376 0, 1, 7936, g, 4, 48, 0, 0, 1, 4) 7377 7378 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP GENMASK(14, 0) 7379 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_SET(x)\ 7380 FIELD_PREP(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) 7381 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_GET(x)\ 7382 FIELD_GET(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) 7383 7384 /* XQS:QLIMIT_SHR:QLIMIT_SHR_ATOP_CFG */ 7385 #define XQS_QLIMIT_SHR_ATOP_CFG(g) __REG(TARGET_XQS,\ 7386 0, 1, 7936, g, 4, 48, 4, 0, 1, 4) 7387 7388 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP GENMASK(14, 0) 7389 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_SET(x)\ 7390 FIELD_PREP(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) 7391 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_GET(x)\ 7392 FIELD_GET(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) 7393 7394 /* XQS:QLIMIT_SHR:QLIMIT_SHR_CTOP_CFG */ 7395 #define XQS_QLIMIT_SHR_CTOP_CFG(g) __REG(TARGET_XQS,\ 7396 0, 1, 7936, g, 4, 48, 8, 0, 1, 4) 7397 7398 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP GENMASK(14, 0) 7399 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_SET(x)\ 7400 FIELD_PREP(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) 7401 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_GET(x)\ 7402 FIELD_GET(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) 7403 7404 /* XQS:QLIMIT_SHR:QLIMIT_SHR_QLIM_CFG */ 7405 #define XQS_QLIMIT_SHR_QLIM_CFG(g) __REG(TARGET_XQS,\ 7406 0, 1, 7936, g, 4, 48, 12, 0, 1, 4) 7407 7408 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM GENMASK(14, 0) 7409 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_SET(x)\ 7410 FIELD_PREP(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) 7411 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_GET(x)\ 7412 FIELD_GET(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) 7413 7414 /* XQS:STAT:CNT */ 7415 #define XQS_CNT(g) __REG(TARGET_XQS,\ 7416 0, 1, 0, g, 1024, 4, 0, 0, 1, 4) 7417 7418 #endif /* _SPARX5_MAIN_REGS_H_ */ 7419