1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2023 Linaro Ltd.
4 * Author: Peter Griffin <peter.griffin@linaro.org>
5 *
6 * Common Clock Framework support for GS101.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13
14 #include <dt-bindings/clock/google,gs101.h>
15
16 #include "clk.h"
17 #include "clk-exynos-arm64.h"
18 #include "clk-pll.h"
19
20 /* NOTE: Must be equal to the last clock ID increased by one */
21 #define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1)
22 #define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1)
23 #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_P_HSI0_ACLK + 1)
24 #define CLKS_NR_HSI2 (CLK_GOUT_HSI2_XIU_P_HSI2_ACLK + 1)
25 #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
26 #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
27 #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)
28
29 /* ---- CMU_TOP ------------------------------------------------------------- */
30
31 /* Register Offset definitions for CMU_TOP (0x1e080000) */
32 #define PLL_LOCKTIME_PLL_SHARED0 0x0000
33 #define PLL_LOCKTIME_PLL_SHARED1 0x0004
34 #define PLL_LOCKTIME_PLL_SHARED2 0x0008
35 #define PLL_LOCKTIME_PLL_SHARED3 0x000c
36 #define PLL_LOCKTIME_PLL_SPARE 0x0010
37 #define PLL_CON0_PLL_SHARED0 0x0100
38 #define PLL_CON1_PLL_SHARED0 0x0104
39 #define PLL_CON2_PLL_SHARED0 0x0108
40 #define PLL_CON3_PLL_SHARED0 0x010c
41 #define PLL_CON4_PLL_SHARED0 0x0110
42 #define PLL_CON0_PLL_SHARED1 0x0140
43 #define PLL_CON1_PLL_SHARED1 0x0144
44 #define PLL_CON2_PLL_SHARED1 0x0148
45 #define PLL_CON3_PLL_SHARED1 0x014c
46 #define PLL_CON4_PLL_SHARED1 0x0150
47 #define PLL_CON0_PLL_SHARED2 0x0180
48 #define PLL_CON1_PLL_SHARED2 0x0184
49 #define PLL_CON2_PLL_SHARED2 0x0188
50 #define PLL_CON3_PLL_SHARED2 0x018c
51 #define PLL_CON4_PLL_SHARED2 0x0190
52 #define PLL_CON0_PLL_SHARED3 0x01c0
53 #define PLL_CON1_PLL_SHARED3 0x01c4
54 #define PLL_CON2_PLL_SHARED3 0x01c8
55 #define PLL_CON3_PLL_SHARED3 0x01cc
56 #define PLL_CON4_PLL_SHARED3 0x01d0
57 #define PLL_CON0_PLL_SPARE 0x0200
58 #define PLL_CON1_PLL_SPARE 0x0204
59 #define PLL_CON2_PLL_SPARE 0x0208
60 #define PLL_CON3_PLL_SPARE 0x020c
61 #define PLL_CON4_PLL_SPARE 0x0210
62 #define CMU_CMU_TOP_CONTROLLER_OPTION 0x0800
63 #define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0 0x0810
64 #define CMU_HCHGEN_CLKMUX_CMU_BOOST 0x0840
65 #define CMU_HCHGEN_CLKMUX_TOP_BOOST 0x0844
66 #define CMU_HCHGEN_CLKMUX 0x0850
67 #define POWER_FAIL_DETECT_PLL 0x0864
68 #define EARLY_WAKEUP_FORCED_0_ENABLE 0x0870
69 #define EARLY_WAKEUP_FORCED_1_ENABLE 0x0874
70 #define EARLY_WAKEUP_APM_CTRL 0x0878
71 #define EARLY_WAKEUP_CLUSTER0_CTRL 0x087c
72 #define EARLY_WAKEUP_DPU_CTRL 0x0880
73 #define EARLY_WAKEUP_CSIS_CTRL 0x0884
74 #define EARLY_WAKEUP_APM_DEST 0x0890
75 #define EARLY_WAKEUP_CLUSTER0_DEST 0x0894
76 #define EARLY_WAKEUP_DPU_DEST 0x0898
77 #define EARLY_WAKEUP_CSIS_DEST 0x089c
78 #define EARLY_WAKEUP_SW_TRIG_APM 0x08c0
79 #define EARLY_WAKEUP_SW_TRIG_APM_SET 0x08c4
80 #define EARLY_WAKEUP_SW_TRIG_APM_CLEAR 0x08c8
81 #define EARLY_WAKEUP_SW_TRIG_CLUSTER0 0x08d0
82 #define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET 0x08d4
83 #define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR 0x08d8
84 #define EARLY_WAKEUP_SW_TRIG_DPU 0x08e0
85 #define EARLY_WAKEUP_SW_TRIG_DPU_SET 0x08e4
86 #define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR 0x08e8
87 #define EARLY_WAKEUP_SW_TRIG_CSIS 0x08f0
88 #define EARLY_WAKEUP_SW_TRIG_CSIS_SET 0x08f4
89 #define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR 0x08f8
90 #define CLK_CON_MUX_MUX_CLKCMU_BO_BUS 0x1000
91 #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x1004
92 #define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1008
93 #define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS 0x100c
94 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1010
95 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1014
96 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1018
97 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x101c
98 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1020
99 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x1024
100 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6 0x1028
101 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7 0x102c
102 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030
103 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1 0x1034
104 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1038
105 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x103c
106 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1040
107 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1044
108 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048
109 #define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c
110 #define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS 0x1050
111 #define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x1054
112 #define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS 0x1058
113 #define CLK_CON_MUX_MUX_CLKCMU_EH_BUS 0x105c
114 #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1060
115 #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1064
116 #define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA 0x1068
117 #define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD 0x106c
118 #define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB 0x1070
119 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1074
120 #define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0 0x1078
121 #define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1 0x107c
122 #define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC 0x1080
123 #define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1084
124 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1088
125 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x108c
126 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1090
127 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG 0x1094
128 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1098
129 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x109c
130 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x10a0
131 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD 0x10a4
132 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a8
133 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x10ac
134 #define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10b0
135 #define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10b4
136 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC 0x10b8
137 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC 0x10bc
138 #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10c0
139 #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c4
140 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c8
141 #define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS 0x10cc
142 #define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS 0x10d0
143 #define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS 0x10d4
144 #define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA 0x10d8
145 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10dc
146 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10e0
147 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10e4
148 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10e8
149 #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10ec
150 #define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1 0x10f0
151 #define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF 0x10f4
152 #define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS 0x10f8
153 #define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU 0x10fc
154 #define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL 0x1100
155 #define CLK_CON_MUX_MUX_CLKCMU_TPU_UART 0x1104
156 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x1108
157 #define CLK_CON_DIV_CLKCMU_BO_BUS 0x1800
158 #define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1804
159 #define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x1808
160 #define CLK_CON_DIV_CLKCMU_BUS2_BUS 0x180c
161 #define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1810
162 #define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1814
163 #define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x1818
164 #define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x181c
165 #define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1820
166 #define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1824
167 #define CLK_CON_DIV_CLKCMU_CIS_CLK6 0x1828
168 #define CLK_CON_DIV_CLKCMU_CIS_CLK7 0x182c
169 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830
170 #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1834
171 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838
172 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
173 #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1840
174 #define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1844
175 #define CLK_CON_DIV_CLKCMU_DISP_BUS 0x1848
176 #define CLK_CON_DIV_CLKCMU_DNS_BUS 0x184c
177 #define CLK_CON_DIV_CLKCMU_DPU_BUS 0x1850
178 #define CLK_CON_DIV_CLKCMU_EH_BUS 0x1854
179 #define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1858
180 #define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x185c
181 #define CLK_CON_DIV_CLKCMU_G3AA_G3AA 0x1860
182 #define CLK_CON_DIV_CLKCMU_G3D_BUSD 0x1864
183 #define CLK_CON_DIV_CLKCMU_G3D_GLB 0x1868
184 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x186c
185 #define CLK_CON_DIV_CLKCMU_GDC_GDC0 0x1870
186 #define CLK_CON_DIV_CLKCMU_GDC_GDC1 0x1874
187 #define CLK_CON_DIV_CLKCMU_GDC_SCSC 0x1878
188 #define CLK_CON_DIV_CLKCMU_HPM 0x187c
189 #define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1880
190 #define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1884
191 #define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1888
192 #define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG 0x188c
193 #define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1890
194 #define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1894
195 #define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1898
196 #define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD 0x189c
197 #define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x18a0
198 #define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x18a4
199 #define CLK_CON_DIV_CLKCMU_IPP_BUS 0x18a8
200 #define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18ac
201 #define CLK_CON_DIV_CLKCMU_MCSC_ITSC 0x18b0
202 #define CLK_CON_DIV_CLKCMU_MCSC_MCSC 0x18b4
203 #define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18b8
204 #define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18bc
205 #define CLK_CON_DIV_CLKCMU_MISC_BUS 0x18c0
206 #define CLK_CON_DIV_CLKCMU_MISC_SSS 0x18c4
207 #define CLK_CON_DIV_CLKCMU_OTP 0x18c8
208 #define CLK_CON_DIV_CLKCMU_PDP_BUS 0x18cc
209 #define CLK_CON_DIV_CLKCMU_PDP_VRA 0x18d0
210 #define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18d4
211 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18d8
212 #define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18dc
213 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18e0
214 #define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18e4
215 #define CLK_CON_DIV_CLKCMU_TPU_BUS 0x18e8
216 #define CLK_CON_DIV_CLKCMU_TPU_TPU 0x18ec
217 #define CLK_CON_DIV_CLKCMU_TPU_TPUCTL 0x18f0
218 #define CLK_CON_DIV_CLKCMU_TPU_UART 0x18f4
219 #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18f8
220 #define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18fc
221 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x1900
222 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1904
223 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1908
224 #define CLK_CON_DIV_PLL_SHARED0_DIV5 0x190c
225 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1910
226 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1914
227 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1918
228 #define CLK_CON_DIV_PLL_SHARED2_DIV2 0x191c
229 #define CLK_CON_DIV_PLL_SHARED3_DIV2 0x1920
230 #define CLK_CON_GAT_CLKCMU_BUS0_BOOST 0x2000
231 #define CLK_CON_GAT_CLKCMU_BUS1_BOOST 0x2004
232 #define CLK_CON_GAT_CLKCMU_BUS2_BOOST 0x2008
233 #define CLK_CON_GAT_CLKCMU_CORE_BOOST 0x200c
234 #define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST 0x2010
235 #define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST 0x2014
236 #define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST 0x2018
237 #define CLK_CON_GAT_CLKCMU_MIF_BOOST 0x201c
238 #define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2020
239 #define CLK_CON_GAT_GATE_CLKCMU_BO_BUS 0x2024
240 #define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2028
241 #define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x202c
242 #define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS 0x2030
243 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x2034
244 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2038
245 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x203c
246 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2040
247 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x2044
248 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2048
249 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6 0x204c
250 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7 0x2050
251 #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2054
252 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2058
253 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x205c
254 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2060
255 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2064
256 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2068
257 #define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x206c
258 #define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS 0x2070
259 #define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x2074
260 #define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2078
261 #define CLK_CON_GAT_GATE_CLKCMU_EH_BUS 0x207c
262 #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x2080
263 #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2084
264 #define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA 0x2088
265 #define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD 0x208c
266 #define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB 0x2090
267 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2094
268 #define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0 0x2098
269 #define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1 0x209c
270 #define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC 0x20a0
271 #define CLK_CON_GAT_GATE_CLKCMU_HPM 0x20a4
272 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x20a8
273 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x20ac
274 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x20b0
275 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG 0x20b4
276 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x20b8
277 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x20bc
278 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20c0
279 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD 0x20c4
280 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20c8
281 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD 0x20cc
282 #define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20d0
283 #define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20d4
284 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC 0x20d8
285 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC 0x20dc
286 #define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20e0
287 #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20e4
288 #define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS 0x20e8
289 #define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS 0x20ec
290 #define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS 0x20f0
291 #define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA 0x20f4
292 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20f8
293 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20fc
294 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x2100
295 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x2104
296 #define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x2108
297 #define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF 0x210c
298 #define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS 0x2110
299 #define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU 0x2114
300 #define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL 0x2118
301 #define CLK_CON_GAT_GATE_CLKCMU_TPU_UART 0x211c
302 #define DMYQCH_CON_CMU_TOP_CMUREF_QCH 0x3000
303 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0 0x3004
304 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1 0x3008
305 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2 0x300c
306 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3 0x3010
307 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4 0x3014
308 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5 0x3018
309 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6 0x301c
310 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7 0x3020
311 #define DMYQCH_CON_OTP_QCH 0x3024
312 #define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP 0x3c00
313 #define QUEUE_ENTRY0_BLK_CMU_CMU_TOP 0x3c10
314 #define QUEUE_ENTRY1_BLK_CMU_CMU_TOP 0x3c14
315 #define QUEUE_ENTRY2_BLK_CMU_CMU_TOP 0x3c18
316 #define QUEUE_ENTRY3_BLK_CMU_CMU_TOP 0x3c1c
317 #define QUEUE_ENTRY4_BLK_CMU_CMU_TOP 0x3c20
318 #define QUEUE_ENTRY5_BLK_CMU_CMU_TOP 0x3c24
319 #define QUEUE_ENTRY6_BLK_CMU_CMU_TOP 0x3c28
320 #define QUEUE_ENTRY7_BLK_CMU_CMU_TOP 0x3c2c
321 #define MIFMIRROR_QUEUE_CTRL_REG 0x3e00
322 #define MIFMIRROR_QUEUE_ENTRY0 0x3e10
323 #define MIFMIRROR_QUEUE_ENTRY1 0x3e14
324 #define MIFMIRROR_QUEUE_ENTRY2 0x3e18
325 #define MIFMIRROR_QUEUE_ENTRY3 0x3e1c
326 #define MIFMIRROR_QUEUE_ENTRY4 0x3e20
327 #define MIFMIRROR_QUEUE_ENTRY5 0x3e24
328 #define MIFMIRROR_QUEUE_ENTRY6 0x3e28
329 #define MIFMIRROR_QUEUE_ENTRY7 0x3e2c
330 #define MIFMIRROR_QUEUE_BUSY 0x3e30
331 #define GENERALIO_ACD_CHANNEL_0 0x3f00
332 #define GENERALIO_ACD_CHANNEL_1 0x3f04
333 #define GENERALIO_ACD_CHANNEL_2 0x3f08
334 #define GENERALIO_ACD_CHANNEL_3 0x3f0c
335 #define GENERALIO_ACD_MASK 0x3f14
336
337 static const unsigned long cmu_top_clk_regs[] __initconst = {
338 PLL_LOCKTIME_PLL_SHARED0,
339 PLL_LOCKTIME_PLL_SHARED1,
340 PLL_LOCKTIME_PLL_SHARED2,
341 PLL_LOCKTIME_PLL_SHARED3,
342 PLL_LOCKTIME_PLL_SPARE,
343 PLL_CON0_PLL_SHARED0,
344 PLL_CON1_PLL_SHARED0,
345 PLL_CON2_PLL_SHARED0,
346 PLL_CON3_PLL_SHARED0,
347 PLL_CON4_PLL_SHARED0,
348 PLL_CON0_PLL_SHARED1,
349 PLL_CON1_PLL_SHARED1,
350 PLL_CON2_PLL_SHARED1,
351 PLL_CON3_PLL_SHARED1,
352 PLL_CON4_PLL_SHARED1,
353 PLL_CON0_PLL_SHARED2,
354 PLL_CON1_PLL_SHARED2,
355 PLL_CON2_PLL_SHARED2,
356 PLL_CON3_PLL_SHARED2,
357 PLL_CON4_PLL_SHARED2,
358 PLL_CON0_PLL_SHARED3,
359 PLL_CON1_PLL_SHARED3,
360 PLL_CON2_PLL_SHARED3,
361 PLL_CON3_PLL_SHARED3,
362 PLL_CON4_PLL_SHARED3,
363 PLL_CON0_PLL_SPARE,
364 PLL_CON1_PLL_SPARE,
365 PLL_CON2_PLL_SPARE,
366 PLL_CON3_PLL_SPARE,
367 PLL_CON4_PLL_SPARE,
368 CMU_CMU_TOP_CONTROLLER_OPTION,
369 CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0,
370 CMU_HCHGEN_CLKMUX_CMU_BOOST,
371 CMU_HCHGEN_CLKMUX_TOP_BOOST,
372 CMU_HCHGEN_CLKMUX,
373 POWER_FAIL_DETECT_PLL,
374 EARLY_WAKEUP_FORCED_0_ENABLE,
375 EARLY_WAKEUP_FORCED_1_ENABLE,
376 EARLY_WAKEUP_APM_CTRL,
377 EARLY_WAKEUP_CLUSTER0_CTRL,
378 EARLY_WAKEUP_DPU_CTRL,
379 EARLY_WAKEUP_CSIS_CTRL,
380 EARLY_WAKEUP_APM_DEST,
381 EARLY_WAKEUP_CLUSTER0_DEST,
382 EARLY_WAKEUP_DPU_DEST,
383 EARLY_WAKEUP_CSIS_DEST,
384 EARLY_WAKEUP_SW_TRIG_APM,
385 EARLY_WAKEUP_SW_TRIG_APM_SET,
386 EARLY_WAKEUP_SW_TRIG_APM_CLEAR,
387 EARLY_WAKEUP_SW_TRIG_CLUSTER0,
388 EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET,
389 EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR,
390 EARLY_WAKEUP_SW_TRIG_DPU,
391 EARLY_WAKEUP_SW_TRIG_DPU_SET,
392 EARLY_WAKEUP_SW_TRIG_DPU_CLEAR,
393 EARLY_WAKEUP_SW_TRIG_CSIS,
394 EARLY_WAKEUP_SW_TRIG_CSIS_SET,
395 EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR,
396 CLK_CON_MUX_MUX_CLKCMU_BO_BUS,
397 CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
398 CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS,
399 CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS,
400 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,
401 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,
402 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,
403 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,
404 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4,
405 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5,
406 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6,
407 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7,
408 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
409 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1,
410 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
411 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
412 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
413 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
414 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
415 CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS,
416 CLK_CON_MUX_MUX_CLKCMU_DISP_BUS,
417 CLK_CON_MUX_MUX_CLKCMU_DNS_BUS,
418 CLK_CON_MUX_MUX_CLKCMU_DPU_BUS,
419 CLK_CON_MUX_MUX_CLKCMU_EH_BUS,
420 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
421 CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
422 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA,
423 CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD,
424 CLK_CON_MUX_MUX_CLKCMU_G3D_GLB,
425 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
426 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0,
427 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1,
428 CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC,
429 CLK_CON_MUX_MUX_CLKCMU_HPM,
430 CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS,
431 CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC,
432 CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,
433 CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG,
434 CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS,
435 CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE,
436 CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS,
437 CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD,
438 CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE,
439 CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
440 CLK_CON_MUX_MUX_CLKCMU_IPP_BUS,
441 CLK_CON_MUX_MUX_CLKCMU_ITP_BUS,
442 CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC,
443 CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC,
444 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
445 CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
446 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
447 CLK_CON_MUX_MUX_CLKCMU_MISC_BUS,
448 CLK_CON_MUX_MUX_CLKCMU_MISC_SSS,
449 CLK_CON_MUX_MUX_CLKCMU_PDP_BUS,
450 CLK_CON_MUX_MUX_CLKCMU_PDP_VRA,
451 CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
452 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
453 CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
454 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
455 CLK_CON_MUX_MUX_CLKCMU_TNR_BUS,
456 CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1,
457 CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF,
458 CLK_CON_MUX_MUX_CLKCMU_TPU_BUS,
459 CLK_CON_MUX_MUX_CLKCMU_TPU_TPU,
460 CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL,
461 CLK_CON_MUX_MUX_CLKCMU_TPU_UART,
462 CLK_CON_MUX_MUX_CMU_CMUREF,
463 CLK_CON_DIV_CLKCMU_BO_BUS,
464 CLK_CON_DIV_CLKCMU_BUS0_BUS,
465 CLK_CON_DIV_CLKCMU_BUS1_BUS,
466 CLK_CON_DIV_CLKCMU_BUS2_BUS,
467 CLK_CON_DIV_CLKCMU_CIS_CLK0,
468 CLK_CON_DIV_CLKCMU_CIS_CLK1,
469 CLK_CON_DIV_CLKCMU_CIS_CLK2,
470 CLK_CON_DIV_CLKCMU_CIS_CLK3,
471 CLK_CON_DIV_CLKCMU_CIS_CLK4,
472 CLK_CON_DIV_CLKCMU_CIS_CLK5,
473 CLK_CON_DIV_CLKCMU_CIS_CLK6,
474 CLK_CON_DIV_CLKCMU_CIS_CLK7,
475 CLK_CON_DIV_CLKCMU_CORE_BUS,
476 CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
477 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
478 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
479 CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH,
480 CLK_CON_DIV_CLKCMU_CSIS_BUS,
481 CLK_CON_DIV_CLKCMU_DISP_BUS,
482 CLK_CON_DIV_CLKCMU_DNS_BUS,
483 CLK_CON_DIV_CLKCMU_DPU_BUS,
484 CLK_CON_DIV_CLKCMU_EH_BUS,
485 CLK_CON_DIV_CLKCMU_G2D_G2D,
486 CLK_CON_DIV_CLKCMU_G2D_MSCL,
487 CLK_CON_DIV_CLKCMU_G3AA_G3AA,
488 CLK_CON_DIV_CLKCMU_G3D_BUSD,
489 CLK_CON_DIV_CLKCMU_G3D_GLB,
490 CLK_CON_DIV_CLKCMU_G3D_SWITCH,
491 CLK_CON_DIV_CLKCMU_GDC_GDC0,
492 CLK_CON_DIV_CLKCMU_GDC_GDC1,
493 CLK_CON_DIV_CLKCMU_GDC_SCSC,
494 CLK_CON_DIV_CLKCMU_HPM,
495 CLK_CON_DIV_CLKCMU_HSI0_BUS,
496 CLK_CON_DIV_CLKCMU_HSI0_DPGTC,
497 CLK_CON_DIV_CLKCMU_HSI0_USB31DRD,
498 CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG,
499 CLK_CON_DIV_CLKCMU_HSI1_BUS,
500 CLK_CON_DIV_CLKCMU_HSI1_PCIE,
501 CLK_CON_DIV_CLKCMU_HSI2_BUS,
502 CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD,
503 CLK_CON_DIV_CLKCMU_HSI2_PCIE,
504 CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD,
505 CLK_CON_DIV_CLKCMU_IPP_BUS,
506 CLK_CON_DIV_CLKCMU_ITP_BUS,
507 CLK_CON_DIV_CLKCMU_MCSC_ITSC,
508 CLK_CON_DIV_CLKCMU_MCSC_MCSC,
509 CLK_CON_DIV_CLKCMU_MFC_MFC,
510 CLK_CON_DIV_CLKCMU_MIF_BUSP,
511 CLK_CON_DIV_CLKCMU_MISC_BUS,
512 CLK_CON_DIV_CLKCMU_MISC_SSS,
513 CLK_CON_DIV_CLKCMU_OTP,
514 CLK_CON_DIV_CLKCMU_PDP_BUS,
515 CLK_CON_DIV_CLKCMU_PDP_VRA,
516 CLK_CON_DIV_CLKCMU_PERIC0_BUS,
517 CLK_CON_DIV_CLKCMU_PERIC0_IP,
518 CLK_CON_DIV_CLKCMU_PERIC1_BUS,
519 CLK_CON_DIV_CLKCMU_PERIC1_IP,
520 CLK_CON_DIV_CLKCMU_TNR_BUS,
521 CLK_CON_DIV_CLKCMU_TPU_BUS,
522 CLK_CON_DIV_CLKCMU_TPU_TPU,
523 CLK_CON_DIV_CLKCMU_TPU_TPUCTL,
524 CLK_CON_DIV_CLKCMU_TPU_UART,
525 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,
526 CLK_CON_DIV_DIV_CLK_CMU_CMUREF,
527 CLK_CON_DIV_PLL_SHARED0_DIV2,
528 CLK_CON_DIV_PLL_SHARED0_DIV3,
529 CLK_CON_DIV_PLL_SHARED0_DIV4,
530 CLK_CON_DIV_PLL_SHARED0_DIV5,
531 CLK_CON_DIV_PLL_SHARED1_DIV2,
532 CLK_CON_DIV_PLL_SHARED1_DIV3,
533 CLK_CON_DIV_PLL_SHARED1_DIV4,
534 CLK_CON_DIV_PLL_SHARED2_DIV2,
535 CLK_CON_DIV_PLL_SHARED3_DIV2,
536 CLK_CON_GAT_CLKCMU_BUS0_BOOST,
537 CLK_CON_GAT_CLKCMU_BUS1_BOOST,
538 CLK_CON_GAT_CLKCMU_BUS2_BOOST,
539 CLK_CON_GAT_CLKCMU_CORE_BOOST,
540 CLK_CON_GAT_CLKCMU_CPUCL0_BOOST,
541 CLK_CON_GAT_CLKCMU_CPUCL1_BOOST,
542 CLK_CON_GAT_CLKCMU_CPUCL2_BOOST,
543 CLK_CON_GAT_CLKCMU_MIF_BOOST,
544 CLK_CON_GAT_CLKCMU_MIF_SWITCH,
545 CLK_CON_GAT_GATE_CLKCMU_BO_BUS,
546 CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS,
547 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS,
548 CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS,
549 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,
550 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,
551 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,
552 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,
553 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4,
554 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5,
555 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6,
556 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7,
557 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
558 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
559 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
560 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
561 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
562 CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
563 CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS,
564 CLK_CON_GAT_GATE_CLKCMU_DISP_BUS,
565 CLK_CON_GAT_GATE_CLKCMU_DNS_BUS,
566 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS,
567 CLK_CON_GAT_GATE_CLKCMU_EH_BUS,
568 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
569 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
570 CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA,
571 CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD,
572 CLK_CON_GAT_GATE_CLKCMU_G3D_GLB,
573 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
574 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0,
575 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1,
576 CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC,
577 CLK_CON_GAT_GATE_CLKCMU_HPM,
578 CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS,
579 CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
580 CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
581 CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG,
582 CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS,
583 CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,
584 CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS,
585 CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD,
586 CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE,
587 CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD,
588 CLK_CON_GAT_GATE_CLKCMU_IPP_BUS,
589 CLK_CON_GAT_GATE_CLKCMU_ITP_BUS,
590 CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC,
591 CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC,
592 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC,
593 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
594 CLK_CON_GAT_GATE_CLKCMU_MISC_BUS,
595 CLK_CON_GAT_GATE_CLKCMU_MISC_SSS,
596 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS,
597 CLK_CON_GAT_GATE_CLKCMU_PDP_VRA,
598 CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
599 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
600 CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
601 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
602 CLK_CON_GAT_GATE_CLKCMU_TNR_BUS,
603 CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF,
604 CLK_CON_GAT_GATE_CLKCMU_TPU_BUS,
605 CLK_CON_GAT_GATE_CLKCMU_TPU_TPU,
606 CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL,
607 CLK_CON_GAT_GATE_CLKCMU_TPU_UART,
608 DMYQCH_CON_CMU_TOP_CMUREF_QCH,
609 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0,
610 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1,
611 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2,
612 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3,
613 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4,
614 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5,
615 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6,
616 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7,
617 DMYQCH_CON_OTP_QCH,
618 QUEUE_CTRL_REG_BLK_CMU_CMU_TOP,
619 QUEUE_ENTRY0_BLK_CMU_CMU_TOP,
620 QUEUE_ENTRY1_BLK_CMU_CMU_TOP,
621 QUEUE_ENTRY2_BLK_CMU_CMU_TOP,
622 QUEUE_ENTRY3_BLK_CMU_CMU_TOP,
623 QUEUE_ENTRY4_BLK_CMU_CMU_TOP,
624 QUEUE_ENTRY5_BLK_CMU_CMU_TOP,
625 QUEUE_ENTRY6_BLK_CMU_CMU_TOP,
626 QUEUE_ENTRY7_BLK_CMU_CMU_TOP,
627 MIFMIRROR_QUEUE_CTRL_REG,
628 MIFMIRROR_QUEUE_ENTRY0,
629 MIFMIRROR_QUEUE_ENTRY1,
630 MIFMIRROR_QUEUE_ENTRY2,
631 MIFMIRROR_QUEUE_ENTRY3,
632 MIFMIRROR_QUEUE_ENTRY4,
633 MIFMIRROR_QUEUE_ENTRY5,
634 MIFMIRROR_QUEUE_ENTRY6,
635 MIFMIRROR_QUEUE_ENTRY7,
636 MIFMIRROR_QUEUE_BUSY,
637 GENERALIO_ACD_CHANNEL_0,
638 GENERALIO_ACD_CHANNEL_1,
639 GENERALIO_ACD_CHANNEL_2,
640 GENERALIO_ACD_CHANNEL_3,
641 GENERALIO_ACD_MASK,
642 };
643
644 static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = {
645 /* CMU_TOP_PURECLKCOMP */
646 PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
647 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
648 NULL),
649 PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
650 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1,
651 NULL),
652 PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
653 PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2,
654 NULL),
655 PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
656 PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3,
657 NULL),
658 PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk",
659 PLL_LOCKTIME_PLL_SPARE, PLL_CON3_PLL_SPARE,
660 NULL),
661 };
662
663 /* List of parent clocks for Muxes in CMU_TOP */
664 PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" };
665 PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" };
666 PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" };
667 PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" };
668 PNAME(mout_pll_spare_p) = { "oscclk", "fout_spare_pll" };
669 PNAME(mout_cmu_bo_bus_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3",
670 "fout_shared3_pll", "dout_cmu_shared1_div3",
671 "dout_cmu_shared0_div4",
672 "dout_cmu_shared1_div4",
673 "fout_spare_pll", "oscclk" };
674 PNAME(mout_cmu_bus0_bus_p) = { "dout_cmu_shared0_div4",
675 "dout_cmu_shared1_div4",
676 "dout_cmu_shared2_div2",
677 "dout_cmu_shared3_div2",
678 "fout_spare_pll", "oscclk",
679 "oscclk", "oscclk" };
680 PNAME(mout_cmu_bus1_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
681 "dout_cmu_shared1_div3",
682 "dout_cmu_shared0_div4",
683 "dout_cmu_shared1_div4",
684 "dout_cmu_shared2_div2",
685 "fout_spare_pll", "oscclk" };
686 PNAME(mout_cmu_bus2_bus_p) = { "dout_cmu_shared0_div2",
687 "dout_cmu_shared1_div2",
688 "fout_shared2_pll", "fout_shared3_pll",
689 "dout_cmu_shared0_div3",
690 "dout_cmu_shared1_div3",
691 "dout_cmu_shared0_div5", "fout_spare_pll" };
692 PNAME(mout_cmu_cis_clk0_7_p) = { "oscclk", "dout_cmu_shared0_div3",
693 "dout_cmu_shared1_div3",
694 "dout_cmu_shared2_div2",
695 "dout_cmu_shared3_div2", "fout_spare_pll",
696 "oscclk", "oscclk" };
697 PNAME(mout_cmu_cmu_boost_p) = { "dout_cmu_shared0_div4",
698 "dout_cmu_shared1_div4",
699 "dout_cmu_shared2_div2",
700 "dout_cmu_shared3_div2" };
701 PNAME(mout_cmu_cmu_boost_option1_p) = { "dout_cmu_cmu_boost",
702 "gout_cmu_boost_option1" };
703 PNAME(mout_cmu_core_bus_p) = { "dout_cmu_shared0_div2",
704 "dout_cmu_shared1_div2",
705 "fout_shared2_pll", "fout_shared3_pll",
706 "dout_cmu_shared0_div3",
707 "dout_cmu_shared1_div3",
708 "dout_cmu_shared0_div5", "fout_spare_pll" };
709 PNAME(mout_cmu_cpucl0_dbg_p) = { "fout_shared2_pll", "fout_shared3_pll",
710 "dout_cmu_shared0_div4",
711 "dout_cmu_shared1_div4",
712 "dout_cmu_shared2_div2", "fout_spare_pll",
713 "oscclk", "oscclk" };
714 PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2",
715 "dout_cmu_shared1_div2", "fout_shared2_pll",
716 "fout_shared3_pll", "dout_cmu_shared0_div3",
717 "dout_cmu_shared1_div3", "fout_spare_pll" };
718 PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2",
719 "dout_cmu_shared1_div2", "fout_shared2_pll",
720 "fout_shared3_pll", "dout_cmu_shared0_div3",
721 "dout_cmu_shared1_div3", "fout_spare_pll" };
722 PNAME(mout_cmu_cpucl2_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2",
723 "dout_cmu_shared1_div2", "fout_shared2_pll",
724 "fout_shared3_pll", "dout_cmu_shared0_div3",
725 "dout_cmu_shared1_div3", "fout_spare_pll" };
726 PNAME(mout_cmu_csis_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
727 "dout_cmu_shared1_div3",
728 "dout_cmu_shared0_div4",
729 "dout_cmu_shared1_div4",
730 "dout_cmu_shared2_div2",
731 "fout_spare_pll", "oscclk" };
732 PNAME(mout_cmu_disp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
733 "dout_cmu_shared1_div3",
734 "dout_cmu_shared0_div4",
735 "dout_cmu_shared1_div4",
736 "dout_cmu_shared2_div2",
737 "fout_spare_pll", "oscclk" };
738 PNAME(mout_cmu_dns_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
739 "dout_cmu_shared1_div3",
740 "dout_cmu_shared0_div4",
741 "dout_cmu_shared1_div4",
742 "dout_cmu_shared2_div2",
743 "fout_spare_pll", "oscclk" };
744 PNAME(mout_cmu_dpu_p) = { "dout_cmu_shared0_div3",
745 "fout_shared3_pll",
746 "dout_cmu_shared1_div3",
747 "dout_cmu_shared0_div4",
748 "dout_cmu_shared1_div4",
749 "dout_cmu_shared2_div2",
750 "fout_spare_pll", "oscclk" };
751 PNAME(mout_cmu_eh_bus_p) = { "dout_cmu_shared0_div2",
752 "dout_cmu_shared1_div2",
753 "fout_shared2_pll", "fout_shared3_pll",
754 "dout_cmu_shared0_div3",
755 "dout_cmu_shared1_div3",
756 "dout_cmu_shared0_div5", "fout_spare_pll" };
757 PNAME(mout_cmu_g2d_g2d_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
758 "dout_cmu_shared1_div3",
759 "dout_cmu_shared0_div4",
760 "dout_cmu_shared1_div4",
761 "dout_cmu_shared2_div2",
762 "fout_spare_pll", "oscclk" };
763 PNAME(mout_cmu_g2d_mscl_p) = { "dout_cmu_shared0_div4",
764 "dout_cmu_shared1_div4",
765 "dout_cmu_shared2_div2",
766 "dout_cmu_shared3_div2",
767 "fout_spare_pll", "oscclk",
768 "oscclk", "oscclk" };
769 PNAME(mout_cmu_g3aa_g3aa_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
770 "dout_cmu_shared1_div3",
771 "dout_cmu_shared0_div4",
772 "dout_cmu_shared1_div4",
773 "dout_cmu_shared2_div2",
774 "fout_spare_pll", "oscclk" };
775 PNAME(mout_cmu_g3d_busd_p) = { "dout_cmu_shared0_div2",
776 "dout_cmu_shared1_div2",
777 "fout_shared2_pll", "fout_shared3_pll",
778 "dout_cmu_shared0_div3",
779 "dout_cmu_shared1_div3",
780 "dout_cmu_shared0_div4", "fout_spare_pll" };
781 PNAME(mout_cmu_g3d_glb_p) = { "dout_cmu_shared0_div2",
782 "dout_cmu_shared1_div2",
783 "fout_shared2_pll", "fout_shared3_pll",
784 "dout_cmu_shared0_div3",
785 "dout_cmu_shared1_div3",
786 "dout_cmu_shared0_div4", "fout_spare_pll" };
787 PNAME(mout_cmu_g3d_switch_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3",
788 "fout_shared3_pll", "dout_cmu_shared1_div3",
789 "dout_cmu_shared0_div4",
790 "dout_cmu_shared1_div4",
791 "fout_spare_pll", "fout_spare_pll"};
792 PNAME(mout_cmu_gdc_gdc0_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
793 "dout_cmu_shared1_div3",
794 "dout_cmu_shared0_div4",
795 "dout_cmu_shared1_div4",
796 "dout_cmu_shared2_div2",
797 "fout_spare_pll", "oscclk" };
798 PNAME(mout_cmu_gdc_gdc1_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
799 "dout_cmu_shared1_div3",
800 "dout_cmu_shared0_div4",
801 "dout_cmu_shared1_div4",
802 "dout_cmu_shared2_div2",
803 "fout_spare_pll", "oscclk" };
804 PNAME(mout_cmu_gdc_scsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
805 "dout_cmu_shared1_div3",
806 "dout_cmu_shared0_div4",
807 "dout_cmu_shared1_div4",
808 "dout_cmu_shared2_div2",
809 "fout_spare_pll", "oscclk" };
810 PNAME(mout_cmu_hpm_p) = { "oscclk", "dout_cmu_shared1_div3",
811 "dout_cmu_shared0_div4",
812 "dout_cmu_shared2_div2" };
813 PNAME(mout_cmu_hsi0_bus_p) = { "dout_cmu_shared0_div4",
814 "dout_cmu_shared1_div4",
815 "dout_cmu_shared2_div2",
816 "dout_cmu_shared3_div2",
817 "fout_spare_pll", "oscclk",
818 "oscclk", "oscclk" };
819 PNAME(mout_cmu_hsi0_dpgtc_p) = { "oscclk", "dout_cmu_shared0_div4",
820 "dout_cmu_shared2_div2", "fout_spare_pll" };
821 PNAME(mout_cmu_hsi0_usb31drd_p) = { "oscclk", "dout_cmu_shared2_div2" };
822 PNAME(mout_cmu_hsi0_usbdpdbg_p) = { "oscclk", "dout_cmu_shared2_div2" };
823 PNAME(mout_cmu_hsi1_bus_p) = { "dout_cmu_shared0_div4",
824 "dout_cmu_shared1_div4",
825 "dout_cmu_shared2_div2",
826 "dout_cmu_shared3_div2",
827 "fout_spare_pll" };
828 PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "dout_cmu_shared2_div2" };
829 PNAME(mout_cmu_hsi2_bus_p) = { "dout_cmu_shared0_div4",
830 "dout_cmu_shared1_div4",
831 "dout_cmu_shared2_div2",
832 "dout_cmu_shared3_div2",
833 "fout_spare_pll", "oscclk",
834 "oscclk", "oscclk" };
835 PNAME(mout_cmu_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll",
836 "dout_cmu_shared0_div4", "fout_spare_pll" };
837 PNAME(mout_cmu_hsi2_pcie0_p) = { "oscclk", "dout_cmu_shared2_div2" };
838 PNAME(mout_cmu_hsi2_ufs_embd_p) = { "oscclk", "dout_cmu_shared0_div4",
839 "dout_cmu_shared2_div2", "fout_spare_pll" };
840 PNAME(mout_cmu_ipp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
841 "dout_cmu_shared1_div3",
842 "dout_cmu_shared0_div4",
843 "dout_cmu_shared1_div4",
844 "dout_cmu_shared2_div2",
845 "fout_spare_pll", "oscclk" };
846 PNAME(mout_cmu_itp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
847 "dout_cmu_shared1_div3",
848 "dout_cmu_shared0_div4",
849 "dout_cmu_shared1_div4",
850 "dout_cmu_shared2_div2",
851 "fout_spare_pll", "oscclk" };
852 PNAME(mout_cmu_mcsc_itsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
853 "dout_cmu_shared1_div3",
854 "dout_cmu_shared0_div4",
855 "dout_cmu_shared1_div4",
856 "dout_cmu_shared2_div2",
857 "fout_spare_pll", "oscclk" };
858 PNAME(mout_cmu_mcsc_mcsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
859 "dout_cmu_shared1_div3",
860 "dout_cmu_shared0_div4",
861 "dout_cmu_shared1_div4",
862 "dout_cmu_shared2_div2",
863 "fout_spare_pll", "oscclk" };
864 PNAME(mout_cmu_mfc_mfc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
865 "dout_cmu_shared0_div4",
866 "dout_cmu_shared1_div4",
867 "dout_cmu_shared2_div2", "fout_spare_pll",
868 "oscclk", "oscclk" };
869 PNAME(mout_cmu_mif_busp_p) = { "dout_cmu_shared0_div4",
870 "dout_cmu_shared1_div4",
871 "dout_cmu_shared0_div5", "fout_spare_pll" };
872 PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
873 "dout_cmu_shared0_div2",
874 "dout_cmu_shared1_div2",
875 "fout_shared2_pll", "dout_cmu_shared0_div3",
876 "fout_shared3_pll", "fout_spare_pll" };
877 PNAME(mout_cmu_misc_bus_p) = { "dout_cmu_shared0_div4",
878 "dout_cmu_shared2_div2",
879 "dout_cmu_shared3_div2", "fout_spare_pll" };
880 PNAME(mout_cmu_misc_sss_p) = { "dout_cmu_shared0_div4",
881 "dout_cmu_shared2_div2",
882 "dout_cmu_shared3_div2", "fout_spare_pll" };
883 PNAME(mout_cmu_pdp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
884 "dout_cmu_shared1_div3",
885 "dout_cmu_shared0_div4",
886 "dout_cmu_shared1_div4",
887 "dout_cmu_shared2_div2",
888 "fout_spare_pll", "oscclk" };
889 PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3",
890 "fout_shared3_pll", "dout_cmu_shared1_div3",
891 "dout_cmu_shared0_div4",
892 "dout_cmu_shared1_div4",
893 "fout_spare_pll", "oscclk" };
894 PNAME(mout_cmu_peric0_bus_p) = { "dout_cmu_shared0_div4",
895 "dout_cmu_shared2_div2",
896 "dout_cmu_shared3_div2", "fout_spare_pll" };
897 PNAME(mout_cmu_peric0_ip_p) = { "dout_cmu_shared0_div4",
898 "dout_cmu_shared2_div2",
899 "dout_cmu_shared3_div2", "fout_spare_pll" };
900 PNAME(mout_cmu_peric1_bus_p) = { "dout_cmu_shared0_div4",
901 "dout_cmu_shared2_div2",
902 "dout_cmu_shared3_div2", "fout_spare_pll" };
903 PNAME(mout_cmu_peric1_ip_p) = { "dout_cmu_shared0_div4",
904 "dout_cmu_shared2_div2",
905 "dout_cmu_shared3_div2", "fout_spare_pll" };
906 PNAME(mout_cmu_tnr_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
907 "dout_cmu_shared1_div3",
908 "dout_cmu_shared0_div4",
909 "dout_cmu_shared1_div4",
910 "dout_cmu_shared2_div2",
911 "fout_spare_pll", "oscclk" };
912 PNAME(mout_cmu_top_boost_option1_p) = { "oscclk",
913 "gout_cmu_boost_option1" };
914 PNAME(mout_cmu_top_cmuref_p) = { "dout_cmu_shared0_div4",
915 "dout_cmu_shared1_div4",
916 "dout_cmu_shared2_div2",
917 "dout_cmu_shared3_div2" };
918 PNAME(mout_cmu_tpu_bus_p) = { "dout_cmu_shared0_div2",
919 "dout_cmu_shared1_div2",
920 "fout_shared2_pll",
921 "fout_shared3_pll",
922 "dout_cmu_shared0_div3",
923 "dout_cmu_shared1_div3",
924 "dout_cmu_shared0_div4",
925 "fout_spare_pll" };
926 PNAME(mout_cmu_tpu_tpu_p) = { "dout_cmu_shared0_div2",
927 "dout_cmu_shared1_div2",
928 "fout_shared2_pll",
929 "fout_shared3_pll",
930 "dout_cmu_shared0_div3",
931 "dout_cmu_shared1_div3",
932 "dout_cmu_shared0_div4", "fout_spare_pll" };
933 PNAME(mout_cmu_tpu_tpuctl_p) = { "dout_cmu_shared0_div2",
934 "dout_cmu_shared1_div2",
935 "fout_shared2_pll", "fout_shared3_pll",
936 "dout_cmu_shared0_div3",
937 "dout_cmu_shared1_div3",
938 "dout_cmu_shared0_div4", "fout_spare_pll" };
939 PNAME(mout_cmu_tpu_uart_p) = { "dout_cmu_shared0_div4",
940 "dout_cmu_shared2_div2",
941 "dout_cmu_shared3_div2", "fout_spare_pll" };
942 PNAME(mout_cmu_cmuref_p) = { "mout_cmu_top_boost_option1",
943 "dout_cmu_cmuref" };
944
945 /*
946 * Register name to clock name mangling strategy used in this file
947 *
948 * Replace PLL_CON0_PLL with CLK_MOUT_PLL and mout_pll
949 * Replace CLK_CON_MUX_MUX_CLKCMU with CLK_MOUT_CMU and mout_cmu
950 * Replace CLK_CON_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu
951 * Replace CLK_CON_DIV_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu
952 * Replace CLK_CON_GAT_CLKCMU with CLK_GOUT_CMU and gout_cmu
953 * Replace CLK_CON_GAT_GATE_CLKCMU with CLK_GOUT_CMU and gout_cmu
954 *
955 * For gates remove _UID _BLK _IPCLKPORT and _RSTNSYNC
956 */
957
958 static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = {
959 MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p,
960 PLL_CON0_PLL_SHARED0, 4, 1),
961 MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p,
962 PLL_CON0_PLL_SHARED1, 4, 1),
963 MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p,
964 PLL_CON0_PLL_SHARED2, 4, 1),
965 MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p,
966 PLL_CON0_PLL_SHARED3, 4, 1),
967 MUX(CLK_MOUT_PLL_SPARE, "mout_pll_spare", mout_pll_spare_p,
968 PLL_CON0_PLL_SPARE, 4, 1),
969 MUX(CLK_MOUT_CMU_BO_BUS, "mout_cmu_bo_bus", mout_cmu_bo_bus_p,
970 CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 3),
971 MUX(CLK_MOUT_CMU_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p,
972 CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 3),
973 MUX(CLK_MOUT_CMU_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p,
974 CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 3),
975 MUX(CLK_MOUT_CMU_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p,
976 CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 3),
977 MUX(CLK_MOUT_CMU_CIS_CLK0, "mout_cmu_cis_clk0", mout_cmu_cis_clk0_7_p,
978 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 3),
979 MUX(CLK_MOUT_CMU_CIS_CLK1, "mout_cmu_cis_clk1", mout_cmu_cis_clk0_7_p,
980 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 3),
981 MUX(CLK_MOUT_CMU_CIS_CLK2, "mout_cmu_cis_clk2", mout_cmu_cis_clk0_7_p,
982 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 3),
983 MUX(CLK_MOUT_CMU_CIS_CLK3, "mout_cmu_cis_clk3", mout_cmu_cis_clk0_7_p,
984 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 3),
985 MUX(CLK_MOUT_CMU_CIS_CLK4, "mout_cmu_cis_clk4", mout_cmu_cis_clk0_7_p,
986 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0, 3),
987 MUX(CLK_MOUT_CMU_CIS_CLK5, "mout_cmu_cis_clk5", mout_cmu_cis_clk0_7_p,
988 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0, 3),
989 MUX(CLK_MOUT_CMU_CIS_CLK6, "mout_cmu_cis_clk6", mout_cmu_cis_clk0_7_p,
990 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 0, 3),
991 MUX(CLK_MOUT_CMU_CIS_CLK7, "mout_cmu_cis_clk7", mout_cmu_cis_clk0_7_p,
992 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 0, 3),
993 MUX(CLK_MOUT_CMU_CMU_BOOST, "mout_cmu_cmu_boost", mout_cmu_cmu_boost_p,
994 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
995 MUX(CLK_MOUT_CMU_BOOST_OPTION1, "mout_cmu_boost_option1",
996 mout_cmu_cmu_boost_option1_p,
997 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, 0, 1),
998 MUX(CLK_MOUT_CMU_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p,
999 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3),
1000 MUX(CLK_MOUT_CMU_CPUCL0_DBG, "mout_cmu_cpucl0_dbg",
1001 mout_cmu_cpucl0_dbg_p, CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3),
1002 MUX(CLK_MOUT_CMU_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch",
1003 mout_cmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
1004 0, 3),
1005 MUX(CLK_MOUT_CMU_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch",
1006 mout_cmu_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
1007 0, 3),
1008 MUX(CLK_MOUT_CMU_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch",
1009 mout_cmu_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
1010 0, 3),
1011 MUX(CLK_MOUT_CMU_CSIS_BUS, "mout_cmu_csis_bus", mout_cmu_csis_bus_p,
1012 CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 3),
1013 MUX(CLK_MOUT_CMU_DISP_BUS, "mout_cmu_disp_bus", mout_cmu_disp_bus_p,
1014 CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 3),
1015 MUX(CLK_MOUT_CMU_DNS_BUS, "mout_cmu_dns_bus", mout_cmu_dns_bus_p,
1016 CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 3),
1017 MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus", mout_cmu_dpu_p,
1018 CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 3),
1019 MUX(CLK_MOUT_CMU_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p,
1020 CLK_CON_MUX_MUX_CLKCMU_EH_BUS, 0, 3),
1021 MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p,
1022 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3),
1023 MUX(CLK_MOUT_CMU_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p,
1024 CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 3),
1025 MUX(CLK_MOUT_CMU_G3AA_G3AA, "mout_cmu_g3aa_g3aa", mout_cmu_g3aa_g3aa_p,
1026 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 3),
1027 MUX(CLK_MOUT_CMU_G3D_BUSD, "mout_cmu_g3d_busd", mout_cmu_g3d_busd_p,
1028 CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 3),
1029 MUX(CLK_MOUT_CMU_G3D_GLB, "mout_cmu_g3d_glb", mout_cmu_g3d_glb_p,
1030 CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 3),
1031 MUX(CLK_MOUT_CMU_G3D_SWITCH, "mout_cmu_g3d_switch",
1032 mout_cmu_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 3),
1033 MUX(CLK_MOUT_CMU_GDC_GDC0, "mout_cmu_gdc_gdc0", mout_cmu_gdc_gdc0_p,
1034 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 3),
1035 MUX(CLK_MOUT_CMU_GDC_GDC1, "mout_cmu_gdc_gdc1", mout_cmu_gdc_gdc1_p,
1036 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 3),
1037 MUX(CLK_MOUT_CMU_GDC_SCSC, "mout_cmu_gdc_scsc", mout_cmu_gdc_scsc_p,
1038 CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 3),
1039 MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p,
1040 CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
1041 MUX(CLK_MOUT_CMU_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p,
1042 CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 3),
1043 MUX(CLK_MOUT_CMU_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc",
1044 mout_cmu_hsi0_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2),
1045 MUX(CLK_MOUT_CMU_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd",
1046 mout_cmu_hsi0_usb31drd_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,
1047 0, 1),
1048 MUX(CLK_MOUT_CMU_HSI0_USBDPDBG, "mout_cmu_hsi0_usbdpdbg",
1049 mout_cmu_hsi0_usbdpdbg_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG,
1050 0, 1),
1051 MUX(CLK_MOUT_CMU_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p,
1052 CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3),
1053 MUX(CLK_MOUT_CMU_HSI1_PCIE, "mout_cmu_hsi1_pcie", mout_cmu_hsi1_pcie_p,
1054 CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 1),
1055 MUX(CLK_MOUT_CMU_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p,
1056 CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 3),
1057 MUX(CLK_MOUT_CMU_HSI2_MMC_CARD, "mout_cmu_hsi2_mmc_card",
1058 mout_cmu_hsi2_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD,
1059 0, 2),
1060 MUX(CLK_MOUT_CMU_HSI2_PCIE, "mout_cmu_hsi2_pcie", mout_cmu_hsi2_pcie0_p,
1061 CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 1),
1062 MUX(CLK_MOUT_CMU_HSI2_UFS_EMBD, "mout_cmu_hsi2_ufs_embd",
1063 mout_cmu_hsi2_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
1064 0, 2),
1065 MUX(CLK_MOUT_CMU_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p,
1066 CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 3),
1067 MUX(CLK_MOUT_CMU_ITP_BUS, "mout_cmu_itp_bus", mout_cmu_itp_bus_p,
1068 CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 3),
1069 MUX(CLK_MOUT_CMU_MCSC_ITSC, "mout_cmu_mcsc_itsc", mout_cmu_mcsc_itsc_p,
1070 CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 3),
1071 MUX(CLK_MOUT_CMU_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p,
1072 CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 3),
1073 MUX(CLK_MOUT_CMU_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p,
1074 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 3),
1075 MUX(CLK_MOUT_CMU_MIF_BUSP, "mout_cmu_mif_busp", mout_cmu_mif_busp_p,
1076 CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
1077 MUX(CLK_MOUT_CMU_MIF_SWITCH, "mout_cmu_mif_switch",
1078 mout_cmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
1079 MUX(CLK_MOUT_CMU_MISC_BUS, "mout_cmu_misc_bus", mout_cmu_misc_bus_p,
1080 CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2),
1081 MUX(CLK_MOUT_CMU_MISC_SSS, "mout_cmu_misc_sss", mout_cmu_misc_sss_p,
1082 CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2),
1083 MUX(CLK_MOUT_CMU_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p,
1084 CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 3),
1085 MUX(CLK_MOUT_CMU_PDP_VRA, "mout_cmu_pdp_vra", mout_cmu_pdp_vra_p,
1086 CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 3),
1087 MUX(CLK_MOUT_CMU_PERIC0_BUS, "mout_cmu_peric0_bus",
1088 mout_cmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
1089 MUX(CLK_MOUT_CMU_PERIC0_IP, "mout_cmu_peric0_ip", mout_cmu_peric0_ip_p,
1090 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
1091 MUX(CLK_MOUT_CMU_PERIC1_BUS, "mout_cmu_peric1_bus",
1092 mout_cmu_peric1_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 2),
1093 MUX(CLK_MOUT_CMU_PERIC1_IP, "mout_cmu_peric1_ip", mout_cmu_peric1_ip_p,
1094 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 2),
1095 MUX(CLK_MOUT_CMU_TNR_BUS, "mout_cmu_tnr_bus", mout_cmu_tnr_bus_p,
1096 CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3),
1097 MUX(CLK_MOUT_CMU_TOP_BOOST_OPTION1, "mout_cmu_top_boost_option1",
1098 mout_cmu_top_boost_option1_p,
1099 CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, 0, 1),
1100 MUX(CLK_MOUT_CMU_TOP_CMUREF, "mout_cmu_top_cmuref",
1101 mout_cmu_top_cmuref_p, CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, 0, 2),
1102 MUX(CLK_MOUT_CMU_TPU_BUS, "mout_cmu_tpu_bus", mout_cmu_tpu_bus_p,
1103 CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 3),
1104 MUX(CLK_MOUT_CMU_TPU_TPU, "mout_cmu_tpu_tpu", mout_cmu_tpu_tpu_p,
1105 CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 3),
1106 MUX(CLK_MOUT_CMU_TPU_TPUCTL, "mout_cmu_tpu_tpuctl",
1107 mout_cmu_tpu_tpuctl_p, CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 3),
1108 MUX(CLK_MOUT_CMU_TPU_UART, "mout_cmu_tpu_uart", mout_cmu_tpu_uart_p,
1109 CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2),
1110 MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref", mout_cmu_cmuref_p,
1111 CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
1112 };
1113
1114 static const struct samsung_div_clock cmu_top_div_clks[] __initconst = {
1115 DIV(CLK_DOUT_CMU_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus",
1116 CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4),
1117 DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus",
1118 CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4),
1119 DIV(CLK_DOUT_CMU_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus",
1120 CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4),
1121 DIV(CLK_DOUT_CMU_BUS2_BUS, "dout_cmu_bus2_bus", "gout_cmu_bus2_bus",
1122 CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4),
1123 DIV(CLK_DOUT_CMU_CIS_CLK0, "dout_cmu_cis_clk0", "gout_cmu_cis_clk0",
1124 CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5),
1125 DIV(CLK_DOUT_CMU_CIS_CLK1, "dout_cmu_cis_clk1", "gout_cmu_cis_clk1",
1126 CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5),
1127 DIV(CLK_DOUT_CMU_CIS_CLK2, "dout_cmu_cis_clk2", "gout_cmu_cis_clk2",
1128 CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5),
1129 DIV(CLK_DOUT_CMU_CIS_CLK3, "dout_cmu_cis_clk3", "gout_cmu_cis_clk3",
1130 CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5),
1131 DIV(CLK_DOUT_CMU_CIS_CLK4, "dout_cmu_cis_clk4", "gout_cmu_cis_clk4",
1132 CLK_CON_DIV_CLKCMU_CIS_CLK4, 0, 5),
1133 DIV(CLK_DOUT_CMU_CIS_CLK5, "dout_cmu_cis_clk5", "gout_cmu_cis_clk5",
1134 CLK_CON_DIV_CLKCMU_CIS_CLK5, 0, 5),
1135 DIV(CLK_DOUT_CMU_CIS_CLK6, "dout_cmu_cis_clk6", "gout_cmu_cis_clk6",
1136 CLK_CON_DIV_CLKCMU_CIS_CLK6, 0, 5),
1137 DIV(CLK_DOUT_CMU_CIS_CLK7, "dout_cmu_cis_clk7", "gout_cmu_cis_clk7",
1138 CLK_CON_DIV_CLKCMU_CIS_CLK7, 0, 5),
1139 DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus",
1140 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
1141 DIV(CLK_DOUT_CMU_CPUCL0_DBG, "dout_cmu_cpucl0_dbg",
1142 "gout_cmu_cpucl0_dbg", CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),
1143 DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch",
1144 "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
1145 DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch",
1146 "gout_cmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
1147 DIV(CLK_DOUT_CMU_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch",
1148 "gout_cmu_cpucl2_switch", CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
1149 DIV(CLK_DOUT_CMU_CSIS_BUS, "dout_cmu_csis_bus", "gout_cmu_csis_bus",
1150 CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4),
1151 DIV(CLK_DOUT_CMU_DISP_BUS, "dout_cmu_disp_bus", "gout_cmu_disp_bus",
1152 CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4),
1153 DIV(CLK_DOUT_CMU_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus",
1154 CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4),
1155 DIV(CLK_DOUT_CMU_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus",
1156 CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4),
1157 DIV(CLK_DOUT_CMU_EH_BUS, "dout_cmu_eh_bus", "gout_cmu_eh_bus",
1158 CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4),
1159 DIV(CLK_DOUT_CMU_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d",
1160 CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
1161 DIV(CLK_DOUT_CMU_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl",
1162 CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
1163 DIV(CLK_DOUT_CMU_G3AA_G3AA, "dout_cmu_g3aa_g3aa", "gout_cmu_g3aa_g3aa",
1164 CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4),
1165 DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd",
1166 CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4),
1167 DIV(CLK_DOUT_CMU_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb",
1168 CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4),
1169 DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_switch",
1170 "gout_cmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
1171 DIV(CLK_DOUT_CMU_GDC_GDC0, "dout_cmu_gdc_gdc0", "gout_cmu_gdc_gdc0",
1172 CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4),
1173 DIV(CLK_DOUT_CMU_GDC_GDC1, "dout_cmu_gdc_gdc1", "gout_cmu_gdc_gdc1",
1174 CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4),
1175 DIV(CLK_DOUT_CMU_GDC_SCSC, "dout_cmu_gdc_scsc", "gout_cmu_gdc_scsc",
1176 CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4),
1177 DIV(CLK_DOUT_CMU_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm",
1178 CLK_CON_DIV_CLKCMU_HPM, 0, 2),
1179 DIV(CLK_DOUT_CMU_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus",
1180 CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4),
1181 DIV(CLK_DOUT_CMU_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc",
1182 "gout_cmu_hsi0_dpgtc", CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4),
1183 DIV(CLK_DOUT_CMU_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd",
1184 "gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5),
1185 DIV(CLK_DOUT_CMU_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus",
1186 CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4),
1187 DIV(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie",
1188 CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3),
1189 DIV(CLK_DOUT_CMU_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus",
1190 CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),
1191 DIV(CLK_DOUT_CMU_HSI2_MMC_CARD, "dout_cmu_hsi2_mmc_card",
1192 "gout_cmu_hsi2_mmc_card", CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9),
1193 DIV(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie",
1194 CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3),
1195 DIV(CLK_DOUT_CMU_HSI2_UFS_EMBD, "dout_cmu_hsi2_ufs_embd",
1196 "gout_cmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4),
1197 DIV(CLK_DOUT_CMU_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus",
1198 CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),
1199 DIV(CLK_DOUT_CMU_ITP_BUS, "dout_cmu_itp_bus", "gout_cmu_itp_bus",
1200 CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4),
1201 DIV(CLK_DOUT_CMU_MCSC_ITSC, "dout_cmu_mcsc_itsc", "gout_cmu_mcsc_itsc",
1202 CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4),
1203 DIV(CLK_DOUT_CMU_MCSC_MCSC, "dout_cmu_mcsc_mcsc", "gout_cmu_mcsc_mcsc",
1204 CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4),
1205 DIV(CLK_DOUT_CMU_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc",
1206 CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
1207 DIV(CLK_DOUT_CMU_MIF_BUSP, "dout_cmu_mif_busp", "gout_cmu_mif_busp",
1208 CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
1209 DIV(CLK_DOUT_CMU_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus",
1210 CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4),
1211 DIV(CLK_DOUT_CMU_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss",
1212 CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4),
1213 DIV(CLK_DOUT_CMU_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus",
1214 CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4),
1215 DIV(CLK_DOUT_CMU_PDP_VRA, "dout_cmu_pdp_vra", "gout_cmu_pdp_vra",
1216 CLK_CON_DIV_CLKCMU_PDP_VRA, 0, 4),
1217 DIV(CLK_DOUT_CMU_PERIC0_BUS, "dout_cmu_peric0_bus",
1218 "gout_cmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
1219 DIV(CLK_DOUT_CMU_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip",
1220 CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
1221 DIV(CLK_DOUT_CMU_PERIC1_BUS, "dout_cmu_peric1_bus",
1222 "gout_cmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
1223 DIV(CLK_DOUT_CMU_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip",
1224 CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
1225 DIV(CLK_DOUT_CMU_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus",
1226 CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),
1227 DIV(CLK_DOUT_CMU_TPU_BUS, "dout_cmu_tpu_bus", "gout_cmu_tpu_bus",
1228 CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4),
1229 DIV(CLK_DOUT_CMU_TPU_TPU, "dout_cmu_tpu_tpu", "gout_cmu_tpu_tpu",
1230 CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4),
1231 DIV(CLK_DOUT_CMU_TPU_TPUCTL, "dout_cmu_tpu_tpuctl",
1232 "gout_cmu_tpu_tpuctl", CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4),
1233 DIV(CLK_DOUT_CMU_TPU_UART, "dout_cmu_tpu_uart", "gout_cmu_tpu_uart",
1234 CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4),
1235 DIV(CLK_DOUT_CMU_CMU_BOOST, "dout_cmu_cmu_boost", "gout_cmu_cmu_boost",
1236 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
1237 DIV(CLK_DOUT_CMU_CMU_CMUREF, "dout_cmu_cmuref", "gout_cmu_cmuref",
1238 CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2),
1239 DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2",
1240 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
1241 DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3",
1242 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
1243 DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4",
1244 "dout_cmu_shared0_div2", CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
1245 DIV(CLK_DOUT_CMU_SHARED0_DIV5, "dout_cmu_shared0_div5",
1246 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
1247 DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2",
1248 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
1249 DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3",
1250 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
1251 DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4",
1252 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
1253 DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2",
1254 "mout_pll_shared2", CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
1255 DIV(CLK_DOUT_CMU_SHARED3_DIV2, "dout_cmu_shared3_div2",
1256 "mout_pll_shared3", CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1),
1257 };
1258
1259 static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = {
1260 FFACTOR(CLK_DOUT_CMU_HSI0_USBDPDBG, "dout_cmu_hsi0_usbdpdbg",
1261 "gout_cmu_hsi0_usbdpdbg", 1, 4, 0),
1262 FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0),
1263 };
1264
1265 static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = {
1266 GATE(CLK_GOUT_CMU_BUS0_BOOST, "gout_cmu_bus0_boost",
1267 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS0_BOOST, 21, 0, 0),
1268 GATE(CLK_GOUT_CMU_BUS1_BOOST, "gout_cmu_bus1_boost",
1269 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS1_BOOST, 21, 0, 0),
1270 GATE(CLK_GOUT_CMU_BUS2_BOOST, "gout_cmu_bus2_boost",
1271 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS2_BOOST, 21, 0, 0),
1272 GATE(CLK_GOUT_CMU_CORE_BOOST, "gout_cmu_core_boost",
1273 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CORE_BOOST, 21, 0, 0),
1274 GATE(CLK_GOUT_CMU_CPUCL0_BOOST, "gout_cmu_cpucl0_boost",
1275 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL0_BOOST,
1276 21, 0, 0),
1277 GATE(CLK_GOUT_CMU_CPUCL1_BOOST, "gout_cmu_cpucl1_boost",
1278 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL1_BOOST,
1279 21, 0, 0),
1280 GATE(CLK_GOUT_CMU_CPUCL2_BOOST, "gout_cmu_cpucl2_boost",
1281 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL2_BOOST,
1282 21, 0, 0),
1283 GATE(CLK_GOUT_CMU_MIF_BOOST, "gout_cmu_mif_boost",
1284 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_MIF_BOOST,
1285 21, 0, 0),
1286 GATE(CLK_GOUT_CMU_MIF_SWITCH, "gout_cmu_mif_switch",
1287 "mout_cmu_mif_switch", CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0),
1288 GATE(CLK_GOUT_CMU_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus",
1289 CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0),
1290 GATE(CLK_GOUT_CMU_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",
1291 CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0),
1292 GATE(CLK_GOUT_CMU_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
1293 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0),
1294 GATE(CLK_GOUT_CMU_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus",
1295 CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0),
1296 GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0",
1297 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0),
1298 GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1",
1299 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0),
1300 GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2",
1301 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0),
1302 GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3",
1303 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0),
1304 GATE(CLK_GOUT_CMU_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4",
1305 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 21, 0, 0),
1306 GATE(CLK_GOUT_CMU_CIS_CLK5, "gout_cmu_cis_clk5", "mout_cmu_cis_clk5",
1307 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 21, 0, 0),
1308 GATE(CLK_GOUT_CMU_CIS_CLK6, "gout_cmu_cis_clk6", "mout_cmu_cis_clk6",
1309 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 21, 0, 0),
1310 GATE(CLK_GOUT_CMU_CIS_CLK7, "gout_cmu_cis_clk7", "mout_cmu_cis_clk7",
1311 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 21, 0, 0),
1312 GATE(CLK_GOUT_CMU_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_cmu_boost",
1313 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0),
1314 GATE(CLK_GOUT_CMU_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus",
1315 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
1316 GATE(CLK_GOUT_CMU_CPUCL0_DBG, "gout_cmu_cpucl0_dbg",
1317 "mout_cmu_cpucl0_dbg", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
1318 21, 0, 0),
1319 GATE(CLK_GOUT_CMU_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch",
1320 "mout_cmu_cpucl0_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
1321 21, 0, 0),
1322 GATE(CLK_GOUT_CMU_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch",
1323 "mout_cmu_cpucl1_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
1324 21, 0, 0),
1325 GATE(CLK_GOUT_CMU_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch",
1326 "mout_cmu_cpucl2_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
1327 21, 0, 0),
1328 GATE(CLK_GOUT_CMU_CSIS_BUS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
1329 CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
1330 GATE(CLK_GOUT_CMU_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus",
1331 CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0),
1332 GATE(CLK_GOUT_CMU_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus",
1333 CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0),
1334 GATE(CLK_GOUT_CMU_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus",
1335 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0),
1336 GATE(CLK_GOUT_CMU_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus",
1337 CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0),
1338 GATE(CLK_GOUT_CMU_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
1339 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
1340 GATE(CLK_GOUT_CMU_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl",
1341 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0),
1342 GATE(CLK_GOUT_CMU_G3AA_G3AA, "gout_cmu_g3aa_g3aa", "mout_cmu_g3aa_g3aa",
1343 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0),
1344 GATE(CLK_GOUT_CMU_G3D_BUSD, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd",
1345 CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0),
1346 GATE(CLK_GOUT_CMU_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb",
1347 CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0),
1348 GATE(CLK_GOUT_CMU_G3D_SWITCH, "gout_cmu_g3d_switch",
1349 "mout_cmu_g3d_switch", CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
1350 21, 0, 0),
1351 GATE(CLK_GOUT_CMU_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0",
1352 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0),
1353 GATE(CLK_GOUT_CMU_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1",
1354 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0),
1355 GATE(CLK_GOUT_CMU_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc",
1356 CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0),
1357 GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",
1358 CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
1359 GATE(CLK_GOUT_CMU_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus",
1360 CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0),
1361 GATE(CLK_GOUT_CMU_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc",
1362 "mout_cmu_hsi0_dpgtc", CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
1363 21, 0, 0),
1364 GATE(CLK_GOUT_CMU_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd",
1365 "mout_cmu_hsi0_usb31drd", CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
1366 21, 0, 0),
1367 GATE(CLK_GOUT_CMU_HSI0_USBDPDBG, "gout_cmu_hsi0_usbdpdbg",
1368 "mout_cmu_hsi0_usbdpdbg", CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG,
1369 21, 0, 0),
1370 GATE(CLK_GOUT_CMU_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus",
1371 CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0),
1372 GATE(CLK_GOUT_CMU_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie",
1373 CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0),
1374 GATE(CLK_GOUT_CMU_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus",
1375 CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0),
1376 GATE(CLK_GOUT_CMU_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card",
1377 "mout_cmu_hsi2_mmc_card", CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD,
1378 21, 0, 0),
1379 GATE(CLK_GOUT_CMU_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie",
1380 CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0),
1381 GATE(CLK_GOUT_CMU_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd",
1382 "mout_cmu_hsi2_ufs_embd", CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD,
1383 21, 0, 0),
1384 GATE(CLK_GOUT_CMU_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
1385 CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
1386 GATE(CLK_GOUT_CMU_ITP_BUS, "gout_cmu_itp_bus", "mout_cmu_itp_bus",
1387 CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0),
1388 GATE(CLK_GOUT_CMU_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc",
1389 CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0),
1390 GATE(CLK_GOUT_CMU_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc",
1391 CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0),
1392 GATE(CLK_GOUT_CMU_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc",
1393 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
1394 GATE(CLK_GOUT_CMU_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp",
1395 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0),
1396 GATE(CLK_GOUT_CMU_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus",
1397 CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0),
1398 GATE(CLK_GOUT_CMU_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss",
1399 CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0),
1400 GATE(CLK_GOUT_CMU_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus",
1401 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
1402 GATE(CLK_GOUT_CMU_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra",
1403 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
1404 GATE(CLK_GOUT_CMU_PERIC0_BUS, "gout_cmu_peric0_bus",
1405 "mout_cmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
1406 21, 0, 0),
1407 GATE(CLK_GOUT_CMU_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip",
1408 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0),
1409 GATE(CLK_GOUT_CMU_PERIC1_BUS, "gout_cmu_peric1_bus",
1410 "mout_cmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
1411 21, 0, 0),
1412 GATE(CLK_GOUT_CMU_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip",
1413 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0),
1414 GATE(CLK_GOUT_CMU_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus",
1415 CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0),
1416 GATE(CLK_GOUT_CMU_TOP_CMUREF, "gout_cmu_top_cmuref",
1417 "mout_cmu_top_cmuref", CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF,
1418 21, 0, 0),
1419 GATE(CLK_GOUT_CMU_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus",
1420 CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0),
1421 GATE(CLK_GOUT_CMU_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu",
1422 CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0),
1423 GATE(CLK_GOUT_CMU_TPU_TPUCTL, "gout_cmu_tpu_tpuctl",
1424 "mout_cmu_tpu_tpuctl", CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL,
1425 21, 0, 0),
1426 GATE(CLK_GOUT_CMU_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart",
1427 CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0),
1428 };
1429
1430 static const struct samsung_cmu_info top_cmu_info __initconst = {
1431 .pll_clks = cmu_top_pll_clks,
1432 .nr_pll_clks = ARRAY_SIZE(cmu_top_pll_clks),
1433 .mux_clks = cmu_top_mux_clks,
1434 .nr_mux_clks = ARRAY_SIZE(cmu_top_mux_clks),
1435 .div_clks = cmu_top_div_clks,
1436 .nr_div_clks = ARRAY_SIZE(cmu_top_div_clks),
1437 .fixed_factor_clks = cmu_top_ffactor,
1438 .nr_fixed_factor_clks = ARRAY_SIZE(cmu_top_ffactor),
1439 .gate_clks = cmu_top_gate_clks,
1440 .nr_gate_clks = ARRAY_SIZE(cmu_top_gate_clks),
1441 .nr_clk_ids = CLKS_NR_TOP,
1442 .clk_regs = cmu_top_clk_regs,
1443 .nr_clk_regs = ARRAY_SIZE(cmu_top_clk_regs),
1444 };
1445
gs101_cmu_top_init(struct device_node * np)1446 static void __init gs101_cmu_top_init(struct device_node *np)
1447 {
1448 exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
1449 }
1450
1451 /* Register CMU_TOP early, as it's a dependency for other early domains */
1452 CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",
1453 gs101_cmu_top_init);
1454
1455 /* ---- CMU_APM ------------------------------------------------------------- */
1456
1457 /* Register Offset definitions for CMU_APM (0x17400000) */
1458 #define APM_CMU_APM_CONTROLLER_OPTION 0x0800
1459 #define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810
1460 #define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000
1461 #define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004
1462 #define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800
1463 #define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804
1464 #define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808
1465 #define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c
1466 #define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000
1467 #define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004
1468 #define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008
1469 #define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c
1470 #define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC 0x2010
1471 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2014
1472 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 0x2018
1473 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x201c
1474 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK 0x2020
1475 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK 0x2024
1476 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK 0x2028
1477 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK 0x202c
1478 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK 0x2030
1479 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK 0x2034
1480 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK 0x2038
1481 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK 0x203c
1482 #define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK 0x2040
1483 #define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK 0x2044
1484 #define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2048
1485 #define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK 0x204c
1486 #define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK 0x2050
1487 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 0x2054
1488 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 0x2058
1489 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK 0x205c
1490 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK 0x2060
1491 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 0x2064
1492 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 0x2068
1493 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK 0x206c
1494 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x2070
1495 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK 0x2074
1496 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK 0x207c
1497 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK 0x2080
1498 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK 0x2084
1499 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x2088
1500 #define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x208c
1501 #define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK 0x2090
1502 #define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK 0x2094
1503 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 0x2098
1504 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 0x209c
1505 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 0x20a0
1506 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 0x20a4
1507 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8
1508 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac
1509 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0
1510 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4
1511 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8
1512 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc
1513 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0
1514 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4
1515 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc
1516 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0
1517 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4
1518 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8
1519 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK 0x20dc
1520 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK 0x20e0
1521 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK 0x20e4
1522 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK 0x20e8
1523 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK 0x20ec
1524 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK 0x20f0
1525 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK 0x20f4
1526 #define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK 0x20f8
1527 #define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK 0x20fc
1528 #define PCH_CON_LHM_AXI_G_SWD_PCH 0x3000
1529 #define PCH_CON_LHM_AXI_P_AOCAPM_PCH 0x3004
1530 #define PCH_CON_LHM_AXI_P_APM_PCH 0x3008
1531 #define PCH_CON_LHS_AXI_D_APM_PCH 0x300c
1532 #define PCH_CON_LHS_AXI_G_DBGCORE_PCH 0x3010
1533 #define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH 0x3014
1534 #define QCH_CON_APBIF_GPIO_ALIVE_QCH 0x3018
1535 #define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH 0x301c
1536 #define QCH_CON_APBIF_PMU_ALIVE_QCH 0x3020
1537 #define QCH_CON_APBIF_RTC_QCH 0x3024
1538 #define QCH_CON_APBIF_TRTC_QCH 0x3028
1539 #define QCH_CON_APM_CMU_APM_QCH 0x302c
1540 #define QCH_CON_APM_USI0_UART_QCH 0x3030
1541 #define QCH_CON_APM_USI0_USI_QCH 0x3034
1542 #define QCH_CON_APM_USI1_UART_QCH 0x3038
1543 #define QCH_CON_D_TZPC_APM_QCH 0x303c
1544 #define QCH_CON_GPC_APM_QCH 0x3040
1545 #define QCH_CON_GREBEINTEGRATION_QCH_DBG 0x3044
1546 #define QCH_CON_GREBEINTEGRATION_QCH_GREBE 0x3048
1547 #define QCH_CON_INTMEM_QCH 0x304c
1548 #define QCH_CON_LHM_AXI_G_SWD_QCH 0x3050
1549 #define QCH_CON_LHM_AXI_P_AOCAPM_QCH 0x3054
1550 #define QCH_CON_LHM_AXI_P_APM_QCH 0x3058
1551 #define QCH_CON_LHS_AXI_D_APM_QCH 0x305c
1552 #define QCH_CON_LHS_AXI_G_DBGCORE_QCH 0x3060
1553 #define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH 0x3064
1554 #define QCH_CON_MAILBOX_APM_AOC_QCH 0x3068
1555 #define QCH_CON_MAILBOX_APM_AP_QCH 0x306c
1556 #define QCH_CON_MAILBOX_APM_GSA_QCH 0x3070
1557 #define QCH_CON_MAILBOX_APM_SWD_QCH 0x3078
1558 #define QCH_CON_MAILBOX_APM_TPU_QCH 0x307c
1559 #define QCH_CON_MAILBOX_AP_AOC_QCH 0x3080
1560 #define QCH_CON_MAILBOX_AP_DBGCORE_QCH 0x3084
1561 #define QCH_CON_PMU_INTR_GEN_QCH 0x3088
1562 #define QCH_CON_ROM_CRC32_HOST_QCH 0x308c
1563 #define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE 0x3090
1564 #define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG 0x3094
1565 #define QCH_CON_SPEEDY_APM_QCH 0x3098
1566 #define QCH_CON_SPEEDY_SUB_APM_QCH 0x309c
1567 #define QCH_CON_SSMT_D_APM_QCH 0x30a0
1568 #define QCH_CON_SSMT_G_DBGCORE_QCH 0x30a4
1569 #define QCH_CON_SS_DBGCORE_QCH_DBG 0x30a8
1570 #define QCH_CON_SS_DBGCORE_QCH_GREBE 0x30ac
1571 #define QCH_CON_SYSMMU_D_APM_QCH 0x30b0
1572 #define QCH_CON_SYSREG_APM_QCH 0x30b8
1573 #define QCH_CON_UASC_APM_QCH 0x30bc
1574 #define QCH_CON_UASC_DBGCORE_QCH 0x30c0
1575 #define QCH_CON_UASC_G_SWD_QCH 0x30c4
1576 #define QCH_CON_UASC_P_AOCAPM_QCH 0x30c8
1577 #define QCH_CON_UASC_P_APM_QCH 0x30cc
1578 #define QCH_CON_WDT_APM_QCH 0x30d0
1579 #define QUEUE_CTRL_REG_BLK_APM_CMU_APM 0x3c00
1580
1581 static const unsigned long apm_clk_regs[] __initconst = {
1582 APM_CMU_APM_CONTROLLER_OPTION,
1583 CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0,
1584 CLK_CON_MUX_MUX_CLKCMU_APM_FUNC,
1585 CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC,
1586 CLK_CON_DIV_DIV_CLK_APM_BOOST,
1587 CLK_CON_DIV_DIV_CLK_APM_USI0_UART,
1588 CLK_CON_DIV_DIV_CLK_APM_USI0_USI,
1589 CLK_CON_DIV_DIV_CLK_APM_USI1_UART,
1590 CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK,
1591 CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1,
1592 CLK_CON_GAT_CLK_CMU_BOOST_OPTION1,
1593 CLK_CON_GAT_CLK_CORE_BOOST_OPTION1,
1594 CLK_CON_GAT_GATE_CLKCMU_APM_FUNC,
1595 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
1596 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
1597 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
1598 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK,
1599 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK,
1600 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK,
1601 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK,
1602 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK,
1603 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK,
1604 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK,
1605 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK,
1606 CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK,
1607 CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK,
1608 CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
1609 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK,
1610 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK,
1611 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK,
1612 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK,
1613 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK,
1614 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,
1615 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK,
1616 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
1617 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK,
1618 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
1619 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK,
1620 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK,
1621 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK,
1622 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK,
1623 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
1624 CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
1625 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK,
1626 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK,
1627 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK,
1628 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK,
1629 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK,
1630 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK,
1631 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK,
1632 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK,
1633 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK,
1634 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK,
1635 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK,
1636 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK,
1637 CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK,
1638 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2,
1639 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
1640 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK,
1641 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK,
1642 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK,
1643 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK,
1644 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK,
1645 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK,
1646 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK,
1647 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK,
1648 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK,
1649 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK,
1650 CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK,
1651 CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK,
1652 };
1653
1654 PNAME(mout_apm_func_p) = { "oscclk", "mout_apm_funcsrc",
1655 "pad_clk_apm", "oscclk" };
1656 PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm",
1657 "pll_alv_div16_apm" };
1658
1659 static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
1660 FRATE(CLK_APM_PLL_DIV2_APM, "pll_alv_div2_apm", NULL, 0, 393216000),
1661 FRATE(CLK_APM_PLL_DIV4_APM, "pll_alv_div4_apm", NULL, 0, 196608000),
1662 FRATE(CLK_APM_PLL_DIV16_APM, "pll_alv_div16_apm", NULL, 0, 49152000),
1663 };
1664
1665 static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
1666 MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p,
1667 CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1),
1668 MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p,
1669 CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1),
1670 };
1671
1672 static const struct samsung_div_clock apm_div_clks[] __initconst = {
1673 DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func",
1674 CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1),
1675 DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func",
1676 CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7),
1677 DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func",
1678 CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7),
1679 DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func",
1680 CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7),
1681 };
1682
1683 static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
1684 GATE(CLK_GOUT_APM_APM_CMU_APM_PCLK,
1685 "gout_apm_apm_cmu_apm_pclk", "mout_apm_func",
1686 CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 21, 0, 0),
1687 GATE(CLK_GOUT_BUS0_BOOST_OPTION1, "gout_bus0_boost_option1",
1688 "dout_apm_boost", CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, 21, 0, 0),
1689 GATE(CLK_GOUT_CMU_BOOST_OPTION1, "gout_cmu_boost_option1",
1690 "dout_apm_boost", CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, 21, 0, 0),
1691 GATE(CLK_GOUT_CORE_BOOST_OPTION1, "gout_core_boost_option1",
1692 "dout_apm_boost", CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, 21, 0, 0),
1693 GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func",
1694 CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0),
1695 GATE(CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK,
1696 "gout_apm_apbif_gpio_alive_pclk", "gout_apm_func",
1697 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
1698 21, 0, 0),
1699 GATE(CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK,
1700 "gout_apm_apbif_gpio_far_alive_pclk", "gout_apm_func",
1701 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
1702 21, 0, 0),
1703 GATE(CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK,
1704 "gout_apm_apbif_pmu_alive_pclk", "gout_apm_func",
1705 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
1706 21, 0, 0),
1707 GATE(CLK_GOUT_APM_APBIF_RTC_PCLK,
1708 "gout_apm_apbif_rtc_pclk", "gout_apm_func",
1709 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 21, 0, 0),
1710 GATE(CLK_GOUT_APM_APBIF_TRTC_PCLK,
1711 "gout_apm_apbif_trtc_pclk", "gout_apm_func",
1712 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, 21, 0, 0),
1713 GATE(CLK_GOUT_APM_APM_USI0_UART_IPCLK,
1714 "gout_apm_apm_usi0_uart_ipclk", "dout_apm_usi0_uart",
1715 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK,
1716 21, 0, 0),
1717 GATE(CLK_GOUT_APM_APM_USI0_UART_PCLK,
1718 "gout_apm_apm_usi0_uart_pclk", "gout_apm_func",
1719 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK,
1720 21, 0, 0),
1721 GATE(CLK_GOUT_APM_APM_USI0_USI_IPCLK,
1722 "gout_apm_apm_usi0_usi_ipclk", "dout_apm_usi0_usi",
1723 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK,
1724 21, 0, 0),
1725 GATE(CLK_GOUT_APM_APM_USI0_USI_PCLK,
1726 "gout_apm_apm_usi0_usi_pclk", "gout_apm_func",
1727 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK,
1728 21, 0, 0),
1729 GATE(CLK_GOUT_APM_APM_USI1_UART_IPCLK,
1730 "gout_apm_apm_usi1_uart_ipclk", "dout_apm_usi1_uart",
1731 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK,
1732 21, 0, 0),
1733 GATE(CLK_GOUT_APM_APM_USI1_UART_PCLK,
1734 "gout_apm_apm_usi1_uart_pclk", "gout_apm_func",
1735 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK,
1736 21, 0, 0),
1737 GATE(CLK_GOUT_APM_D_TZPC_APM_PCLK,
1738 "gout_apm_d_tzpc_apm_pclk", "gout_apm_func",
1739 CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, 21, 0, 0),
1740 GATE(CLK_GOUT_APM_GPC_APM_PCLK,
1741 "gout_apm_gpc_apm_pclk", "gout_apm_func",
1742 CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, 21, 0, 0),
1743 GATE(CLK_GOUT_APM_GREBEINTEGRATION_HCLK,
1744 "gout_apm_grebeintegration_hclk", "gout_apm_func",
1745 CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
1746 21, 0, 0),
1747 GATE(CLK_GOUT_APM_INTMEM_ACLK,
1748 "gout_apm_intmem_aclk", "gout_apm_func",
1749 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, 21, 0, 0),
1750 GATE(CLK_GOUT_APM_INTMEM_PCLK,
1751 "gout_apm_intmem_pclk", "gout_apm_func",
1752 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, 21, 0, 0),
1753 GATE(CLK_GOUT_APM_LHM_AXI_G_SWD_I_CLK,
1754 "gout_apm_lhm_axi_g_swd_i_clk", "gout_apm_func",
1755 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK,
1756 21, 0, 0),
1757 GATE(CLK_GOUT_APM_LHM_AXI_P_AOCAPM_I_CLK,
1758 "gout_apm_lhm_axi_p_aocapm_i_clk", "gout_apm_func",
1759 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK,
1760 21, 0, 0),
1761 GATE(CLK_GOUT_APM_LHM_AXI_P_APM_I_CLK,
1762 "gout_apm_lhm_axi_p_apm_i_clk", "gout_apm_func",
1763 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,
1764 21, 0, 0),
1765 GATE(CLK_GOUT_APM_LHS_AXI_D_APM_I_CLK,
1766 "gout_apm_lhs_axi_d_apm_i_clk", "gout_apm_func",
1767 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,
1768 21, 0, 0),
1769 GATE(CLK_GOUT_APM_LHS_AXI_G_DBGCORE_I_CLK,
1770 "gout_apm_lhs_axi_g_dbgcore_i_clk", "gout_apm_func",
1771 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK,
1772 21, 0, 0),
1773 GATE(CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_I_CLK,
1774 "gout_apm_lhs_axi_g_scan2dram_i_clk",
1775 "gout_apm_func",
1776 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
1777 21, 0, 0),
1778 GATE(CLK_GOUT_APM_MAILBOX_APM_AOC_PCLK,
1779 "gout_apm_mailbox_apm_aoc_pclk", "gout_apm_func",
1780 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK,
1781 21, 0, 0),
1782 GATE(CLK_GOUT_APM_MAILBOX_APM_AP_PCLK,
1783 "gout_apm_mailbox_apm_ap_pclk", "gout_apm_func",
1784 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
1785 21, 0, 0),
1786 GATE(CLK_GOUT_APM_MAILBOX_APM_GSA_PCLK,
1787 "gout_apm_mailbox_apm_gsa_pclk", "gout_apm_func",
1788 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK,
1789 21, 0, 0),
1790 GATE(CLK_GOUT_APM_MAILBOX_APM_SWD_PCLK,
1791 "gout_apm_mailbox_apm_swd_pclk", "gout_apm_func",
1792 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK,
1793 21, 0, 0),
1794 GATE(CLK_GOUT_APM_MAILBOX_APM_TPU_PCLK,
1795 "gout_apm_mailbox_apm_tpu_pclk", "gout_apm_func",
1796 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK,
1797 21, 0, 0),
1798 GATE(CLK_GOUT_APM_MAILBOX_AP_AOC_PCLK,
1799 "gout_apm_mailbox_ap_aoc_pclk", "gout_apm_func",
1800 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK,
1801 21, 0, 0),
1802 GATE(CLK_GOUT_APM_MAILBOX_AP_DBGCORE_PCLK,
1803 "gout_apm_mailbox_ap_dbgcore_pclk", "gout_apm_func",
1804 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
1805 21, 0, 0),
1806 GATE(CLK_GOUT_APM_PMU_INTR_GEN_PCLK,
1807 "gout_apm_pmu_intr_gen_pclk", "gout_apm_func",
1808 CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
1809 21, 0, 0),
1810 GATE(CLK_GOUT_APM_ROM_CRC32_HOST_ACLK,
1811 "gout_apm_rom_crc32_host_aclk", "gout_apm_func",
1812 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK,
1813 21, 0, 0),
1814 GATE(CLK_GOUT_APM_ROM_CRC32_HOST_PCLK,
1815 "gout_apm_rom_crc32_host_pclk", "gout_apm_func",
1816 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK,
1817 21, 0, 0),
1818 GATE(CLK_GOUT_APM_CLK_APM_BUS_CLK,
1819 "gout_apm_clk_apm_bus_clk", "gout_apm_func",
1820 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK,
1821 21, 0, 0),
1822 GATE(CLK_GOUT_APM_CLK_APM_USI0_UART_CLK,
1823 "gout_apm_clk_apm_usi0_uart_clk",
1824 "dout_apm_usi0_uart",
1825 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK,
1826 21, 0, 0),
1827 GATE(CLK_GOUT_APM_CLK_APM_USI0_USI_CLK,
1828 "gout_apm_clk_apm_usi0_usi_clk",
1829 "dout_apm_usi0_usi",
1830 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK,
1831 21, 0, 0),
1832 GATE(CLK_GOUT_APM_CLK_APM_USI1_UART_CLK,
1833 "gout_apm_clk_apm_usi1_uart_clk",
1834 "dout_apm_usi1_uart",
1835 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK,
1836 21, 0, 0),
1837 GATE(CLK_GOUT_APM_SPEEDY_APM_PCLK,
1838 "gout_apm_speedy_apm_pclk", "gout_apm_func",
1839 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, 21, 0, 0),
1840 GATE(CLK_GOUT_APM_SPEEDY_SUB_APM_PCLK,
1841 "gout_apm_speedy_sub_apm_pclk", "gout_apm_func",
1842 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK,
1843 21, 0, 0),
1844 GATE(CLK_GOUT_APM_SSMT_D_APM_ACLK,
1845 "gout_apm_ssmt_d_apm_aclk", "gout_apm_func",
1846 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, 21, 0, 0),
1847 GATE(CLK_GOUT_APM_SSMT_D_APM_PCLK,
1848 "gout_apm_ssmt_d_apm_pclk", "gout_apm_func",
1849 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, 21, 0, 0),
1850 GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_ACLK,
1851 "gout_apm_ssmt_g_dbgcore_aclk", "gout_apm_func",
1852 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK,
1853 21, 0, 0),
1854 GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_PCLK,
1855 "gout_apm_ssmt_g_dbgcore_pclk", "gout_apm_func",
1856 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK,
1857 21, 0, 0),
1858 GATE(CLK_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK,
1859 "gout_apm_ss_dbgcore_ss_dbgcore_hclk",
1860 "gout_apm_func",
1861 CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK,
1862 21, 0, 0),
1863 GATE(CLK_GOUT_APM_SYSMMU_D_APM_CLK_S2,
1864 "gout_apm_sysmmu_d_dpm_clk_s2", "gout_apm_func",
1865 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2,
1866 21, 0, 0),
1867 GATE(CLK_GOUT_APM_SYSREG_APM_PCLK,
1868 "gout_apm_sysreg_apm_pclk", "gout_apm_func",
1869 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 21, 0, 0),
1870 GATE(CLK_GOUT_APM_UASC_APM_ACLK,
1871 "gout_apm_uasc_apm_aclk", "gout_apm_func",
1872 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, 21, 0, 0),
1873 GATE(CLK_GOUT_APM_UASC_APM_PCLK,
1874 "gout_apm_uasc_apm_pclk", "gout_apm_func",
1875 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, 21, 0, 0),
1876 GATE(CLK_GOUT_APM_UASC_DBGCORE_ACLK,
1877 "gout_apm_uasc_dbgcore_aclk", "gout_apm_func",
1878 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK,
1879 21, 0, 0),
1880 GATE(CLK_GOUT_APM_UASC_DBGCORE_PCLK,
1881 "gout_apm_uasc_dbgcore_pclk", "gout_apm_func",
1882 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK,
1883 21, 0, 0),
1884 GATE(CLK_GOUT_APM_UASC_G_SWD_ACLK,
1885 "gout_apm_uasc_g_swd_aclk", "gout_apm_func",
1886 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, 21, 0, 0),
1887 GATE(CLK_GOUT_APM_UASC_G_SWD_PCLK,
1888 "gout_apm_uasc_g_swd_pclk", "gout_apm_func",
1889 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0),
1890 GATE(CLK_GOUT_APM_UASC_P_AOCAPM_ACLK,
1891 "gout_apm_uasc_p_aocapm_aclk", "gout_apm_func",
1892 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK,
1893 21, 0, 0),
1894 GATE(CLK_GOUT_APM_UASC_P_AOCAPM_PCLK,
1895 "gout_apm_uasc_p_aocapm_pclk", "gout_apm_func",
1896 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0),
1897 GATE(CLK_GOUT_APM_UASC_P_APM_ACLK,
1898 "gout_apm_uasc_p_apm_aclk", "gout_apm_func",
1899 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 21, CLK_IS_CRITICAL, 0),
1900 GATE(CLK_GOUT_APM_UASC_P_APM_PCLK,
1901 "gout_apm_uasc_p_apm_pclk", "gout_apm_func",
1902 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 21, CLK_IS_CRITICAL, 0),
1903 GATE(CLK_GOUT_APM_WDT_APM_PCLK,
1904 "gout_apm_wdt_apm_pclk", "gout_apm_func",
1905 CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 21, 0, 0),
1906 GATE(CLK_GOUT_APM_XIU_DP_APM_ACLK,
1907 "gout_apm_xiu_dp_apm_aclk", "gout_apm_func",
1908 CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, CLK_IS_CRITICAL, 0),
1909 };
1910
1911 static const struct samsung_cmu_info apm_cmu_info __initconst = {
1912 .mux_clks = apm_mux_clks,
1913 .nr_mux_clks = ARRAY_SIZE(apm_mux_clks),
1914 .div_clks = apm_div_clks,
1915 .nr_div_clks = ARRAY_SIZE(apm_div_clks),
1916 .gate_clks = apm_gate_clks,
1917 .nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
1918 .fixed_clks = apm_fixed_clks,
1919 .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
1920 .nr_clk_ids = CLKS_NR_APM,
1921 .clk_regs = apm_clk_regs,
1922 .nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
1923 };
1924
1925 /* ---- CMU_HSI0 ------------------------------------------------------------ */
1926
1927 /* Register Offset definitions for CMU_HSI0 (0x11000000) */
1928 #define PLL_LOCKTIME_PLL_USB 0x0004
1929 #define PLL_CON0_PLL_USB 0x0140
1930 #define PLL_CON1_PLL_USB 0x0144
1931 #define PLL_CON2_PLL_USB 0x0148
1932 #define PLL_CON3_PLL_USB 0x014c
1933 #define PLL_CON4_PLL_USB 0x0150
1934 #define PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER 0x0600
1935 #define PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER 0x0604
1936 #define PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER 0x0610
1937 #define PLL_CON1_MUX_CLKCMU_HSI0_BUS_USER 0x0614
1938 #define PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER 0x0620
1939 #define PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER 0x0624
1940 #define PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER 0x0630
1941 #define PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER 0x0634
1942 #define PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER 0x0640
1943 #define PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER 0x0644
1944 #define PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER 0x0650
1945 #define PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER 0x0654
1946 #define PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER 0x0660
1947 #define PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER 0x0664
1948 #define HSI0_CMU_HSI0_CONTROLLER_OPTION 0x0800
1949 #define CLKOUT_CON_BLK_HSI0_CMU_HSI0_CLKOUT0 0x0810
1950 #define CLK_CON_MUX_MUX_CLK_HSI0_BUS 0x1000
1951 #define CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF 0x1004
1952 #define CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD 0x1008
1953 #define CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD 0x1800
1954 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK 0x2000
1955 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26 0x2004
1956 #define CLK_CON_GAT_CLK_HSI0_ALT 0x2008
1957 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK 0x200c
1958 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK 0x2010
1959 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK 0x2014
1960 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK 0x2018
1961 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK 0x201c
1962 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK 0x2020
1963 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_G_ETR_HSI0_IPCLKPORT_I_CLK 0x2024
1964 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK 0x2028
1965 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK 0x202c
1966 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK 0x2030
1967 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK 0x2034
1968 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK 0x2038
1969 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK 0x203c
1970 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_ACLK 0x2040
1971 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_PCLK 0x2044
1972 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK 0x2048
1973 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK 0x204c
1974 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK 0x2050
1975 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2 0x2054
1976 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK 0x2058
1977 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK 0x205c
1978 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK 0x2060
1979 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK 0x2064
1980 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK 0x2068
1981 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL 0x206c
1982 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY 0x2070
1983 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26 0x2074
1984 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40 0x2078
1985 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL 0x207c
1986 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK 0x2080
1987 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK 0x2084
1988 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK 0x2088
1989 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK 0x208c
1990 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK 0x2090
1991 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK 0x2094
1992 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK 0x2098
1993 #define DMYQCH_CON_USB31DRD_QCH 0x3000
1994 #define DMYQCH_CON_USB31DRD_QCH_REF 0x3004
1995 #define PCH_CON_LHM_AXI_G_ETR_HSI0_PCH 0x3008
1996 #define PCH_CON_LHM_AXI_P_AOCHSI0_PCH 0x300c
1997 #define PCH_CON_LHM_AXI_P_HSI0_PCH 0x3010
1998 #define PCH_CON_LHS_ACEL_D_HSI0_PCH 0x3014
1999 #define PCH_CON_LHS_AXI_D_HSI0AOC_PCH 0x3018
2000 #define QCH_CON_DP_LINK_QCH_GTC_CLK 0x301c
2001 #define QCH_CON_DP_LINK_QCH_PCLK 0x3020
2002 #define QCH_CON_D_TZPC_HSI0_QCH 0x3024
2003 #define QCH_CON_ETR_MIU_QCH_ACLK 0x3028
2004 #define QCH_CON_ETR_MIU_QCH_PCLK 0x302c
2005 #define QCH_CON_GPC_HSI0_QCH 0x3030
2006 #define QCH_CON_HSI0_CMU_HSI0_QCH 0x3034
2007 #define QCH_CON_LHM_AXI_G_ETR_HSI0_QCH 0x3038
2008 #define QCH_CON_LHM_AXI_P_AOCHSI0_QCH 0x303c
2009 #define QCH_CON_LHM_AXI_P_HSI0_QCH 0x3040
2010 #define QCH_CON_LHS_ACEL_D_HSI0_QCH 0x3044
2011 #define QCH_CON_LHS_AXI_D_HSI0AOC_QCH 0x3048
2012 #define QCH_CON_PPMU_HSI0_AOC_QCH 0x304c
2013 #define QCH_CON_PPMU_HSI0_BUS0_QCH 0x3050
2014 #define QCH_CON_SSMT_USB_QCH 0x3054
2015 #define QCH_CON_SYSMMU_USB_QCH 0x3058
2016 #define QCH_CON_SYSREG_HSI0_QCH 0x305c
2017 #define QCH_CON_UASC_HSI0_CTRL_QCH 0x3060
2018 #define QCH_CON_UASC_HSI0_LINK_QCH 0x3064
2019 #define QCH_CON_USB31DRD_QCH_APB 0x3068
2020 #define QCH_CON_USB31DRD_QCH_DBG 0x306c
2021 #define QCH_CON_USB31DRD_QCH_PCS 0x3070
2022 #define QCH_CON_USB31DRD_QCH_SLV_CTRL 0x3074
2023 #define QCH_CON_USB31DRD_QCH_SLV_LINK 0x3078
2024 #define QUEUE_CTRL_REG_BLK_HSI0_CMU_HSI0 0x3c00
2025
2026 static const unsigned long hsi0_clk_regs[] __initconst = {
2027 PLL_LOCKTIME_PLL_USB,
2028 PLL_CON0_PLL_USB,
2029 PLL_CON1_PLL_USB,
2030 PLL_CON2_PLL_USB,
2031 PLL_CON3_PLL_USB,
2032 PLL_CON4_PLL_USB,
2033 PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER,
2034 PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER,
2035 PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER,
2036 PLL_CON1_MUX_CLKCMU_HSI0_BUS_USER,
2037 PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER,
2038 PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER,
2039 PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER,
2040 PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER,
2041 PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER,
2042 PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER,
2043 PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER,
2044 PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER,
2045 PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER,
2046 PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER,
2047 HSI0_CMU_HSI0_CONTROLLER_OPTION,
2048 CLKOUT_CON_BLK_HSI0_CMU_HSI0_CLKOUT0,
2049 CLK_CON_MUX_MUX_CLK_HSI0_BUS,
2050 CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF,
2051 CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD,
2052 CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD,
2053 CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK,
2054 CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26,
2055 CLK_CON_GAT_CLK_HSI0_ALT,
2056 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
2057 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK,
2058 CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK,
2059 CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK,
2060 CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK,
2061 CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK,
2062 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_G_ETR_HSI0_IPCLKPORT_I_CLK,
2063 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK,
2064 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK,
2065 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK,
2066 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK,
2067 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK,
2068 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK,
2069 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_ACLK,
2070 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_PCLK,
2071 CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK,
2072 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK,
2073 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK,
2074 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2,
2075 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK,
2076 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK,
2077 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK,
2078 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK,
2079 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK,
2080 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL,
2081 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY,
2082 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26,
2083 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40,
2084 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL,
2085 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK,
2086 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK,
2087 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK,
2088 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK,
2089 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK,
2090 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK,
2091 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK,
2092 DMYQCH_CON_USB31DRD_QCH,
2093 DMYQCH_CON_USB31DRD_QCH_REF,
2094 PCH_CON_LHM_AXI_G_ETR_HSI0_PCH,
2095 PCH_CON_LHM_AXI_P_AOCHSI0_PCH,
2096 PCH_CON_LHM_AXI_P_HSI0_PCH,
2097 PCH_CON_LHS_ACEL_D_HSI0_PCH,
2098 PCH_CON_LHS_AXI_D_HSI0AOC_PCH,
2099 QCH_CON_DP_LINK_QCH_GTC_CLK,
2100 QCH_CON_DP_LINK_QCH_PCLK,
2101 QCH_CON_D_TZPC_HSI0_QCH,
2102 QCH_CON_ETR_MIU_QCH_ACLK,
2103 QCH_CON_ETR_MIU_QCH_PCLK,
2104 QCH_CON_GPC_HSI0_QCH,
2105 QCH_CON_HSI0_CMU_HSI0_QCH,
2106 QCH_CON_LHM_AXI_G_ETR_HSI0_QCH,
2107 QCH_CON_LHM_AXI_P_AOCHSI0_QCH,
2108 QCH_CON_LHM_AXI_P_HSI0_QCH,
2109 QCH_CON_LHS_ACEL_D_HSI0_QCH,
2110 QCH_CON_LHS_AXI_D_HSI0AOC_QCH,
2111 QCH_CON_PPMU_HSI0_AOC_QCH,
2112 QCH_CON_PPMU_HSI0_BUS0_QCH,
2113 QCH_CON_SSMT_USB_QCH,
2114 QCH_CON_SYSMMU_USB_QCH,
2115 QCH_CON_SYSREG_HSI0_QCH,
2116 QCH_CON_UASC_HSI0_CTRL_QCH,
2117 QCH_CON_UASC_HSI0_LINK_QCH,
2118 QCH_CON_USB31DRD_QCH_APB,
2119 QCH_CON_USB31DRD_QCH_DBG,
2120 QCH_CON_USB31DRD_QCH_PCS,
2121 QCH_CON_USB31DRD_QCH_SLV_CTRL,
2122 QCH_CON_USB31DRD_QCH_SLV_LINK,
2123 QUEUE_CTRL_REG_BLK_HSI0_CMU_HSI0,
2124 };
2125
2126 /* List of parent clocks for Muxes in CMU_HSI0 */
2127 PNAME(mout_pll_usb_p) = { "oscclk", "fout_usb_pll" };
2128 PNAME(mout_hsi0_alt_user_p) = { "oscclk",
2129 "gout_hsi0_clk_hsi0_alt" };
2130 PNAME(mout_hsi0_bus_user_p) = { "oscclk", "dout_cmu_hsi0_bus" };
2131 PNAME(mout_hsi0_dpgtc_user_p) = { "oscclk", "dout_cmu_hsi0_dpgtc" };
2132 PNAME(mout_hsi0_tcxo_user_p) = { "oscclk", "tcxo_hsi1_hsi0" };
2133 PNAME(mout_hsi0_usb20_user_p) = { "oscclk", "usb20phy_phy_clock" };
2134 PNAME(mout_hsi0_usb31drd_user_p) = { "oscclk",
2135 "dout_cmu_hsi0_usb31drd" };
2136 PNAME(mout_hsi0_usbdpdbg_user_p) = { "oscclk",
2137 "dout_cmu_hsi0_usbdpdbg" };
2138 PNAME(mout_hsi0_bus_p) = { "mout_hsi0_bus_user",
2139 "mout_hsi0_alt_user" };
2140 PNAME(mout_hsi0_usb20_ref_p) = { "fout_usb_pll",
2141 "mout_hsi0_tcxo_user" };
2142 PNAME(mout_hsi0_usb31drd_p) = { "fout_usb_pll",
2143 "mout_hsi0_usb31drd_user",
2144 "dout_hsi0_usb31drd",
2145 "fout_usb_pll" };
2146
2147 static const struct samsung_pll_rate_table cmu_hsi0_usb_pll_rates[] __initconst = {
2148 PLL_35XX_RATE(24576000, 19200000, 150, 6, 5),
2149 { /* sentinel */ }
2150 };
2151
2152 static const struct samsung_pll_clock cmu_hsi0_pll_clks[] __initconst = {
2153 PLL(pll_0518x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk",
2154 PLL_LOCKTIME_PLL_USB, PLL_CON3_PLL_USB,
2155 cmu_hsi0_usb_pll_rates),
2156 };
2157
2158 static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = {
2159 MUX(CLK_MOUT_PLL_USB,
2160 "mout_pll_usb", mout_pll_usb_p,
2161 PLL_CON0_PLL_USB, 4, 1),
2162 MUX(CLK_MOUT_HSI0_ALT_USER,
2163 "mout_hsi0_alt_user", mout_hsi0_alt_user_p,
2164 PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER, 4, 1),
2165 MUX(CLK_MOUT_HSI0_BUS_USER,
2166 "mout_hsi0_bus_user", mout_hsi0_bus_user_p,
2167 PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER, 4, 1),
2168 MUX(CLK_MOUT_HSI0_DPGTC_USER,
2169 "mout_hsi0_dpgtc_user", mout_hsi0_dpgtc_user_p,
2170 PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER, 4, 1),
2171 MUX(CLK_MOUT_HSI0_TCXO_USER,
2172 "mout_hsi0_tcxo_user", mout_hsi0_tcxo_user_p,
2173 PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER, 4, 1),
2174 MUX(CLK_MOUT_HSI0_USB20_USER,
2175 "mout_hsi0_usb20_user", mout_hsi0_usb20_user_p,
2176 PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER, 4, 1),
2177 MUX(CLK_MOUT_HSI0_USB31DRD_USER,
2178 "mout_hsi0_usb31drd_user", mout_hsi0_usb31drd_user_p,
2179 PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER, 4, 1),
2180 MUX(CLK_MOUT_HSI0_USBDPDBG_USER,
2181 "mout_hsi0_usbdpdbg_user", mout_hsi0_usbdpdbg_user_p,
2182 PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER, 4, 1),
2183 MUX(CLK_MOUT_HSI0_BUS,
2184 "mout_hsi0_bus", mout_hsi0_bus_p,
2185 CLK_CON_MUX_MUX_CLK_HSI0_BUS, 0, 1),
2186 MUX(CLK_MOUT_HSI0_USB20_REF,
2187 "mout_hsi0_usb20_ref", mout_hsi0_usb20_ref_p,
2188 CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF, 0, 1),
2189 MUX(CLK_MOUT_HSI0_USB31DRD,
2190 "mout_hsi0_usb31drd", mout_hsi0_usb31drd_p,
2191 CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD, 0, 2),
2192 };
2193
2194 static const struct samsung_div_clock hsi0_div_clks[] __initconst = {
2195 DIV(CLK_DOUT_HSI0_USB31DRD,
2196 "dout_hsi0_usb31drd", "mout_hsi0_usb20_user",
2197 CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD, 0, 3),
2198 };
2199
2200 static const struct samsung_gate_clock hsi0_gate_clks[] __initconst = {
2201 /* TODO: should have a driver for this */
2202 GATE(CLK_GOUT_HSI0_PCLK,
2203 "gout_hsi0_hsi0_pclk", "mout_hsi0_bus",
2204 CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK,
2205 21, CLK_IGNORE_UNUSED, 0),
2206 GATE(CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26,
2207 "gout_hsi0_usb31drd_i_usb31drd_suspend_clk_26",
2208 "mout_hsi0_usb20_ref",
2209 CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26,
2210 21, 0, 0),
2211 GATE(CLK_GOUT_HSI0_CLK_HSI0_ALT,
2212 "gout_hsi0_clk_hsi0_alt", "ioclk_clk_hsi0_alt",
2213 CLK_CON_GAT_CLK_HSI0_ALT, 21, 0, 0),
2214 GATE(CLK_GOUT_HSI0_DP_LINK_I_DP_GTC_CLK,
2215 "gout_hsi0_dp_link_i_dp_gtc_clk", "mout_hsi0_dpgtc_user",
2216 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
2217 21, 0, 0),
2218 GATE(CLK_GOUT_HSI0_DP_LINK_I_PCLK,
2219 "gout_hsi0_dp_link_i_pclk", "mout_hsi0_bus",
2220 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK, 21, 0, 0),
2221 GATE(CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK,
2222 "gout_hsi0_d_tzpc_hsi0_pclk", "mout_hsi0_bus",
2223 CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK,
2224 21, 0, 0),
2225 GATE(CLK_GOUT_HSI0_ETR_MIU_I_ACLK,
2226 "gout_hsi0_etr_miu_i_aclk", "mout_hsi0_bus",
2227 CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK, 21, 0, 0),
2228 GATE(CLK_GOUT_HSI0_ETR_MIU_I_PCLK,
2229 "gout_hsi0_etr_miu_i_pclk", "mout_hsi0_bus",
2230 CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK, 21, 0, 0),
2231 GATE(CLK_GOUT_HSI0_GPC_HSI0_PCLK,
2232 "gout_hsi0_gpc_hsi0_pclk", "mout_hsi0_bus",
2233 CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK, 21, 0, 0),
2234 GATE(CLK_GOUT_HSI0_LHM_AXI_G_ETR_HSI0_I_CLK,
2235 "gout_hsi0_lhm_axi_g_etr_hsi0_i_clk", "mout_hsi0_bus",
2236 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_G_ETR_HSI0_IPCLKPORT_I_CLK,
2237 21, 0, 0),
2238 GATE(CLK_GOUT_HSI0_LHM_AXI_P_AOCHSI0_I_CLK,
2239 "gout_hsi0_lhm_axi_p_aochsi0_i_clk", "mout_hsi0_bus",
2240 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK,
2241 21, 0, 0),
2242 /* TODO: should have a driver for this */
2243 GATE(CLK_GOUT_HSI0_LHM_AXI_P_HSI0_I_CLK,
2244 "gout_hsi0_lhm_axi_p_hsi0_i_clk", "mout_hsi0_bus",
2245 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK,
2246 21, CLK_IGNORE_UNUSED, 0),
2247 /* TODO: should have a driver for this */
2248 GATE(CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_I_CLK,
2249 "gout_hsi0_lhs_acel_d_hsi0_i_clk", "mout_hsi0_bus",
2250 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK,
2251 21, CLK_IGNORE_UNUSED, 0),
2252 GATE(CLK_GOUT_HSI0_LHS_AXI_D_HSI0AOC_I_CLK,
2253 "gout_hsi0_lhs_axi_d_hsi0aoc_i_clk", "mout_hsi0_bus",
2254 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK,
2255 21, 0, 0),
2256 GATE(CLK_GOUT_HSI0_PPMU_HSI0_AOC_ACLK,
2257 "gout_hsi0_ppmu_hsi0_aoc_aclk", "mout_hsi0_bus",
2258 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK,
2259 21, 0, 0),
2260 GATE(CLK_GOUT_HSI0_PPMU_HSI0_AOC_PCLK,
2261 "gout_hsi0_ppmu_hsi0_aoc_pclk", "mout_hsi0_bus",
2262 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK,
2263 21, 0, 0),
2264 GATE(CLK_GOUT_HSI0_PPMU_HSI0_BUS0_ACLK,
2265 "gout_hsi0_ppmu_hsi0_bus0_aclk", "mout_hsi0_bus",
2266 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_ACLK,
2267 21, 0, 0),
2268 GATE(CLK_GOUT_HSI0_PPMU_HSI0_BUS0_PCLK,
2269 "gout_hsi0_ppmu_hsi0_bus0_pclk", "mout_hsi0_bus",
2270 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_PCLK,
2271 21, 0, 0),
2272 GATE(CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK,
2273 "gout_hsi0_clk_hsi0_bus_clk", "mout_hsi0_bus",
2274 CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK,
2275 21, 0, 0),
2276 /* TODO: should have a driver for this */
2277 GATE(CLK_GOUT_HSI0_SSMT_USB_ACLK,
2278 "gout_hsi0_ssmt_usb_aclk", "mout_hsi0_bus",
2279 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK,
2280 21, CLK_IGNORE_UNUSED, 0),
2281 /* TODO: should have a driver for this */
2282 GATE(CLK_GOUT_HSI0_SSMT_USB_PCLK,
2283 "gout_hsi0_ssmt_usb_pclk", "mout_hsi0_bus",
2284 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK,
2285 21, CLK_IGNORE_UNUSED, 0),
2286 /* TODO: should have a driver for this */
2287 GATE(CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2,
2288 "gout_hsi0_sysmmu_usb_clk_s2", "mout_hsi0_bus",
2289 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2,
2290 21, CLK_IGNORE_UNUSED, 0),
2291 GATE(CLK_GOUT_HSI0_SYSREG_HSI0_PCLK,
2292 "gout_hsi0_sysreg_hsi0_pclk", "mout_hsi0_bus",
2293 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK,
2294 21, 0, 0),
2295 GATE(CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK,
2296 "gout_hsi0_uasc_hsi0_ctrl_aclk", "mout_hsi0_bus",
2297 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK,
2298 21, 0, 0),
2299 GATE(CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK,
2300 "gout_hsi0_uasc_hsi0_ctrl_pclk", "mout_hsi0_bus",
2301 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK,
2302 21, 0, 0),
2303 GATE(CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK,
2304 "gout_hsi0_uasc_hsi0_link_aclk", "mout_hsi0_bus",
2305 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK,
2306 21, 0, 0),
2307 GATE(CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK,
2308 "gout_hsi0_uasc_hsi0_link_pclk", "mout_hsi0_bus",
2309 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK,
2310 21, 0, 0),
2311 GATE(CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL,
2312 "gout_hsi0_usb31drd_aclk_phyctrl", "mout_hsi0_bus",
2313 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL,
2314 21, 0, 0),
2315 GATE(CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY,
2316 "gout_hsi0_usb31drd_bus_clk_early", "mout_hsi0_bus",
2317 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY,
2318 21, 0, 0),
2319 GATE(CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26,
2320 "gout_hsi0_usb31drd_i_usb20_phy_refclk_26", "mout_hsi0_usb20_ref",
2321 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26,
2322 21, 0, 0),
2323 GATE(CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40,
2324 "gout_hsi0_usb31drd_i_usb31drd_ref_clk_40", "mout_hsi0_usb31drd",
2325 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40,
2326 21, 0, 0),
2327 GATE(CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_REF_SOC_PLL,
2328 "gout_hsi0_usb31drd_i_usbdpphy_ref_soc_pll",
2329 "mout_hsi0_usbdpdbg_user",
2330 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL,
2331 21, 0, 0),
2332 GATE(CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK,
2333 "gout_hsi0_usb31drd_i_usbdpphy_scl_apb_pclk", "mout_hsi0_bus",
2334 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK,
2335 21, 0, 0),
2336 GATE(CLK_GOUT_HSI0_USB31DRD_I_USBPCS_APB_CLK,
2337 "gout_hsi0_usb31drd_i_usbpcs_apb_clk", "mout_hsi0_bus",
2338 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK,
2339 21, 0, 0),
2340 GATE(CLK_GOUT_HSI0_USB31DRD_USBDPPHY_I_ACLK,
2341 "gout_hsi0_usb31drd_usbdpphy_i_aclk", "mout_hsi0_bus",
2342 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK,
2343 21, 0, 0),
2344 GATE(CLK_GOUT_HSI0_USB31DRD_USBDPPHY_UDBG_I_APB_PCLK,
2345 "gout_hsi0_usb31drd_usbdpphy_udbg_i_apb_pclk", "mout_hsi0_bus",
2346 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK,
2347 21, 0, 0),
2348 /* TODO: should have a driver for this */
2349 GATE(CLK_GOUT_HSI0_XIU_D0_HSI0_ACLK,
2350 "gout_hsi0_xiu_d0_hsi0_aclk", "mout_hsi0_bus",
2351 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK,
2352 21, CLK_IGNORE_UNUSED, 0),
2353 /* TODO: should have a driver for this */
2354 GATE(CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK,
2355 "gout_hsi0_xiu_d1_hsi0_aclk", "mout_hsi0_bus",
2356 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK,
2357 21, CLK_IGNORE_UNUSED, 0),
2358 /* TODO: should have a driver for this */
2359 GATE(CLK_GOUT_HSI0_XIU_P_HSI0_ACLK,
2360 "gout_hsi0_xiu_p_hsi0_aclk", "mout_hsi0_bus",
2361 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK,
2362 21, CLK_IGNORE_UNUSED, 0),
2363 };
2364
2365 static const struct samsung_fixed_rate_clock hsi0_fixed_clks[] __initconst = {
2366 FRATE(0, "tcxo_hsi1_hsi0", NULL, 0, 26000000),
2367 FRATE(0, "usb20phy_phy_clock", NULL, 0, 120000000),
2368 /* until we implement APMGSA */
2369 FRATE(0, "ioclk_clk_hsi0_alt", NULL, 0, 213000000),
2370 };
2371
2372 static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
2373 .pll_clks = cmu_hsi0_pll_clks,
2374 .nr_pll_clks = ARRAY_SIZE(cmu_hsi0_pll_clks),
2375 .mux_clks = hsi0_mux_clks,
2376 .nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks),
2377 .div_clks = hsi0_div_clks,
2378 .nr_div_clks = ARRAY_SIZE(hsi0_div_clks),
2379 .gate_clks = hsi0_gate_clks,
2380 .nr_gate_clks = ARRAY_SIZE(hsi0_gate_clks),
2381 .fixed_clks = hsi0_fixed_clks,
2382 .nr_fixed_clks = ARRAY_SIZE(hsi0_fixed_clks),
2383 .nr_clk_ids = CLKS_NR_HSI0,
2384 .clk_regs = hsi0_clk_regs,
2385 .nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs),
2386 .clk_name = "bus",
2387 };
2388
2389 /* ---- CMU_HSI2 ------------------------------------------------------------ */
2390
2391 /* Register Offset definitions for CMU_HSI2 (0x14400000) */
2392 #define PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER 0x0600
2393 #define PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER 0x0604
2394 #define PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0610
2395 #define PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0614
2396 #define PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER 0x0620
2397 #define PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER 0x0624
2398 #define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0630
2399 #define PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0634
2400 #define HSI2_CMU_HSI2_CONTROLLER_OPTION 0x0800
2401 #define CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0 0x0810
2402 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2000
2403 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2004
2404 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK 0x2008
2405 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK 0x200c
2406 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK 0x2010
2407 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK 0x2014
2408 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK 0x201c
2409 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK 0x2020
2410 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK 0x2024
2411 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK 0x2028
2412 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK 0x202c
2413 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK 0x2030
2414 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2034
2415 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x2038
2416 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x203c
2417 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2040
2418 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2044
2419 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2048
2420 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x204c
2421 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2050
2422 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2054
2423 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2058
2424 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK 0x205c
2425 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK 0x2060
2426 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK 0x2064
2427 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK 0x2068
2428 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK 0x206c
2429 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK 0x2070
2430 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK 0x2074
2431 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK 0x2078
2432 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK 0x207c
2433 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK 0x2080
2434 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK 0x2084
2435 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK 0x2088
2436 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK 0x208c
2437 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK 0x2090
2438 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK 0x2094
2439 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK 0x2098
2440 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK 0x209c
2441 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK 0x20a0
2442 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK 0x20a4
2443 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2 0x20a8
2444 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK 0x20ac
2445 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK 0x20b0
2446 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK 0x20b4
2447 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK 0x20b8
2448 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK 0x20bc
2449 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK 0x20c0
2450 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK 0x20c4
2451 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK 0x20c8
2452 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK 0x20cc
2453 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK 0x20d0
2454 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO 0x20d4
2455 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK 0x20d8
2456 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK 0x20dc
2457 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK 0x20e0
2458 #define DMYQCH_CON_PCIE_GEN4_1_QCH_SCLK_1 0x3000
2459 #define PCH_CON_LHM_AXI_P_HSI2_PCH 0x3008
2460 #define PCH_CON_LHS_ACEL_D_HSI2_PCH 0x300c
2461 #define QCH_CON_D_TZPC_HSI2_QCH 0x3010
2462 #define QCH_CON_GPC_HSI2_QCH 0x3014
2463 #define QCH_CON_GPIO_HSI2_QCH 0x3018
2464 #define QCH_CON_HSI2_CMU_HSI2_QCH 0x301c
2465 #define QCH_CON_LHM_AXI_P_HSI2_QCH 0x3020
2466 #define QCH_CON_LHS_ACEL_D_HSI2_QCH 0x3024
2467 #define QCH_CON_MMC_CARD_QCH 0x3028
2468 #define QCH_CON_PCIE_GEN4_1_QCH_APB_1 0x302c
2469 #define QCH_CON_PCIE_GEN4_1_QCH_APB_2 0x3030
2470 #define QCH_CON_PCIE_GEN4_1_QCH_AXI_1 0x3034
2471 #define QCH_CON_PCIE_GEN4_1_QCH_AXI_2 0x3038
2472 #define QCH_CON_PCIE_GEN4_1_QCH_DBG_1 0x303c
2473 #define QCH_CON_PCIE_GEN4_1_QCH_DBG_2 0x3040
2474 #define QCH_CON_PCIE_GEN4_1_QCH_PCS_APB 0x3044
2475 #define QCH_CON_PCIE_GEN4_1_QCH_PMA_APB 0x3048
2476 #define QCH_CON_PCIE_GEN4_1_QCH_UDBG 0x304c
2477 #define QCH_CON_PCIE_IA_GEN4A_1_QCH 0x3050
2478 #define QCH_CON_PCIE_IA_GEN4B_1_QCH 0x3054
2479 #define QCH_CON_PPMU_HSI2_QCH 0x3058
2480 #define QCH_CON_QE_MMC_CARD_HSI2_QCH 0x305c
2481 #define QCH_CON_QE_PCIE_GEN4A_HSI2_QCH 0x3060
2482 #define QCH_CON_QE_PCIE_GEN4B_HSI2_QCH 0x3064
2483 #define QCH_CON_QE_UFS_EMBD_HSI2_QCH 0x3068
2484 #define QCH_CON_SSMT_HSI2_QCH 0x306c
2485 #define QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH 0x3070
2486 #define QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH 0x3074
2487 #define QCH_CON_SYSMMU_HSI2_QCH 0x3078
2488 #define QCH_CON_SYSREG_HSI2_QCH 0x307c
2489 #define QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH 0x3080
2490 #define QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH 0x3084
2491 #define QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH 0x3088
2492 #define QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH 0x308c
2493 #define QCH_CON_UFS_EMBD_QCH 0x3090
2494 #define QCH_CON_UFS_EMBD_QCH_FMP 0x3094
2495 #define QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2 0x3c00
2496
2497 static const unsigned long cmu_hsi2_clk_regs[] __initconst = {
2498 PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER,
2499 PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER,
2500 PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER,
2501 PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER,
2502 PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER,
2503 PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER,
2504 PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
2505 PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
2506 HSI2_CMU_HSI2_CONTROLLER_OPTION,
2507 CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0,
2508 CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
2509 CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
2510 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK,
2511 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK,
2512 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK,
2513 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK,
2514 CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK,
2515 CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK,
2516 CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK,
2517 CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK,
2518 CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK,
2519 CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK,
2520 CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK,
2521 CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
2522 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
2523 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
2524 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
2525 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
2526 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
2527 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
2528 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
2529 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
2530 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK,
2531 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK,
2532 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK,
2533 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK,
2534 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK,
2535 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK,
2536 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK,
2537 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK,
2538 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK,
2539 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK,
2540 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK,
2541 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK,
2542 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK,
2543 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK,
2544 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK,
2545 CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK,
2546 CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK,
2547 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK,
2548 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK,
2549 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2,
2550 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK,
2551 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK,
2552 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK,
2553 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK,
2554 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK,
2555 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK,
2556 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK,
2557 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK,
2558 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK,
2559 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
2560 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
2561 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
2562 CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK,
2563 CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK,
2564 DMYQCH_CON_PCIE_GEN4_1_QCH_SCLK_1,
2565 PCH_CON_LHM_AXI_P_HSI2_PCH,
2566 PCH_CON_LHS_ACEL_D_HSI2_PCH,
2567 QCH_CON_D_TZPC_HSI2_QCH,
2568 QCH_CON_GPC_HSI2_QCH,
2569 QCH_CON_GPIO_HSI2_QCH,
2570 QCH_CON_HSI2_CMU_HSI2_QCH,
2571 QCH_CON_LHM_AXI_P_HSI2_QCH,
2572 QCH_CON_LHS_ACEL_D_HSI2_QCH,
2573 QCH_CON_MMC_CARD_QCH,
2574 QCH_CON_PCIE_GEN4_1_QCH_APB_1,
2575 QCH_CON_PCIE_GEN4_1_QCH_APB_2,
2576 QCH_CON_PCIE_GEN4_1_QCH_AXI_1,
2577 QCH_CON_PCIE_GEN4_1_QCH_AXI_2,
2578 QCH_CON_PCIE_GEN4_1_QCH_DBG_1,
2579 QCH_CON_PCIE_GEN4_1_QCH_DBG_2,
2580 QCH_CON_PCIE_GEN4_1_QCH_PCS_APB,
2581 QCH_CON_PCIE_GEN4_1_QCH_PMA_APB,
2582 QCH_CON_PCIE_GEN4_1_QCH_UDBG,
2583 QCH_CON_PCIE_IA_GEN4A_1_QCH,
2584 QCH_CON_PCIE_IA_GEN4B_1_QCH,
2585 QCH_CON_PPMU_HSI2_QCH,
2586 QCH_CON_QE_MMC_CARD_HSI2_QCH,
2587 QCH_CON_QE_PCIE_GEN4A_HSI2_QCH,
2588 QCH_CON_QE_PCIE_GEN4B_HSI2_QCH,
2589 QCH_CON_QE_UFS_EMBD_HSI2_QCH,
2590 QCH_CON_SSMT_HSI2_QCH,
2591 QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH,
2592 QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH,
2593 QCH_CON_SYSMMU_HSI2_QCH,
2594 QCH_CON_SYSREG_HSI2_QCH,
2595 QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH,
2596 QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH,
2597 QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH,
2598 QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH,
2599 QCH_CON_UFS_EMBD_QCH,
2600 QCH_CON_UFS_EMBD_QCH_FMP,
2601 QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2,
2602 };
2603
2604 PNAME(mout_hsi2_bus_user_p) = { "oscclk", "dout_cmu_hsi2_bus" };
2605 PNAME(mout_hsi2_mmc_card_user_p) = { "oscclk", "dout_cmu_hsi2_mmc_card" };
2606 PNAME(mout_hsi2_pcie_user_p) = { "oscclk", "dout_cmu_hsi2_pcie" };
2607 PNAME(mout_hsi2_ufs_embd_user_p) = { "oscclk", "dout_cmu_hsi2_ufs_embd" };
2608
2609 static const struct samsung_mux_clock hsi2_mux_clks[] __initconst = {
2610 MUX(CLK_MOUT_HSI2_BUS_USER, "mout_hsi2_bus_user", mout_hsi2_bus_user_p,
2611 PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER, 4, 1),
2612 MUX(CLK_MOUT_HSI2_MMC_CARD_USER, "mout_hsi2_mmc_card_user",
2613 mout_hsi2_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER,
2614 4, 1),
2615 MUX(CLK_MOUT_HSI2_PCIE_USER, "mout_hsi2_pcie_user",
2616 mout_hsi2_pcie_user_p, PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER,
2617 4, 1),
2618 MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_hsi2_ufs_embd_user",
2619 mout_hsi2_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
2620 4, 1),
2621 };
2622
2623 static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = {
2624 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_PHY_REFCLK_IN,
2625 "gout_hsi2_pcie_gen4_1_pcie_003_phy_refclk_in",
2626 "mout_hsi2_pcie_user",
2627 CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
2628 21, 0, 0),
2629 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_PHY_REFCLK_IN,
2630 "gout_hsi2_pcie_gen4_1_pcie_004_phy_refclk_in",
2631 "mout_hsi2_pcie_user",
2632 CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
2633 21, 0, 0),
2634 GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_ACLK,
2635 "gout_hsi2_ssmt_pcie_ia_gen4a_1_aclk", "mout_hsi2_bus_user",
2636 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK,
2637 21, 0, 0),
2638 GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_PCLK,
2639 "gout_hsi2_ssmt_pcie_ia_gen4a_1_pclk", "mout_hsi2_bus_user",
2640 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK,
2641 21, 0, 0),
2642 GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_ACLK,
2643 "gout_hsi2_ssmt_pcie_ia_gen4b_1_aclk", "mout_hsi2_bus_user",
2644 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK,
2645 21, 0, 0),
2646 GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_PCLK,
2647 "gout_hsi2_ssmt_pcie_ia_gen4b_1_pclk", "mout_hsi2_bus_user",
2648 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK,
2649 21, 0, 0),
2650 GATE(CLK_GOUT_HSI2_D_TZPC_HSI2_PCLK,
2651 "gout_hsi2_d_tzpc_hsi2_pclk", "mout_hsi2_bus_user",
2652 CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK,
2653 21, 0, 0),
2654 GATE(CLK_GOUT_HSI2_GPC_HSI2_PCLK,
2655 "gout_hsi2_gpc_hsi2_pclk", "mout_hsi2_bus_user",
2656 CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK, 21, 0, 0),
2657 GATE(CLK_GOUT_HSI2_GPIO_HSI2_PCLK,
2658 "gout_hsi2_gpio_hsi2_pclk", "mout_hsi2_bus_user",
2659 CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK, 21,
2660 CLK_IGNORE_UNUSED, 0),
2661 /* Disabling this clock makes the system hang. Mark the clock as critical. */
2662 GATE(CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK,
2663 "gout_hsi2_hsi2_cmu_hsi2_pclk", "mout_hsi2_bus_user",
2664 CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK,
2665 21, CLK_IS_CRITICAL, 0),
2666 /* Disabling this clock makes the system hang. Mark the clock as critical. */
2667 GATE(CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK,
2668 "gout_hsi2_lhm_axi_p_hsi2_i_clk", "mout_hsi2_bus_user",
2669 CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK,
2670 21, CLK_IS_CRITICAL, 0),
2671 /* TODO: should have a driver for this */
2672 GATE(CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK,
2673 "gout_hsi2_lhs_acel_d_hsi2_i_clk", "mout_hsi2_bus_user",
2674 CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK,
2675 21, CLK_IGNORE_UNUSED, 0),
2676 GATE(CLK_GOUT_HSI2_MMC_CARD_I_ACLK,
2677 "gout_hsi2_mmc_card_i_aclk", "mout_hsi2_bus_user",
2678 CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK,
2679 21, 0, 0),
2680 GATE(CLK_GOUT_HSI2_MMC_CARD_SDCLKIN,
2681 "gout_hsi2_mmc_card_sdclkin", "mout_hsi2_mmc_card_user",
2682 CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
2683 21, 0, 0),
2684 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_DBI_ACLK_UG,
2685 "gout_hsi2_pcie_gen4_1_pcie_003_dbi_aclk_ug", "mout_hsi2_bus_user",
2686 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
2687 21, 0, 0),
2688 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_MSTR_ACLK_UG,
2689 "gout_hsi2_pcie_gen4_1_pcie_003_mstr_aclk_ug",
2690 "mout_hsi2_bus_user",
2691 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
2692 21, 0, 0),
2693 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_SLV_ACLK_UG,
2694 "gout_hsi2_pcie_gen4_1_pcie_003_slv_aclk_ug", "mout_hsi2_bus_user",
2695 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
2696 21, 0, 0),
2697 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_I_DRIVER_APB_CLK,
2698 "gout_hsi2_pcie_gen4_1_pcie_003_i_driver_apb_clk",
2699 "mout_hsi2_bus_user",
2700 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
2701 21, 0, 0),
2702 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_DBI_ACLK_UG,
2703 "gout_hsi2_pcie_gen4_1_pcie_004_dbi_aclk_ug", "mout_hsi2_bus_user",
2704 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
2705 21, 0, 0),
2706 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_MSTR_ACLK_UG,
2707 "gout_hsi2_pcie_gen4_1_pcie_004_mstr_aclk_ug",
2708 "mout_hsi2_bus_user",
2709 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
2710 21, 0, 0),
2711 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_SLV_ACLK_UG,
2712 "gout_hsi2_pcie_gen4_1_pcie_004_slv_aclk_ug", "mout_hsi2_bus_user",
2713 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
2714 21, 0, 0),
2715 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_I_DRIVER_APB_CLK,
2716 "gout_hsi2_pcie_gen4_1_pcie_004_i_driver_apb_clk",
2717 "mout_hsi2_bus_user",
2718 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
2719 21, 0, 0),
2720 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PHY_UDBG_I_APB_PCLK,
2721 "gout_hsi2_pcie_gen4_1_pcs_pma_phy_udbg_i_apb_pclk",
2722 "mout_hsi2_bus_user",
2723 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK,
2724 21, 0, 0),
2725 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PIPE_PAL_PCIE_I_APB_PCLK,
2726 "gout_hsi2_pcie_gen4_1_pcs_pma_pipe_pal_pcie_i_apb_pclk",
2727 "mout_hsi2_bus_user",
2728 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK,
2729 21, 0, 0),
2730 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PCIEPHY210X2_QCH_I_APB_PCLK,
2731 "gout_hsi2_pcie_gen4_1_pcs_pma_pciephy210x2_qch_i_apb_pclk",
2732 "mout_hsi2_bus_user",
2733 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK,
2734 21, 0, 0),
2735 GATE(CLK_GOUT_HSI2_PCIE_IA_GEN4A_1_I_CLK,
2736 "gout_hsi2_pcie_ia_gen4a_1_i_clk", "mout_hsi2_bus_user",
2737 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK,
2738 21, 0, 0),
2739 GATE(CLK_GOUT_HSI2_PCIE_IA_GEN4B_1_I_CLK,
2740 "gout_hsi2_pcie_ia_gen4b_1_i_clk", "mout_hsi2_bus_user",
2741 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK,
2742 21, 0, 0),
2743 GATE(CLK_GOUT_HSI2_PPMU_HSI2_ACLK,
2744 "gout_hsi2_ppmu_hsi2_aclk", "mout_hsi2_bus_user",
2745 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK,
2746 21, 0, 0),
2747 GATE(CLK_GOUT_HSI2_PPMU_HSI2_PCLK,
2748 "gout_hsi2_ppmu_hsi2_pclk", "mout_hsi2_bus_user",
2749 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK,
2750 21, 0, 0),
2751 GATE(CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_ACLK,
2752 "gout_hsi2_qe_mmc_card_hsi2_aclk", "mout_hsi2_bus_user",
2753 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK,
2754 21, 0, 0),
2755 GATE(CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_PCLK,
2756 "gout_hsi2_qe_mmc_card_hsi2_pclk", "mout_hsi2_bus_user",
2757 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK,
2758 21, 0, 0),
2759 GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_ACLK,
2760 "gout_hsi2_qe_pcie_gen4a_hsi2_aclk", "mout_hsi2_bus_user",
2761 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK,
2762 21, 0, 0),
2763 GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_PCLK,
2764 "gout_hsi2_qe_pcie_gen4a_hsi2_pclk", "mout_hsi2_bus_user",
2765 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK,
2766 21, 0, 0),
2767 GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_ACLK,
2768 "gout_hsi2_qe_pcie_gen4b_hsi2_aclk", "mout_hsi2_bus_user",
2769 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK,
2770 21, 0, 0),
2771 GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_PCLK,
2772 "gout_hsi2_qe_pcie_gen4b_hsi2_pclk", "mout_hsi2_bus_user",
2773 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK,
2774 21, 0, 0),
2775 GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK,
2776 "gout_hsi2_qe_ufs_embd_hsi2_aclk", "mout_hsi2_bus_user",
2777 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK,
2778 21, CLK_IS_CRITICAL, 0),
2779 GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK,
2780 "gout_hsi2_qe_ufs_embd_hsi2_pclk", "mout_hsi2_bus_user",
2781 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK,
2782 21, CLK_IS_CRITICAL, 0),
2783 GATE(CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK,
2784 "gout_hsi2_clk_hsi2_bus_clk", "mout_hsi2_bus_user",
2785 CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK,
2786 21, CLK_IS_CRITICAL, 0),
2787 GATE(CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK,
2788 "gout_hsi2_clk_hsi2_oscclk_clk", "oscclk",
2789 CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK,
2790 21, 0, 0),
2791 /* TODO: should have a driver for this */
2792 GATE(CLK_GOUT_HSI2_SSMT_HSI2_ACLK,
2793 "gout_hsi2_ssmt_hsi2_aclk", "mout_hsi2_bus_user",
2794 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK,
2795 21, CLK_IGNORE_UNUSED, 0),
2796 /* TODO: should have a driver for this */
2797 GATE(CLK_GOUT_HSI2_SSMT_HSI2_PCLK,
2798 "gout_hsi2_ssmt_hsi2_pclk", "mout_hsi2_bus_user",
2799 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK,
2800 21, CLK_IGNORE_UNUSED, 0),
2801 /* TODO: should have a driver for this */
2802 GATE(CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2,
2803 "gout_hsi2_sysmmu_hsi2_clk_s2", "mout_hsi2_bus_user",
2804 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2,
2805 21, CLK_IGNORE_UNUSED, 0),
2806 GATE(CLK_GOUT_HSI2_SYSREG_HSI2_PCLK,
2807 "gout_hsi2_sysreg_hsi2_pclk", "mout_hsi2_bus_user",
2808 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK,
2809 21, CLK_IS_CRITICAL, 0),
2810 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK,
2811 "gout_hsi2_uasc_pcie_gen4a_dbi_1_aclk", "mout_hsi2_bus_user",
2812 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK,
2813 21, 0, 0),
2814 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_PCLK,
2815 "gout_hsi2_uasc_pcie_gen4a_dbi_1_pclk", "mout_hsi2_bus_user",
2816 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK,
2817 21, 0, 0),
2818 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_ACLK,
2819 "gout_hsi2_uasc_pcie_gen4a_slv_1_aclk", "mout_hsi2_bus_user",
2820 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK,
2821 21, 0, 0),
2822 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_PCLK,
2823 "gout_hsi2_uasc_pcie_gen4a_slv_1_pclk", "mout_hsi2_bus_user",
2824 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK,
2825 21, 0, 0),
2826 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_ACLK,
2827 "gout_hsi2_uasc_pcie_gen4b_dbi_1_aclk", "mout_hsi2_bus_user",
2828 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK,
2829 21, 0, 0),
2830 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_PCLK,
2831 "gout_hsi2_uasc_pcie_gen4b_dbi_1_pclk", "mout_hsi2_bus_user",
2832 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK,
2833 21, 0, 0),
2834 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_ACLK,
2835 "gout_hsi2_uasc_pcie_gen4b_slv_1_aclk", "mout_hsi2_bus_user",
2836 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK,
2837 21, 0, 0),
2838 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_PCLK,
2839 "gout_hsi2_uasc_pcie_gen4b_slv_1_pclk", "mout_hsi2_bus_user",
2840 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK,
2841 21, 0, 0),
2842 GATE(CLK_GOUT_HSI2_UFS_EMBD_I_ACLK,
2843 "gout_hsi2_ufs_embd_i_aclk", "mout_hsi2_bus_user",
2844 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
2845 21, CLK_IS_CRITICAL, 0),
2846 GATE(CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO,
2847 "gout_hsi2_ufs_embd_i_clk_unipro", "mout_hsi2_ufs_embd_user",
2848 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
2849 21, CLK_IS_CRITICAL, 0),
2850 GATE(CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK,
2851 "gout_hsi2_ufs_embd_i_fmp_clk", "mout_hsi2_bus_user",
2852 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
2853 21, CLK_IS_CRITICAL, 0),
2854 /* TODO: should have a driver for this */
2855 GATE(CLK_GOUT_HSI2_XIU_D_HSI2_ACLK,
2856 "gout_hsi2_xiu_d_hsi2_aclk", "mout_hsi2_bus_user",
2857 CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK,
2858 21, CLK_IGNORE_UNUSED, 0),
2859 /* TODO: should have a driver for this */
2860 GATE(CLK_GOUT_HSI2_XIU_P_HSI2_ACLK,
2861 "gout_hsi2_xiu_p_hsi2_aclk", "mout_hsi2_bus_user",
2862 CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK,
2863 21, CLK_IGNORE_UNUSED, 0),
2864 };
2865
2866 static const struct samsung_cmu_info hsi2_cmu_info __initconst = {
2867 .mux_clks = hsi2_mux_clks,
2868 .nr_mux_clks = ARRAY_SIZE(hsi2_mux_clks),
2869 .gate_clks = hsi2_gate_clks,
2870 .nr_gate_clks = ARRAY_SIZE(hsi2_gate_clks),
2871 .nr_clk_ids = CLKS_NR_HSI2,
2872 .clk_regs = cmu_hsi2_clk_regs,
2873 .nr_clk_regs = ARRAY_SIZE(cmu_hsi2_clk_regs),
2874 .clk_name = "bus",
2875 };
2876
2877 /* ---- CMU_MISC ------------------------------------------------------------ */
2878
2879 /* Register Offset definitions for CMU_MISC (0x10010000) */
2880 #define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER 0x0600
2881 #define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER 0x0604
2882 #define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER 0x0610
2883 #define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER 0x0614
2884 #define MISC_CMU_MISC_CONTROLLER_OPTION 0x0800
2885 #define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0 0x0810
2886 #define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000
2887 #define CLK_CON_DIV_DIV_CLK_MISC_BUSP 0x1800
2888 #define CLK_CON_DIV_DIV_CLK_MISC_GIC 0x1804
2889 #define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK 0x2000
2890 #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2004
2891 #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK 0x2008
2892 #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x200c
2893 #define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK 0x2010
2894 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM 0x2014
2895 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM 0x2018
2896 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM 0x201c
2897 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A 0x2020
2898 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK 0x2024
2899 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK 0x2028
2900 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK 0x202c
2901 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK 0x2030
2902 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK 0x2034
2903 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK 0x2038
2904 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK 0x203c
2905 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK 0x2040
2906 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK 0x2044
2907 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK 0x2048
2908 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK 0x204c
2909 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2050
2910 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK 0x2054
2911 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x2058
2912 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK 0x205c
2913 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK 0x2060
2914 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK 0x2064
2915 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK 0x2068
2916 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK 0x206c
2917 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK 0x2070
2918 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK 0x2074
2919 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK 0x2078
2920 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK 0x207c
2921 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK 0x2080
2922 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK 0x2084
2923 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK 0x2088
2924 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK 0x208c
2925 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK 0x2090
2926 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK 0x2094
2927 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK 0x2098
2928 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK 0x209c
2929 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK 0x20a0
2930 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK 0x20a4
2931 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK 0x20a8
2932 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK 0x20ac
2933 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK 0x20b0
2934 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK 0x20b4
2935 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK 0x20b8
2936 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK 0x20bc
2937 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK 0x20c0
2938 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK 0x20c4
2939 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK 0x20c8
2940 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK 0x20cc
2941 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK 0x20d0
2942 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK 0x20d4
2943 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK 0x20d8
2944 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK 0x20dc
2945 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK 0x20e0
2946 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK 0x20e4
2947 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK 0x20e8
2948 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK 0x20ec
2949 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK 0x20f0
2950 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2 0x20f4
2951 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1 0x20f8
2952 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK 0x20fc
2953 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK 0x2100
2954 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK 0x2104
2955 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x2108
2956 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x210c
2957 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK 0x2110
2958 #define DMYQCH_CON_PPMU_DMA_QCH 0x3000
2959 #define DMYQCH_CON_PUF_QCH 0x3004
2960 #define PCH_CON_LHM_AXI_D_SSS_PCH 0x300c
2961 #define PCH_CON_LHM_AXI_P_GIC_PCH 0x3010
2962 #define PCH_CON_LHM_AXI_P_MISC_PCH 0x3014
2963 #define PCH_CON_LHS_ACEL_D_MISC_PCH 0x3018
2964 #define PCH_CON_LHS_AST_IRI_GICCPU_PCH 0x301c
2965 #define PCH_CON_LHS_AXI_D_SSS_PCH 0x3020
2966 #define QCH_CON_ADM_AHB_SSS_QCH 0x3024
2967 #define QCH_CON_DIT_QCH 0x3028
2968 #define QCH_CON_GIC_QCH 0x3030
2969 #define QCH_CON_LHM_AST_ICC_CPUGIC_QCH 0x3038
2970 #define QCH_CON_LHM_AXI_D_SSS_QCH 0x303c
2971 #define QCH_CON_LHM_AXI_P_GIC_QCH 0x3040
2972 #define QCH_CON_LHM_AXI_P_MISC_QCH 0x3044
2973 #define QCH_CON_LHS_ACEL_D_MISC_QCH 0x3048
2974 #define QCH_CON_LHS_AST_IRI_GICCPU_QCH 0x304c
2975 #define QCH_CON_LHS_AXI_D_SSS_QCH 0x3050
2976 #define QCH_CON_MCT_QCH 0x3054
2977 #define QCH_CON_MISC_CMU_MISC_QCH 0x3058
2978 #define QCH_CON_OTP_CON_BIRA_QCH 0x305c
2979 #define QCH_CON_OTP_CON_BISR_QCH 0x3060
2980 #define QCH_CON_OTP_CON_TOP_QCH 0x3064
2981 #define QCH_CON_PDMA_QCH 0x3068
2982 #define QCH_CON_PPMU_MISC_QCH 0x306c
2983 #define QCH_CON_QE_DIT_QCH 0x3070
2984 #define QCH_CON_QE_PDMA_QCH 0x3074
2985 #define QCH_CON_QE_PPMU_DMA_QCH 0x3078
2986 #define QCH_CON_QE_RTIC_QCH 0x307c
2987 #define QCH_CON_QE_SPDMA_QCH 0x3080
2988 #define QCH_CON_QE_SSS_QCH 0x3084
2989 #define QCH_CON_RTIC_QCH 0x3088
2990 #define QCH_CON_SPDMA_QCH 0x308c
2991 #define QCH_CON_SSMT_DIT_QCH 0x3090
2992 #define QCH_CON_SSMT_PDMA_QCH 0x3094
2993 #define QCH_CON_SSMT_PPMU_DMA_QCH 0x3098
2994 #define QCH_CON_SSMT_RTIC_QCH 0x309c
2995 #define QCH_CON_SSMT_SPDMA_QCH 0x30a0
2996 #define QCH_CON_SSMT_SSS_QCH 0x30a4
2997 #define QCH_CON_SSS_QCH 0x30a8
2998 #define QCH_CON_SYSMMU_MISC_QCH 0x30ac
2999 #define QCH_CON_SYSMMU_SSS_QCH 0x30b0
3000 #define QCH_CON_SYSREG_MISC_QCH 0x30b4
3001 #define QCH_CON_TMU_SUB_QCH 0x30b8
3002 #define QCH_CON_TMU_TOP_QCH 0x30bc
3003 #define QCH_CON_WDT_CLUSTER0_QCH 0x30c0
3004 #define QCH_CON_WDT_CLUSTER1_QCH 0x30c4
3005 #define QUEUE_CTRL_REG_BLK_MISC_CMU_MISC 0x3c00
3006
3007 static const unsigned long misc_clk_regs[] __initconst = {
3008 PLL_CON0_MUX_CLKCMU_MISC_BUS_USER,
3009 PLL_CON1_MUX_CLKCMU_MISC_BUS_USER,
3010 PLL_CON0_MUX_CLKCMU_MISC_SSS_USER,
3011 PLL_CON1_MUX_CLKCMU_MISC_SSS_USER,
3012 MISC_CMU_MISC_CONTROLLER_OPTION,
3013 CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0,
3014 CLK_CON_MUX_MUX_CLK_MISC_GIC,
3015 CLK_CON_DIV_DIV_CLK_MISC_BUSP,
3016 CLK_CON_DIV_DIV_CLK_MISC_GIC,
3017 CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,
3018 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
3019 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK,
3020 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
3021 CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK,
3022 CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,
3023 CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM,
3024 CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM,
3025 CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A,
3026 CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK,
3027 CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK,
3028 CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK,
3029 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK,
3030 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK,
3031 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK,
3032 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK,
3033 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK,
3034 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK,
3035 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK,
3036 CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK,
3037 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
3038 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK,
3039 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
3040 CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK,
3041 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK,
3042 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK,
3043 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK,
3044 CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK,
3045 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK,
3046 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK,
3047 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK,
3048 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK,
3049 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK,
3050 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK,
3051 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK,
3052 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK,
3053 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK,
3054 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK,
3055 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK,
3056 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK,
3057 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK,
3058 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK,
3059 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK,
3060 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK,
3061 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK,
3062 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK,
3063 CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK,
3064 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK,
3065 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK,
3066 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK,
3067 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK,
3068 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK,
3069 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK,
3070 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK,
3071 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK,
3072 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK,
3073 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK,
3074 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK,
3075 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK,
3076 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK,
3077 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK,
3078 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2,
3079 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1,
3080 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,
3081 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK,
3082 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK,
3083 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
3084 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
3085 CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK,
3086 DMYQCH_CON_PPMU_DMA_QCH,
3087 DMYQCH_CON_PUF_QCH,
3088 PCH_CON_LHM_AXI_D_SSS_PCH,
3089 PCH_CON_LHM_AXI_P_GIC_PCH,
3090 PCH_CON_LHM_AXI_P_MISC_PCH,
3091 PCH_CON_LHS_ACEL_D_MISC_PCH,
3092 PCH_CON_LHS_AST_IRI_GICCPU_PCH,
3093 PCH_CON_LHS_AXI_D_SSS_PCH,
3094 QCH_CON_ADM_AHB_SSS_QCH,
3095 QCH_CON_DIT_QCH,
3096 QCH_CON_GIC_QCH,
3097 QCH_CON_LHM_AST_ICC_CPUGIC_QCH,
3098 QCH_CON_LHM_AXI_D_SSS_QCH,
3099 QCH_CON_LHM_AXI_P_GIC_QCH,
3100 QCH_CON_LHM_AXI_P_MISC_QCH,
3101 QCH_CON_LHS_ACEL_D_MISC_QCH,
3102 QCH_CON_LHS_AST_IRI_GICCPU_QCH,
3103 QCH_CON_LHS_AXI_D_SSS_QCH,
3104 QCH_CON_MCT_QCH,
3105 QCH_CON_MISC_CMU_MISC_QCH,
3106 QCH_CON_OTP_CON_BIRA_QCH,
3107 QCH_CON_OTP_CON_BISR_QCH,
3108 QCH_CON_OTP_CON_TOP_QCH,
3109 QCH_CON_PDMA_QCH,
3110 QCH_CON_PPMU_MISC_QCH,
3111 QCH_CON_QE_DIT_QCH,
3112 QCH_CON_QE_PDMA_QCH,
3113 QCH_CON_QE_PPMU_DMA_QCH,
3114 QCH_CON_QE_RTIC_QCH,
3115 QCH_CON_QE_SPDMA_QCH,
3116 QCH_CON_QE_SSS_QCH,
3117 QCH_CON_RTIC_QCH,
3118 QCH_CON_SPDMA_QCH,
3119 QCH_CON_SSMT_DIT_QCH,
3120 QCH_CON_SSMT_PDMA_QCH,
3121 QCH_CON_SSMT_PPMU_DMA_QCH,
3122 QCH_CON_SSMT_RTIC_QCH,
3123 QCH_CON_SSMT_SPDMA_QCH,
3124 QCH_CON_SSMT_SSS_QCH,
3125 QCH_CON_SSS_QCH,
3126 QCH_CON_SYSMMU_MISC_QCH,
3127 QCH_CON_SYSMMU_SSS_QCH,
3128 QCH_CON_SYSREG_MISC_QCH,
3129 QCH_CON_TMU_SUB_QCH,
3130 QCH_CON_TMU_TOP_QCH,
3131 QCH_CON_WDT_CLUSTER0_QCH,
3132 QCH_CON_WDT_CLUSTER1_QCH,
3133 QUEUE_CTRL_REG_BLK_MISC_CMU_MISC,
3134 };
3135
3136 /* List of parent clocks for Muxes in CMU_MISC */
3137 PNAME(mout_misc_bus_user_p) = { "oscclk", "dout_cmu_misc_bus" };
3138 PNAME(mout_misc_sss_user_p) = { "oscclk", "dout_cmu_misc_sss" };
3139 PNAME(mout_misc_gic_p) = { "dout_misc_gic", "oscclk" };
3140
3141 static const struct samsung_mux_clock misc_mux_clks[] __initconst = {
3142 MUX(CLK_MOUT_MISC_BUS_USER, "mout_misc_bus_user", mout_misc_bus_user_p,
3143 PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 4, 1),
3144 MUX(CLK_MOUT_MISC_SSS_USER, "mout_misc_sss_user", mout_misc_sss_user_p,
3145 PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 4, 1),
3146 MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic", mout_misc_gic_p,
3147 CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 0),
3148 };
3149
3150 static const struct samsung_div_clock misc_div_clks[] __initconst = {
3151 DIV(CLK_DOUT_MISC_BUSP, "dout_misc_busp", "mout_misc_bus_user",
3152 CLK_CON_DIV_DIV_CLK_MISC_BUSP, 0, 3),
3153 DIV(CLK_DOUT_MISC_GIC, "dout_misc_gic", "mout_misc_bus_user",
3154 CLK_CON_DIV_DIV_CLK_MISC_GIC, 0, 3),
3155 };
3156
3157 static const struct samsung_gate_clock misc_gate_clks[] __initconst = {
3158 GATE(CLK_GOUT_MISC_MISC_CMU_MISC_PCLK,
3159 "gout_misc_misc_cmu_misc_pclk", "dout_misc_busp",
3160 CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,
3161 21, 0, 0),
3162 GATE(CLK_GOUT_MISC_OTP_CON_BIRA_I_OSCCLK,
3163 "gout_misc_otp_con_bira_i_oscclk", "oscclk",
3164 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
3165 21, 0, 0),
3166 GATE(CLK_GOUT_MISC_OTP_CON_BISR_I_OSCCLK,
3167 "gout_misc_otp_con_bisr_i_oscclk", "oscclk",
3168 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK,
3169 21, 0, 0),
3170 GATE(CLK_GOUT_MISC_OTP_CON_TOP_I_OSCCLK,
3171 "gout_misc_otp_con_top_i_oscclk", "oscclk",
3172 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
3173 21, 0, 0),
3174 GATE(CLK_GOUT_MISC_CLK_MISC_OSCCLK_CLK,
3175 "gout_misc_clk_misc_oscclk_clk", "oscclk",
3176 CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK,
3177 21, 0, 0),
3178 GATE(CLK_GOUT_MISC_ADM_AHB_SSS_HCLKM,
3179 "gout_misc_adm_ahb_sss_hclkm", "mout_misc_sss_user",
3180 CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,
3181 21, 0, 0),
3182 GATE(CLK_GOUT_MISC_AD_APB_DIT_PCLKM,
3183 "gout_misc_ad_apb_dit_pclkm", "mout_misc_bus_user",
3184 CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM,
3185 21, 0, 0),
3186 GATE(CLK_GOUT_MISC_D_TZPC_MISC_PCLK,
3187 "gout_misc_d_tzpc_misc_pclk", "dout_misc_busp",
3188 CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK,
3189 21, 0, 0),
3190 GATE(CLK_GOUT_MISC_GIC_GICCLK,
3191 "gout_misc_gic_gicclk", "mout_misc_gic",
3192 CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK,
3193 21, 0, 0),
3194 GATE(CLK_GOUT_MISC_GPC_MISC_PCLK,
3195 "gout_misc_gpc_misc_pclk", "dout_misc_busp",
3196 CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK,
3197 21, 0, 0),
3198 GATE(CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_I_CLK,
3199 "gout_misc_lhm_ast_icc_gpugic_i_clk", "mout_misc_gic",
3200 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK,
3201 21, 0, 0),
3202 GATE(CLK_GOUT_MISC_LHM_AXI_D_SSS_I_CLK,
3203 "gout_misc_lhm_axi_d_sss_i_clk", "mout_misc_bus_user",
3204 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK,
3205 21, 0, 0),
3206 GATE(CLK_GOUT_MISC_LHM_AXI_P_GIC_I_CLK,
3207 "gout_misc_lhm_axi_p_gic_i_clk", "mout_misc_gic",
3208 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK,
3209 21, 0, 0),
3210 GATE(CLK_GOUT_MISC_LHM_AXI_P_MISC_I_CLK,
3211 "gout_misc_lhm_axi_p_misc_i_clk", "dout_misc_busp",
3212 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK,
3213 21, 0, 0),
3214 GATE(CLK_GOUT_MISC_LHS_ACEL_D_MISC_I_CLK,
3215 "gout_misc_lhs_acel_d_misc_i_clk", "mout_misc_bus_user",
3216 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK,
3217 21, 0, 0),
3218 GATE(CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_I_CLK,
3219 "gout_misc_lhs_ast_iri_giccpu_i_clk", "mout_misc_gic",
3220 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK,
3221 21, 0, 0),
3222 GATE(CLK_GOUT_MISC_LHS_AXI_D_SSS_I_CLK,
3223 "gout_misc_lhs_axi_d_sss_i_clk", "mout_misc_sss_user",
3224 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK,
3225 21, 0, 0),
3226 GATE(CLK_GOUT_MISC_MCT_PCLK, "gout_misc_mct_pclk",
3227 "dout_misc_busp",
3228 CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK,
3229 21, 0, 0),
3230 GATE(CLK_GOUT_MISC_OTP_CON_BIRA_PCLK,
3231 "gout_misc_otp_con_bira_pclk", "dout_misc_busp",
3232 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
3233 21, 0, 0),
3234 GATE(CLK_GOUT_MISC_OTP_CON_BISR_PCLK,
3235 "gout_misc_otp_con_bisr_pclk", "dout_misc_busp",
3236 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK,
3237 21, 0, 0),
3238 GATE(CLK_GOUT_MISC_OTP_CON_TOP_PCLK,
3239 "gout_misc_otp_con_top_pclk", "dout_misc_busp",
3240 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
3241 21, 0, 0),
3242 GATE(CLK_GOUT_MISC_PDMA_ACLK, "gout_misc_pdma_aclk",
3243 "mout_misc_bus_user",
3244 CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK,
3245 21, 0, 0),
3246 GATE(CLK_GOUT_MISC_PPMU_MISC_ACLK,
3247 "gout_misc_ppmu_misc_aclk", "mout_misc_bus_user",
3248 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK,
3249 21, 0, 0),
3250 GATE(CLK_GOUT_MISC_PPMU_MISC_PCLK,
3251 "gout_misc_ppmu_misc_pclk", "dout_misc_busp",
3252 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK,
3253 21, 0, 0),
3254 GATE(CLK_GOUT_MISC_PUF_I_CLK,
3255 "gout_misc_puf_i_clk", "mout_misc_sss_user",
3256 CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK,
3257 21, 0, 0),
3258 GATE(CLK_GOUT_MISC_QE_DIT_ACLK,
3259 "gout_misc_qe_dit_aclk", "mout_misc_bus_user",
3260 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK,
3261 21, 0, 0),
3262 GATE(CLK_GOUT_MISC_QE_DIT_PCLK,
3263 "gout_misc_qe_dit_pclk", "dout_misc_busp",
3264 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK,
3265 21, 0, 0),
3266 GATE(CLK_GOUT_MISC_QE_PDMA_ACLK,
3267 "gout_misc_qe_pdma_aclk", "mout_misc_bus_user",
3268 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK,
3269 21, 0, 0),
3270 GATE(CLK_GOUT_MISC_QE_PDMA_PCLK,
3271 "gout_misc_qe_pdma_pclk", "dout_misc_busp",
3272 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK,
3273 21, 0, 0),
3274 GATE(CLK_GOUT_MISC_QE_PPMU_DMA_ACLK,
3275 "gout_misc_qe_ppmu_dma_aclk", "mout_misc_bus_user",
3276 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK,
3277 21, 0, 0),
3278 GATE(CLK_GOUT_MISC_QE_PPMU_DMA_PCLK,
3279 "gout_misc_qe_ppmu_dma_pclk", "dout_misc_busp",
3280 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK,
3281 21, 0, 0),
3282 GATE(CLK_GOUT_MISC_QE_RTIC_ACLK,
3283 "gout_misc_qe_rtic_aclk", "mout_misc_bus_user",
3284 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK,
3285 21, 0, 0),
3286 GATE(CLK_GOUT_MISC_QE_RTIC_PCLK,
3287 "gout_misc_qe_rtic_pclk", "dout_misc_busp",
3288 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK,
3289 21, 0, 0),
3290 GATE(CLK_GOUT_MISC_QE_SPDMA_ACLK,
3291 "gout_misc_qe_spdma_aclk", "mout_misc_bus_user",
3292 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK,
3293 21, 0, 0),
3294 GATE(CLK_GOUT_MISC_QE_SPDMA_PCLK,
3295 "gout_misc_qe_spdma_pclk", "dout_misc_busp",
3296 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK,
3297 21, 0, 0),
3298 GATE(CLK_GOUT_MISC_QE_SSS_ACLK,
3299 "gout_misc_qe_sss_aclk", "mout_misc_sss_user",
3300 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK,
3301 21, 0, 0),
3302 GATE(CLK_GOUT_MISC_QE_SSS_PCLK,
3303 "gout_misc_qe_sss_pclk", "dout_misc_busp",
3304 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK,
3305 21, 0, 0),
3306 GATE(CLK_GOUT_MISC_CLK_MISC_BUSD_CLK,
3307 "gout_misc_clk_misc_busd_clk", "mout_misc_bus_user",
3308 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK,
3309 21, 0, 0),
3310 GATE(CLK_GOUT_MISC_CLK_MISC_BUSP_CLK,
3311 "gout_misc_clk_misc_busp_clk", "dout_misc_busp",
3312 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK,
3313 21, 0, 0),
3314 GATE(CLK_GOUT_MISC_CLK_MISC_GIC_CLK,
3315 "gout_misc_clk_misc_gic_clk", "mout_misc_gic",
3316 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK,
3317 21, 0, 0),
3318 GATE(CLK_GOUT_MISC_CLK_MISC_SSS_CLK,
3319 "gout_misc_clk_misc_sss_clk", "mout_misc_sss_user",
3320 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK,
3321 21, 0, 0),
3322 GATE(CLK_GOUT_MISC_RTIC_I_ACLK,
3323 "gout_misc_rtic_i_aclk", "mout_misc_bus_user",
3324 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK,
3325 21, 0, 0),
3326 GATE(CLK_GOUT_MISC_RTIC_I_PCLK, "gout_misc_rtic_i_pclk",
3327 "dout_misc_busp",
3328 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK,
3329 21, 0, 0),
3330 GATE(CLK_GOUT_MISC_SPDMA_ACLK,
3331 "gout_misc_spdma_ipclockport_aclk", "mout_misc_bus_user",
3332 CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK,
3333 21, 0, 0),
3334 GATE(CLK_GOUT_MISC_SSMT_DIT_ACLK,
3335 "gout_misc_ssmt_dit_aclk", "mout_misc_bus_user",
3336 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK,
3337 21, 0, 0),
3338 GATE(CLK_GOUT_MISC_SSMT_DIT_PCLK,
3339 "gout_misc_ssmt_dit_pclk", "dout_misc_busp",
3340 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK,
3341 21, 0, 0),
3342 GATE(CLK_GOUT_MISC_SSMT_PDMA_ACLK,
3343 "gout_misc_ssmt_pdma_aclk", "mout_misc_bus_user",
3344 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK,
3345 21, 0, 0),
3346 GATE(CLK_GOUT_MISC_SSMT_PDMA_PCLK,
3347 "gout_misc_ssmt_pdma_pclk", "dout_misc_busp",
3348 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK,
3349 21, 0, 0),
3350 GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_ACLK,
3351 "gout_misc_ssmt_ppmu_dma_aclk", "mout_misc_bus_user",
3352 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK,
3353 21, 0, 0),
3354 GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_PCLK,
3355 "gout_misc_ssmt_ppmu_dma_pclk", "dout_misc_busp",
3356 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK,
3357 21, 0, 0),
3358 GATE(CLK_GOUT_MISC_SSMT_RTIC_ACLK,
3359 "gout_misc_ssmt_rtic_aclk", "mout_misc_bus_user",
3360 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK,
3361 21, 0, 0),
3362 GATE(CLK_GOUT_MISC_SSMT_RTIC_PCLK,
3363 "gout_misc_ssmt_rtic_pclk", "dout_misc_busp",
3364 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK,
3365 21, 0, 0),
3366 GATE(CLK_GOUT_MISC_SSMT_SPDMA_ACLK,
3367 "gout_misc_ssmt_spdma_aclk", "mout_misc_bus_user",
3368 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK,
3369 21, 0, 0),
3370 GATE(CLK_GOUT_MISC_SSMT_SPDMA_PCLK,
3371 "gout_misc_ssmt_spdma_pclk", "dout_misc_busp",
3372 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK,
3373 21, 0, 0),
3374 GATE(CLK_GOUT_MISC_SSMT_SSS_ACLK,
3375 "gout_misc_ssmt_sss_aclk", "mout_misc_bus_user",
3376 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK,
3377 21, 0, 0),
3378 GATE(CLK_GOUT_MISC_SSMT_SSS_PCLK,
3379 "gout_misc_ssmt_sss_pclk", "dout_misc_busp",
3380 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK,
3381 21, 0, 0),
3382 GATE(CLK_GOUT_MISC_SSS_I_ACLK,
3383 "gout_misc_sss_i_aclk", "mout_misc_bus_user",
3384 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK,
3385 21, 0, 0),
3386 GATE(CLK_GOUT_MISC_SSS_I_PCLK,
3387 "gout_misc_sss_i_pclk", "dout_misc_busp",
3388 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK,
3389 21, 0, 0),
3390 GATE(CLK_GOUT_MISC_SYSMMU_MISC_CLK_S2,
3391 "gout_misc_sysmmu_misc_clk_s2", "mout_misc_bus_user",
3392 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2,
3393 21, 0, 0),
3394 GATE(CLK_GOUT_MISC_SYSMMU_SSS_CLK_S1,
3395 "gout_misc_sysmmu_sss_clk_s1", "mout_misc_sss_user",
3396 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1,
3397 21, 0, 0),
3398 GATE(CLK_GOUT_MISC_SYSREG_MISC_PCLK,
3399 "gout_misc_sysreg_misc_pclk", "dout_misc_busp",
3400 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,
3401 21, 0, 0),
3402 GATE(CLK_GOUT_MISC_TMU_SUB_PCLK,
3403 "gout_misc_tmu_sub_pclk", "dout_misc_busp",
3404 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK,
3405 21, 0, 0),
3406 GATE(CLK_GOUT_MISC_TMU_TOP_PCLK,
3407 "gout_misc_tmu_top_pclk", "dout_misc_busp",
3408 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK,
3409 21, 0, 0),
3410 GATE(CLK_GOUT_MISC_WDT_CLUSTER0_PCLK,
3411 "gout_misc_wdt_cluster0_pclk", "dout_misc_busp",
3412 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
3413 21, 0, 0),
3414 GATE(CLK_GOUT_MISC_WDT_CLUSTER1_PCLK,
3415 "gout_misc_wdt_cluster1_pclk", "dout_misc_busp",
3416 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
3417 21, 0, 0),
3418 GATE(CLK_GOUT_MISC_XIU_D_MISC_ACLK,
3419 "gout_misc_xiu_d_misc_aclk", "mout_misc_bus_user",
3420 CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK,
3421 21, 0, 0),
3422 };
3423
3424 static const struct samsung_cmu_info misc_cmu_info __initconst = {
3425 .mux_clks = misc_mux_clks,
3426 .nr_mux_clks = ARRAY_SIZE(misc_mux_clks),
3427 .div_clks = misc_div_clks,
3428 .nr_div_clks = ARRAY_SIZE(misc_div_clks),
3429 .gate_clks = misc_gate_clks,
3430 .nr_gate_clks = ARRAY_SIZE(misc_gate_clks),
3431 .nr_clk_ids = CLKS_NR_MISC,
3432 .clk_regs = misc_clk_regs,
3433 .nr_clk_regs = ARRAY_SIZE(misc_clk_regs),
3434 .clk_name = "bus",
3435 };
3436
gs101_cmu_misc_init(struct device_node * np)3437 static void __init gs101_cmu_misc_init(struct device_node *np)
3438 {
3439 exynos_arm64_register_cmu(NULL, np, &misc_cmu_info);
3440 }
3441
3442 /* Register CMU_MISC early, as it's needed for MCT timer */
3443 CLK_OF_DECLARE(gs101_cmu_misc, "google,gs101-cmu-misc",
3444 gs101_cmu_misc_init);
3445
3446 /* ---- CMU_PERIC0 ---------------------------------------------------------- */
3447
3448 /* Register Offset definitions for CMU_PERIC0 (0x10800000) */
3449 #define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600
3450 #define PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER 0x0604
3451 #define PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER 0x0610
3452 #define PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER 0x0614
3453 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0620
3454 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0624
3455 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0640
3456 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0644
3457 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0650
3458 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0654
3459 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0660
3460 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0664
3461 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0670
3462 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0674
3463 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0680
3464 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0684
3465 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0690
3466 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0694
3467 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a0
3468 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a4
3469 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b0
3470 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b4
3471 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c0
3472 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c4
3473 #define PERIC0_CMU_PERIC0_CONTROLLER_OPTION 0x0800
3474 #define CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0 0x0810
3475 #define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800
3476 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART 0x1804
3477 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI 0x180c
3478 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI 0x1810
3479 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI 0x1814
3480 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI 0x1820
3481 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI 0x1824
3482 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI 0x1828
3483 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI 0x182c
3484 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI 0x1830
3485 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI 0x1834
3486 #define CLK_CON_BUF_CLKBUF_PERIC0_IP 0x2000
3487 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2004
3488 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK 0x2008
3489 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x200c
3490 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK 0x2010
3491 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2014
3492 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK 0x2018
3493 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x201c
3494 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2020
3495 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x2024
3496 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2028
3497 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12 0x202c
3498 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13 0x2030
3499 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14 0x2034
3500 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15 0x2038
3501 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x203c
3502 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2040
3503 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x2044
3504 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2048
3505 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x204c
3506 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2050
3507 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x2054
3508 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2058
3509 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x205c
3510 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2060
3511 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x2064
3512 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2068
3513 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12 0x206c
3514 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13 0x2070
3515 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14 0x2074
3516 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15 0x2078
3517 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x207c
3518 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x2080
3519 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2084
3520 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2088
3521 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x208c
3522 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x2090
3523 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2094
3524 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2098
3525 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0 0x209c
3526 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2 0x20a4
3527 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0 0x20a8
3528 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2 0x20b0
3529 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK 0x20b4
3530 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK 0x20b8
3531 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK 0x20bc
3532 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK 0x20c4
3533 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK 0x20c8
3534 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK 0x20cc
3535 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK 0x20d0
3536 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK 0x20d4
3537 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK 0x20d8
3538 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK 0x20dc
3539 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK 0x20e0
3540 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK 0x20e4
3541 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x20e8
3542 #define DMYQCH_CON_PERIC0_TOP0_QCH_S1 0x3000
3543 #define DMYQCH_CON_PERIC0_TOP0_QCH_S2 0x3004
3544 #define DMYQCH_CON_PERIC0_TOP0_QCH_S3 0x3008
3545 #define DMYQCH_CON_PERIC0_TOP0_QCH_S4 0x300c
3546 #define DMYQCH_CON_PERIC0_TOP0_QCH_S5 0x3010
3547 #define DMYQCH_CON_PERIC0_TOP0_QCH_S6 0x3014
3548 #define DMYQCH_CON_PERIC0_TOP0_QCH_S7 0x3018
3549 #define DMYQCH_CON_PERIC0_TOP0_QCH_S8 0x301c
3550 #define PCH_CON_LHM_AXI_P_PERIC0_PCH 0x3020
3551 #define QCH_CON_D_TZPC_PERIC0_QCH 0x3024
3552 #define QCH_CON_GPC_PERIC0_QCH 0x3028
3553 #define QCH_CON_GPIO_PERIC0_QCH 0x302c
3554 #define QCH_CON_LHM_AXI_P_PERIC0_QCH 0x3030
3555 #define QCH_CON_PERIC0_CMU_PERIC0_QCH 0x3034
3556 #define QCH_CON_PERIC0_TOP0_QCH_I3C1 0x3038
3557 #define QCH_CON_PERIC0_TOP0_QCH_I3C2 0x303c
3558 #define QCH_CON_PERIC0_TOP0_QCH_I3C3 0x3040
3559 #define QCH_CON_PERIC0_TOP0_QCH_I3C4 0x3044
3560 #define QCH_CON_PERIC0_TOP0_QCH_I3C5 0x3048
3561 #define QCH_CON_PERIC0_TOP0_QCH_I3C6 0x304c
3562 #define QCH_CON_PERIC0_TOP0_QCH_I3C7 0x3050
3563 #define QCH_CON_PERIC0_TOP0_QCH_I3C8 0x3054
3564 #define QCH_CON_PERIC0_TOP0_QCH_USI1_USI 0x3058
3565 #define QCH_CON_PERIC0_TOP0_QCH_USI2_USI 0x305c
3566 #define QCH_CON_PERIC0_TOP0_QCH_USI3_USI 0x3060
3567 #define QCH_CON_PERIC0_TOP0_QCH_USI4_USI 0x3064
3568 #define QCH_CON_PERIC0_TOP0_QCH_USI5_USI 0x3068
3569 #define QCH_CON_PERIC0_TOP0_QCH_USI6_USI 0x306c
3570 #define QCH_CON_PERIC0_TOP0_QCH_USI7_USI 0x3070
3571 #define QCH_CON_PERIC0_TOP0_QCH_USI8_USI 0x3074
3572 #define QCH_CON_PERIC0_TOP1_QCH_USI0_UART 0x3078
3573 #define QCH_CON_PERIC0_TOP1_QCH_USI14_UART 0x307c
3574 #define QCH_CON_SYSREG_PERIC0_QCH 0x3080
3575 #define QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0 0x3c00
3576
3577 static const unsigned long peric0_clk_regs[] __initconst = {
3578 PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,
3579 PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER,
3580 PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER,
3581 PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER,
3582 PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER,
3583 PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER,
3584 PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER,
3585 PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER,
3586 PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER,
3587 PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER,
3588 PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER,
3589 PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER,
3590 PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER,
3591 PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER,
3592 PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER,
3593 PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER,
3594 PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER,
3595 PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER,
3596 PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER,
3597 PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER,
3598 PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER,
3599 PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER,
3600 PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER,
3601 PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER,
3602 PERIC0_CMU_PERIC0_CONTROLLER_OPTION,
3603 CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0,
3604 CLK_CON_DIV_DIV_CLK_PERIC0_I3C,
3605 CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART,
3606 CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI,
3607 CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI,
3608 CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI,
3609 CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI,
3610 CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI,
3611 CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI,
3612 CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI,
3613 CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI,
3614 CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI,
3615 CLK_CON_BUF_CLKBUF_PERIC0_IP,
3616 CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
3617 CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK,
3618 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK,
3619 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK,
3620 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
3621 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
3622 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
3623 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
3624 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
3625 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
3626 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12,
3627 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13,
3628 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14,
3629 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15,
3630 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
3631 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
3632 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
3633 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
3634 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
3635 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
3636 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
3637 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
3638 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
3639 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
3640 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
3641 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
3642 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12,
3643 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13,
3644 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14,
3645 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15,
3646 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
3647 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
3648 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
3649 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
3650 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
3651 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
3652 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
3653 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
3654 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0,
3655 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2,
3656 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0,
3657 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2,
3658 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
3659 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK,
3660 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK,
3661 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK,
3662 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK,
3663 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK,
3664 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK,
3665 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK,
3666 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK,
3667 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK,
3668 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK,
3669 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK,
3670 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
3671 DMYQCH_CON_PERIC0_TOP0_QCH_S1,
3672 DMYQCH_CON_PERIC0_TOP0_QCH_S2,
3673 DMYQCH_CON_PERIC0_TOP0_QCH_S3,
3674 DMYQCH_CON_PERIC0_TOP0_QCH_S4,
3675 DMYQCH_CON_PERIC0_TOP0_QCH_S5,
3676 DMYQCH_CON_PERIC0_TOP0_QCH_S6,
3677 DMYQCH_CON_PERIC0_TOP0_QCH_S7,
3678 DMYQCH_CON_PERIC0_TOP0_QCH_S8,
3679 PCH_CON_LHM_AXI_P_PERIC0_PCH,
3680 QCH_CON_D_TZPC_PERIC0_QCH,
3681 QCH_CON_GPC_PERIC0_QCH,
3682 QCH_CON_GPIO_PERIC0_QCH,
3683 QCH_CON_LHM_AXI_P_PERIC0_QCH,
3684 QCH_CON_PERIC0_CMU_PERIC0_QCH,
3685 QCH_CON_PERIC0_TOP0_QCH_I3C1,
3686 QCH_CON_PERIC0_TOP0_QCH_I3C2,
3687 QCH_CON_PERIC0_TOP0_QCH_I3C3,
3688 QCH_CON_PERIC0_TOP0_QCH_I3C4,
3689 QCH_CON_PERIC0_TOP0_QCH_I3C5,
3690 QCH_CON_PERIC0_TOP0_QCH_I3C6,
3691 QCH_CON_PERIC0_TOP0_QCH_I3C7,
3692 QCH_CON_PERIC0_TOP0_QCH_I3C8,
3693 QCH_CON_PERIC0_TOP0_QCH_USI1_USI,
3694 QCH_CON_PERIC0_TOP0_QCH_USI2_USI,
3695 QCH_CON_PERIC0_TOP0_QCH_USI3_USI,
3696 QCH_CON_PERIC0_TOP0_QCH_USI4_USI,
3697 QCH_CON_PERIC0_TOP0_QCH_USI5_USI,
3698 QCH_CON_PERIC0_TOP0_QCH_USI6_USI,
3699 QCH_CON_PERIC0_TOP0_QCH_USI7_USI,
3700 QCH_CON_PERIC0_TOP0_QCH_USI8_USI,
3701 QCH_CON_PERIC0_TOP1_QCH_USI0_UART,
3702 QCH_CON_PERIC0_TOP1_QCH_USI14_UART,
3703 QCH_CON_SYSREG_PERIC0_QCH,
3704 QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0,
3705 };
3706
3707 /* List of parent clocks for Muxes in CMU_PERIC0 */
3708 PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_cmu_peric0_bus" };
3709 PNAME(mout_peric0_i3c_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
3710 PNAME(mout_peric0_usi0_uart_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
3711 PNAME(mout_peric0_usi_usi_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
3712
3713 static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
3714 MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user",
3715 mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1),
3716 MUX(CLK_MOUT_PERIC0_I3C_USER, "mout_peric0_i3c_user",
3717 mout_peric0_i3c_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, 4, 1),
3718 MUX(CLK_MOUT_PERIC0_USI0_UART_USER,
3719 "mout_peric0_usi0_uart_user", mout_peric0_usi0_uart_user_p,
3720 PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 4, 1),
3721 nMUX(CLK_MOUT_PERIC0_USI14_USI_USER,
3722 "mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p,
3723 PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1),
3724 nMUX(CLK_MOUT_PERIC0_USI1_USI_USER,
3725 "mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p,
3726 PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1),
3727 nMUX(CLK_MOUT_PERIC0_USI2_USI_USER,
3728 "mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p,
3729 PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1),
3730 nMUX(CLK_MOUT_PERIC0_USI3_USI_USER,
3731 "mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p,
3732 PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1),
3733 nMUX(CLK_MOUT_PERIC0_USI4_USI_USER,
3734 "mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p,
3735 PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1),
3736 nMUX(CLK_MOUT_PERIC0_USI5_USI_USER,
3737 "mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p,
3738 PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1),
3739 nMUX(CLK_MOUT_PERIC0_USI6_USI_USER,
3740 "mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p,
3741 PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1),
3742 nMUX(CLK_MOUT_PERIC0_USI7_USI_USER,
3743 "mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p,
3744 PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1),
3745 nMUX(CLK_MOUT_PERIC0_USI8_USI_USER,
3746 "mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p,
3747 PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1),
3748 };
3749
3750 static const struct samsung_div_clock peric0_div_clks[] __initconst = {
3751 DIV(CLK_DOUT_PERIC0_I3C, "dout_peric0_i3c", "mout_peric0_i3c_user",
3752 CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 4),
3753 DIV(CLK_DOUT_PERIC0_USI0_UART,
3754 "dout_peric0_usi0_uart", "mout_peric0_usi0_uart_user",
3755 CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 0, 4),
3756 DIV_F(CLK_DOUT_PERIC0_USI14_USI,
3757 "dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user",
3758 CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4,
3759 CLK_SET_RATE_PARENT, 0),
3760 DIV_F(CLK_DOUT_PERIC0_USI1_USI,
3761 "dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user",
3762 CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 4,
3763 CLK_SET_RATE_PARENT, 0),
3764 DIV_F(CLK_DOUT_PERIC0_USI2_USI,
3765 "dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user",
3766 CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 4,
3767 CLK_SET_RATE_PARENT, 0),
3768 DIV_F(CLK_DOUT_PERIC0_USI3_USI,
3769 "dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user",
3770 CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 4,
3771 CLK_SET_RATE_PARENT, 0),
3772 DIV_F(CLK_DOUT_PERIC0_USI4_USI,
3773 "dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user",
3774 CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 4,
3775 CLK_SET_RATE_PARENT, 0),
3776 DIV_F(CLK_DOUT_PERIC0_USI5_USI,
3777 "dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user",
3778 CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 4,
3779 CLK_SET_RATE_PARENT, 0),
3780 DIV_F(CLK_DOUT_PERIC0_USI6_USI,
3781 "dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user",
3782 CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 4,
3783 CLK_SET_RATE_PARENT, 0),
3784 DIV_F(CLK_DOUT_PERIC0_USI7_USI,
3785 "dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user",
3786 CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 4,
3787 CLK_SET_RATE_PARENT, 0),
3788 DIV_F(CLK_DOUT_PERIC0_USI8_USI,
3789 "dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user",
3790 CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 4,
3791 CLK_SET_RATE_PARENT, 0),
3792 };
3793
3794 static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
3795 /* Disabling this clock makes the system hang. Mark the clock as critical. */
3796 GATE(CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK,
3797 "gout_peric0_peric0_cmu_peric0_pclk", "mout_peric0_bus_user",
3798 CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
3799 21, CLK_IS_CRITICAL, 0),
3800 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK,
3801 "gout_peric0_clk_peric0_oscclk_clk", "oscclk",
3802 CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK,
3803 21, 0, 0),
3804 GATE(CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK,
3805 "gout_peric0_d_tzpc_peric0_pclk", "mout_peric0_bus_user",
3806 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK,
3807 21, 0, 0),
3808 GATE(CLK_GOUT_PERIC0_GPC_PERIC0_PCLK,
3809 "gout_peric0_gpc_peric0_pclk", "mout_peric0_bus_user",
3810 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK,
3811 21, 0, 0),
3812 GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK,
3813 "gout_peric0_gpio_peric0_pclk", "mout_peric0_bus_user",
3814 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
3815 21, CLK_IGNORE_UNUSED, 0),
3816 /* Disabling this clock makes the system hang. Mark the clock as critical. */
3817 GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK,
3818 "gout_peric0_lhm_axi_p_peric0_i_clk", "mout_peric0_bus_user",
3819 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
3820 21, CLK_IS_CRITICAL, 0),
3821 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0,
3822 "gout_peric0_peric0_top0_ipclk_0", "dout_peric0_usi1_usi",
3823 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
3824 21, CLK_SET_RATE_PARENT, 0),
3825 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1,
3826 "gout_peric0_peric0_top0_ipclk_1", "dout_peric0_usi2_usi",
3827 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
3828 21, CLK_SET_RATE_PARENT, 0),
3829 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10,
3830 "gout_peric0_peric0_top0_ipclk_10", "dout_peric0_i3c",
3831 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
3832 21, 0, 0),
3833 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11,
3834 "gout_peric0_peric0_top0_ipclk_11", "dout_peric0_i3c",
3835 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
3836 21, 0, 0),
3837 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12,
3838 "gout_peric0_peric0_top0_ipclk_12", "dout_peric0_i3c",
3839 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12,
3840 21, 0, 0),
3841 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13,
3842 "gout_peric0_peric0_top0_ipclk_13", "dout_peric0_i3c",
3843 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13,
3844 21, 0, 0),
3845 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14,
3846 "gout_peric0_peric0_top0_ipclk_14", "dout_peric0_i3c",
3847 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14,
3848 21, 0, 0),
3849 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15,
3850 "gout_peric0_peric0_top0_ipclk_15", "dout_peric0_i3c",
3851 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15,
3852 21, 0, 0),
3853 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2,
3854 "gout_peric0_peric0_top0_ipclk_2", "dout_peric0_usi3_usi",
3855 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
3856 21, CLK_SET_RATE_PARENT, 0),
3857 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3,
3858 "gout_peric0_peric0_top0_ipclk_3", "dout_peric0_usi4_usi",
3859 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
3860 21, CLK_SET_RATE_PARENT, 0),
3861 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4,
3862 "gout_peric0_peric0_top0_ipclk_4", "dout_peric0_usi5_usi",
3863 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
3864 21, CLK_SET_RATE_PARENT, 0),
3865 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5,
3866 "gout_peric0_peric0_top0_ipclk_5", "dout_peric0_usi6_usi",
3867 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
3868 21, CLK_SET_RATE_PARENT, 0),
3869 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6,
3870 "gout_peric0_peric0_top0_ipclk_6", "dout_peric0_usi7_usi",
3871 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
3872 21, CLK_SET_RATE_PARENT, 0),
3873 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7,
3874 "gout_peric0_peric0_top0_ipclk_7", "dout_peric0_usi8_usi",
3875 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
3876 21, CLK_SET_RATE_PARENT, 0),
3877 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8,
3878 "gout_peric0_peric0_top0_ipclk_8", "dout_peric0_i3c",
3879 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
3880 21, 0, 0),
3881 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9,
3882 "gout_peric0_peric0_top0_ipclk_9", "dout_peric0_i3c",
3883 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
3884 21, 0, 0),
3885 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0,
3886 "gout_peric0_peric0_top0_pclk_0", "mout_peric0_bus_user",
3887 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
3888 21, 0, 0),
3889 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1,
3890 "gout_peric0_peric0_top0_pclk_1", "mout_peric0_bus_user",
3891 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
3892 21, 0, 0),
3893 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10,
3894 "gout_peric0_peric0_top0_pclk_10", "mout_peric0_bus_user",
3895 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
3896 21, 0, 0),
3897 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11,
3898 "gout_peric0_peric0_top0_pclk_11", "mout_peric0_bus_user",
3899 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
3900 21, 0, 0),
3901 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12,
3902 "gout_peric0_peric0_top0_pclk_12", "mout_peric0_bus_user",
3903 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12,
3904 21, 0, 0),
3905 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13,
3906 "gout_peric0_peric0_top0_pclk_13", "mout_peric0_bus_user",
3907 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13,
3908 21, 0, 0),
3909 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14,
3910 "gout_peric0_peric0_top0_pclk_14", "mout_peric0_bus_user",
3911 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14,
3912 21, 0, 0),
3913 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15,
3914 "gout_peric0_peric0_top0_pclk_15", "mout_peric0_bus_user",
3915 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15,
3916 21, 0, 0),
3917 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2,
3918 "gout_peric0_peric0_top0_pclk_2", "mout_peric0_bus_user",
3919 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
3920 21, 0, 0),
3921 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3,
3922 "gout_peric0_peric0_top0_pclk_3", "mout_peric0_bus_user",
3923 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
3924 21, 0, 0),
3925 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4,
3926 "gout_peric0_peric0_top0_pclk_4", "mout_peric0_bus_user",
3927 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
3928 21, 0, 0),
3929 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5,
3930 "gout_peric0_peric0_top0_pclk_5", "mout_peric0_bus_user",
3931 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
3932 21, 0, 0),
3933 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6,
3934 "gout_peric0_peric0_top0_pclk_6", "mout_peric0_bus_user",
3935 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
3936 21, 0, 0),
3937 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7,
3938 "gout_peric0_peric0_top0_pclk_7", "mout_peric0_bus_user",
3939 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
3940 21, 0, 0),
3941 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8,
3942 "gout_peric0_peric0_top0_pclk_8", "mout_peric0_bus_user",
3943 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
3944 21, 0, 0),
3945 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9,
3946 "gout_peric0_peric0_top0_pclk_9", "mout_peric0_bus_user",
3947 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
3948 21, 0, 0),
3949 /* Disabling this clock makes the system hang. Mark the clock as critical. */
3950 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0,
3951 "gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart",
3952 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0,
3953 21, CLK_IS_CRITICAL, 0),
3954 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2,
3955 "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi",
3956 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2,
3957 21, CLK_SET_RATE_PARENT, 0),
3958 /* Disabling this clock makes the system hang. Mark the clock as critical. */
3959 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0,
3960 "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user",
3961 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0,
3962 21, CLK_IS_CRITICAL, 0),
3963 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2,
3964 "gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user",
3965 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2,
3966 21, 0, 0),
3967 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK,
3968 "gout_peric0_clk_peric0_busp_clk", "mout_peric0_bus_user",
3969 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
3970 21, 0, 0),
3971 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK,
3972 "gout_peric0_clk_peric0_i3c_clk", "dout_peric0_i3c",
3973 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK,
3974 21, 0, 0),
3975 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK,
3976 "gout_peric0_clk_peric0_usi0_uart_clk", "dout_peric0_usi0_uart",
3977 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK,
3978 21, 0, 0),
3979 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK,
3980 "gout_peric0_clk_peric0_usi14_usi_clk", "dout_peric0_usi14_usi",
3981 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK,
3982 21, 0, 0),
3983 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK,
3984 "gout_peric0_clk_peric0_usi1_usi_clk", "dout_peric0_usi1_usi",
3985 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK,
3986 21, 0, 0),
3987 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK,
3988 "gout_peric0_clk_peric0_usi2_usi_clk", "dout_peric0_usi2_usi",
3989 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK,
3990 21, 0, 0),
3991 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK,
3992 "gout_peric0_clk_peric0_usi3_usi_clk", "dout_peric0_usi3_usi",
3993 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK,
3994 21, 0, 0),
3995 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK,
3996 "gout_peric0_clk_peric0_usi4_usi_clk", "dout_peric0_usi4_usi",
3997 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK,
3998 21, 0, 0),
3999 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK,
4000 "gout_peric0_clk_peric0_usi5_usi_clk", "dout_peric0_usi5_usi",
4001 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK,
4002 21, 0, 0),
4003 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK,
4004 "gout_peric0_clk_peric0_usi6_usi_clk", "dout_peric0_usi6_usi",
4005 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK,
4006 21, 0, 0),
4007 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK,
4008 "gout_peric0_clk_peric0_usi7_usi_clk", "dout_peric0_usi7_usi",
4009 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK,
4010 21, 0, 0),
4011 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK,
4012 "gout_peric0_clk_peric0_usi8_usi_clk", "dout_peric0_usi8_usi",
4013 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK,
4014 21, 0, 0),
4015 GATE(CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK,
4016 "gout_peric0_sysreg_peric0_pclk", "mout_peric0_bus_user",
4017 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
4018 21, 0, 0),
4019 };
4020
4021 static const struct samsung_cmu_info peric0_cmu_info __initconst = {
4022 .mux_clks = peric0_mux_clks,
4023 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
4024 .div_clks = peric0_div_clks,
4025 .nr_div_clks = ARRAY_SIZE(peric0_div_clks),
4026 .gate_clks = peric0_gate_clks,
4027 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
4028 .nr_clk_ids = CLKS_NR_PERIC0,
4029 .clk_regs = peric0_clk_regs,
4030 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
4031 .clk_name = "bus",
4032 };
4033
4034 /* ---- CMU_PERIC1 ---------------------------------------------------------- */
4035
4036 /* Register Offset definitions for CMU_PERIC1 (0x10c00000) */
4037 #define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600
4038 #define PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER 0x0604
4039 #define PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER 0x0610
4040 #define PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER 0x0614
4041 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0620
4042 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0624
4043 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0630
4044 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0634
4045 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0640
4046 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0644
4047 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0650
4048 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0654
4049 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0660
4050 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0664
4051 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0670
4052 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0674
4053 #define PERIC1_CMU_PERIC1_CONTROLLER_OPTION 0x0800
4054 #define CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0 0x0810
4055 #define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800
4056 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI 0x1804
4057 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808
4058 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c
4059 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810
4060 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814
4061 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI 0x1818
4062 #define CLK_CON_BUF_CLKBUF_PERIC1_IP 0x2000
4063 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK 0x2004
4064 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK 0x2008
4065 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK 0x200c
4066 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK 0x2010
4067 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK 0x2014
4068 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x2018
4069 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK 0x201c
4070 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0x2020
4071 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0x2024
4072 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0x2028
4073 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x202c
4074 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0x2030
4075 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0x2034
4076 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0x2038
4077 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x203c
4078 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15 0x2040
4079 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2044
4080 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2048
4081 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x204c
4082 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2050
4083 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2054
4084 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x2058
4085 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK 0x205c
4086 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK 0x2060
4087 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK 0x2064
4088 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK 0x2068
4089 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK 0x206c
4090 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK 0x2070
4091 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK 0x2074
4092 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2078
4093 #define DMYQCH_CON_PERIC1_TOP0_QCH_S 0x3000
4094 #define PCH_CON_LHM_AXI_P_PERIC1_PCH 0x3004
4095 #define QCH_CON_D_TZPC_PERIC1_QCH 0x3008
4096 #define QCH_CON_GPC_PERIC1_QCH 0x300c
4097 #define QCH_CON_GPIO_PERIC1_QCH 0x3010
4098 #define QCH_CON_LHM_AXI_P_PERIC1_QCH 0x3014
4099 #define QCH_CON_PERIC1_CMU_PERIC1_QCH 0x3018
4100 #define QCH_CON_PERIC1_TOP0_QCH_I3C0 0x301c
4101 #define QCH_CON_PERIC1_TOP0_QCH_PWM 0x3020
4102 #define QCH_CON_PERIC1_TOP0_QCH_USI0_USI 0x3024
4103 #define QCH_CON_PERIC1_TOP0_QCH_USI10_USI 0x3028
4104 #define QCH_CON_PERIC1_TOP0_QCH_USI11_USI 0x302c
4105 #define QCH_CON_PERIC1_TOP0_QCH_USI12_USI 0x3030
4106 #define QCH_CON_PERIC1_TOP0_QCH_USI13_USI 0x3034
4107 #define QCH_CON_PERIC1_TOP0_QCH_USI9_USI 0x3038
4108 #define QCH_CON_SYSREG_PERIC1_QCH 0x303c
4109 #define QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1 0x3c00
4110
4111 static const unsigned long peric1_clk_regs[] __initconst = {
4112 PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,
4113 PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER,
4114 PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER,
4115 PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER,
4116 PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER,
4117 PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER,
4118 PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER,
4119 PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER,
4120 PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER,
4121 PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER,
4122 PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER,
4123 PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER,
4124 PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER,
4125 PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER,
4126 PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER,
4127 PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER,
4128 PERIC1_CMU_PERIC1_CONTROLLER_OPTION,
4129 CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0,
4130 CLK_CON_DIV_DIV_CLK_PERIC1_I3C,
4131 CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI,
4132 CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
4133 CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
4134 CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
4135 CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,
4136 CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI,
4137 CLK_CON_BUF_CLKBUF_PERIC1_IP,
4138 CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
4139 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK,
4140 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK,
4141 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
4142 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK,
4143 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
4144 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
4145 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
4146 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
4147 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
4148 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
4149 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
4150 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
4151 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
4152 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
4153 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15,
4154 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
4155 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
4156 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
4157 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
4158 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
4159 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
4160 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
4161 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK,
4162 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK,
4163 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,
4164 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK,
4165 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK,
4166 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK,
4167 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
4168 DMYQCH_CON_PERIC1_TOP0_QCH_S,
4169 PCH_CON_LHM_AXI_P_PERIC1_PCH,
4170 QCH_CON_D_TZPC_PERIC1_QCH,
4171 QCH_CON_GPC_PERIC1_QCH,
4172 QCH_CON_GPIO_PERIC1_QCH,
4173 QCH_CON_LHM_AXI_P_PERIC1_QCH,
4174 QCH_CON_PERIC1_CMU_PERIC1_QCH,
4175 QCH_CON_PERIC1_TOP0_QCH_I3C0,
4176 QCH_CON_PERIC1_TOP0_QCH_PWM,
4177 QCH_CON_PERIC1_TOP0_QCH_USI0_USI,
4178 QCH_CON_PERIC1_TOP0_QCH_USI10_USI,
4179 QCH_CON_PERIC1_TOP0_QCH_USI11_USI,
4180 QCH_CON_PERIC1_TOP0_QCH_USI12_USI,
4181 QCH_CON_PERIC1_TOP0_QCH_USI13_USI,
4182 QCH_CON_PERIC1_TOP0_QCH_USI9_USI,
4183 QCH_CON_SYSREG_PERIC1_QCH,
4184 QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1,
4185 };
4186
4187 /* List of parent clocks for Muxes in CMU_PERIC1 */
4188 PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_cmu_peric1_bus" };
4189 PNAME(mout_peric1_nonbususer_p) = { "oscclk", "dout_cmu_peric1_ip" };
4190
4191 static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
4192 MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user",
4193 mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1),
4194 MUX(CLK_MOUT_PERIC1_I3C_USER,
4195 "mout_peric1_i3c_user", mout_peric1_nonbususer_p,
4196 PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 4, 1),
4197 nMUX(CLK_MOUT_PERIC1_USI0_USI_USER,
4198 "mout_peric1_usi0_usi_user", mout_peric1_nonbususer_p,
4199 PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4, 1),
4200 nMUX(CLK_MOUT_PERIC1_USI10_USI_USER,
4201 "mout_peric1_usi10_usi_user", mout_peric1_nonbususer_p,
4202 PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1),
4203 nMUX(CLK_MOUT_PERIC1_USI11_USI_USER,
4204 "mout_peric1_usi11_usi_user", mout_peric1_nonbususer_p,
4205 PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1),
4206 nMUX(CLK_MOUT_PERIC1_USI12_USI_USER,
4207 "mout_peric1_usi12_usi_user", mout_peric1_nonbususer_p,
4208 PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1),
4209 nMUX(CLK_MOUT_PERIC1_USI13_USI_USER,
4210 "mout_peric1_usi13_usi_user", mout_peric1_nonbususer_p,
4211 PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4, 1),
4212 nMUX(CLK_MOUT_PERIC1_USI9_USI_USER,
4213 "mout_peric1_usi9_usi_user", mout_peric1_nonbususer_p,
4214 PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4, 1),
4215 };
4216
4217 static const struct samsung_div_clock peric1_div_clks[] __initconst = {
4218 DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c", "mout_peric1_i3c_user",
4219 CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4),
4220 DIV_F(CLK_DOUT_PERIC1_USI0_USI,
4221 "dout_peric1_usi0_usi", "mout_peric1_usi0_usi_user",
4222 CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4,
4223 CLK_SET_RATE_PARENT, 0),
4224 DIV_F(CLK_DOUT_PERIC1_USI10_USI,
4225 "dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user",
4226 CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4,
4227 CLK_SET_RATE_PARENT, 0),
4228 DIV_F(CLK_DOUT_PERIC1_USI11_USI,
4229 "dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user",
4230 CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4,
4231 CLK_SET_RATE_PARENT, 0),
4232 DIV_F(CLK_DOUT_PERIC1_USI12_USI,
4233 "dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user",
4234 CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4,
4235 CLK_SET_RATE_PARENT, 0),
4236 DIV_F(CLK_DOUT_PERIC1_USI13_USI,
4237 "dout_peric1_usi13_usi", "mout_peric1_usi13_usi_user",
4238 CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4,
4239 CLK_SET_RATE_PARENT, 0),
4240 DIV_F(CLK_DOUT_PERIC1_USI9_USI,
4241 "dout_peric1_usi9_usi", "mout_peric1_usi9_usi_user",
4242 CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4,
4243 CLK_SET_RATE_PARENT, 0),
4244 };
4245
4246 static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
4247 GATE(CLK_GOUT_PERIC1_PCLK,
4248 "gout_peric1_peric1_pclk", "mout_peric1_bus_user",
4249 CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
4250 21, CLK_IS_CRITICAL, 0),
4251 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK,
4252 "gout_peric1_clk_peric1_i3c_clk", "dout_peric1_i3c",
4253 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK,
4254 21, 0, 0),
4255 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK,
4256 "gout_peric1_clk_peric1_oscclk_clk", "oscclk",
4257 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK,
4258 21, 0, 0),
4259 GATE(CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK,
4260 "gout_peric1_d_tzpc_peric1_pclk", "mout_peric1_bus_user",
4261 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
4262 21, 0, 0),
4263 GATE(CLK_GOUT_PERIC1_GPC_PERIC1_PCLK,
4264 "gout_peric1_gpc_peric1_pclk", "mout_peric1_bus_user",
4265 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK,
4266 21, 0, 0),
4267 GATE(CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK,
4268 "gout_peric1_gpio_peric1_pclk", "mout_peric1_bus_user",
4269 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
4270 21, CLK_IGNORE_UNUSED, 0),
4271 GATE(CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK,
4272 "gout_peric1_lhm_axi_p_peric1_i_clk", "mout_peric1_bus_user",
4273 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
4274 21, CLK_IS_CRITICAL, 0),
4275 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1,
4276 "gout_peric1_peric1_top0_ipclk_1", "dout_peric1_usi0_usi",
4277 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
4278 21, CLK_SET_RATE_PARENT, 0),
4279 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2,
4280 "gout_peric1_peric1_top0_ipclk_2", "dout_peric1_usi9_usi",
4281 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
4282 21, CLK_SET_RATE_PARENT, 0),
4283 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3,
4284 "gout_peric1_peric1_top0_ipclk_3", "dout_peric1_usi10_usi",
4285 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
4286 21, CLK_SET_RATE_PARENT, 0),
4287 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4,
4288 "gout_peric1_peric1_top0_ipclk_4", "dout_peric1_usi11_usi",
4289 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
4290 21, CLK_SET_RATE_PARENT, 0),
4291 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5,
4292 "gout_peric1_peric1_top0_ipclk_5", "dout_peric1_usi12_usi",
4293 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
4294 21, CLK_SET_RATE_PARENT, 0),
4295 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6,
4296 "gout_peric1_peric1_top0_ipclk_6", "dout_peric1_usi13_usi",
4297 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
4298 21, CLK_SET_RATE_PARENT, 0),
4299 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8,
4300 "gout_peric1_peric1_top0_ipclk_8", "dout_peric1_i3c",
4301 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
4302 21, 0, 0),
4303 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1,
4304 "gout_peric1_peric1_top0_pclk_1", "mout_peric1_bus_user",
4305 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
4306 21, 0, 0),
4307 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15,
4308 "gout_peric1_peric1_top0_pclk_15", "mout_peric1_bus_user",
4309 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15,
4310 21, 0, 0),
4311 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2,
4312 "gout_peric1_peric1_top0_pclk_2", "mout_peric1_bus_user",
4313 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
4314 21, 0, 0),
4315 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3,
4316 "gout_peric1_peric1_top0_pclk_3", "mout_peric1_bus_user",
4317 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
4318 21, 0, 0),
4319 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4,
4320 "gout_peric1_peric1_top0_pclk_4", "mout_peric1_bus_user",
4321 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
4322 21, 0, 0),
4323 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5,
4324 "gout_peric1_peric1_top0_pclk_5", "mout_peric1_bus_user",
4325 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
4326 21, 0, 0),
4327 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6,
4328 "gout_peric1_peric1_top0_pclk_6", "mout_peric1_bus_user",
4329 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
4330 21, 0, 0),
4331 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8,
4332 "gout_peric1_peric1_top0_pclk_8", "mout_peric1_bus_user",
4333 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
4334 21, 0, 0),
4335 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK,
4336 "gout_peric1_clk_peric1_busp_clk", "mout_peric1_bus_user",
4337 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
4338 21, 0, 0),
4339 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK,
4340 "gout_peric1_clk_peric1_usi0_usi_clk", "dout_peric1_usi0_usi",
4341 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK,
4342 21, 0, 0),
4343 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK,
4344 "gout_peric1_clk_peric1_usi10_usi_clk", "dout_peric1_usi10_usi",
4345 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK,
4346 21, 0, 0),
4347 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK,
4348 "gout_peric1_clk_peric1_usi11_usi_clk", "dout_peric1_usi11_usi",
4349 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,
4350 21, 0, 0),
4351 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK,
4352 "gout_peric1_clk_peric1_usi12_usi_clk", "dout_peric1_usi12_usi",
4353 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK,
4354 21, 0, 0),
4355 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK,
4356 "gout_peric1_clk_peric1_usi13_usi_clk", "dout_peric1_usi13_usi",
4357 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK,
4358 21, 0, 0),
4359 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK,
4360 "gout_peric1_clk_peric1_usi9_usi_clk", "dout_peric1_usi9_usi",
4361 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK,
4362 21, 0, 0),
4363 GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK,
4364 "gout_peric1_sysreg_peric1_pclk", "mout_peric1_bus_user",
4365 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
4366 21, 0, 0),
4367 };
4368
4369 static const struct samsung_cmu_info peric1_cmu_info __initconst = {
4370 .mux_clks = peric1_mux_clks,
4371 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
4372 .div_clks = peric1_div_clks,
4373 .nr_div_clks = ARRAY_SIZE(peric1_div_clks),
4374 .gate_clks = peric1_gate_clks,
4375 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
4376 .nr_clk_ids = CLKS_NR_PERIC1,
4377 .clk_regs = peric1_clk_regs,
4378 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
4379 .clk_name = "bus",
4380 };
4381
4382 /* ---- platform_driver ----------------------------------------------------- */
4383
gs101_cmu_probe(struct platform_device * pdev)4384 static int __init gs101_cmu_probe(struct platform_device *pdev)
4385 {
4386 const struct samsung_cmu_info *info;
4387 struct device *dev = &pdev->dev;
4388
4389 info = of_device_get_match_data(dev);
4390 exynos_arm64_register_cmu(dev, dev->of_node, info);
4391
4392 return 0;
4393 }
4394
4395 static const struct of_device_id gs101_cmu_of_match[] = {
4396 {
4397 .compatible = "google,gs101-cmu-apm",
4398 .data = &apm_cmu_info,
4399 }, {
4400 .compatible = "google,gs101-cmu-hsi0",
4401 .data = &hsi0_cmu_info,
4402 }, {
4403 .compatible = "google,gs101-cmu-hsi2",
4404 .data = &hsi2_cmu_info,
4405 }, {
4406 .compatible = "google,gs101-cmu-peric0",
4407 .data = &peric0_cmu_info,
4408 }, {
4409 .compatible = "google,gs101-cmu-peric1",
4410 .data = &peric1_cmu_info,
4411 }, {
4412 },
4413 };
4414
4415 static struct platform_driver gs101_cmu_driver __refdata = {
4416 .driver = {
4417 .name = "gs101-cmu",
4418 .of_match_table = gs101_cmu_of_match,
4419 .suppress_bind_attrs = true,
4420 },
4421 .probe = gs101_cmu_probe,
4422 };
4423
gs101_cmu_init(void)4424 static int __init gs101_cmu_init(void)
4425 {
4426 return platform_driver_register(&gs101_cmu_driver);
4427 }
4428 core_initcall(gs101_cmu_init);
4429