1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/module.h>
8 #include <linux/msi.h>
9 #include <linux/pci.h>
10 #if defined(CONFIG_OF)
11 #include <linux/of.h>
12 #endif
13 #if defined(__FreeBSD__)
14 #include <linux/delay.h>
15 #include <linux/cpu.h>
16 #endif
17
18 #include "pci.h"
19 #include "core.h"
20 #include "hif.h"
21 #include "mhi.h"
22 #include "debug.h"
23 #include "pcic.h"
24 #include "qmi.h"
25
26 #define ATH11K_PCI_BAR_NUM 0
27 #define ATH11K_PCI_DMA_MASK 32
28
29 #define TCSR_SOC_HW_VERSION 0x0224
30 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
31 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0)
32
33 #define QCA6390_DEVICE_ID 0x1101
34 #define QCN9074_DEVICE_ID 0x1104
35 #define WCN6855_DEVICE_ID 0x1103
36
37 static const struct pci_device_id ath11k_pci_id_table[] = {
38 { PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) },
39 { PCI_VDEVICE(QCOM, WCN6855_DEVICE_ID) },
40 { PCI_VDEVICE(QCOM, QCN9074_DEVICE_ID) },
41 {0}
42 };
43
44 MODULE_DEVICE_TABLE(pci, ath11k_pci_id_table);
45
ath11k_pci_bus_wake_up(struct ath11k_base * ab)46 static int ath11k_pci_bus_wake_up(struct ath11k_base *ab)
47 {
48 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
49
50 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
51 }
52
ath11k_pci_bus_release(struct ath11k_base * ab)53 static void ath11k_pci_bus_release(struct ath11k_base *ab)
54 {
55 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
56
57 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
58 }
59
ath11k_pci_get_window_start(struct ath11k_base * ab,u32 offset)60 static u32 ath11k_pci_get_window_start(struct ath11k_base *ab, u32 offset)
61 {
62 if (!ab->hw_params.static_window_map)
63 return ATH11K_PCI_WINDOW_START;
64
65 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK)
66 /* if offset lies within DP register range, use 3rd window */
67 return 3 * ATH11K_PCI_WINDOW_START;
68 else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) <
69 ATH11K_PCI_WINDOW_RANGE_MASK)
70 /* if offset lies within CE register range, use 2nd window */
71 return 2 * ATH11K_PCI_WINDOW_START;
72 else
73 return ATH11K_PCI_WINDOW_START;
74 }
75
ath11k_pci_select_window(struct ath11k_pci * ab_pci,u32 offset)76 static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset)
77 {
78 struct ath11k_base *ab = ab_pci->ab;
79
80 u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset);
81
82 lockdep_assert_held(&ab_pci->window_lock);
83
84 if (window != ab_pci->register_window) {
85 #if defined(__linux__)
86 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
87 ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
88 ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
89 #elif defined(__FreeBSD__)
90 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
91 (char *)ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
92 ioread32((char *)ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
93 #endif
94 ab_pci->register_window = window;
95 }
96 }
97
98 static void
ath11k_pci_window_write32(struct ath11k_base * ab,u32 offset,u32 value)99 ath11k_pci_window_write32(struct ath11k_base *ab, u32 offset, u32 value)
100 {
101 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
102 u32 window_start;
103
104 window_start = ath11k_pci_get_window_start(ab, offset);
105
106 if (window_start == ATH11K_PCI_WINDOW_START) {
107 spin_lock_bh(&ab_pci->window_lock);
108 ath11k_pci_select_window(ab_pci, offset);
109 #if defined(__linux__)
110 iowrite32(value, ab->mem + window_start +
111 #elif defined(__FreeBSD__)
112 iowrite32(value, (char *)ab->mem + window_start +
113 #endif
114 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
115 spin_unlock_bh(&ab_pci->window_lock);
116 } else {
117 #if defined(__linux__)
118 iowrite32(value, ab->mem + window_start +
119 #elif defined(__FreeBSD__)
120 iowrite32(value, (char *)ab->mem + window_start +
121 #endif
122 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
123 }
124 }
125
ath11k_pci_window_read32(struct ath11k_base * ab,u32 offset)126 static u32 ath11k_pci_window_read32(struct ath11k_base *ab, u32 offset)
127 {
128 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
129 u32 window_start, val;
130
131 window_start = ath11k_pci_get_window_start(ab, offset);
132
133 if (window_start == ATH11K_PCI_WINDOW_START) {
134 spin_lock_bh(&ab_pci->window_lock);
135 ath11k_pci_select_window(ab_pci, offset);
136 #if defined(__linux__)
137 val = ioread32(ab->mem + window_start +
138 #elif defined(__FreeBSD__)
139 val = ioread32((char *)ab->mem + window_start +
140 #endif
141 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
142 spin_unlock_bh(&ab_pci->window_lock);
143 } else {
144 #if defined(__linux__)
145 val = ioread32(ab->mem + window_start +
146 #elif defined(__FreeBSD__)
147 val = ioread32((char *)ab->mem + window_start +
148 #endif
149 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
150 }
151
152 return val;
153 }
154
ath11k_pci_get_msi_irq(struct ath11k_base * ab,unsigned int vector)155 int ath11k_pci_get_msi_irq(struct ath11k_base *ab, unsigned int vector)
156 {
157 struct pci_dev *pci_dev = to_pci_dev(ab->dev);
158
159 return pci_irq_vector(pci_dev, vector);
160 }
161
162 static const struct ath11k_pci_ops ath11k_pci_ops_qca6390 = {
163 .wakeup = ath11k_pci_bus_wake_up,
164 .release = ath11k_pci_bus_release,
165 .get_msi_irq = ath11k_pci_get_msi_irq,
166 .window_write32 = ath11k_pci_window_write32,
167 .window_read32 = ath11k_pci_window_read32,
168 };
169
170 static const struct ath11k_pci_ops ath11k_pci_ops_qcn9074 = {
171 .wakeup = NULL,
172 .release = NULL,
173 .get_msi_irq = ath11k_pci_get_msi_irq,
174 .window_write32 = ath11k_pci_window_write32,
175 .window_read32 = ath11k_pci_window_read32,
176 };
177
178 static const struct ath11k_msi_config msi_config_one_msi = {
179 .total_vectors = 1,
180 .total_users = 4,
181 .users = (struct ath11k_msi_user[]) {
182 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
183 { .name = "CE", .num_vectors = 1, .base_vector = 0 },
184 { .name = "WAKE", .num_vectors = 1, .base_vector = 0 },
185 { .name = "DP", .num_vectors = 1, .base_vector = 0 },
186 },
187 };
188
ath11k_pci_select_static_window(struct ath11k_pci * ab_pci)189 static inline void ath11k_pci_select_static_window(struct ath11k_pci *ab_pci)
190 {
191 u32 umac_window;
192 u32 ce_window;
193 u32 window;
194
195 umac_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET);
196 ce_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE);
197 window = (umac_window << 12) | (ce_window << 6);
198
199 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
200 #if defined(__linux__)
201 ab_pci->ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
202 #elif defined(__FreeBSD__)
203 (char *)ab_pci->ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
204 #endif
205 }
206
ath11k_pci_soc_global_reset(struct ath11k_base * ab)207 static void ath11k_pci_soc_global_reset(struct ath11k_base *ab)
208 {
209 u32 val, delay;
210
211 val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET);
212
213 val |= PCIE_SOC_GLOBAL_RESET_V;
214
215 ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
216
217 /* TODO: exact time to sleep is uncertain */
218 delay = 10;
219 mdelay(delay);
220
221 /* Need to toggle V bit back otherwise stuck in reset status */
222 val &= ~PCIE_SOC_GLOBAL_RESET_V;
223
224 ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
225
226 mdelay(delay);
227
228 val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET);
229 if (val == 0xffffffff)
230 ath11k_warn(ab, "link down error during global reset\n");
231 }
232
ath11k_pci_clear_dbg_registers(struct ath11k_base * ab)233 static void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab)
234 {
235 u32 val;
236
237 /* read cookie */
238 val = ath11k_pcic_read32(ab, PCIE_Q6_COOKIE_ADDR);
239 ath11k_dbg(ab, ATH11K_DBG_PCI, "pcie_q6_cookie_addr 0x%x\n", val);
240
241 val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
242 ath11k_dbg(ab, ATH11K_DBG_PCI, "wlaon_warm_sw_entry 0x%x\n", val);
243
244 /* TODO: exact time to sleep is uncertain */
245 mdelay(10);
246
247 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from
248 * continuing warm path and entering dead loop.
249 */
250 ath11k_pcic_write32(ab, WLAON_WARM_SW_ENTRY, 0);
251 mdelay(10);
252
253 val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
254 ath11k_dbg(ab, ATH11K_DBG_PCI, "wlaon_warm_sw_entry 0x%x\n", val);
255
256 /* A read clear register. clear the register to prevent
257 * Q6 from entering wrong code path.
258 */
259 val = ath11k_pcic_read32(ab, WLAON_SOC_RESET_CAUSE_REG);
260 ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause %d\n", val);
261 }
262
ath11k_pci_set_link_reg(struct ath11k_base * ab,u32 offset,u32 value,u32 mask)263 static int ath11k_pci_set_link_reg(struct ath11k_base *ab,
264 u32 offset, u32 value, u32 mask)
265 {
266 u32 v;
267 int i;
268
269 v = ath11k_pcic_read32(ab, offset);
270 if ((v & mask) == value)
271 return 0;
272
273 for (i = 0; i < 10; i++) {
274 ath11k_pcic_write32(ab, offset, (v & ~mask) | value);
275
276 v = ath11k_pcic_read32(ab, offset);
277 if ((v & mask) == value)
278 return 0;
279
280 mdelay(2);
281 }
282
283 ath11k_warn(ab, "failed to set pcie link register 0x%08x: 0x%08x != 0x%08x\n",
284 offset, v & mask, value);
285
286 return -ETIMEDOUT;
287 }
288
ath11k_pci_fix_l1ss(struct ath11k_base * ab)289 static int ath11k_pci_fix_l1ss(struct ath11k_base *ab)
290 {
291 int ret;
292
293 ret = ath11k_pci_set_link_reg(ab,
294 PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(ab),
295 PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL,
296 PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK);
297 if (ret) {
298 ath11k_warn(ab, "failed to set sysclk: %d\n", ret);
299 return ret;
300 }
301
302 ret = ath11k_pci_set_link_reg(ab,
303 PCIE_PCS_OSC_DTCT_CONFIG1_REG(ab),
304 PCIE_PCS_OSC_DTCT_CONFIG1_VAL,
305 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
306 if (ret) {
307 ath11k_warn(ab, "failed to set dtct config1 error: %d\n", ret);
308 return ret;
309 }
310
311 ret = ath11k_pci_set_link_reg(ab,
312 PCIE_PCS_OSC_DTCT_CONFIG2_REG(ab),
313 PCIE_PCS_OSC_DTCT_CONFIG2_VAL,
314 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
315 if (ret) {
316 ath11k_warn(ab, "failed to set dtct config2: %d\n", ret);
317 return ret;
318 }
319
320 ret = ath11k_pci_set_link_reg(ab,
321 PCIE_PCS_OSC_DTCT_CONFIG4_REG(ab),
322 PCIE_PCS_OSC_DTCT_CONFIG4_VAL,
323 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
324 if (ret) {
325 ath11k_warn(ab, "failed to set dtct config4: %d\n", ret);
326 return ret;
327 }
328
329 return 0;
330 }
331
ath11k_pci_enable_ltssm(struct ath11k_base * ab)332 static void ath11k_pci_enable_ltssm(struct ath11k_base *ab)
333 {
334 u32 val;
335 int i;
336
337 val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM);
338
339 /* PCIE link seems very unstable after the Hot Reset*/
340 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) {
341 if (val == 0xffffffff)
342 mdelay(5);
343
344 ath11k_pcic_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE);
345 val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM);
346 }
347
348 ath11k_dbg(ab, ATH11K_DBG_PCI, "ltssm 0x%x\n", val);
349
350 val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST);
351 val |= GCC_GCC_PCIE_HOT_RST_VAL;
352 ath11k_pcic_write32(ab, GCC_GCC_PCIE_HOT_RST, val);
353 val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST);
354
355 ath11k_dbg(ab, ATH11K_DBG_PCI, "pcie_hot_rst 0x%x\n", val);
356
357 mdelay(5);
358 }
359
ath11k_pci_clear_all_intrs(struct ath11k_base * ab)360 static void ath11k_pci_clear_all_intrs(struct ath11k_base *ab)
361 {
362 /* This is a WAR for PCIE Hotreset.
363 * When target receive Hotreset, but will set the interrupt.
364 * So when download SBL again, SBL will open Interrupt and
365 * receive it, and crash immediately.
366 */
367 ath11k_pcic_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL);
368 }
369
ath11k_pci_set_wlaon_pwr_ctrl(struct ath11k_base * ab)370 static void ath11k_pci_set_wlaon_pwr_ctrl(struct ath11k_base *ab)
371 {
372 u32 val;
373
374 val = ath11k_pcic_read32(ab, WLAON_QFPROM_PWR_CTRL_REG);
375 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK;
376 ath11k_pcic_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val);
377 }
378
ath11k_pci_force_wake(struct ath11k_base * ab)379 static void ath11k_pci_force_wake(struct ath11k_base *ab)
380 {
381 ath11k_pcic_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1);
382 mdelay(5);
383 }
384
ath11k_pci_sw_reset(struct ath11k_base * ab,bool power_on)385 static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on)
386 {
387 mdelay(100);
388
389 if (power_on) {
390 ath11k_pci_enable_ltssm(ab);
391 ath11k_pci_clear_all_intrs(ab);
392 ath11k_pci_set_wlaon_pwr_ctrl(ab);
393 if (ab->hw_params.fix_l1ss)
394 ath11k_pci_fix_l1ss(ab);
395 }
396
397 ath11k_mhi_clear_vector(ab);
398 ath11k_pci_clear_dbg_registers(ab);
399 ath11k_pci_soc_global_reset(ab);
400 ath11k_mhi_set_mhictrl_reset(ab);
401 }
402
ath11k_pci_init_qmi_ce_config(struct ath11k_base * ab)403 static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab)
404 {
405 struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;
406
407 cfg->tgt_ce = ab->hw_params.target_ce_config;
408 cfg->tgt_ce_len = ab->hw_params.target_ce_count;
409
410 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map;
411 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len;
412 ab->qmi.service_ins_id = ab->hw_params.qmi_service_ins_id;
413
414 ath11k_ce_get_shadow_config(ab, &cfg->shadow_reg_v2,
415 &cfg->shadow_reg_v2_len);
416 }
417
ath11k_pci_msi_config(struct ath11k_pci * ab_pci,bool enable)418 static void ath11k_pci_msi_config(struct ath11k_pci *ab_pci, bool enable)
419 {
420 struct pci_dev *dev = ab_pci->pdev;
421 u16 control;
422
423 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
424
425 if (enable)
426 control |= PCI_MSI_FLAGS_ENABLE;
427 else
428 control &= ~PCI_MSI_FLAGS_ENABLE;
429
430 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
431 }
432
ath11k_pci_msi_enable(struct ath11k_pci * ab_pci)433 static void ath11k_pci_msi_enable(struct ath11k_pci *ab_pci)
434 {
435 ath11k_pci_msi_config(ab_pci, true);
436 }
437
ath11k_pci_msi_disable(struct ath11k_pci * ab_pci)438 static void ath11k_pci_msi_disable(struct ath11k_pci *ab_pci)
439 {
440 ath11k_pci_msi_config(ab_pci, false);
441 }
442
ath11k_pci_alloc_msi(struct ath11k_pci * ab_pci)443 static int ath11k_pci_alloc_msi(struct ath11k_pci *ab_pci)
444 {
445 struct ath11k_base *ab = ab_pci->ab;
446 const struct ath11k_msi_config *msi_config = ab->pci.msi.config;
447 struct pci_dev *pci_dev = ab_pci->pdev;
448 struct msi_desc *msi_desc;
449 int num_vectors;
450 int ret;
451
452 num_vectors = pci_alloc_irq_vectors(pci_dev,
453 msi_config->total_vectors,
454 msi_config->total_vectors,
455 PCI_IRQ_MSI);
456 if (num_vectors == msi_config->total_vectors) {
457 set_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags);
458 } else {
459 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev,
460 1,
461 1,
462 PCI_IRQ_MSI);
463 if (num_vectors < 0) {
464 ret = -EINVAL;
465 goto reset_msi_config;
466 }
467 clear_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags);
468 ab->pci.msi.config = &msi_config_one_msi;
469 ath11k_dbg(ab, ATH11K_DBG_PCI, "request one msi vector\n");
470 }
471 ath11k_info(ab, "MSI vectors: %d\n", num_vectors);
472
473 ath11k_pci_msi_disable(ab_pci);
474
475 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
476 if (!msi_desc) {
477 ath11k_err(ab, "msi_desc is NULL!\n");
478 ret = -EINVAL;
479 goto free_msi_vector;
480 }
481
482 ab->pci.msi.ep_base_data = msi_desc->msg.data;
483
484 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO,
485 &ab->pci.msi.addr_lo);
486
487 if (msi_desc->pci.msi_attrib.is_64) {
488 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI,
489 &ab->pci.msi.addr_hi);
490 } else {
491 ab->pci.msi.addr_hi = 0;
492 }
493
494 ath11k_dbg(ab, ATH11K_DBG_PCI, "msi base data is %d\n", ab->pci.msi.ep_base_data);
495
496 return 0;
497
498 free_msi_vector:
499 pci_free_irq_vectors(ab_pci->pdev);
500
501 reset_msi_config:
502 return ret;
503 }
504
ath11k_pci_free_msi(struct ath11k_pci * ab_pci)505 static void ath11k_pci_free_msi(struct ath11k_pci *ab_pci)
506 {
507 pci_free_irq_vectors(ab_pci->pdev);
508 }
509
ath11k_pci_config_msi_data(struct ath11k_pci * ab_pci)510 static int ath11k_pci_config_msi_data(struct ath11k_pci *ab_pci)
511 {
512 struct msi_desc *msi_desc;
513
514 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
515 if (!msi_desc) {
516 ath11k_err(ab_pci->ab, "msi_desc is NULL!\n");
517 pci_free_irq_vectors(ab_pci->pdev);
518 return -EINVAL;
519 }
520
521 ab_pci->ab->pci.msi.ep_base_data = msi_desc->msg.data;
522
523 ath11k_dbg(ab_pci->ab, ATH11K_DBG_PCI, "after request_irq msi_ep_base_data %d\n",
524 ab_pci->ab->pci.msi.ep_base_data);
525
526 return 0;
527 }
528
ath11k_pci_claim(struct ath11k_pci * ab_pci,struct pci_dev * pdev)529 static int ath11k_pci_claim(struct ath11k_pci *ab_pci, struct pci_dev *pdev)
530 {
531 struct ath11k_base *ab = ab_pci->ab;
532 u16 device_id;
533 int ret = 0;
534
535 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
536 if (device_id != ab_pci->dev_id) {
537 ath11k_err(ab, "pci device id mismatch: 0x%x 0x%x\n",
538 device_id, ab_pci->dev_id);
539 ret = -EIO;
540 goto out;
541 }
542
543 ret = pci_assign_resource(pdev, ATH11K_PCI_BAR_NUM);
544 if (ret) {
545 ath11k_err(ab, "failed to assign pci resource: %d\n", ret);
546 goto out;
547 }
548
549 ret = pci_enable_device(pdev);
550 if (ret) {
551 ath11k_err(ab, "failed to enable pci device: %d\n", ret);
552 goto out;
553 }
554
555 ret = pci_request_region(pdev, ATH11K_PCI_BAR_NUM, "ath11k_pci");
556 if (ret) {
557 ath11k_err(ab, "failed to request pci region: %d\n", ret);
558 goto disable_device;
559 }
560
561 ret = dma_set_mask_and_coherent(&pdev->dev,
562 DMA_BIT_MASK(ATH11K_PCI_DMA_MASK));
563 if (ret) {
564 ath11k_err(ab, "failed to set pci dma mask to %d: %d\n",
565 ATH11K_PCI_DMA_MASK, ret);
566 goto release_region;
567 }
568
569 pci_set_master(pdev);
570
571 ab->mem_len = pci_resource_len(pdev, ATH11K_PCI_BAR_NUM);
572 ab->mem = pci_iomap(pdev, ATH11K_PCI_BAR_NUM, 0);
573 if (!ab->mem) {
574 ath11k_err(ab, "failed to map pci bar %d\n", ATH11K_PCI_BAR_NUM);
575 ret = -EIO;
576 goto release_region;
577 }
578
579 ab->mem_ce = ab->mem;
580
581 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pci_mem 0x%p\n", ab->mem);
582 return 0;
583
584 release_region:
585 pci_release_region(pdev, ATH11K_PCI_BAR_NUM);
586 disable_device:
587 pci_disable_device(pdev);
588 out:
589 return ret;
590 }
591
ath11k_pci_free_region(struct ath11k_pci * ab_pci)592 static void ath11k_pci_free_region(struct ath11k_pci *ab_pci)
593 {
594 struct ath11k_base *ab = ab_pci->ab;
595 struct pci_dev *pci_dev = ab_pci->pdev;
596
597 pci_iounmap(pci_dev, ab->mem);
598 ab->mem = NULL;
599 pci_release_region(pci_dev, ATH11K_PCI_BAR_NUM);
600 if (pci_is_enabled(pci_dev))
601 pci_disable_device(pci_dev);
602 }
603
ath11k_pci_aspm_disable(struct ath11k_pci * ab_pci)604 static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci)
605 {
606 struct ath11k_base *ab = ab_pci->ab;
607
608 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL,
609 &ab_pci->link_ctl);
610
611 ath11k_dbg(ab, ATH11K_DBG_PCI, "link_ctl 0x%04x L0s %d L1 %d\n",
612 ab_pci->link_ctl,
613 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S),
614 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1));
615
616 /* disable L0s and L1 */
617 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
618 ab_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC);
619
620 set_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags);
621 }
622
ath11k_pci_aspm_restore(struct ath11k_pci * ab_pci)623 static void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci)
624 {
625 if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags))
626 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
627 ab_pci->link_ctl);
628 }
629
ath11k_pci_power_up(struct ath11k_base * ab)630 static int ath11k_pci_power_up(struct ath11k_base *ab)
631 {
632 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
633 int ret;
634
635 ab_pci->register_window = 0;
636 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);
637 ath11k_pci_sw_reset(ab_pci->ab, true);
638
639 /* Disable ASPM during firmware download due to problems switching
640 * to AMSS state.
641 */
642 ath11k_pci_aspm_disable(ab_pci);
643
644 ath11k_pci_msi_enable(ab_pci);
645
646 ret = ath11k_mhi_start(ab_pci);
647 if (ret) {
648 ath11k_err(ab, "failed to start mhi: %d\n", ret);
649 return ret;
650 }
651
652 if (ab->hw_params.static_window_map)
653 ath11k_pci_select_static_window(ab_pci);
654
655 return 0;
656 }
657
ath11k_pci_power_down(struct ath11k_base * ab)658 static void ath11k_pci_power_down(struct ath11k_base *ab)
659 {
660 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
661
662 /* restore aspm in case firmware bootup fails */
663 ath11k_pci_aspm_restore(ab_pci);
664
665 ath11k_pci_force_wake(ab_pci->ab);
666
667 ath11k_pci_msi_disable(ab_pci);
668
669 ath11k_mhi_stop(ab_pci);
670 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);
671 ath11k_pci_sw_reset(ab_pci->ab, false);
672 }
673
ath11k_pci_hif_suspend(struct ath11k_base * ab)674 static int ath11k_pci_hif_suspend(struct ath11k_base *ab)
675 {
676 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab);
677
678 return ath11k_mhi_suspend(ar_pci);
679 }
680
ath11k_pci_hif_resume(struct ath11k_base * ab)681 static int ath11k_pci_hif_resume(struct ath11k_base *ab)
682 {
683 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab);
684
685 return ath11k_mhi_resume(ar_pci);
686 }
687
ath11k_pci_hif_ce_irq_enable(struct ath11k_base * ab)688 static void ath11k_pci_hif_ce_irq_enable(struct ath11k_base *ab)
689 {
690 ath11k_pcic_ce_irqs_enable(ab);
691 }
692
ath11k_pci_hif_ce_irq_disable(struct ath11k_base * ab)693 static void ath11k_pci_hif_ce_irq_disable(struct ath11k_base *ab)
694 {
695 ath11k_pcic_ce_irq_disable_sync(ab);
696 }
697
ath11k_pci_start(struct ath11k_base * ab)698 static int ath11k_pci_start(struct ath11k_base *ab)
699 {
700 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
701
702 /* TODO: for now don't restore ASPM in case of single MSI
703 * vector as MHI register reading in M2 causes system hang.
704 */
705 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
706 ath11k_pci_aspm_restore(ab_pci);
707 else
708 ath11k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n");
709
710 ath11k_pcic_start(ab);
711
712 return 0;
713 }
714
715 static const struct ath11k_hif_ops ath11k_pci_hif_ops = {
716 .start = ath11k_pci_start,
717 .stop = ath11k_pcic_stop,
718 .read32 = ath11k_pcic_read32,
719 .write32 = ath11k_pcic_write32,
720 .read = ath11k_pcic_read,
721 .power_down = ath11k_pci_power_down,
722 .power_up = ath11k_pci_power_up,
723 .suspend = ath11k_pci_hif_suspend,
724 .resume = ath11k_pci_hif_resume,
725 .irq_enable = ath11k_pcic_ext_irq_enable,
726 .irq_disable = ath11k_pcic_ext_irq_disable,
727 .get_msi_address = ath11k_pcic_get_msi_address,
728 .get_user_msi_vector = ath11k_pcic_get_user_msi_assignment,
729 .map_service_to_pipe = ath11k_pcic_map_service_to_pipe,
730 .ce_irq_enable = ath11k_pci_hif_ce_irq_enable,
731 .ce_irq_disable = ath11k_pci_hif_ce_irq_disable,
732 .get_ce_msi_idx = ath11k_pcic_get_ce_msi_idx,
733 };
734
ath11k_pci_read_hw_version(struct ath11k_base * ab,u32 * major,u32 * minor)735 static void ath11k_pci_read_hw_version(struct ath11k_base *ab, u32 *major, u32 *minor)
736 {
737 u32 soc_hw_version;
738
739 soc_hw_version = ath11k_pcic_read32(ab, TCSR_SOC_HW_VERSION);
740 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK,
741 soc_hw_version);
742 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK,
743 soc_hw_version);
744
745 ath11k_dbg(ab, ATH11K_DBG_PCI, "tcsr_soc_hw_version major %d minor %d\n",
746 *major, *minor);
747 }
748
ath11k_pci_set_irq_affinity_hint(struct ath11k_pci * ab_pci,const struct cpumask * m)749 static int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
750 #if defined(__linux__)
751 const struct cpumask *m)
752 #elif defined(__FreeBSD__)
753 const cpumask_t *m)
754 #endif
755 {
756 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab_pci->ab->dev_flags))
757 return 0;
758
759 return irq_set_affinity_hint(ab_pci->pdev->irq, m);
760 }
761
ath11k_pci_probe(struct pci_dev * pdev,const struct pci_device_id * pci_dev)762 static int ath11k_pci_probe(struct pci_dev *pdev,
763 const struct pci_device_id *pci_dev)
764 {
765 struct ath11k_base *ab;
766 struct ath11k_pci *ab_pci;
767 #if defined(__linux__)
768 u32 soc_hw_version_major, soc_hw_version_minor, addr;
769 #elif defined(__FreeBSD__)
770 u32 soc_hw_version_major, soc_hw_version_minor;
771 #endif
772 const struct ath11k_pci_ops *pci_ops;
773 int ret;
774
775 ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI);
776
777 if (!ab) {
778 dev_err(&pdev->dev, "failed to allocate ath11k base\n");
779 return -ENOMEM;
780 }
781
782 ab->dev = &pdev->dev;
783 pci_set_drvdata(pdev, ab);
784 ab_pci = ath11k_pci_priv(ab);
785 ab_pci->dev_id = pci_dev->device;
786 ab_pci->ab = ab;
787 ab_pci->pdev = pdev;
788 ab->hif.ops = &ath11k_pci_hif_ops;
789 ab->fw_mode = ATH11K_FIRMWARE_MODE_NORMAL;
790 pci_set_drvdata(pdev, ab);
791 spin_lock_init(&ab_pci->window_lock);
792
793 /* Set fixed_mem_region to true for platforms support reserved memory
794 * from DT. If memory is reserved from DT for FW, ath11k driver need not
795 * allocate memory.
796 */
797 #if defined(__linux__)
798 ret = of_property_read_u32(ab->dev->of_node, "memory-region", &addr);
799 if (!ret)
800 set_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags);
801 #endif
802
803 ret = ath11k_pci_claim(ab_pci, pdev);
804 if (ret) {
805 ath11k_err(ab, "failed to claim device: %d\n", ret);
806 goto err_free_core;
807 }
808
809 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n",
810 pdev->vendor, pdev->device,
811 pdev->subsystem_vendor, pdev->subsystem_device);
812
813 ab->id.vendor = pdev->vendor;
814 ab->id.device = pdev->device;
815 ab->id.subsystem_vendor = pdev->subsystem_vendor;
816 ab->id.subsystem_device = pdev->subsystem_device;
817
818 switch (pci_dev->device) {
819 case QCA6390_DEVICE_ID:
820 ath11k_pci_read_hw_version(ab, &soc_hw_version_major,
821 &soc_hw_version_minor);
822 switch (soc_hw_version_major) {
823 case 2:
824 ab->hw_rev = ATH11K_HW_QCA6390_HW20;
825 break;
826 default:
827 dev_err(&pdev->dev, "Unsupported QCA6390 SOC hardware version: %d %d\n",
828 soc_hw_version_major, soc_hw_version_minor);
829 ret = -EOPNOTSUPP;
830 goto err_pci_free_region;
831 }
832
833 pci_ops = &ath11k_pci_ops_qca6390;
834 break;
835 case QCN9074_DEVICE_ID:
836 pci_ops = &ath11k_pci_ops_qcn9074;
837 ab->hw_rev = ATH11K_HW_QCN9074_HW10;
838 break;
839 case WCN6855_DEVICE_ID:
840 ab->id.bdf_search = ATH11K_BDF_SEARCH_BUS_AND_BOARD;
841 ath11k_pci_read_hw_version(ab, &soc_hw_version_major,
842 &soc_hw_version_minor);
843 switch (soc_hw_version_major) {
844 case 2:
845 switch (soc_hw_version_minor) {
846 case 0x00:
847 case 0x01:
848 ab->hw_rev = ATH11K_HW_WCN6855_HW20;
849 break;
850 case 0x10:
851 case 0x11:
852 ab->hw_rev = ATH11K_HW_WCN6855_HW21;
853 break;
854 default:
855 goto unsupported_wcn6855_soc;
856 }
857 break;
858 default:
859 unsupported_wcn6855_soc:
860 dev_err(&pdev->dev, "Unsupported WCN6855 SOC hardware version: %d %d\n",
861 soc_hw_version_major, soc_hw_version_minor);
862 ret = -EOPNOTSUPP;
863 goto err_pci_free_region;
864 }
865
866 pci_ops = &ath11k_pci_ops_qca6390;
867 break;
868 default:
869 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n",
870 pci_dev->device);
871 ret = -EOPNOTSUPP;
872 goto err_pci_free_region;
873 }
874
875 ret = ath11k_pcic_register_pci_ops(ab, pci_ops);
876 if (ret) {
877 ath11k_err(ab, "failed to register PCI ops: %d\n", ret);
878 goto err_pci_free_region;
879 }
880
881 ret = ath11k_pcic_init_msi_config(ab);
882 if (ret) {
883 ath11k_err(ab, "failed to init msi config: %d\n", ret);
884 goto err_pci_free_region;
885 }
886
887 ret = ath11k_pci_alloc_msi(ab_pci);
888 if (ret) {
889 ath11k_err(ab, "failed to enable msi: %d\n", ret);
890 goto err_pci_free_region;
891 }
892
893 ret = ath11k_core_pre_init(ab);
894 if (ret)
895 goto err_pci_disable_msi;
896
897 ret = ath11k_mhi_register(ab_pci);
898 if (ret) {
899 ath11k_err(ab, "failed to register mhi: %d\n", ret);
900 goto err_pci_disable_msi;
901 }
902
903 ret = ath11k_hal_srng_init(ab);
904 if (ret)
905 goto err_mhi_unregister;
906
907 ret = ath11k_ce_alloc_pipes(ab);
908 if (ret) {
909 ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret);
910 goto err_hal_srng_deinit;
911 }
912
913 ath11k_pci_init_qmi_ce_config(ab);
914
915 ret = ath11k_pcic_config_irq(ab);
916 if (ret) {
917 ath11k_err(ab, "failed to config irq: %d\n", ret);
918 goto err_ce_free;
919 }
920
921 ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0));
922 if (ret) {
923 ath11k_err(ab, "failed to set irq affinity %d\n", ret);
924 goto err_free_irq;
925 }
926
927 /* kernel may allocate a dummy vector before request_irq and
928 * then allocate a real vector when request_irq is called.
929 * So get msi_data here again to avoid spurious interrupt
930 * as msi_data will configured to srngs.
931 */
932 ret = ath11k_pci_config_msi_data(ab_pci);
933 if (ret) {
934 ath11k_err(ab, "failed to config msi_data: %d\n", ret);
935 goto err_irq_affinity_cleanup;
936 }
937
938 ret = ath11k_core_init(ab);
939 if (ret) {
940 ath11k_err(ab, "failed to init core: %d\n", ret);
941 goto err_irq_affinity_cleanup;
942 }
943 ath11k_qmi_fwreset_from_cold_boot(ab);
944 return 0;
945
946 err_irq_affinity_cleanup:
947 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
948
949 err_free_irq:
950 ath11k_pcic_free_irq(ab);
951
952 err_ce_free:
953 ath11k_ce_free_pipes(ab);
954
955 err_hal_srng_deinit:
956 ath11k_hal_srng_deinit(ab);
957
958 err_mhi_unregister:
959 ath11k_mhi_unregister(ab_pci);
960
961 err_pci_disable_msi:
962 ath11k_pci_free_msi(ab_pci);
963
964 err_pci_free_region:
965 ath11k_pci_free_region(ab_pci);
966
967 err_free_core:
968 ath11k_core_free(ab);
969
970 return ret;
971 }
972
ath11k_pci_remove(struct pci_dev * pdev)973 static void ath11k_pci_remove(struct pci_dev *pdev)
974 {
975 struct ath11k_base *ab = pci_get_drvdata(pdev);
976 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
977
978 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
979
980 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
981 ath11k_pci_power_down(ab);
982 ath11k_debugfs_soc_destroy(ab);
983 ath11k_qmi_deinit_service(ab);
984 goto qmi_fail;
985 }
986
987 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags);
988
989 ath11k_core_deinit(ab);
990
991 qmi_fail:
992 ath11k_mhi_unregister(ab_pci);
993
994 ath11k_pcic_free_irq(ab);
995 ath11k_pci_free_msi(ab_pci);
996 ath11k_pci_free_region(ab_pci);
997
998 ath11k_hal_srng_deinit(ab);
999 ath11k_ce_free_pipes(ab);
1000 ath11k_core_free(ab);
1001 }
1002
ath11k_pci_shutdown(struct pci_dev * pdev)1003 static void ath11k_pci_shutdown(struct pci_dev *pdev)
1004 {
1005 struct ath11k_base *ab = pci_get_drvdata(pdev);
1006 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
1007
1008 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
1009 ath11k_pci_power_down(ab);
1010 }
1011
1012 #ifdef CONFIG_PM
ath11k_pci_pm_suspend(struct device * dev)1013 static __maybe_unused int ath11k_pci_pm_suspend(struct device *dev)
1014 {
1015 struct ath11k_base *ab = dev_get_drvdata(dev);
1016 int ret;
1017
1018 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
1019 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci suspend as qmi is not initialised\n");
1020 return 0;
1021 }
1022
1023 ret = ath11k_core_suspend(ab);
1024 if (ret)
1025 ath11k_warn(ab, "failed to suspend core: %d\n", ret);
1026
1027 return 0;
1028 }
1029
ath11k_pci_pm_resume(struct device * dev)1030 static __maybe_unused int ath11k_pci_pm_resume(struct device *dev)
1031 {
1032 struct ath11k_base *ab = dev_get_drvdata(dev);
1033 int ret;
1034
1035 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
1036 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci resume as qmi is not initialised\n");
1037 return 0;
1038 }
1039
1040 ret = ath11k_core_resume(ab);
1041 if (ret)
1042 ath11k_warn(ab, "failed to resume core: %d\n", ret);
1043
1044 return ret;
1045 }
1046
1047 static SIMPLE_DEV_PM_OPS(ath11k_pci_pm_ops,
1048 ath11k_pci_pm_suspend,
1049 ath11k_pci_pm_resume);
1050 #endif
1051
1052 static struct pci_driver ath11k_pci_driver = {
1053 .name = "ath11k_pci",
1054 .id_table = ath11k_pci_id_table,
1055 .probe = ath11k_pci_probe,
1056 .remove = ath11k_pci_remove,
1057 .shutdown = ath11k_pci_shutdown,
1058 #ifdef CONFIG_PM
1059 .driver.pm = &ath11k_pci_pm_ops,
1060 #endif
1061 };
1062
ath11k_pci_init(void)1063 static int ath11k_pci_init(void)
1064 {
1065 int ret;
1066
1067 ret = pci_register_driver(&ath11k_pci_driver);
1068 if (ret)
1069 pr_err("failed to register ath11k pci driver: %d\n",
1070 ret);
1071
1072 return ret;
1073 }
1074 module_init(ath11k_pci_init);
1075
ath11k_pci_exit(void)1076 static void ath11k_pci_exit(void)
1077 {
1078 pci_unregister_driver(&ath11k_pci_driver);
1079 }
1080
1081 module_exit(ath11k_pci_exit);
1082
1083 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN PCIe devices");
1084 MODULE_LICENSE("Dual BSD/GPL");
1085 #if defined(__FreeBSD__)
1086 MODULE_VERSION(ath11k_pci, 1);
1087 MODULE_DEPEND(ath11k_pci, linuxkpi, 1, 1, 1);
1088 MODULE_DEPEND(ath11k_pci, linuxkpi_wlan, 1, 1, 1);
1089 MODULE_DEPEND(ath11k_pci, athk_common, 1, 1, 1);
1090 #ifdef CONFIG_ATH11K_DEBUGFS
1091 MODULE_DEPEND(ath11k_pci, debugfs, 1, 1, 1);
1092 #endif
1093 #endif
1094
1095 /* firmware files */
1096 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/*");
1097 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCN9074/hw1.0/*");
1098 MODULE_FIRMWARE(ATH11K_FW_DIR "/WCN6855/hw2.0/*");
1099 MODULE_FIRMWARE(ATH11K_FW_DIR "/WCN6855/hw2.1/*");
1100