1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares the ARM specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H 14 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H 15 16 #include "ARMBaseInstrInfo.h" 17 #include "ARMBaseRegisterInfo.h" 18 #include "ARMConstantPoolValue.h" 19 #include "ARMFrameLowering.h" 20 #include "ARMISelLowering.h" 21 #include "ARMMachineFunctionInfo.h" 22 #include "ARMSelectionDAGInfo.h" 23 #include "llvm/Analysis/TargetTransformInfo.h" 24 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 25 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 26 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 27 #include "llvm/CodeGen/MachineFunction.h" 28 #include "llvm/CodeGen/RegisterBankInfo.h" 29 #include "llvm/CodeGen/TargetSubtargetInfo.h" 30 #include "llvm/MC/MCInstrItineraries.h" 31 #include "llvm/MC/MCSchedule.h" 32 #include "llvm/Target/TargetMachine.h" 33 #include "llvm/Target/TargetOptions.h" 34 #include "llvm/TargetParser/Triple.h" 35 #include <bitset> 36 #include <memory> 37 #include <string> 38 39 #define GET_SUBTARGETINFO_HEADER 40 #include "ARMGenSubtargetInfo.inc" 41 42 namespace llvm { 43 44 class ARMBaseTargetMachine; 45 class GlobalValue; 46 class StringRef; 47 48 class ARMSubtarget : public ARMGenSubtargetInfo { 49 protected: 50 enum ARMProcFamilyEnum { 51 Others, 52 #define ARM_PROCESSOR_FAMILY(ENUM) ENUM, 53 #include "llvm/TargetParser/ARMTargetParserDef.inc" 54 #undef ARM_PROCESSOR_FAMILY 55 }; 56 enum ARMProcClassEnum { 57 None, 58 59 AClass, 60 MClass, 61 RClass 62 }; 63 enum ARMArchEnum { 64 #define ARM_ARCHITECTURE(ENUM) ENUM, 65 #include "llvm/TargetParser/ARMTargetParserDef.inc" 66 #undef ARM_ARCHITECTURE 67 }; 68 69 public: 70 /// What kind of timing do load multiple/store multiple instructions have. 71 enum ARMLdStMultipleTiming { 72 /// Can load/store 2 registers/cycle. 73 DoubleIssue, 74 /// Can load/store 2 registers/cycle, but needs an extra cycle if the access 75 /// is not 64-bit aligned. 76 DoubleIssueCheckUnalignedAccess, 77 /// Can load/store 1 register/cycle. 78 SingleIssue, 79 /// Can load/store 1 register/cycle, but needs an extra cycle for address 80 /// computation and potentially also for register writeback. 81 SingleIssuePlusExtras, 82 }; 83 84 /// How the push and pop instructions of callee saved general-purpose 85 /// registers should be split. 86 enum PushPopSplitVariation { 87 /// All GPRs can be pushed in a single instruction. 88 /// push {r0-r12, lr} 89 /// vpush {d8-d15} 90 NoSplit, 91 92 /// R7 and LR must be adjacent, because R7 is the frame pointer, and must 93 /// point to a frame record consisting of the previous frame pointer and the 94 /// return address. 95 /// push {r0-r7, lr} 96 /// push {r8-r12} 97 /// vpush {d8-d15} 98 /// Note that Thumb1 changes this layout when the frame pointer is R11, 99 /// using a longer sequence of instructions because R11 can't be used by a 100 /// Thumb1 push instruction. This doesn't currently have a separate enum 101 /// value, and is handled entriely within Thumb1FrameLowering::emitPrologue. 102 SplitR7, 103 104 /// When the stack frame size is not known (because of variable-sized 105 /// objects or realignment), Windows SEH requires the callee-saved registers 106 /// to be stored in three regions, with R11 and LR below the floating-point 107 /// registers. 108 /// push {r0-r10, r12} 109 /// vpush {d8-d15} 110 /// push {r11, lr} 111 SplitR11WindowsSEH, 112 113 /// When generating AAPCS-compilant frame chains, R11 is the frame pointer, 114 /// and must be pushed adjacent to the return address (LR). Normally this 115 /// isn't a problem, because the only register between them is r12, which is 116 /// the intra-procedure-call scratch register, so doesn't need to be saved. 117 /// However, when PACBTI is in use, r12 contains the authentication code, so 118 /// does need to be saved. This means that we need a separate push for R11 119 /// and LR. 120 /// push {r0-r10, r12} 121 /// push {r11, lr} 122 /// vpush {d8-d15} 123 SplitR11AAPCSSignRA, 124 }; 125 126 protected: 127 // Bool members corresponding to the SubtargetFeatures defined in tablegen 128 #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \ 129 bool ATTRIBUTE = DEFAULT; 130 #include "ARMGenSubtargetInfo.inc" 131 132 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others. 133 ARMProcFamilyEnum ARMProcFamily = Others; 134 135 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass. 136 ARMProcClassEnum ARMProcClass = None; 137 138 /// ARMArch - ARM architecture 139 ARMArchEnum ARMArch = ARMv4t; 140 141 /// UseMulOps - True if non-microcoded fused integer multiply-add and 142 /// multiply-subtract instructions should be used. 143 bool UseMulOps = false; 144 145 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker 146 /// must be able to synthesize call stubs for interworking between ARM and 147 /// Thumb. 148 bool SupportsTailCall = false; 149 150 /// RestrictIT - If true, the subtarget disallows generation of complex IT 151 /// blocks. 152 bool RestrictIT = false; 153 154 /// stackAlignment - The minimum alignment known to hold of the stack frame on 155 /// entry to the function and which must be maintained by every function. 156 Align stackAlignment = Align(4); 157 158 /// CPUString - String name of used CPU. 159 std::string CPUString; 160 161 unsigned MaxInterleaveFactor = 1; 162 163 /// Clearance before partial register updates (in number of instructions) 164 unsigned PartialUpdateClearance = 0; 165 166 /// What kind of timing do load multiple/store multiple have (double issue, 167 /// single issue etc). 168 ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue; 169 170 /// The adjustment that we need to apply to get the operand latency from the 171 /// operand cycle returned by the itinerary data for pre-ISel operands. 172 int PreISelOperandLatencyAdjustment = 2; 173 174 /// What alignment is preferred for loop bodies and functions, in log2(bytes). 175 unsigned PreferBranchLogAlignment = 0; 176 177 /// The cost factor for MVE instructions, representing the multiple beats an 178 // instruction can take. The default is 2, (set in initSubtargetFeatures so 179 // that we can use subtarget features less than 2). 180 unsigned MVEVectorCostFactor = 0; 181 182 /// OptMinSize - True if we're optimising for minimum code size, equal to 183 /// the function attribute. 184 bool OptMinSize = false; 185 186 /// IsLittle - The target is Little Endian 187 bool IsLittle; 188 189 /// TargetTriple - What processor and OS we're targeting. 190 Triple TargetTriple; 191 192 /// SchedModel - Processor specific instruction costs. 193 MCSchedModel SchedModel; 194 195 /// Selected instruction itineraries (one entry per itinerary class.) 196 InstrItineraryData InstrItins; 197 198 /// Options passed via command line that could influence the target 199 const TargetOptions &Options; 200 201 const ARMBaseTargetMachine &TM; 202 203 public: 204 /// This constructor initializes the data members to match that 205 /// of the specified triple. 206 /// 207 ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, 208 const ARMBaseTargetMachine &TM, bool IsLittle, 209 bool MinSize = false); 210 211 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size 212 /// that still makes it profitable to inline the call. getMaxInlineSizeThreshold()213 unsigned getMaxInlineSizeThreshold() const { 214 return 64; 215 } 216 217 /// getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size 218 /// that still makes it profitable to inline a llvm.memcpy as a Tail 219 /// Predicated loop. 220 /// This threshold should only be used for constant size inputs. getMaxMemcpyTPInlineSizeThreshold()221 unsigned getMaxMemcpyTPInlineSizeThreshold() const { return 128; } 222 223 /// ParseSubtargetFeatures - Parses features string setting specified 224 /// subtarget options. Definition of function is auto generated by tblgen. 225 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); 226 227 /// initializeSubtargetDependencies - Initializes using a CPU and feature string 228 /// so that we can use initializer lists for subtarget initialization. 229 ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); 230 getSelectionDAGInfo()231 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override { 232 return &TSInfo; 233 } 234 getInstrInfo()235 const ARMBaseInstrInfo *getInstrInfo() const override { 236 return InstrInfo.get(); 237 } 238 getTargetLowering()239 const ARMTargetLowering *getTargetLowering() const override { 240 return &TLInfo; 241 } 242 getFrameLowering()243 const ARMFrameLowering *getFrameLowering() const override { 244 return FrameLowering.get(); 245 } 246 getRegisterInfo()247 const ARMBaseRegisterInfo *getRegisterInfo() const override { 248 return &InstrInfo->getRegisterInfo(); 249 } 250 251 const CallLowering *getCallLowering() const override; 252 InstructionSelector *getInstructionSelector() const override; 253 const LegalizerInfo *getLegalizerInfo() const override; 254 const RegisterBankInfo *getRegBankInfo() const override; 255 256 private: 257 ARMSelectionDAGInfo TSInfo; 258 // Either Thumb1FrameLowering or ARMFrameLowering. 259 std::unique_ptr<ARMFrameLowering> FrameLowering; 260 // Either Thumb1InstrInfo or Thumb2InstrInfo. 261 std::unique_ptr<ARMBaseInstrInfo> InstrInfo; 262 ARMTargetLowering TLInfo; 263 264 /// GlobalISel related APIs. 265 std::unique_ptr<CallLowering> CallLoweringInfo; 266 std::unique_ptr<InstructionSelector> InstSelector; 267 std::unique_ptr<LegalizerInfo> Legalizer; 268 std::unique_ptr<RegisterBankInfo> RegBankInfo; 269 270 void initSubtargetFeatures(StringRef CPU, StringRef FS); 271 ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS); 272 273 std::bitset<8> CoprocCDE = {}; 274 public: 275 // Getters for SubtargetFeatures defined in tablegen 276 #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \ 277 bool GETTER() const { return ATTRIBUTE; } 278 #include "ARMGenSubtargetInfo.inc" 279 280 /// @{ 281 /// These functions are obsolete, please consider adding subtarget features 282 /// or properties instead of calling them. isCortexA5()283 bool isCortexA5() const { return ARMProcFamily == CortexA5; } isCortexA7()284 bool isCortexA7() const { return ARMProcFamily == CortexA7; } isCortexA8()285 bool isCortexA8() const { return ARMProcFamily == CortexA8; } isCortexA9()286 bool isCortexA9() const { return ARMProcFamily == CortexA9; } isCortexA15()287 bool isCortexA15() const { return ARMProcFamily == CortexA15; } isSwift()288 bool isSwift() const { return ARMProcFamily == Swift; } isCortexM3()289 bool isCortexM3() const { return ARMProcFamily == CortexM3; } isCortexM55()290 bool isCortexM55() const { return ARMProcFamily == CortexM55; } isCortexM7()291 bool isCortexM7() const { return ARMProcFamily == CortexM7; } isCortexM85()292 bool isCortexM85() const { return ARMProcFamily == CortexM85; } isLikeA9()293 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); } isCortexR5()294 bool isCortexR5() const { return ARMProcFamily == CortexR5; } isKrait()295 bool isKrait() const { return ARMProcFamily == Krait; } 296 /// @} 297 hasARMOps()298 bool hasARMOps() const { return !NoARM; } 299 useNEONForSinglePrecisionFP()300 bool useNEONForSinglePrecisionFP() const { 301 return hasNEON() && hasNEONForFP(); 302 } 303 hasVFP2Base()304 bool hasVFP2Base() const { return hasVFPv2SP(); } hasVFP3Base()305 bool hasVFP3Base() const { return hasVFPv3D16SP(); } hasVFP4Base()306 bool hasVFP4Base() const { return hasVFPv4D16SP(); } hasFPARMv8Base()307 bool hasFPARMv8Base() const { return hasFPARMv8D16SP(); } 308 hasAnyDataBarrier()309 bool hasAnyDataBarrier() const { 310 return HasDataBarrier || (hasV6Ops() && !isThumb()); 311 } 312 useMulOps()313 bool useMulOps() const { return UseMulOps; } useFPVMLx()314 bool useFPVMLx() const { return !SlowFPVMLx; } useFPVFMx()315 bool useFPVFMx() const { 316 return !isTargetDarwin() && hasVFP4Base() && !SlowFPVFMx; 317 } useFPVFMx16()318 bool useFPVFMx16() const { return useFPVFMx() && hasFullFP16(); } useFPVFMx64()319 bool useFPVFMx64() const { return useFPVFMx() && hasFP64(); } hasBaseDSP()320 bool hasBaseDSP() const { 321 if (isThumb()) 322 return hasThumb2() && hasDSP(); 323 else 324 return hasV5TEOps(); 325 } 326 327 /// Return true if the CPU supports any kind of instruction fusion. hasFusion()328 bool hasFusion() const { return hasFuseAES() || hasFuseLiterals(); } 329 getTargetTriple()330 const Triple &getTargetTriple() const { return TargetTriple; } 331 332 /// @{ 333 /// These properties are per-module, please use the TargetMachine 334 /// TargetTriple. isTargetDarwin()335 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } isTargetIOS()336 bool isTargetIOS() const { return TargetTriple.isiOS(); } isTargetWatchOS()337 bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); } isTargetWatchABI()338 bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); } isTargetDriverKit()339 bool isTargetDriverKit() const { return TargetTriple.isDriverKit(); } isTargetLinux()340 bool isTargetLinux() const { return TargetTriple.isOSLinux(); } isTargetNaCl()341 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } isTargetNetBSD()342 bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); } isTargetWindows()343 bool isTargetWindows() const { return TargetTriple.isOSWindows(); } 344 isTargetCOFF()345 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); } isTargetELF()346 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } isTargetMachO()347 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); } 348 isTargetAEABI()349 bool isTargetAEABI() const { return TargetTriple.isTargetAEABI(); } 350 isTargetGNUAEABI()351 bool isTargetGNUAEABI() const { return TargetTriple.isTargetGNUAEABI(); } 352 isTargetMuslAEABI()353 bool isTargetMuslAEABI() const { return TargetTriple.isTargetMuslAEABI(); } 354 355 // ARM Targets that support EHABI exception handling standard 356 // Darwin uses SjLj. Other targets might need more checks. isTargetEHABICompatible()357 bool isTargetEHABICompatible() const { 358 return TargetTriple.isTargetEHABICompatible(); 359 } 360 /// @} 361 isReadTPSoft()362 bool isReadTPSoft() const { 363 return !(isReadTPTPIDRURW() || isReadTPTPIDRURO() || isReadTPTPIDRPRW()); 364 } 365 isTargetAndroid()366 bool isTargetAndroid() const { return TargetTriple.isAndroid(); } 367 368 bool isXRaySupported() const override; 369 370 bool isROPI() const; 371 bool isRWPI() const; 372 useMachineScheduler()373 bool useMachineScheduler() const { return UseMISched; } useMachinePipeliner()374 bool useMachinePipeliner() const { return UseMIPipeliner; } hasMinSize()375 bool hasMinSize() const { return OptMinSize; } isThumb1Only()376 bool isThumb1Only() const { return isThumb() && !hasThumb2(); } isThumb2()377 bool isThumb2() const { return isThumb() && hasThumb2(); } isMClass()378 bool isMClass() const { return ARMProcClass == MClass; } isRClass()379 bool isRClass() const { return ARMProcClass == RClass; } isAClass()380 bool isAClass() const { return ARMProcClass == AClass; } 381 isR9Reserved()382 bool isR9Reserved() const { 383 return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9; 384 } 385 getFramePointerReg()386 MCPhysReg getFramePointerReg() const { 387 if (isTargetDarwin() || 388 (!isTargetWindows() && isThumb() && !createAAPCSFrameChain())) 389 return ARM::R7; 390 return ARM::R11; 391 } 392 393 enum PushPopSplitVariation 394 getPushPopSplitVariation(const MachineFunction &MF) const; 395 396 bool useStride4VFPs() const; 397 398 bool useMovt() const; 399 supportsTailCall()400 bool supportsTailCall() const { return SupportsTailCall; } 401 allowsUnalignedMem()402 bool allowsUnalignedMem() const { return !StrictAlign; } 403 restrictIT()404 bool restrictIT() const { return RestrictIT; } 405 getCPUString()406 const std::string & getCPUString() const { return CPUString; } 407 isLittle()408 bool isLittle() const { return IsLittle; } 409 410 unsigned getMispredictionPenalty() const; 411 412 /// Returns true if machine scheduler should be enabled. 413 bool enableMachineScheduler() const override; 414 415 /// Returns true if machine pipeliner should be enabled. 416 bool enableMachinePipeliner() const override; 417 bool useDFAforSMS() const override; 418 419 /// True for some subtargets at > -O0. 420 bool enablePostRAScheduler() const override; 421 422 /// True for some subtargets at > -O0. 423 bool enablePostRAMachineScheduler() const override; 424 425 /// Check whether this subtarget wants to use subregister liveness. 426 bool enableSubRegLiveness() const override; 427 428 /// Enable use of alias analysis during code generation (during MI 429 /// scheduling, DAGCombine, etc.). useAA()430 bool useAA() const override { return true; } 431 432 /// getInstrItins - Return the instruction itineraries based on subtarget 433 /// selection. getInstrItineraryData()434 const InstrItineraryData *getInstrItineraryData() const override { 435 return &InstrItins; 436 } 437 438 /// getStackAlignment - Returns the minimum alignment known to hold of the 439 /// stack frame on entry to the function and which must be maintained by every 440 /// function for this subtarget. getStackAlignment()441 Align getStackAlignment() const { return stackAlignment; } 442 443 // Returns the required alignment for LDRD/STRD instructions getDualLoadStoreAlignment()444 Align getDualLoadStoreAlignment() const { 445 return Align(hasV7Ops() || allowsUnalignedMem() ? 4 : 8); 446 } 447 getMaxInterleaveFactor()448 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; } 449 getPartialUpdateClearance()450 unsigned getPartialUpdateClearance() const { return PartialUpdateClearance; } 451 getLdStMultipleTiming()452 ARMLdStMultipleTiming getLdStMultipleTiming() const { 453 return LdStMultipleTiming; 454 } 455 getPreISelOperandLatencyAdjustment()456 int getPreISelOperandLatencyAdjustment() const { 457 return PreISelOperandLatencyAdjustment; 458 } 459 460 /// True if the GV will be accessed via an indirect symbol. 461 bool isGVIndirectSymbol(const GlobalValue *GV) const; 462 463 /// Returns the constant pool modifier needed to access the GV. 464 bool isGVInGOT(const GlobalValue *GV) const; 465 466 /// True if fast-isel is used. 467 bool useFastISel() const; 468 469 /// Returns the correct return opcode for the current feature set. 470 /// Use BX if available to allow mixing thumb/arm code, but fall back 471 /// to plain mov pc,lr on ARMv4. getReturnOpcode()472 unsigned getReturnOpcode() const { 473 if (isThumb()) 474 return ARM::tBX_RET; 475 if (hasV4TOps()) 476 return ARM::BX_RET; 477 return ARM::MOVPCLR; 478 } 479 480 /// Allow movt+movw for PIC global address calculation. 481 /// ELF does not have GOT relocations for movt+movw. 482 /// ROPI does not use GOT. allowPositionIndependentMovt()483 bool allowPositionIndependentMovt() const { 484 return isROPI() || !isTargetELF(); 485 } 486 getPreferBranchLogAlignment()487 unsigned getPreferBranchLogAlignment() const { 488 return PreferBranchLogAlignment; 489 } 490 491 unsigned getMVEVectorCostFactor(TargetTransformInfo::TargetCostKind CostKind)492 getMVEVectorCostFactor(TargetTransformInfo::TargetCostKind CostKind) const { 493 if (CostKind == TargetTransformInfo::TCK_CodeSize) 494 return 1; 495 return MVEVectorCostFactor; 496 } 497 498 bool ignoreCSRForAllocationOrder(const MachineFunction &MF, 499 MCRegister PhysReg) const override; 500 unsigned getGPRAllocationOrder(const MachineFunction &MF) const; 501 }; 502 503 } // end namespace llvm 504 505 #endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H 506