xref: /titanic_41/usr/src/uts/common/sys/ecppreg.h (revision 7c478bd95313f5f23a4c958a745db2134aa03244)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 1992-2002 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef	_SYS_ECPPREG_H
28 #define	_SYS_ECPPREG_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #ifdef	__cplusplus
33 extern "C" {
34 #endif
35 
36 /*
37  * Register definitions for the National Semiconductor PC87332VLJ
38  * SuperI/O chip.
39  */
40 
41 /*
42  * configuration registers
43  */
44 struct config_reg {
45 	uint8_t index;
46 	uint8_t data;
47 };
48 
49 /* index values for the configuration registers */
50 #define	FER	0x0	/* Function Enable Register */
51 #define	FAR	0x1	/* Function Address Register */
52 #define	PTR	0x2	/* Power and Test Register */
53 #define	FCR	0x3	/* Function Control Register */
54 #define	PCR	0x4	/* Printer Control Register */
55 #define	KRR	0x5	/* Keyboard and RTC control Register */
56 #define	PMC	0x6	/* Power Management Control register */
57 #define	TUP	0x7	/* Tape, UART, and Parallel port register */
58 #define	SID	0x8	/* Super I/O Identification register */
59 
60 #define	SIO_LITE	0x40
61 #define	SIO_LITE_B	0x90
62 #define	SIO_REVA	0x1a
63 #define	SIO_REVB	0x1b
64 
65 /* bit definitions for the FCR register */
66 #define	PC87332_FCR_MSD_SEL		0x01
67 #define	PC87332_FCR_RESERVED		0x02
68 #define	PC87332_FCR_PPM_EN		0x04
69 #define	PC87332_FCR_PPM_FLOAT_CTL	0x08
70 #define	PC87332_FCR_LDX			0x10
71 #define	PC87332_FCR_ZWS_EN		0x20
72 #define	PC87332_FCR_ZWS_SEL		0x40
73 #define	PC87332_FCR_IOCHRDY_SEL		0x80
74 
75 /* bit definitions for the PCR register */
76 #define	PC87332_PCR_EPP_EN		0x01
77 #define	PC87332_PCR_EPP_VER		0x02
78 #define	PC87332_PCR_ECP_EN		0x04
79 #define	PC87332_PCR_ECP_CLK_FZ		0x08
80 #define	PC87332_PCR_INTR_LEVL		0x10
81 #define	PC87332_PCR_INTR_POL		0x20
82 #define	PC87332_PCR_INTR_DRAIN		0x40
83 #define	PC87332_PCR_RESERVED		0x80
84 
85 /* bit definitions for the PMC register */
86 #define	PC87332_PMC_IDE_TRISTATE	0x01
87 #define	PC87332_PMC_FDC_TRISTATE	0x02
88 #define	PC87332_PMC_UART_TRISTATE	0x04
89 #define	PC87332_PMC_ECP_DMA_CONFIG	0x08
90 #define	PC87332_PMC_FDC_PD		0x10
91 #define	PC87332_PMC_SLB			0x20
92 #define	PC87332_PMC_PP_TRISTATE		0x40
93 #define	PC87332_PMC_RESERVED		0x80
94 
95 /*
96  * National 97317 superio registers
97  */
98 #define	PC97317_CONFIG_DEV_NO		0x07
99 #define	PC97317_CONFIG_ACTIVATE		0x30
100 #define	PC97317_CONFIG_IO_RANGE		0x31
101 #define	PC97317_CONFIG_BASE_ADDR_MSB	0x60
102 #define	PC97317_CONFIG_BASE_ADDR_LSB	0x61
103 #define	PC97317_CONFIG_INTR_SEL		0x70
104 #define	PC97317_CONFIG_INTR_TYPE	0x71
105 #define	PC97317_CONFIG_DMA0_CHAN	0x74
106 #define	PC97317_CONFIG_DMA1_CHAN	0x75
107 #define	PC97317_CONFIG_PP_CONFIG	0xF0
108 
109 /*
110  * Plug N Play configuration superio registers
111  * used in PC97317 & M1553
112  */
113 #define	PnP_CONFIG_DEV_NO		0x07
114 #define	PnP_CONFIG_ACTIVATE		0x30
115 #define	PnP_CONFIG_IO_RANGE		0x31
116 #define	PnP_CONFIG_BASE_ADDR_MSB	0x60
117 #define	PnP_CONFIG_BASE_ADDR_LSB	0x61
118 #define	PnP_CONFIG_INTR_SEL		0x70
119 #define	PnP_CONFIG_INTR_TYPE		0x71
120 #define	PnP_CONFIG_DMA0_CHAN		0x74
121 #define	PnP_CONFIG_DMA1_CHAN		0x75
122 #define	PnP_CONFIG_PP_CONFIG0		0xF0
123 #define	PnP_CONFIG_PP_CONFIG1		0xF1
124 
125 
126 /*
127  * parallel port interface registers - same for all 1284 modes.
128  */
129 struct info_reg {
130 	union {
131 		uint8_t	datar;
132 		uint8_t	afifo;
133 	} ir;
134 	uint8_t dsr;
135 	uint8_t dcr;
136 	uint8_t epp_addr;
137 	uint8_t epp_data;
138 	uint8_t epp_data32[3];
139 };
140 
141 /*
142  * additional ECP mode registers.
143  */
144 struct fifo_reg {
145 	union {
146 		uint8_t cfifo;
147 		uint8_t dfifo;
148 		uint8_t tfifo;
149 		uint8_t config_a;
150 	} fr;
151 	uint8_t config_b;
152 	uint8_t ecr;
153 };
154 
155 /*
156  * Values for the ECR field
157  *
158  * The ECR has 3 read-only bits - bits 0,1,2.  Bits 3,4,5,6,7 are read/write.
159  * While writing to this register (ECPPIOC_SETREGS), bits 0,1,2 must be 0.
160  * If not, ECPPIOC_SETREGS will return EINVAL.
161  */
162 
163 #define	ECPP_FIFO_EMPTY		0x01	/* 1 when FIFO empty */
164 #define	ECPP_FIFO_FULL		0x02	/* 1 when FIFO full  */
165 #define	ECPP_INTR_SRV		0x04
166 
167 /*
168  * When bit is 0, bit will be set to 1
169  * and interrupt will be generated if
170  * any of the three events occur:
171  * (a) TC is reached while DMA enabled
172  * (b) If DMA disabled & DCR5 = 0, 8 or more bytes free in FIFO,
173  * (c) IF DMA disable & DCR5 = 1, 8 or more bytes to be read in FIFO.
174  *
175  * When this bit is 1, DMA & (a), (b), (c)
176  * interrupts are disabled.
177  */
178 
179 #define	ECPP_DMA_ENABLE		0x08  /* DMA enable =1 */
180 #define	ECPP_INTR_MASK		0x10  /* intr-enable nErr mask=1 */
181 #define	ECR_mode_000		0x00  /* PIO CENTRONICS */
182 #define	ECR_mode_001		0x20  /* PIO NIBBLE */
183 #define	ECR_mode_010		0x40  /* DMA CENTRONICS */
184 #define	ECR_mode_011		0x60  /* DMA ECP */
185 #define	ECR_mode_100		0x80  /* PIO EPP */
186 #define	ECR_mode_110		0xc0  /* TDMA (TFIFO) */
187 #define	ECR_mode_111		0xe0  /* Config Mode */
188 
189 /*
190  * 97317 second level configuration registers
191  */
192 struct config2_reg {
193 	uint8_t		eir;	/* Extended Index Register */
194 	uint8_t		edr;	/* Extended Data Register */
195 };
196 
197 /*
198  * Second level offset
199  */
200 #define	PC97317_CONFIG2_CONTROL0	0x00
201 #define	PC97317_CONFIG2_CONTROL2	0x02
202 #define	PC97317_CONFIG2_CONTROL4	0x04
203 #define	PC97317_CONFIG2_PPCONFG0	0x05
204 
205 /* Cheerio Ebus DMAC */
206 
207 struct cheerio_dma_reg {
208 	uint32_t csr;	/* Data Control Status Register */
209 	uint32_t acr;	/* DMA Address Count Registers */
210 	uint32_t bcr;	/* DMA Byte Count Register */
211 };
212 
213 /*
214  * DMA Control and Status Register(DCSR) definitions.  See Cheerio spec
215  * for more details
216  */
217 #define	DCSR_INT_PEND 	0x00000001	/* 1= pport or dma interrupts */
218 #define	DCSR_ERR_PEND 	0x00000002	/* 1= host bus error detected */
219 #define	DCSR_INT_EN 	0x00000010	/* 1= enable sidewinder/ebus intr */
220 #define	DCSR_RESET  	0x00000080	/* 1= resets the DCSR */
221 #define	DCSR_WRITE  	0x00000100  	/* DMA direction; 1 = memory */
222 #define	DCSR_EN_DMA  	0x00000200  	/* 1= enable DMA */
223 #define	DCSR_CYC_PEND	0x00000400	/* 1 = DMA pending */
224 #define	DCSR_EN_CNT 	0x00002000	/* 1= enables byte counter */
225 #define	DCSR_TC		0x00004000  	/* 1= Terminal Count occurred */
226 #define	DCSR_CSR_DRAIN 	0x00000000 	/* 1= disable draining */
227 #define	DCSR_BURST_0    0x00040000 	/* Burst Size bit 0 */
228 #define	DCSR_BURST_1    0x00080000 	/* Burst Size bit 1 */
229 #define	DCSR_DIAG	0x00000000 	/* 1= diag enable */
230 #define	DCSR_TCI_DIS 	0x00800000	/* 1= TC won't cause interrupt */
231 
232 
233 /* Southbridge support */
234 struct isaspace {
235 	uchar_t	isa_reg[0x500];	/* 0x500 regs from isa config space */
236 };
237 
238 
239 #ifdef	__cplusplus
240 }
241 #endif
242 
243 #endif	/* _SYS_ECPPREG_H */
244