xref: /illumos-gate/usr/src/uts/common/sys/ecppreg.h (revision 2d6eb4a5e0a47d30189497241345dc5466bb68ab)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 1992-2002 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef	_SYS_ECPPREG_H
28 #define	_SYS_ECPPREG_H
29 
30 #ifdef	__cplusplus
31 extern "C" {
32 #endif
33 
34 /*
35  * Register definitions for the National Semiconductor PC87332VLJ
36  * SuperI/O chip.
37  */
38 
39 /*
40  * configuration registers
41  */
42 struct config_reg {
43 	uint8_t index;
44 	uint8_t data;
45 };
46 
47 /* index values for the configuration registers */
48 #define	FER	0x0	/* Function Enable Register */
49 #define	FAR	0x1	/* Function Address Register */
50 #define	PTR	0x2	/* Power and Test Register */
51 #define	FCR	0x3	/* Function Control Register */
52 #define	PCR	0x4	/* Printer Control Register */
53 #define	KRR	0x5	/* Keyboard and RTC control Register */
54 #define	PMC	0x6	/* Power Management Control register */
55 #define	TUP	0x7	/* Tape, UART, and Parallel port register */
56 #define	SID	0x8	/* Super I/O Identification register */
57 
58 #define	SIO_LITE	0x40
59 #define	SIO_LITE_B	0x90
60 #define	SIO_REVA	0x1a
61 #define	SIO_REVB	0x1b
62 
63 /* bit definitions for the FCR register */
64 #define	PC87332_FCR_MSD_SEL		0x01
65 #define	PC87332_FCR_RESERVED		0x02
66 #define	PC87332_FCR_PPM_EN		0x04
67 #define	PC87332_FCR_PPM_FLOAT_CTL	0x08
68 #define	PC87332_FCR_LDX			0x10
69 #define	PC87332_FCR_ZWS_EN		0x20
70 #define	PC87332_FCR_ZWS_SEL		0x40
71 #define	PC87332_FCR_IOCHRDY_SEL		0x80
72 
73 /* bit definitions for the PCR register */
74 #define	PC87332_PCR_EPP_EN		0x01
75 #define	PC87332_PCR_EPP_VER		0x02
76 #define	PC87332_PCR_ECP_EN		0x04
77 #define	PC87332_PCR_ECP_CLK_FZ		0x08
78 #define	PC87332_PCR_INTR_LEVL		0x10
79 #define	PC87332_PCR_INTR_POL		0x20
80 #define	PC87332_PCR_INTR_DRAIN		0x40
81 #define	PC87332_PCR_RESERVED		0x80
82 
83 /* bit definitions for the PMC register */
84 #define	PC87332_PMC_IDE_TRISTATE	0x01
85 #define	PC87332_PMC_FDC_TRISTATE	0x02
86 #define	PC87332_PMC_UART_TRISTATE	0x04
87 #define	PC87332_PMC_ECP_DMA_CONFIG	0x08
88 #define	PC87332_PMC_FDC_PD		0x10
89 #define	PC87332_PMC_SLB			0x20
90 #define	PC87332_PMC_PP_TRISTATE		0x40
91 #define	PC87332_PMC_RESERVED		0x80
92 
93 /*
94  * National 97317 superio registers
95  */
96 #define	PC97317_CONFIG_DEV_NO		0x07
97 #define	PC97317_CONFIG_ACTIVATE		0x30
98 #define	PC97317_CONFIG_IO_RANGE		0x31
99 #define	PC97317_CONFIG_BASE_ADDR_MSB	0x60
100 #define	PC97317_CONFIG_BASE_ADDR_LSB	0x61
101 #define	PC97317_CONFIG_INTR_SEL		0x70
102 #define	PC97317_CONFIG_INTR_TYPE	0x71
103 #define	PC97317_CONFIG_DMA0_CHAN	0x74
104 #define	PC97317_CONFIG_DMA1_CHAN	0x75
105 #define	PC97317_CONFIG_PP_CONFIG	0xF0
106 
107 /*
108  * Plug N Play configuration superio registers
109  * used in PC97317 & M1553
110  */
111 #define	PnP_CONFIG_DEV_NO		0x07
112 #define	PnP_CONFIG_ACTIVATE		0x30
113 #define	PnP_CONFIG_IO_RANGE		0x31
114 #define	PnP_CONFIG_BASE_ADDR_MSB	0x60
115 #define	PnP_CONFIG_BASE_ADDR_LSB	0x61
116 #define	PnP_CONFIG_INTR_SEL		0x70
117 #define	PnP_CONFIG_INTR_TYPE		0x71
118 #define	PnP_CONFIG_DMA0_CHAN		0x74
119 #define	PnP_CONFIG_DMA1_CHAN		0x75
120 #define	PnP_CONFIG_PP_CONFIG0		0xF0
121 #define	PnP_CONFIG_PP_CONFIG1		0xF1
122 
123 
124 /*
125  * parallel port interface registers - same for all 1284 modes.
126  */
127 struct info_reg {
128 	union {
129 		uint8_t	datar;
130 		uint8_t	afifo;
131 	} ir;
132 	uint8_t dsr;
133 	uint8_t dcr;
134 	uint8_t epp_addr;
135 	uint8_t epp_data;
136 	uint8_t epp_data32[3];
137 };
138 
139 /*
140  * additional ECP mode registers.
141  */
142 struct fifo_reg {
143 	union {
144 		uint8_t cfifo;
145 		uint8_t dfifo;
146 		uint8_t tfifo;
147 		uint8_t config_a;
148 	} fr;
149 	uint8_t config_b;
150 	uint8_t ecr;
151 };
152 
153 /*
154  * Values for the ECR field
155  *
156  * The ECR has 3 read-only bits - bits 0,1,2.  Bits 3,4,5,6,7 are read/write.
157  * While writing to this register (ECPPIOC_SETREGS), bits 0,1,2 must be 0.
158  * If not, ECPPIOC_SETREGS will return EINVAL.
159  */
160 
161 #define	ECPP_FIFO_EMPTY		0x01	/* 1 when FIFO empty */
162 #define	ECPP_FIFO_FULL		0x02	/* 1 when FIFO full  */
163 #define	ECPP_INTR_SRV		0x04
164 
165 /*
166  * When bit is 0, bit will be set to 1
167  * and interrupt will be generated if
168  * any of the three events occur:
169  * (a) TC is reached while DMA enabled
170  * (b) If DMA disabled & DCR5 = 0, 8 or more bytes free in FIFO,
171  * (c) IF DMA disable & DCR5 = 1, 8 or more bytes to be read in FIFO.
172  *
173  * When this bit is 1, DMA & (a), (b), (c)
174  * interrupts are disabled.
175  */
176 
177 #define	ECPP_DMA_ENABLE		0x08  /* DMA enable =1 */
178 #define	ECPP_INTR_MASK		0x10  /* intr-enable nErr mask=1 */
179 #define	ECR_mode_000		0x00  /* PIO CENTRONICS */
180 #define	ECR_mode_001		0x20  /* PIO NIBBLE */
181 #define	ECR_mode_010		0x40  /* DMA CENTRONICS */
182 #define	ECR_mode_011		0x60  /* DMA ECP */
183 #define	ECR_mode_100		0x80  /* PIO EPP */
184 #define	ECR_mode_110		0xc0  /* TDMA (TFIFO) */
185 #define	ECR_mode_111		0xe0  /* Config Mode */
186 
187 /*
188  * 97317 second level configuration registers
189  */
190 struct config2_reg {
191 	uint8_t		eir;	/* Extended Index Register */
192 	uint8_t		edr;	/* Extended Data Register */
193 };
194 
195 /*
196  * Second level offset
197  */
198 #define	PC97317_CONFIG2_CONTROL0	0x00
199 #define	PC97317_CONFIG2_CONTROL2	0x02
200 #define	PC97317_CONFIG2_CONTROL4	0x04
201 #define	PC97317_CONFIG2_PPCONFG0	0x05
202 
203 /* Cheerio Ebus DMAC */
204 
205 struct cheerio_dma_reg {
206 	uint32_t csr;	/* Data Control Status Register */
207 	uint32_t acr;	/* DMA Address Count Registers */
208 	uint32_t bcr;	/* DMA Byte Count Register */
209 };
210 
211 /*
212  * DMA Control and Status Register(DCSR) definitions.  See Cheerio spec
213  * for more details
214  */
215 #define	DCSR_INT_PEND 	0x00000001	/* 1= pport or dma interrupts */
216 #define	DCSR_ERR_PEND 	0x00000002	/* 1= host bus error detected */
217 #define	DCSR_INT_EN 	0x00000010	/* 1= enable sidewinder/ebus intr */
218 #define	DCSR_RESET  	0x00000080	/* 1= resets the DCSR */
219 #define	DCSR_WRITE  	0x00000100  	/* DMA direction; 1 = memory */
220 #define	DCSR_EN_DMA  	0x00000200  	/* 1= enable DMA */
221 #define	DCSR_CYC_PEND	0x00000400	/* 1 = DMA pending */
222 #define	DCSR_EN_CNT 	0x00002000	/* 1= enables byte counter */
223 #define	DCSR_TC		0x00004000  	/* 1= Terminal Count occurred */
224 #define	DCSR_CSR_DRAIN 	0x00000000 	/* 1= disable draining */
225 #define	DCSR_BURST_0    0x00040000 	/* Burst Size bit 0 */
226 #define	DCSR_BURST_1    0x00080000 	/* Burst Size bit 1 */
227 #define	DCSR_DIAG	0x00000000 	/* 1= diag enable */
228 #define	DCSR_TCI_DIS 	0x00800000	/* 1= TC won't cause interrupt */
229 
230 
231 /* Southbridge support */
232 struct isaspace {
233 	uchar_t	isa_reg[0x500];	/* 0x500 regs from isa config space */
234 };
235 
236 
237 #ifdef	__cplusplus
238 }
239 #endif
240 
241 #endif	/* _SYS_ECPPREG_H */
242