1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_ERR_H 27 #define _SYS_PX_ERR_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 typedef enum { 36 PX_ERR_JBC, 37 PX_ERR_UBC, 38 PX_ERR_MMU, 39 PX_ERR_IMU, 40 PX_ERR_TLU_UE, 41 PX_ERR_TLU_CE, 42 PX_ERR_TLU_OE, 43 PX_ERR_ILU, 44 PX_ERR_LPU_LINK, 45 PX_ERR_LPU_PHY, 46 PX_ERR_LPU_RX, 47 PX_ERR_LPU_TX, 48 PX_ERR_LPU_LTSSM, 49 PX_ERR_LPU_GIGABLZ 50 } px_err_id_t; 51 52 #define PX_ERR_ENABLE B_TRUE 53 #define PX_ERR_DISABLE B_FALSE 54 55 void px_err_reg_enable(px_err_id_t reg_id, caddr_t csr_base); 56 void px_err_reg_disable(px_err_id_t reg_id, caddr_t csr_base); 57 void px_err_reg_setup_pcie(uint8_t chip_mask, caddr_t csr_base, 58 boolean_t enable); 59 60 #define PX_ERR_EN_ALL -1ull 61 #define PX_ERR_MASK_NONE 0ull 62 63 #define LPU_INTR_ENABLE 0ull 64 #define LPU_INTR_DISABLE -1ull 65 66 extern uint64_t px_tlu_ue_intr_mask; 67 extern uint64_t px_tlu_ue_log_mask; 68 extern uint64_t px_tlu_ue_count_mask; 69 70 extern uint64_t px_tlu_ce_intr_mask; 71 extern uint64_t px_tlu_ce_log_mask; 72 extern uint64_t px_tlu_ce_count_mask; 73 74 extern uint64_t px_tlu_oe_intr_mask; 75 extern uint64_t px_tlu_oe_log_mask; 76 extern uint64_t px_tlu_oe_count_mask; 77 78 extern uint64_t px_mmu_intr_mask; 79 extern uint64_t px_mmu_log_mask; 80 extern uint64_t px_mmu_count_mask; 81 82 extern uint64_t px_imu_intr_mask; 83 extern uint64_t px_imu_log_mask; 84 extern uint64_t px_imu_count_mask; 85 86 extern uint64_t px_ilu_intr_mask; 87 extern uint64_t px_ilu_log_mask; 88 extern uint64_t px_ilu_count_mask; 89 90 #ifdef __cplusplus 91 } 92 #endif 93 94 #endif /* _SYS_PX_ERR_H */ 95