1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef __COMMON_HSI__ 30 #define __COMMON_HSI__ 31 /********************************/ 32 /* PROTOCOL COMMON FW CONSTANTS */ 33 /********************************/ 34 35 /* Temporarily here should be added to HSI automatically by resource allocation tool.*/ 36 #define T_TEST_AGG_INT_TEMP 6 37 #define M_TEST_AGG_INT_TEMP 8 38 #define U_TEST_AGG_INT_TEMP 6 39 #define X_TEST_AGG_INT_TEMP 14 40 #define Y_TEST_AGG_INT_TEMP 4 41 #define P_TEST_AGG_INT_TEMP 4 42 43 #define X_FINAL_CLEANUP_AGG_INT 1 44 45 #define EVENT_RING_PAGE_SIZE_BYTES 4096 46 47 #define NUM_OF_GLOBAL_QUEUES 128 48 #define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64 49 50 #define ISCSI_CDU_TASK_SEG_TYPE 0 51 #define FCOE_CDU_TASK_SEG_TYPE 0 52 #define RDMA_CDU_TASK_SEG_TYPE 1 53 54 #define FW_ASSERT_GENERAL_ATTN_IDX 32 55 56 #define MAX_PINNED_CCFC 32 57 58 #define EAGLE_ENG1_WORKAROUND_NIG_FLOWCTRL_MODE 3 59 60 /* Queue Zone sizes in bytes */ 61 #define TSTORM_QZONE_SIZE 8 /*tstorm_scsi_queue_zone*/ 62 #define MSTORM_QZONE_SIZE 16 /*mstorm_eth_queue_zone. Used only for RX producer of VFs in backward compatibility mode.*/ 63 #define USTORM_QZONE_SIZE 8 /*ustorm_eth_queue_zone*/ 64 #define XSTORM_QZONE_SIZE 8 /*xstorm_eth_queue_zone*/ 65 #define YSTORM_QZONE_SIZE 0 66 #define PSTORM_QZONE_SIZE 0 67 68 #define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7 /*Log of mstorm default VF zone size.*/ 69 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16 /*Maximum number of RX queues that can be allocated to VF by default*/ 70 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48 /*Maximum number of RX queues that can be allocated to VF with doubled VF zone size. Up to 96 VF supported in this mode*/ 71 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112 /*Maximum number of RX queues that can be allocated to VF with 4 VF zone size. Up to 48 VF supported in this mode*/ 72 73 /********************************/ 74 /* CORE (LIGHT L2) FW CONSTANTS */ 75 /********************************/ 76 77 #define CORE_LL2_MAX_RAMROD_PER_CON 8 78 #define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096 79 #define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096 80 #define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096 81 #define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1 82 83 #define CORE_LL2_TX_MAX_BDS_PER_PACKET 12 84 85 #define CORE_SPQE_PAGE_SIZE_BYTES 4096 86 87 /* 88 * Usually LL2 queues are opened in pairs � TX-RX. 89 * There is a hard restriction on number of RX queues (limited by Tstorm RAM) and TX counters (Pstorm RAM). 90 * Number of TX queues is almost unlimited. 91 * The constants are different so as to allow asymmetric LL2 connections 92 */ 93 94 #define MAX_NUM_LL2_RX_QUEUES 48 95 #define MAX_NUM_LL2_TX_STATS_COUNTERS 48 96 97 /////////////////////////////////////////////////////////////////////////////////////////////////// 98 // Include firmware verison number only- do not add constants here to avoid redundunt compilations 99 /////////////////////////////////////////////////////////////////////////////////////////////////// 100 101 #define FW_MAJOR_VERSION 8 102 #define FW_MINOR_VERSION 33 103 #define FW_REVISION_VERSION 7 104 #define FW_ENGINEERING_VERSION 0 105 106 /***********************/ 107 /* COMMON HW CONSTANTS */ 108 /***********************/ 109 110 /* PCI functions */ 111 #define MAX_NUM_PORTS_BB (2) 112 #define MAX_NUM_PORTS_K2 (4) 113 #define MAX_NUM_PORTS_E5 (4) 114 #define MAX_NUM_PORTS (MAX_NUM_PORTS_E5) 115 116 #define MAX_NUM_PFS_BB (8) 117 #define MAX_NUM_PFS_K2 (16) 118 #define MAX_NUM_PFS_E5 (16) 119 #define MAX_NUM_PFS (MAX_NUM_PFS_E5) 120 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ 121 122 #define MAX_NUM_VFS_BB (120) 123 #define MAX_NUM_VFS_K2 (192) 124 #define MAX_NUM_VFS_E4 (MAX_NUM_VFS_K2) 125 #define MAX_NUM_VFS_E5 (240) 126 #define COMMON_MAX_NUM_VFS (MAX_NUM_VFS_E5) 127 128 #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB) 129 #define MAX_NUM_FUNCTIONS_K2 (MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2) 130 #define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + MAX_NUM_VFS_E4) 131 132 /* in both BB and K2, the VF number starts from 16. so for arrays containing all */ 133 /* possible PFs and VFs - we need a constant for this size */ 134 #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB) 135 #define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2) 136 #define MAX_FUNCTION_NUMBER_E4 (MAX_NUM_PFS + MAX_NUM_VFS_E4) 137 #define MAX_FUNCTION_NUMBER_E5 (MAX_NUM_PFS + MAX_NUM_VFS_E5) 138 #define COMMON_MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS_E5) 139 140 #define MAX_NUM_VPORTS_K2 (208) 141 #define MAX_NUM_VPORTS_BB (160) 142 #define MAX_NUM_VPORTS_E4 (MAX_NUM_VPORTS_K2) 143 #define MAX_NUM_VPORTS_E5 (256) 144 #define COMMON_MAX_NUM_VPORTS (MAX_NUM_VPORTS_E5) 145 146 #define MAX_NUM_L2_QUEUES_BB (256) 147 #define MAX_NUM_L2_QUEUES_K2 (320) 148 #define MAX_NUM_L2_QUEUES_E5 (320) /* TODO_E5_VITALY - fix to 512 */ 149 #define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_E5) 150 151 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ 152 #define NUM_PHYS_TCS_4PORT_K2 4 153 #define NUM_PHYS_TCS_4PORT_TX_E5 6 154 #define NUM_PHYS_TCS_4PORT_RX_E5 4 155 #define NUM_OF_PHYS_TCS 8 156 #define PURE_LB_TC NUM_OF_PHYS_TCS 157 #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) 158 #define NUM_TCS_4PORT_TX_E5 (NUM_PHYS_TCS_4PORT_TX_E5 + 1) 159 #define NUM_TCS_4PORT_RX_E5 (NUM_PHYS_TCS_4PORT_RX_E5 + 1) 160 #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) 161 162 /* CIDs */ 163 #define NUM_OF_CONNECTION_TYPES_E4 (8) 164 #define NUM_OF_CONNECTION_TYPES_E5 (16) 165 #define NUM_OF_TASK_TYPES (8) 166 #define NUM_OF_LCIDS (320) 167 #define NUM_OF_LTIDS (320) 168 169 /* Global PXP windows (GTT) */ 170 #define NUM_OF_GTT 19 171 #define GTT_DWORD_SIZE_BITS 10 172 #define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2) 173 #define GTT_DWORD_SIZE (1 << GTT_DWORD_SIZE_BITS) 174 175 /* Tools Version */ 176 #define TOOLS_VERSION 10 177 /*****************/ 178 /* CDU CONSTANTS */ 179 /*****************/ 180 181 #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17) 182 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff) 183 184 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12) 185 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff) 186 187 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0) 188 #define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT (1) 189 #define CDU_CONTEXT_VALIDATION_CFG_USE_TYPE (2) 190 #define CDU_CONTEXT_VALIDATION_CFG_USE_REGION (3) 191 #define CDU_CONTEXT_VALIDATION_CFG_USE_CID (4) 192 #define CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE (5) 193 194 /*****************/ 195 /* DQ CONSTANTS */ 196 /*****************/ 197 198 /* DEMS */ 199 #define DQ_DEMS_LEGACY 0 200 #define DQ_DEMS_TOE_MORE_TO_SEND 3 201 #define DQ_DEMS_TOE_LOCAL_ADV_WND 4 202 #define DQ_DEMS_ROCE_CQ_CONS 7 203 204 /* XCM agg val selection (HW) */ 205 #define DQ_XCM_AGG_VAL_SEL_WORD2 0 206 #define DQ_XCM_AGG_VAL_SEL_WORD3 1 207 #define DQ_XCM_AGG_VAL_SEL_WORD4 2 208 #define DQ_XCM_AGG_VAL_SEL_WORD5 3 209 #define DQ_XCM_AGG_VAL_SEL_REG3 4 210 #define DQ_XCM_AGG_VAL_SEL_REG4 5 211 #define DQ_XCM_AGG_VAL_SEL_REG5 6 212 #define DQ_XCM_AGG_VAL_SEL_REG6 7 213 214 /* XCM agg val selection (FW) */ 215 #define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 216 #define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 217 #define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 218 #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2 219 #define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 220 #define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 221 #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5 222 #define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 223 #define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 224 #define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5 225 #define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 226 #define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 227 #define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 228 #define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6 229 #define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 230 #define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 231 #define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 232 #define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4 233 234 /* UCM agg val selection (HW) */ 235 #define DQ_UCM_AGG_VAL_SEL_WORD0 0 236 #define DQ_UCM_AGG_VAL_SEL_WORD1 1 237 #define DQ_UCM_AGG_VAL_SEL_WORD2 2 238 #define DQ_UCM_AGG_VAL_SEL_WORD3 3 239 #define DQ_UCM_AGG_VAL_SEL_REG0 4 240 #define DQ_UCM_AGG_VAL_SEL_REG1 5 241 #define DQ_UCM_AGG_VAL_SEL_REG2 6 242 #define DQ_UCM_AGG_VAL_SEL_REG3 7 243 244 /* UCM agg val selection (FW) */ 245 #define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2 246 #define DQ_UCM_ETH_PMD_RX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD3 247 #define DQ_UCM_ROCE_CQ_CONS_CMD DQ_UCM_AGG_VAL_SEL_REG0 248 #define DQ_UCM_ROCE_CQ_PROD_CMD DQ_UCM_AGG_VAL_SEL_REG2 249 250 /* TCM agg val selection (HW) */ 251 #define DQ_TCM_AGG_VAL_SEL_WORD0 0 252 #define DQ_TCM_AGG_VAL_SEL_WORD1 1 253 #define DQ_TCM_AGG_VAL_SEL_WORD2 2 254 #define DQ_TCM_AGG_VAL_SEL_WORD3 3 255 #define DQ_TCM_AGG_VAL_SEL_REG1 4 256 #define DQ_TCM_AGG_VAL_SEL_REG2 5 257 #define DQ_TCM_AGG_VAL_SEL_REG6 6 258 #define DQ_TCM_AGG_VAL_SEL_REG9 7 259 260 /* TCM agg val selection (FW) */ 261 #define DQ_TCM_L2B_BD_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD1 262 #define DQ_TCM_ROCE_RQ_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD0 263 264 /* XCM agg counter flag selection (HW) */ 265 #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0 266 #define DQ_XCM_AGG_FLG_SHIFT_BIT15 1 267 #define DQ_XCM_AGG_FLG_SHIFT_CF12 2 268 #define DQ_XCM_AGG_FLG_SHIFT_CF13 3 269 #define DQ_XCM_AGG_FLG_SHIFT_CF18 4 270 #define DQ_XCM_AGG_FLG_SHIFT_CF19 5 271 #define DQ_XCM_AGG_FLG_SHIFT_CF22 6 272 #define DQ_XCM_AGG_FLG_SHIFT_CF23 7 273 274 /* XCM agg counter flag selection (FW) */ 275 #define DQ_XCM_CORE_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18) 276 #define DQ_XCM_CORE_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 277 #define DQ_XCM_CORE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 278 #define DQ_XCM_ETH_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18) 279 #define DQ_XCM_ETH_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 280 #define DQ_XCM_ETH_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 281 #define DQ_XCM_ETH_TPH_EN_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23) 282 #define DQ_XCM_FCOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 283 #define DQ_XCM_ISCSI_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 284 #define DQ_XCM_ISCSI_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 285 #define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23) 286 #define DQ_XCM_TOE_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 287 #define DQ_XCM_TOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 288 289 /* UCM agg counter flag selection (HW) */ 290 #define DQ_UCM_AGG_FLG_SHIFT_CF0 0 291 #define DQ_UCM_AGG_FLG_SHIFT_CF1 1 292 #define DQ_UCM_AGG_FLG_SHIFT_CF3 2 293 #define DQ_UCM_AGG_FLG_SHIFT_CF4 3 294 #define DQ_UCM_AGG_FLG_SHIFT_CF5 4 295 #define DQ_UCM_AGG_FLG_SHIFT_CF6 5 296 #define DQ_UCM_AGG_FLG_SHIFT_RULE0EN 6 297 #define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7 298 299 /* UCM agg counter flag selection (FW) */ 300 #define DQ_UCM_ETH_PMD_TX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 301 #define DQ_UCM_ETH_PMD_RX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 302 #define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 303 #define DQ_UCM_ROCE_CQ_ARM_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 304 #define DQ_UCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF3) 305 #define DQ_UCM_TOE_SLOW_PATH_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 306 #define DQ_UCM_TOE_DQ_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 307 308 /* TCM agg counter flag selection (HW) */ 309 #define DQ_TCM_AGG_FLG_SHIFT_CF0 0 310 #define DQ_TCM_AGG_FLG_SHIFT_CF1 1 311 #define DQ_TCM_AGG_FLG_SHIFT_CF2 2 312 #define DQ_TCM_AGG_FLG_SHIFT_CF3 3 313 #define DQ_TCM_AGG_FLG_SHIFT_CF4 4 314 #define DQ_TCM_AGG_FLG_SHIFT_CF5 5 315 #define DQ_TCM_AGG_FLG_SHIFT_CF6 6 316 #define DQ_TCM_AGG_FLG_SHIFT_CF7 7 317 318 /* TCM agg counter flag selection (FW) */ 319 #define DQ_TCM_FCOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 320 #define DQ_TCM_FCOE_DUMMY_TIMER_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF2) 321 #define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 322 #define DQ_TCM_ISCSI_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 323 #define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 324 #define DQ_TCM_TOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 325 #define DQ_TCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 326 #define DQ_TCM_IWARP_POST_RQ_CF_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 327 328 /* PWM address mapping */ 329 #define DQ_PWM_OFFSET_DPM_BASE 0x0 330 #define DQ_PWM_OFFSET_DPM_END 0x27 331 #define DQ_PWM_OFFSET_XCM16_BASE 0x40 332 #define DQ_PWM_OFFSET_XCM32_BASE 0x44 333 #define DQ_PWM_OFFSET_UCM16_BASE 0x48 334 #define DQ_PWM_OFFSET_UCM32_BASE 0x4C 335 #define DQ_PWM_OFFSET_UCM16_4 0x50 336 #define DQ_PWM_OFFSET_TCM16_BASE 0x58 337 #define DQ_PWM_OFFSET_TCM32_BASE 0x5C 338 #define DQ_PWM_OFFSET_XCM_FLAGS 0x68 339 #define DQ_PWM_OFFSET_UCM_FLAGS 0x69 340 #define DQ_PWM_OFFSET_TCM_FLAGS 0x6B 341 342 #define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2) 343 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE) 344 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT (DQ_PWM_OFFSET_UCM16_4) 345 #define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT (DQ_PWM_OFFSET_UCM16_BASE + 2) 346 #define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS) 347 #define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1) 348 #define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3) 349 350 #define DQ_REGION_SHIFT (12) 351 352 /* DPM */ 353 #define DQ_DPM_WQE_BUFF_SIZE (320) 354 355 // Conn type ranges 356 #define DQ_CONN_TYPE_RANGE_SHIFT (4) 357 358 /*****************/ 359 /* QM CONSTANTS */ 360 /*****************/ 361 362 /* number of TX queues in the QM */ 363 #define MAX_QM_TX_QUEUES_K2 512 364 #define MAX_QM_TX_QUEUES_BB 448 365 #define MAX_QM_TX_QUEUES_E5 MAX_QM_TX_QUEUES_K2 366 #define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2 367 368 /* number of Other queues in the QM */ 369 #define MAX_QM_OTHER_QUEUES_BB 64 370 #define MAX_QM_OTHER_QUEUES_K2 128 371 #define MAX_QM_OTHER_QUEUES_E5 MAX_QM_OTHER_QUEUES_K2 372 #define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2 373 374 /* number of queues in a PF queue group */ 375 #define QM_PF_QUEUE_GROUP_SIZE 8 376 377 /* the size of a single queue element in bytes */ 378 #define QM_PQ_ELEMENT_SIZE 4 379 380 /* base number of Tx PQs in the CM PQ representation. 381 should be used when storing PQ IDs in CM PQ registers and context */ 382 #define CM_TX_PQ_BASE 0x200 383 384 /* number of global Vport/QCN rate limiters */ 385 #define MAX_QM_GLOBAL_RLS 256 386 387 /* QM registers data */ 388 #define QM_LINE_CRD_REG_WIDTH 16 389 #define QM_LINE_CRD_REG_SIGN_BIT (1 << (QM_LINE_CRD_REG_WIDTH - 1)) 390 #define QM_BYTE_CRD_REG_WIDTH 24 391 #define QM_BYTE_CRD_REG_SIGN_BIT (1 << (QM_BYTE_CRD_REG_WIDTH - 1)) 392 #define QM_WFQ_CRD_REG_WIDTH 32 393 #define QM_WFQ_CRD_REG_SIGN_BIT (1 << (QM_WFQ_CRD_REG_WIDTH - 1)) 394 #define QM_RL_CRD_REG_WIDTH 32 395 #define QM_RL_CRD_REG_SIGN_BIT (1 << (QM_RL_CRD_REG_WIDTH - 1)) 396 397 /*****************/ 398 /* CAU CONSTANTS */ 399 /*****************/ 400 401 #define CAU_FSM_ETH_RX 0 402 #define CAU_FSM_ETH_TX 1 403 404 /* Number of Protocol Indices per Status Block */ 405 #define PIS_PER_SB_E4 12 406 #define PIS_PER_SB_E5 8 407 #define MAX_PIS_PER_SB OSAL_MAX_T(PIS_PER_SB_E4,PIS_PER_SB_E5) 408 409 #define CAU_HC_STOPPED_STATE 3 /* fsm is stopped or not valid for this sb */ 410 #define CAU_HC_DISABLE_STATE 4 /* fsm is working without interrupt coalescing for this sb*/ 411 #define CAU_HC_ENABLE_STATE 0 /* fsm is working with interrupt coalescing for this sb*/ 412 413 /*****************/ 414 /* IGU CONSTANTS */ 415 /*****************/ 416 417 #define MAX_SB_PER_PATH_K2 (368) 418 #define MAX_SB_PER_PATH_BB (288) 419 #define MAX_SB_PER_PATH_E5 (512) 420 #define MAX_TOT_SB_PER_PATH MAX_SB_PER_PATH_E5 421 422 #define MAX_SB_PER_PF_MIMD 129 423 #define MAX_SB_PER_PF_SIMD 64 424 #define MAX_SB_PER_VF 64 425 426 /* Memory addresses on the BAR for the IGU Sub Block */ 427 #define IGU_MEM_BASE 0x0000 428 429 #define IGU_MEM_MSIX_BASE 0x0000 430 #define IGU_MEM_MSIX_UPPER 0x0101 431 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 432 433 #define IGU_MEM_PBA_MSIX_BASE 0x0200 434 #define IGU_MEM_PBA_MSIX_UPPER 0x0202 435 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 436 437 #define IGU_CMD_INT_ACK_BASE 0x0400 438 #define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + MAX_TOT_SB_PER_PATH - 1) 439 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff 440 441 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0 442 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1 443 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2 444 445 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3 446 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4 447 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5 448 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6 449 450 #define IGU_CMD_PROD_UPD_BASE 0x0600 451 #define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE + MAX_TOT_SB_PER_PATH - 1) 452 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff 453 454 /*****************/ 455 /* PXP CONSTANTS */ 456 /*****************/ 457 458 /* Bars for Blocks */ 459 #define PXP_BAR_GRC 0 460 #define PXP_BAR_TSDM 0 461 #define PXP_BAR_USDM 0 462 #define PXP_BAR_XSDM 0 463 #define PXP_BAR_MSDM 0 464 #define PXP_BAR_YSDM 0 465 #define PXP_BAR_PSDM 0 466 #define PXP_BAR_IGU 0 467 #define PXP_BAR_DQ 1 468 469 /* PTT and GTT */ 470 #define PXP_PER_PF_ENTRY_SIZE 8 471 #define PXP_NUM_GLOBAL_WINDOWS 243 472 #define PXP_GLOBAL_ENTRY_SIZE 4 473 #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4 474 #define PXP_PF_WINDOW_ADMIN_START 0 475 #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000 476 #define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + PXP_PF_WINDOW_ADMIN_LENGTH - 1) 477 #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0 478 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * PXP_PER_PF_ENTRY_SIZE) 479 #define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1) 480 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200 481 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * PXP_GLOBAL_ENTRY_SIZE) 482 #define PXP_PF_WINDOW_ADMIN_GLOBAL_END (PXP_PF_WINDOW_ADMIN_GLOBAL_START + PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1) 483 #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0 484 #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4 485 #define PXP_PF_ME_OPAQUE_ADDR 0x1f8 486 #define PXP_PF_ME_CONCRETE_ADDR 0x1fc 487 488 #define PXP_NUM_PF_WINDOWS 12 489 490 #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000 491 #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS 492 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000 493 #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) 494 #define PXP_EXTERNAL_BAR_PF_WINDOW_END (PXP_EXTERNAL_BAR_PF_WINDOW_START + PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1) 495 496 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1) 497 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS 498 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000 499 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE) 500 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1) 501 502 /* PF BAR */ 503 #define PXP_BAR0_START_GRC 0x0000 504 #define PXP_BAR0_GRC_LENGTH 0x1C00000 505 #define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + PXP_BAR0_GRC_LENGTH - 1) 506 507 #define PXP_BAR0_START_IGU 0x1C00000 508 #define PXP_BAR0_IGU_LENGTH 0x10000 509 #define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + PXP_BAR0_IGU_LENGTH - 1) 510 511 #define PXP_BAR0_START_TSDM 0x1C80000 512 #define PXP_BAR0_SDM_LENGTH 0x40000 513 #define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000 514 #define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + PXP_BAR0_SDM_LENGTH - 1) 515 516 #define PXP_BAR0_START_MSDM 0x1D00000 517 #define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + PXP_BAR0_SDM_LENGTH - 1) 518 519 #define PXP_BAR0_START_USDM 0x1D80000 520 #define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + PXP_BAR0_SDM_LENGTH - 1) 521 522 #define PXP_BAR0_START_XSDM 0x1E00000 523 #define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + PXP_BAR0_SDM_LENGTH - 1) 524 525 #define PXP_BAR0_START_YSDM 0x1E80000 526 #define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + PXP_BAR0_SDM_LENGTH - 1) 527 528 #define PXP_BAR0_START_PSDM 0x1F00000 529 #define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + PXP_BAR0_SDM_LENGTH - 1) 530 531 #define PXP_BAR0_FIRST_INVALID_ADDRESS (PXP_BAR0_END_PSDM + 1) 532 533 /* VF BAR */ 534 #define PXP_VF_BAR0 0 535 536 #define PXP_VF_BAR0_START_IGU 0 537 #define PXP_VF_BAR0_IGU_LENGTH 0x3000 538 #define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + PXP_VF_BAR0_IGU_LENGTH - 1) 539 540 #define PXP_VF_BAR0_START_DQ 0x3000 541 #define PXP_VF_BAR0_DQ_LENGTH 0x200 542 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0 543 #define PXP_VF_BAR0_ME_OPAQUE_ADDRESS (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_OPAQUE_OFFSET) 544 #define PXP_VF_BAR0_ME_CONCRETE_ADDRESS (PXP_VF_BAR0_ME_OPAQUE_ADDRESS + 4) 545 #define PXP_VF_BAR0_END_DQ (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_LENGTH - 1) 546 547 #define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200 548 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200 549 #define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 550 551 #define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400 552 #define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 553 554 #define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600 555 #define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 556 557 #define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800 558 #define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 559 560 #define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00 561 #define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 562 563 #define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00 564 #define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 565 566 #define PXP_VF_BAR0_START_GRC 0x3E00 567 #define PXP_VF_BAR0_GRC_LENGTH 0x200 568 #define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + PXP_VF_BAR0_GRC_LENGTH - 1) 569 570 #define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000 571 #define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000 572 573 #define PXP_VF_BAR0_START_IGU2 0x10000 574 #define PXP_VF_BAR0_IGU2_LENGTH 0xD000 575 #define PXP_VF_BAR0_END_IGU2 (PXP_VF_BAR0_START_IGU2 + PXP_VF_BAR0_IGU2_LENGTH - 1) 576 577 #define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32 578 579 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12 580 #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024 581 582 // ILT Records 583 #define PXP_NUM_ILT_RECORDS_BB 7600 584 #define PXP_NUM_ILT_RECORDS_K2 11000 585 #define MAX_NUM_ILT_RECORDS OSAL_MAX_T(PXP_NUM_ILT_RECORDS_BB,PXP_NUM_ILT_RECORDS_K2) 586 587 #define PXP_NUM_ILT_RECORDS_E5 13664 588 589 // Host Interface 590 #define PXP_QUEUES_ZONE_MAX_NUM_E4 320 591 #define PXP_QUEUES_ZONE_MAX_NUM_E5 512 592 593 /*****************/ 594 /* PRM CONSTANTS */ 595 /*****************/ 596 #define PRM_DMA_PAD_BYTES_NUM 2 597 /*****************/ 598 /* SDMs CONSTANTS */ 599 /*****************/ 600 601 #define SDM_OP_GEN_TRIG_NONE 0 602 #define SDM_OP_GEN_TRIG_WAKE_THREAD 1 603 #define SDM_OP_GEN_TRIG_AGG_INT 2 604 #define SDM_OP_GEN_TRIG_LOADER 4 605 #define SDM_OP_GEN_TRIG_INDICATE_ERROR 6 606 #define SDM_OP_GEN_TRIG_INC_ORDER_CNT 9 607 608 ///////////////////////////////////////////////////////////// 609 // Completion types 610 ///////////////////////////////////////////////////////////// 611 612 #define SDM_COMP_TYPE_NONE 0 613 #define SDM_COMP_TYPE_WAKE_THREAD 1 614 #define SDM_COMP_TYPE_AGG_INT 2 615 #define SDM_COMP_TYPE_CM 3 // Send direct message to local CM and/or remote CMs. Destinations are defined by vector in CompParams. 616 #define SDM_COMP_TYPE_LOADER 4 617 #define SDM_COMP_TYPE_PXP 5 // Send direct message to PXP (like "internal write" command) to write to remote Storm RAM via remote SDM 618 #define SDM_COMP_TYPE_INDICATE_ERROR 6 // Indicate error per thread 619 #define SDM_COMP_TYPE_RELEASE_THREAD 7 // Obsolete in E5 620 #define SDM_COMP_TYPE_RAM 8 // Write to local RAM as a completion 621 #define SDM_COMP_TYPE_INC_ORDER_CNT 9 // Applicable only for E4 622 623 /******************/ 624 /* PBF CONSTANTS */ 625 /******************/ 626 627 /* Number of PBF command queue lines. Each line is 32B. */ 628 #define PBF_MAX_CMD_LINES_E4 3328 629 #define PBF_MAX_CMD_LINES_E5 5280 630 631 /* Number of BTB blocks. Each block is 256B. */ 632 #define BTB_MAX_BLOCKS 1440 633 634 /*****************/ 635 /* PRS CONSTANTS */ 636 /*****************/ 637 638 #define PRS_GFT_CAM_LINES_NO_MATCH 31 639 640 /* 641 * Interrupt coalescing TimeSet 642 */ 643 struct coalescing_timeset 644 { 645 u8 value; 646 #define COALESCING_TIMESET_TIMESET_MASK 0x7F /* Interrupt coalescing TimeSet (timeout_ticks = TimeSet shl (TimerRes+1)) */ 647 #define COALESCING_TIMESET_TIMESET_SHIFT 0 648 #define COALESCING_TIMESET_VALID_MASK 0x1 /* Only if this flag is set, timeset will take effect */ 649 #define COALESCING_TIMESET_VALID_SHIFT 7 650 }; 651 652 struct common_queue_zone 653 { 654 __le16 ring_drv_data_consumer; 655 __le16 reserved; 656 }; 657 658 /* 659 * ETH Rx producers data 660 */ 661 struct eth_rx_prod_data 662 { 663 __le16 bd_prod /* BD producer. */; 664 __le16 cqe_prod /* CQE producer. */; 665 }; 666 667 struct tcp_ulp_connect_done_params 668 { 669 __le16 mss; 670 u8 snd_wnd_scale; 671 u8 flags; 672 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_MASK 0x1 673 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_SHIFT 0 674 #define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_MASK 0x7F 675 #define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_SHIFT 1 676 }; 677 678 struct iscsi_connect_done_results 679 { 680 __le16 icid /* Context ID of the connection */; 681 __le16 conn_id /* Driver connection ID */; 682 struct tcp_ulp_connect_done_params params /* decided tcp params after connect done */; 683 }; 684 685 struct iscsi_eqe_data 686 { 687 __le16 icid /* Context ID of the connection */; 688 __le16 conn_id /* Driver connection ID */; 689 __le16 reserved; 690 u8 error_code /* error code - relevant only if the opcode indicates its an error */; 691 u8 error_pdu_opcode_reserved; 692 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F /* The processed PDUs opcode on which happened the error - updated for specific error codes, by defualt=0xFF */ 693 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0 694 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1 /* Indication for driver is the error_pdu_opcode field has valid value */ 695 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6 696 #define ISCSI_EQE_DATA_RESERVED0_MASK 0x1 697 #define ISCSI_EQE_DATA_RESERVED0_SHIFT 7 698 }; 699 700 /* 701 * Multi function mode 702 */ 703 enum mf_mode 704 { 705 ERROR_MODE /* Unsupported mode */, 706 MF_OVLAN /* Multi function based on outer VLAN */, 707 MF_NPAR /* Multi function based on MAC address (NIC partitioning) */, 708 MAX_MF_MODE 709 }; 710 711 /* 712 * Per-protocol connection types 713 */ 714 enum protocol_type 715 { 716 PROTOCOLID_ISCSI /* iSCSI */, 717 PROTOCOLID_FCOE /* FCoE */, 718 PROTOCOLID_ROCE /* RoCE */, 719 PROTOCOLID_CORE /* Core (light L2, slow path core) */, 720 PROTOCOLID_ETH /* Ethernet */, 721 PROTOCOLID_IWARP /* iWARP */, 722 PROTOCOLID_TOE /* TOE */, 723 PROTOCOLID_PREROCE /* Pre (tapeout) RoCE */, 724 PROTOCOLID_COMMON /* ProtocolCommon */, 725 PROTOCOLID_TCP /* TCP */, 726 MAX_PROTOCOL_TYPE 727 }; 728 729 struct regpair 730 { 731 __le32 lo /* low word for reg-pair */; 732 __le32 hi /* high word for reg-pair */; 733 }; 734 735 /* 736 * RoCE Destroy Event Data 737 */ 738 struct rdma_eqe_destroy_qp 739 { 740 __le32 cid /* Dedicated field RoCE destroy QP event */; 741 u8 reserved[4]; 742 }; 743 744 /* 745 * RDMA Event Data Union 746 */ 747 union rdma_eqe_data 748 { 749 struct regpair async_handle /* Host handle for the Async Completions */; 750 struct rdma_eqe_destroy_qp rdma_destroy_qp_data /* RoCE Destroy Event Data */; 751 }; 752 753 /* 754 * Ustorm Queue Zone 755 */ 756 struct ustorm_eth_queue_zone 757 { 758 struct coalescing_timeset int_coalescing_timeset /* Rx interrupt coalescing TimeSet */; 759 u8 reserved[3]; 760 }; 761 762 struct ustorm_queue_zone 763 { 764 struct ustorm_eth_queue_zone eth; 765 struct common_queue_zone common; 766 }; 767 768 /* 769 * status block structure 770 */ 771 struct cau_pi_entry 772 { 773 __le32 prod; 774 #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF /* A per protocol indexPROD value. */ 775 #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0 776 #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F /* This value determines the TimeSet that the PI is associated with */ 777 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16 778 #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1 /* Select the FSM within the SB */ 779 #define CAU_PI_ENTRY_FSM_SEL_SHIFT 23 780 #define CAU_PI_ENTRY_RESERVED_MASK 0xFF /* Select the FSM within the SB */ 781 #define CAU_PI_ENTRY_RESERVED_SHIFT 24 782 }; 783 784 /* 785 * status block structure 786 */ 787 struct cau_sb_entry 788 { 789 __le32 data; 790 #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF /* The SB PROD index which is sent to the IGU. */ 791 #define CAU_SB_ENTRY_SB_PROD_SHIFT 0 792 #define CAU_SB_ENTRY_STATE0_MASK 0xF /* RX state */ 793 #define CAU_SB_ENTRY_STATE0_SHIFT 24 794 #define CAU_SB_ENTRY_STATE1_MASK 0xF /* TX state */ 795 #define CAU_SB_ENTRY_STATE1_SHIFT 28 796 __le32 params; 797 #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F /* Indicates the RX TimeSet that this SB is associated with. */ 798 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0 799 #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F /* Indicates the TX TimeSet that this SB is associated with. */ 800 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7 801 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3 /* This value will determine the RX FSM timer resolution in ticks */ 802 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14 803 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3 /* This value will determine the TX FSM timer resolution in ticks */ 804 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16 805 #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF 806 #define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18 807 #define CAU_SB_ENTRY_VF_VALID_MASK 0x1 808 #define CAU_SB_ENTRY_VF_VALID_SHIFT 26 809 #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF 810 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27 811 #define CAU_SB_ENTRY_TPH_MASK 0x1 /* If set then indicates that the TPH STAG is equal to the SB number. Otherwise the STAG will be equal to all ones. */ 812 #define CAU_SB_ENTRY_TPH_SHIFT 31 813 }; 814 815 /* 816 * Igu cleanup bit values to distinguish between clean or producer consumer update. 817 */ 818 enum command_type_bit 819 { 820 IGU_COMMAND_TYPE_NOP=0, 821 IGU_COMMAND_TYPE_SET=1, 822 MAX_COMMAND_TYPE_BIT 823 }; 824 825 /* 826 * core doorbell data 827 */ 828 struct core_db_data 829 { 830 u8 params; 831 #define CORE_DB_DATA_DEST_MASK 0x3 /* destination of doorbell (use enum db_dest) */ 832 #define CORE_DB_DATA_DEST_SHIFT 0 833 #define CORE_DB_DATA_AGG_CMD_MASK 0x3 /* aggregative command to CM (use enum db_agg_cmd_sel) */ 834 #define CORE_DB_DATA_AGG_CMD_SHIFT 2 835 #define CORE_DB_DATA_BYPASS_EN_MASK 0x1 /* enable QM bypass */ 836 #define CORE_DB_DATA_BYPASS_EN_SHIFT 4 837 #define CORE_DB_DATA_RESERVED_MASK 0x1 838 #define CORE_DB_DATA_RESERVED_SHIFT 5 839 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3 /* aggregative value selection */ 840 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6 841 u8 agg_flags /* bit for every DQ counter flags in CM context that DQ can increment */; 842 __le16 spq_prod; 843 }; 844 845 /* 846 * Enum of doorbell aggregative command selection 847 */ 848 enum db_agg_cmd_sel 849 { 850 DB_AGG_CMD_NOP /* No operation */, 851 DB_AGG_CMD_SET /* Set the value */, 852 DB_AGG_CMD_ADD /* Add the value */, 853 DB_AGG_CMD_MAX /* Set max of current and new value */, 854 MAX_DB_AGG_CMD_SEL 855 }; 856 857 /* 858 * Enum of doorbell destination 859 */ 860 enum db_dest 861 { 862 DB_DEST_XCM /* TX doorbell to XCM */, 863 DB_DEST_UCM /* RX doorbell to UCM */, 864 DB_DEST_TCM /* RX doorbell to TCM */, 865 DB_NUM_DESTINATIONS, 866 MAX_DB_DEST 867 }; 868 869 /* 870 * Enum of doorbell DPM types 871 */ 872 enum db_dpm_type 873 { 874 DPM_LEGACY /* Legacy DPM- to Xstorm RAM */, 875 DPM_RDMA /* RDMA DPM (only RoCE in E4) - to NIG */, 876 DPM_L2_INLINE /* L2 DPM inline- to PBF, with packet data on doorbell */, 877 DPM_L2_BD /* L2 DPM with BD- to PBF, with TX BD data on doorbell */, 878 MAX_DB_DPM_TYPE 879 }; 880 881 /* 882 * Structure for doorbell data, in L2 DPM mode, for the first doorbell in a DPM burst 883 */ 884 struct db_l2_dpm_data 885 { 886 __le16 icid /* internal CID */; 887 __le16 bd_prod /* bd producer value to update */; 888 __le32 params; 889 #define DB_L2_DPM_DATA_SIZE_MASK 0x3F /* Size in QWORD-s of the DPM burst */ 890 #define DB_L2_DPM_DATA_SIZE_SHIFT 0 891 #define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3 /* Type of DPM transaction (DPM_L2_INLINE or DPM_L2_BD) (use enum db_dpm_type) */ 892 #define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6 893 #define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF /* number of BD-s */ 894 #define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8 895 #define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF /* size of the packet to be transmitted in bytes */ 896 #define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16 897 #define DB_L2_DPM_DATA_RESERVED0_MASK 0x1 898 #define DB_L2_DPM_DATA_RESERVED0_SHIFT 27 899 #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7 /* In DPM_L2_BD mode: the number of SGE-s */ 900 #define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28 901 #define DB_L2_DPM_DATA_GFS_SRC_EN_MASK 0x1 /* Flag indicating whether to enable GFS search */ 902 #define DB_L2_DPM_DATA_GFS_SRC_EN_SHIFT 31 903 }; 904 905 /* 906 * Structure for SGE in a DPM doorbell of type DPM_L2_BD 907 */ 908 struct db_l2_dpm_sge 909 { 910 struct regpair addr /* Single continuous buffer */; 911 __le16 nbytes /* Number of bytes in this BD. */; 912 __le16 bitfields; 913 #define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF /* The TPH STAG index value */ 914 #define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0 915 #define DB_L2_DPM_SGE_RESERVED0_MASK 0x3 916 #define DB_L2_DPM_SGE_RESERVED0_SHIFT 9 917 #define DB_L2_DPM_SGE_ST_VALID_MASK 0x1 /* Indicate if ST hint is requested or not */ 918 #define DB_L2_DPM_SGE_ST_VALID_SHIFT 11 919 #define DB_L2_DPM_SGE_RESERVED1_MASK 0xF 920 #define DB_L2_DPM_SGE_RESERVED1_SHIFT 12 921 __le32 reserved2; 922 }; 923 924 /* 925 * Structure for doorbell address, in legacy mode 926 */ 927 struct db_legacy_addr 928 { 929 __le32 addr; 930 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3 931 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0 932 #define DB_LEGACY_ADDR_DEMS_MASK 0x7 /* doorbell extraction mode specifier- 0 if not used */ 933 #define DB_LEGACY_ADDR_DEMS_SHIFT 2 934 #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF /* internal CID */ 935 #define DB_LEGACY_ADDR_ICID_SHIFT 5 936 }; 937 938 /* 939 * Structure for doorbell address, in PWM mode 940 */ 941 struct db_pwm_addr 942 { 943 __le32 addr; 944 #define DB_PWM_ADDR_RESERVED0_MASK 0x7 945 #define DB_PWM_ADDR_RESERVED0_SHIFT 0 946 #define DB_PWM_ADDR_OFFSET_MASK 0x7F /* Offset in PWM address space */ 947 #define DB_PWM_ADDR_OFFSET_SHIFT 3 948 #define DB_PWM_ADDR_WID_MASK 0x3 /* Window ID */ 949 #define DB_PWM_ADDR_WID_SHIFT 10 950 #define DB_PWM_ADDR_DPI_MASK 0xFFFF /* Doorbell page ID */ 951 #define DB_PWM_ADDR_DPI_SHIFT 12 952 #define DB_PWM_ADDR_RESERVED1_MASK 0xF 953 #define DB_PWM_ADDR_RESERVED1_SHIFT 28 954 }; 955 956 /* 957 * Parameters to RDMA firmware, passed in EDPM doorbell 958 */ 959 struct db_rdma_dpm_params 960 { 961 __le32 params; 962 #define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F /* Size in QWORD-s of the DPM burst */ 963 #define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0 964 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3 /* Type of DPM transacation (DPM_RDMA) (use enum db_dpm_type) */ 965 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6 966 #define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF /* opcode for RDMA operation */ 967 #define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8 968 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF /* the size of the WQE payload in bytes */ 969 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16 970 #define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1 971 #define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27 972 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 /* RoCE completion flag */ 973 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28 974 #define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1 /* RoCE S flag */ 975 #define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29 976 #define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x1 977 #define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30 978 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1 /* Connection type is iWARP */ 979 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31 980 }; 981 982 /* 983 * Structure for doorbell data, in RDMA DPM mode, for the first doorbell in a DPM burst 984 */ 985 struct db_rdma_dpm_data 986 { 987 __le16 icid /* internal CID */; 988 __le16 prod_val /* aggregated value to update */; 989 struct db_rdma_dpm_params params /* parametes passed to RDMA firmware */; 990 }; 991 992 /* 993 * Igu interrupt command 994 */ 995 enum igu_int_cmd 996 { 997 IGU_INT_ENABLE=0, 998 IGU_INT_DISABLE=1, 999 IGU_INT_NOP=2, 1000 IGU_INT_NOP2=3, 1001 MAX_IGU_INT_CMD 1002 }; 1003 1004 /* 1005 * IGU producer or consumer update command 1006 */ 1007 struct igu_prod_cons_update 1008 { 1009 __le32 sb_id_and_flags; 1010 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF 1011 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0 1012 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1 1013 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24 1014 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3 /* interrupt enable/disable/nop (use enum igu_int_cmd) */ 1015 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25 1016 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1 /* (use enum igu_seg_access) */ 1017 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27 1018 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1 1019 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28 1020 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3 1021 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29 1022 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1 /* must always be set cleared (use enum command_type_bit) */ 1023 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31 1024 __le32 reserved1; 1025 }; 1026 1027 /* 1028 * Igu segments access for default status block only 1029 */ 1030 enum igu_seg_access 1031 { 1032 IGU_SEG_ACCESS_REG=0, 1033 IGU_SEG_ACCESS_ATTN=1, 1034 MAX_IGU_SEG_ACCESS 1035 }; 1036 1037 /* 1038 * Enumeration for L3 type field of parsing_and_err_flags. L3Type: 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled according to the last-ethertype) 1039 */ 1040 enum l3_type 1041 { 1042 e_l3_type_unknown, 1043 e_l3_type_ipv4, 1044 e_l3_type_ipv6, 1045 MAX_L3_TYPE 1046 }; 1047 1048 /* 1049 * Enumeration for l4Protocol field of parsing_and_err_flags. L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the first fragment, the protocol-type should be set to none. 1050 */ 1051 enum l4_protocol 1052 { 1053 e_l4_protocol_none, 1054 e_l4_protocol_tcp, 1055 e_l4_protocol_udp, 1056 MAX_L4_PROTOCOL 1057 }; 1058 1059 /* 1060 * Parsing and error flags field. 1061 */ 1062 struct parsing_and_err_flags 1063 { 1064 __le16 flags; 1065 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3 /* L3Type: 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled according to the last-ethertype) (use enum l3_type) */ 1066 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0 1067 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3 /* L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the first fragment, the protocol-type should be set to none. (use enum l4_protocol) */ 1068 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2 1069 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1 /* Set if the packet is IPv4/IPv6 fragment. */ 1070 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4 1071 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1 /* corresponds to the same 8021q tag that is selected for 8021q-tag fiel. This flag should be set if the tag appears in the packet, regardless of its value. */ 1072 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5 1073 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1 /* Set if L4 checksum was calculated. taken from the EOP descriptor. */ 1074 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6 1075 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1 /* Set for PTP packet. */ 1076 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7 1077 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1 /* Set if PTP timestamp recorded. */ 1078 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8 1079 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1 /* Set if either version-mismatch or hdr-len-error or ipv4-cksm is set or ipv6 ver mismatch */ 1080 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9 1081 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1 /* Set if L4 checksum validation failed. Valid only if L4 checksum was calculated. */ 1082 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10 1083 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1 /* Set if GRE/VXLAN/GENEVE tunnel detected. */ 1084 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11 1085 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1 /* This flag should be set if the tag appears in the packet tunnel header, regardless of its value.. */ 1086 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12 1087 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1 /* Set if either tunnel-ipv4-version-mismatch or tunnel-ipv4-hdr-len-error or tunnel-ipv4-cksm is set or tunneling ipv6 ver mismatch */ 1088 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13 1089 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1 /* taken from the EOP descriptor. */ 1090 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14 1091 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1 /* Set if tunnel L4 checksum validation failed. Valid only if tunnel L4 checksum was calculated. */ 1092 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15 1093 }; 1094 1095 /* 1096 * Parsing error flags bitmap. 1097 */ 1098 struct parsing_err_flags 1099 { 1100 __le16 flags; 1101 #define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1 /* MAC error indication */ 1102 #define PARSING_ERR_FLAGS_MAC_ERROR_SHIFT 0 1103 #define PARSING_ERR_FLAGS_TRUNC_ERROR_MASK 0x1 /* truncation error indication */ 1104 #define PARSING_ERR_FLAGS_TRUNC_ERROR_SHIFT 1 1105 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_MASK 0x1 /* packet too small indication */ 1106 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_SHIFT 2 1107 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_MASK 0x1 /* Header Missing Tag */ 1108 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_SHIFT 3 1109 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_MASK 0x1 /* from frame cracker output */ 1110 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_SHIFT 4 1111 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_MASK 0x1 /* from frame cracker output */ 1112 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_SHIFT 5 1113 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_MASK 0x1 /* set this error if: 1. total-len is smaller than hdr-len 2. total-ip-len indicates number that is bigger than real packet length 3. tunneling: total-ip-length of the outer header points to offset that is smaller than the one pointed to by the total-ip-len of the inner hdr. */ 1114 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_SHIFT 6 1115 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_MASK 0x1 /* from frame cracker output */ 1116 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_SHIFT 7 1117 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_MASK 0x1 /* from frame cracker output. for either TCP or UDP */ 1118 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_SHIFT 8 1119 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_MASK 0x1 /* from frame cracker output */ 1120 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_SHIFT 9 1121 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_MASK 0x1 /* cksm calculated and value isnt 0xffff or L4-cksm-wasnt-calculated for any reason, like: udp/ipv4 checksum is 0 etc. */ 1122 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_SHIFT 10 1123 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_MASK 0x1 /* from frame cracker output */ 1124 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_SHIFT 11 1125 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_MASK 0x1 /* from frame cracker output */ 1126 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_SHIFT 12 1127 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_MASK 0x1 /* set if geneve option size was over 32 byte */ 1128 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_SHIFT 13 1129 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_MASK 0x1 /* from frame cracker output */ 1130 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_SHIFT 14 1131 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_MASK 0x1 /* from frame cracker output */ 1132 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT 15 1133 }; 1134 1135 /* 1136 * Pb context 1137 */ 1138 struct pb_context 1139 { 1140 __le32 crc[4]; 1141 }; 1142 1143 /* 1144 * Concrete Function ID. 1145 */ 1146 struct pxp_concrete_fid 1147 { 1148 __le16 fid; 1149 #define PXP_CONCRETE_FID_PFID_MASK 0xF /* Parent PFID */ 1150 #define PXP_CONCRETE_FID_PFID_SHIFT 0 1151 #define PXP_CONCRETE_FID_PORT_MASK 0x3 /* port number */ 1152 #define PXP_CONCRETE_FID_PORT_SHIFT 4 1153 #define PXP_CONCRETE_FID_PATH_MASK 0x1 /* path number */ 1154 #define PXP_CONCRETE_FID_PATH_SHIFT 6 1155 #define PXP_CONCRETE_FID_VFVALID_MASK 0x1 1156 #define PXP_CONCRETE_FID_VFVALID_SHIFT 7 1157 #define PXP_CONCRETE_FID_VFID_MASK 0xFF 1158 #define PXP_CONCRETE_FID_VFID_SHIFT 8 1159 }; 1160 1161 /* 1162 * Concrete Function ID. 1163 */ 1164 struct pxp_pretend_concrete_fid 1165 { 1166 __le16 fid; 1167 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF /* Parent PFID */ 1168 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0 1169 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7 /* port number. Only when part of ME register. */ 1170 #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4 1171 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1 1172 #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7 1173 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF 1174 #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8 1175 }; 1176 1177 /* 1178 * Function ID. 1179 */ 1180 union pxp_pretend_fid 1181 { 1182 struct pxp_pretend_concrete_fid concrete_fid; 1183 __le16 opaque_fid; 1184 }; 1185 1186 /* 1187 * Pxp Pretend Command Register. 1188 */ 1189 struct pxp_pretend_cmd 1190 { 1191 union pxp_pretend_fid fid; 1192 __le16 control; 1193 #define PXP_PRETEND_CMD_PATH_MASK 0x1 1194 #define PXP_PRETEND_CMD_PATH_SHIFT 0 1195 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1 1196 #define PXP_PRETEND_CMD_USE_PORT_SHIFT 1 1197 #define PXP_PRETEND_CMD_PORT_MASK 0x3 1198 #define PXP_PRETEND_CMD_PORT_SHIFT 2 1199 #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF 1200 #define PXP_PRETEND_CMD_RESERVED0_SHIFT 4 1201 #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF 1202 #define PXP_PRETEND_CMD_RESERVED1_SHIFT 8 1203 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1 /* is pretend mode? */ 1204 #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12 1205 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1 /* is pretend mode? */ 1206 #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13 1207 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1 /* is pretend mode? */ 1208 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14 1209 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1 /* is fid concrete? */ 1210 #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15 1211 }; 1212 1213 /* 1214 * PTT Record in PXP Admin Window. 1215 */ 1216 struct pxp_ptt_entry 1217 { 1218 __le32 offset; 1219 #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF 1220 #define PXP_PTT_ENTRY_OFFSET_SHIFT 0 1221 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF 1222 #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23 1223 struct pxp_pretend_cmd pretend; 1224 }; 1225 1226 /* 1227 * VF Zone A Permission Register. 1228 */ 1229 struct pxp_vf_zone_a_permission 1230 { 1231 __le32 control; 1232 #define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF 1233 #define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0 1234 #define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1 1235 #define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8 1236 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F 1237 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9 1238 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF 1239 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16 1240 }; 1241 1242 /* 1243 * Rdif context 1244 */ 1245 struct rdif_task_context 1246 { 1247 __le32 initial_ref_tag; 1248 __le16 app_tag_value; 1249 __le16 app_tag_mask; 1250 u8 flags0; 1251 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1 1252 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0 1253 #define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1 1254 #define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1 1255 #define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1 /* 0 = IP checksum, 1 = CRC */ 1256 #define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2 1257 #define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1 1258 #define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3 1259 #define RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3 /* 1/2/3 - Protection Type */ 1260 #define RDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4 1261 #define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 /* 0=0x0000, 1=0xffff */ 1262 #define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1263 #define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1 /* Keep reference tag constant */ 1264 #define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 7 1265 u8 partial_dif_data[7]; 1266 __le16 partial_crc_value; 1267 __le16 partial_checksum_value; 1268 __le32 offset_in_io; 1269 __le16 flags1; 1270 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1 1271 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0 1272 #define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1 1273 #define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1 1274 #define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1 1275 #define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2 1276 #define RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1 1277 #define RDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3 1278 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1 1279 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4 1280 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1 1281 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5 1282 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */ 1283 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6 1284 #define RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3 /* 0=None, 1=DIF, 2=DIX */ 1285 #define RDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9 1286 #define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1 /* DIF tag right at the beginning of DIF interval */ 1287 #define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11 1288 #define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1 1289 #define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12 1290 #define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1 /* 0=None, 1=DIF */ 1291 #define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13 1292 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1 /* Forward application tag with mask */ 1293 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 14 1294 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1 /* Forward reference tag with mask */ 1295 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 15 1296 __le16 state; 1297 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK 0xF 1298 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT 0 1299 #define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK 0xF 1300 #define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_SHIFT 4 1301 #define RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK 0x1 1302 #define RDIF_TASK_CONTEXT_ERROR_IN_IO_SHIFT 8 1303 #define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK 0x1 1304 #define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_SHIFT 9 1305 #define RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF /* mask for refernce tag handling */ 1306 #define RDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 10 1307 #define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3 1308 #define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14 1309 __le32 reserved2; 1310 }; 1311 1312 /* 1313 * status block structure 1314 */ 1315 struct status_block_e4 1316 { 1317 __le16 pi_array[PIS_PER_SB_E4]; 1318 __le32 sb_num; 1319 #define STATUS_BLOCK_E4_SB_NUM_MASK 0x1FF 1320 #define STATUS_BLOCK_E4_SB_NUM_SHIFT 0 1321 #define STATUS_BLOCK_E4_ZERO_PAD_MASK 0x7F 1322 #define STATUS_BLOCK_E4_ZERO_PAD_SHIFT 9 1323 #define STATUS_BLOCK_E4_ZERO_PAD2_MASK 0xFFFF 1324 #define STATUS_BLOCK_E4_ZERO_PAD2_SHIFT 16 1325 __le32 prod_index; 1326 #define STATUS_BLOCK_E4_PROD_INDEX_MASK 0xFFFFFF 1327 #define STATUS_BLOCK_E4_PROD_INDEX_SHIFT 0 1328 #define STATUS_BLOCK_E4_ZERO_PAD3_MASK 0xFF 1329 #define STATUS_BLOCK_E4_ZERO_PAD3_SHIFT 24 1330 }; 1331 1332 /* 1333 * status block structure 1334 */ 1335 struct status_block_e5 1336 { 1337 __le16 pi_array[PIS_PER_SB_E5]; 1338 __le32 sb_num; 1339 #define STATUS_BLOCK_E5_SB_NUM_MASK 0x1FF 1340 #define STATUS_BLOCK_E5_SB_NUM_SHIFT 0 1341 #define STATUS_BLOCK_E5_ZERO_PAD_MASK 0x7F 1342 #define STATUS_BLOCK_E5_ZERO_PAD_SHIFT 9 1343 #define STATUS_BLOCK_E5_ZERO_PAD2_MASK 0xFFFF 1344 #define STATUS_BLOCK_E5_ZERO_PAD2_SHIFT 16 1345 __le32 prod_index; 1346 #define STATUS_BLOCK_E5_PROD_INDEX_MASK 0xFFFFFF 1347 #define STATUS_BLOCK_E5_PROD_INDEX_SHIFT 0 1348 #define STATUS_BLOCK_E5_ZERO_PAD3_MASK 0xFF 1349 #define STATUS_BLOCK_E5_ZERO_PAD3_SHIFT 24 1350 }; 1351 1352 /* 1353 * Tdif context 1354 */ 1355 struct tdif_task_context 1356 { 1357 __le32 initial_ref_tag; 1358 __le16 app_tag_value; 1359 __le16 app_tag_mask; 1360 __le16 partial_crc_value_b; 1361 __le16 partial_checksum_value_b; 1362 __le16 stateB; 1363 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK 0xF 1364 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT 0 1365 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK 0xF 1366 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_SHIFT 4 1367 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK 0x1 1368 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_SHIFT 8 1369 #define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK 0x1 1370 #define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_SHIFT 9 1371 #define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F 1372 #define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10 1373 u8 reserved1; 1374 u8 flags0; 1375 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1 1376 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0 1377 #define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1 1378 #define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1 1379 #define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1 /* 0 = IP checksum, 1 = CRC */ 1380 #define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2 1381 #define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1 1382 #define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3 1383 #define TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3 /* 1/2/3 - Protection Type */ 1384 #define TDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4 1385 #define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 /* 0=0x0000, 1=0xffff */ 1386 #define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1387 #define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1 1388 #define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7 1389 __le32 flags1; 1390 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1 1391 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0 1392 #define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1 1393 #define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1 1394 #define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1 1395 #define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2 1396 #define TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1 1397 #define TDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3 1398 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1 1399 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4 1400 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1 1401 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5 1402 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */ 1403 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6 1404 #define TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3 /* 0=None, 1=DIF, 2=DIX */ 1405 #define TDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9 1406 #define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1 /* DIF tag right at the beginning of DIF interval */ 1407 #define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11 1408 #define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1 /* reserved */ 1409 #define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12 1410 #define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1 /* 0=None, 1=DIF */ 1411 #define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13 1412 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK 0xF 1413 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_SHIFT 14 1414 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK 0xF 1415 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_SHIFT 18 1416 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK 0x1 1417 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_SHIFT 22 1418 #define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK 0x1 1419 #define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_SHIFT 23 1420 #define TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF /* mask for refernce tag handling */ 1421 #define TDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 24 1422 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1 /* Forward application tag with mask */ 1423 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 28 1424 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1 /* Forward reference tag with mask */ 1425 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 29 1426 #define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1 /* Keep reference tag constant */ 1427 #define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 30 1428 #define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1 1429 #define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31 1430 __le32 offset_in_io_b; 1431 __le16 partial_crc_value_a; 1432 __le16 partial_checksum_value_a; 1433 __le32 offset_in_io_a; 1434 u8 partial_dif_data_a[8]; 1435 u8 partial_dif_data_b[8]; 1436 }; 1437 1438 /* 1439 * Timers context 1440 */ 1441 struct timers_context 1442 { 1443 __le32 logical_client_0; 1444 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF /* Expiration time of logical client 0 */ 1445 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0 1446 #define TIMERS_CONTEXT_RESERVED0_MASK 0x1 1447 #define TIMERS_CONTEXT_RESERVED0_SHIFT 27 1448 #define TIMERS_CONTEXT_VALIDLC0_MASK 0x1 /* Valid bit of logical client 0 */ 1449 #define TIMERS_CONTEXT_VALIDLC0_SHIFT 28 1450 #define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1 /* Active bit of logical client 0 */ 1451 #define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29 1452 #define TIMERS_CONTEXT_RESERVED1_MASK 0x3 1453 #define TIMERS_CONTEXT_RESERVED1_SHIFT 30 1454 __le32 logical_client_1; 1455 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0x7FFFFFF /* Expiration time of logical client 1 */ 1456 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0 1457 #define TIMERS_CONTEXT_RESERVED2_MASK 0x1 1458 #define TIMERS_CONTEXT_RESERVED2_SHIFT 27 1459 #define TIMERS_CONTEXT_VALIDLC1_MASK 0x1 /* Valid bit of logical client 1 */ 1460 #define TIMERS_CONTEXT_VALIDLC1_SHIFT 28 1461 #define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1 /* Active bit of logical client 1 */ 1462 #define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29 1463 #define TIMERS_CONTEXT_RESERVED3_MASK 0x3 1464 #define TIMERS_CONTEXT_RESERVED3_SHIFT 30 1465 __le32 logical_client_2; 1466 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0x7FFFFFF /* Expiration time of logical client 2 */ 1467 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0 1468 #define TIMERS_CONTEXT_RESERVED4_MASK 0x1 1469 #define TIMERS_CONTEXT_RESERVED4_SHIFT 27 1470 #define TIMERS_CONTEXT_VALIDLC2_MASK 0x1 /* Valid bit of logical client 2 */ 1471 #define TIMERS_CONTEXT_VALIDLC2_SHIFT 28 1472 #define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1 /* Active bit of logical client 2 */ 1473 #define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29 1474 #define TIMERS_CONTEXT_RESERVED5_MASK 0x3 1475 #define TIMERS_CONTEXT_RESERVED5_SHIFT 30 1476 __le32 host_expiration_fields; 1477 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0x7FFFFFF /* Expiration time on host (closest one) */ 1478 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0 1479 #define TIMERS_CONTEXT_RESERVED6_MASK 0x1 1480 #define TIMERS_CONTEXT_RESERVED6_SHIFT 27 1481 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1 /* Valid bit of host expiration */ 1482 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28 1483 #define TIMERS_CONTEXT_RESERVED7_MASK 0x7 1484 #define TIMERS_CONTEXT_RESERVED7_SHIFT 29 1485 }; 1486 1487 /* 1488 * Enum for next_protocol field of tunnel_parsing_flags / tunnelTypeDesc 1489 */ 1490 enum tunnel_next_protocol 1491 { 1492 e_unknown=0, 1493 e_l2=1, 1494 e_ipv4=2, 1495 e_ipv6=3, 1496 MAX_TUNNEL_NEXT_PROTOCOL 1497 }; 1498 1499 #endif /* __COMMON_HSI__ */ 1500