xref: /illumos-gate/usr/src/uts/i86pc/sys/mach_mmu.h (revision e309284527479df5fbac1270f2abd4a739f1ab72)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  *
25  * Copyright 2018 Joyent, Inc.
26  * Copyright 2022 Tintri by DDN, Inc. All rights reserved.
27  */
28 
29 #ifndef _SYS_MACH_MMU_H
30 #define	_SYS_MACH_MMU_H
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
36 #ifndef _ASM
37 
38 #include <sys/types.h>
39 #include <sys/systm.h>
40 
41 /*
42  * Platform-dependent MMU routines and types.
43  *
44  * WARNING: this header file is used by both dboot and i86pc, so don't go using
45  * normal kernel headers.
46  */
47 
48 #define	TWO_MEG		(2 * 1024 * 1024)
49 
50 /*
51  * This is:
52  *	The kernel nucleus pagesizes, ie: bi->bi_kseg_size
53  *	The grub 64 bit file load address (see multiboot header in dboot_grub.s)
54  *	The grub 32 bit and hypervisor physical load addresses of
55  *	    the kernel text/data (see Mapfile.unix)
56  */
57 #define	FOUR_MEG	(4 * 1024 * 1024)
58 
59 #define	ONE_GIG		(1024 * 1024 * 1024)
60 #define	FOUR_GIG	((uint64_t)4 * ONE_GIG)
61 
62 #define	MMU_STD_PAGESIZE	4096
63 
64 /*
65  * Defines for 4 and 5 level Virtual address ranges
66  */
67 #define	MMU_NPGOFFBITS		12
68 #define	MMU_NPTIXBITS		9
69 #define	MMU_MAX4LEVELVABITS	(4 * MMU_NPTIXBITS + MMU_NPGOFFBITS)
70 #define	MMU_MAX5LEVELVABITS	(5 * MMU_NPTIXBITS + MMU_NPGOFFBITS)
71 
72 #ifdef __amd64
73 #define	MMU_STD_PAGEMASK	0xFFFFFFFFFFFFF000ULL
74 #else
75 #define	MMU_STD_PAGEMASK	0xFFFFF000UL
76 #endif
77 
78 /*
79  * Defines for the bits in X86 and AMD64 Page Tables
80  *
81  * Notes:
82  *
83  * Largepages and PAT bits:
84  *
85  * bit 7 at level 0 is the PAT bit
86  * bit 7 above level 0 is the Pagesize bit (set for large page)
87  * bit 12 (when a large page) is the PAT bit
88  *
89  * In Solaris the PAT/PWT/PCD values are set up so that:
90  *
91  * PAT & PWT -> Write Protected
92  * PAT & PCD -> Write Combining
93  * PAT by itself (PWT == 0 && PCD == 0) yields uncacheable (same as PCD == 1)
94  *
95  *
96  * Permission bits:
97  *
98  * - PT_USER must be set in all levels for user pages
99  * - PT_WRITE must be set in all levels for user writable pages
100  * - PT_NX applies if set at any level
101  *
102  * For these, we use the "allow" settings in all tables above level 0 and only
103  * ever disable things in PTEs.
104  *
105  * The use of PT_GLOBAL and PT_NX depend on being enabled in processor
106  * control registers. Hence, we use a variable to reference these bit
107  * masks. During hat_kern_setup() if the feature isn't enabled we
108  * clear out the variables.
109  */
110 #define	PT_VALID	(0x001)	/* a valid translation is present */
111 #define	PT_WRITABLE	(0x002)	/* the page is writable */
112 #define	PT_USER		(0x004)	/* the page is accessible by user mode */
113 #define	PT_WRITETHRU	(0x008)	/* write back caching is disabled (non-PAT) */
114 #define	PT_NOCACHE	(0x010)	/* page is not cacheable (non-PAT) */
115 #define	PT_REF		(0x020)	/* page was referenced */
116 #define	PT_MOD		(0x040)	/* page was modified */
117 #define	PT_PAGESIZE	(0x080)	/* above level 0, indicates a large page */
118 #define	PT_PAT_4K	(0x080) /* at level 0, used for write combining */
119 #define	PT_GLOBAL	(0x100)	/* the mapping is global */
120 #define	PT_SOFTWARE	(0xe00)	/* software bits */
121 
122 #define	PT_PAT_LARGE	(0x1000)	/* PAT bit for large pages */
123 
124 #define	PT_PTPBITS	(PT_VALID | PT_USER | PT_WRITABLE | PT_REF)
125 #define	PT_FLAGBITS	(0xfff)	/* for masking off flag bits */
126 
127 /*
128  * The software bits are used by the HAT to track attributes.
129  * Note that the attributes are inclusive as the values increase.
130  *
131  * PT_NOSYNC - The PT_REF/PT_MOD bits are not sync'd to page_t.
132  *             The hat will install them as always set.
133  *
134  * PT_NOCONSIST - There is no hment entry for this mapping.
135  *
136  * PT_FOREIGN - used for the hypervisor, check via
137  *		(pte & PT_SOFTWARE) >= PT_FOREIGN
138  *		as it might set	0x800 for foreign grant table mappings.
139  */
140 #define	PT_NOSYNC	(0x200)	/* PTE was created with HAT_NOSYNC */
141 #define	PT_NOCONSIST	(0x400)	/* PTE was created with HAT_LOAD_NOCONSIST */
142 #define	PT_FOREIGN	(0x600)	/* MFN mapped on the hypervisor has no PFN */
143 
144 #ifndef _BOOT
145 
146 extern ulong_t getcr3(void);
147 extern void setcr3(ulong_t);
148 
149 #define	getcr3_pa() (getcr3() & MMU_PAGEMASK)
150 #define	getpcid() ((getcr4() & CR4_PCIDE) ? \
151 	(getcr3() & MMU_PAGEOFFSET) : PCID_NONE)
152 
153 extern void mmu_invlpg(caddr_t);
154 
155 #endif
156 
157 #ifdef __xpv
158 #include <sys/xen_mmu.h>
159 #else
160 #include <sys/pc_mmu.h>
161 #endif
162 
163 /*
164  * The software extraction for a single Page Table Entry will always
165  * be a 64 bit unsigned int. If running a non-PAE hat, the page table
166  * access routines know to extend/shorten it to 32 bits.
167  */
168 typedef uint64_t x86pte_t;
169 typedef uint32_t x86pte32_t;
170 
171 x86pte_t get_pteval(paddr_t, uint_t);
172 void set_pteval(paddr_t, uint_t, uint_t, x86pte_t);
173 paddr_t make_ptable(x86pte_t *, uint_t);
174 x86pte_t *find_pte(uint64_t, paddr_t *, uint_t, uint_t);
175 x86pte_t *map_pte(paddr_t, uint_t);
176 
177 extern uint_t *shift_amt;
178 extern uint_t ptes_per_table;
179 extern paddr_t top_page_table;
180 extern uint_t top_level;
181 extern uint_t pte_size;
182 extern uint_t shift_amt_nopae[];
183 extern uint_t shift_amt_pae[];
184 extern uint32_t lpagesize;
185 
186 #ifdef __cplusplus
187 }
188 #endif
189 
190 #endif /* _ASM */
191 
192 #endif	/* _SYS_MACH_MMU_H */
193