1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * SMP support for power macintosh.
4 *
5 * We support both the old "powersurge" SMP architecture
6 * and the current Core99 (G4 PowerMac) machines.
7 *
8 * Note that we don't support the very first rev. of
9 * Apple/DayStar 2 CPUs board, the one with the funky
10 * watchdog. Hopefully, none of these should be there except
11 * maybe internally to Apple. I should probably still add some
12 * code to detect this card though and disable SMP. --BenH.
13 *
14 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
15 * and Ben Herrenschmidt <benh@kernel.crashing.org>.
16 *
17 * Support for DayStar quad CPU cards
18 * Copyright (C) XLR8, Inc. 1994-2000
19 */
20 #include <linux/kernel.h>
21 #include <linux/sched.h>
22 #include <linux/sched/hotplug.h>
23 #include <linux/smp.h>
24 #include <linux/interrupt.h>
25 #include <linux/irqdomain.h>
26 #include <linux/kernel_stat.h>
27 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/spinlock.h>
30 #include <linux/errno.h>
31 #include <linux/hardirq.h>
32 #include <linux/cpu.h>
33 #include <linux/compiler.h>
34 #include <linux/pgtable.h>
35
36 #include <asm/ptrace.h>
37 #include <linux/atomic.h>
38 #include <asm/code-patching.h>
39 #include <asm/irq.h>
40 #include <asm/page.h>
41 #include <asm/sections.h>
42 #include <asm/io.h>
43 #include <asm/smp.h>
44 #include <asm/machdep.h>
45 #include <asm/pmac_feature.h>
46 #include <asm/time.h>
47 #include <asm/mpic.h>
48 #include <asm/cacheflush.h>
49 #include <asm/keylargo.h>
50 #include <asm/pmac_low_i2c.h>
51 #include <asm/pmac_pfunc.h>
52 #include <asm/inst.h>
53
54 #include "pmac.h"
55
56 #undef DEBUG
57
58 #ifdef DEBUG
59 #define DBG(fmt...) udbg_printf(fmt)
60 #else
61 #define DBG(fmt...)
62 #endif
63
64 extern void __secondary_start_pmac_0(void);
65
66 static void (*pmac_tb_freeze)(int freeze);
67 static u64 timebase;
68 static int tb_req;
69
70 #ifdef CONFIG_PPC_PMAC32_PSURGE
71
72 /*
73 * Powersurge (old powermac SMP) support.
74 */
75
76 /* Addresses for powersurge registers */
77 #define HAMMERHEAD_BASE 0xf8000000
78 #define HHEAD_CONFIG 0x90
79 #define HHEAD_SEC_INTR 0xc0
80
81 /* register for interrupting the primary processor on the powersurge */
82 /* N.B. this is actually the ethernet ROM! */
83 #define PSURGE_PRI_INTR 0xf3019000
84
85 /* register for storing the start address for the secondary processor */
86 /* N.B. this is the PCI config space address register for the 1st bridge */
87 #define PSURGE_START 0xf2800000
88
89 /* Daystar/XLR8 4-CPU card */
90 #define PSURGE_QUAD_REG_ADDR 0xf8800000
91
92 #define PSURGE_QUAD_IRQ_SET 0
93 #define PSURGE_QUAD_IRQ_CLR 1
94 #define PSURGE_QUAD_IRQ_PRIMARY 2
95 #define PSURGE_QUAD_CKSTOP_CTL 3
96 #define PSURGE_QUAD_PRIMARY_ARB 4
97 #define PSURGE_QUAD_BOARD_ID 6
98 #define PSURGE_QUAD_WHICH_CPU 7
99 #define PSURGE_QUAD_CKSTOP_RDBK 8
100 #define PSURGE_QUAD_RESET_CTL 11
101
102 #define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v)))
103 #define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
104 #define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
105 #define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
106
107 /* virtual addresses for the above */
108 static volatile u8 __iomem *hhead_base;
109 static volatile u8 __iomem *quad_base;
110 static volatile u32 __iomem *psurge_pri_intr;
111 static volatile u8 __iomem *psurge_sec_intr;
112 static volatile u32 __iomem *psurge_start;
113
114 /* values for psurge_type */
115 #define PSURGE_NONE -1
116 #define PSURGE_DUAL 0
117 #define PSURGE_QUAD_OKEE 1
118 #define PSURGE_QUAD_COTTON 2
119 #define PSURGE_QUAD_ICEGRASS 3
120
121 /* what sort of powersurge board we have */
122 static int psurge_type = PSURGE_NONE;
123
124 /* irq for secondary cpus to report */
125 static struct irq_domain *psurge_host;
126 int psurge_secondary_virq;
127
128 /*
129 * Set and clear IPIs for powersurge.
130 */
psurge_set_ipi(int cpu)131 static inline void psurge_set_ipi(int cpu)
132 {
133 if (psurge_type == PSURGE_NONE)
134 return;
135 if (cpu == 0)
136 in_be32(psurge_pri_intr);
137 else if (psurge_type == PSURGE_DUAL)
138 out_8(psurge_sec_intr, 0);
139 else
140 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
141 }
142
psurge_clr_ipi(int cpu)143 static inline void psurge_clr_ipi(int cpu)
144 {
145 if (cpu > 0) {
146 switch(psurge_type) {
147 case PSURGE_DUAL:
148 out_8(psurge_sec_intr, ~0);
149 break;
150 case PSURGE_NONE:
151 break;
152 default:
153 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
154 }
155 }
156 }
157
158 /*
159 * On powersurge (old SMP powermac architecture) we don't have
160 * separate IPIs for separate messages like openpic does. Instead
161 * use the generic demux helpers
162 * -- paulus.
163 */
psurge_ipi_intr(int irq,void * d)164 static irqreturn_t psurge_ipi_intr(int irq, void *d)
165 {
166 psurge_clr_ipi(smp_processor_id());
167 smp_ipi_demux();
168
169 return IRQ_HANDLED;
170 }
171
smp_psurge_cause_ipi(int cpu)172 static void smp_psurge_cause_ipi(int cpu)
173 {
174 psurge_set_ipi(cpu);
175 }
176
psurge_host_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)177 static int psurge_host_map(struct irq_domain *h, unsigned int virq,
178 irq_hw_number_t hw)
179 {
180 irq_set_chip_and_handler(virq, &dummy_irq_chip, handle_percpu_irq);
181
182 return 0;
183 }
184
185 static const struct irq_domain_ops psurge_host_ops = {
186 .map = psurge_host_map,
187 };
188
psurge_secondary_ipi_init(void)189 static int __init psurge_secondary_ipi_init(void)
190 {
191 int rc = -ENOMEM;
192
193 psurge_host = irq_domain_add_nomap(NULL, ~0, &psurge_host_ops, NULL);
194
195 if (psurge_host)
196 psurge_secondary_virq = irq_create_direct_mapping(psurge_host);
197
198 if (psurge_secondary_virq)
199 rc = request_irq(psurge_secondary_virq, psurge_ipi_intr,
200 IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL);
201
202 if (rc)
203 pr_err("Failed to setup secondary cpu IPI\n");
204
205 return rc;
206 }
207
208 /*
209 * Determine a quad card presence. We read the board ID register, we
210 * force the data bus to change to something else, and we read it again.
211 * It it's stable, then the register probably exist (ugh !)
212 */
psurge_quad_probe(void)213 static int __init psurge_quad_probe(void)
214 {
215 int type;
216 unsigned int i;
217
218 type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
219 if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
220 || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
221 return PSURGE_DUAL;
222
223 /* looks OK, try a slightly more rigorous test */
224 /* bogus is not necessarily cacheline-aligned,
225 though I don't suppose that really matters. -- paulus */
226 for (i = 0; i < 100; i++) {
227 volatile u32 bogus[8];
228 bogus[(0+i)%8] = 0x00000000;
229 bogus[(1+i)%8] = 0x55555555;
230 bogus[(2+i)%8] = 0xFFFFFFFF;
231 bogus[(3+i)%8] = 0xAAAAAAAA;
232 bogus[(4+i)%8] = 0x33333333;
233 bogus[(5+i)%8] = 0xCCCCCCCC;
234 bogus[(6+i)%8] = 0xCCCCCCCC;
235 bogus[(7+i)%8] = 0x33333333;
236 wmb();
237 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
238 mb();
239 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
240 return PSURGE_DUAL;
241 }
242 return type;
243 }
244
psurge_quad_init(void)245 static void __init psurge_quad_init(void)
246 {
247 int procbits;
248
249 if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
250 procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
251 if (psurge_type == PSURGE_QUAD_ICEGRASS)
252 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
253 else
254 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
255 mdelay(33);
256 out_8(psurge_sec_intr, ~0);
257 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
258 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
259 if (psurge_type != PSURGE_QUAD_ICEGRASS)
260 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
261 PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
262 mdelay(33);
263 PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
264 mdelay(33);
265 PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
266 mdelay(33);
267 }
268
smp_psurge_probe(void)269 static void __init smp_psurge_probe(void)
270 {
271 int i, ncpus;
272 struct device_node *dn;
273
274 /*
275 * The powersurge cpu board can be used in the generation
276 * of powermacs that have a socket for an upgradeable cpu card,
277 * including the 7500, 8500, 9500, 9600.
278 * The device tree doesn't tell you if you have 2 cpus because
279 * OF doesn't know anything about the 2nd processor.
280 * Instead we look for magic bits in magic registers,
281 * in the hammerhead memory controller in the case of the
282 * dual-cpu powersurge board. -- paulus.
283 */
284 dn = of_find_node_by_name(NULL, "hammerhead");
285 if (dn == NULL)
286 return;
287 of_node_put(dn);
288
289 hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
290 quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
291 psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
292
293 psurge_type = psurge_quad_probe();
294 if (psurge_type != PSURGE_DUAL) {
295 psurge_quad_init();
296 /* All released cards using this HW design have 4 CPUs */
297 ncpus = 4;
298 /* No sure how timebase sync works on those, let's use SW */
299 smp_ops->give_timebase = smp_generic_give_timebase;
300 smp_ops->take_timebase = smp_generic_take_timebase;
301 } else {
302 iounmap(quad_base);
303 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
304 /* not a dual-cpu card */
305 iounmap(hhead_base);
306 psurge_type = PSURGE_NONE;
307 return;
308 }
309 ncpus = 2;
310 }
311
312 if (psurge_secondary_ipi_init())
313 return;
314
315 psurge_start = ioremap(PSURGE_START, 4);
316 psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
317
318 /* This is necessary because OF doesn't know about the
319 * secondary cpu(s), and thus there aren't nodes in the
320 * device tree for them, and smp_setup_cpu_maps hasn't
321 * set their bits in cpu_present_mask.
322 */
323 if (ncpus > NR_CPUS)
324 ncpus = NR_CPUS;
325 for (i = 1; i < ncpus ; ++i)
326 set_cpu_present(i, true);
327
328 if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
329 }
330
smp_psurge_kick_cpu(int nr)331 static int __init smp_psurge_kick_cpu(int nr)
332 {
333 unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8;
334 unsigned long a, flags;
335 int i, j;
336
337 /* Defining this here is evil ... but I prefer hiding that
338 * crap to avoid giving people ideas that they can do the
339 * same.
340 */
341 extern volatile unsigned int cpu_callin_map[NR_CPUS];
342
343 /* may need to flush here if secondary bats aren't setup */
344 for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
345 asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
346 asm volatile("sync");
347
348 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
349
350 /* This is going to freeze the timeebase, we disable interrupts */
351 local_irq_save(flags);
352
353 out_be32(psurge_start, start);
354 mb();
355
356 psurge_set_ipi(nr);
357
358 /*
359 * We can't use udelay here because the timebase is now frozen.
360 */
361 for (i = 0; i < 2000; ++i)
362 asm volatile("nop" : : : "memory");
363 psurge_clr_ipi(nr);
364
365 /*
366 * Also, because the timebase is frozen, we must not return to the
367 * caller which will try to do udelay's etc... Instead, we wait -here-
368 * for the CPU to callin.
369 */
370 for (i = 0; i < 100000 && !cpu_callin_map[nr]; ++i) {
371 for (j = 1; j < 10000; j++)
372 asm volatile("nop" : : : "memory");
373 asm volatile("sync" : : : "memory");
374 }
375 if (!cpu_callin_map[nr])
376 goto stuck;
377
378 /* And we do the TB sync here too for standard dual CPU cards */
379 if (psurge_type == PSURGE_DUAL) {
380 while(!tb_req)
381 barrier();
382 tb_req = 0;
383 mb();
384 timebase = get_tb();
385 mb();
386 while (timebase)
387 barrier();
388 mb();
389 }
390 stuck:
391 /* now interrupt the secondary, restarting both TBs */
392 if (psurge_type == PSURGE_DUAL)
393 psurge_set_ipi(1);
394
395 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
396
397 return 0;
398 }
399
smp_psurge_setup_cpu(int cpu_nr)400 static void __init smp_psurge_setup_cpu(int cpu_nr)
401 {
402 unsigned long flags = IRQF_PERCPU | IRQF_NO_THREAD;
403 int irq;
404
405 if (cpu_nr != 0 || !psurge_start)
406 return;
407
408 /* reset the entry point so if we get another intr we won't
409 * try to startup again */
410 out_be32(psurge_start, 0x100);
411 irq = irq_create_mapping(NULL, 30);
412 if (request_irq(irq, psurge_ipi_intr, flags, "primary IPI", NULL))
413 printk(KERN_ERR "Couldn't get primary IPI interrupt");
414 }
415
smp_psurge_take_timebase(void)416 static void __init smp_psurge_take_timebase(void)
417 {
418 if (psurge_type != PSURGE_DUAL)
419 return;
420
421 tb_req = 1;
422 mb();
423 while (!timebase)
424 barrier();
425 mb();
426 set_tb(timebase >> 32, timebase & 0xffffffff);
427 timebase = 0;
428 mb();
429 set_dec(tb_ticks_per_jiffy/2);
430 }
431
smp_psurge_give_timebase(void)432 static void __init smp_psurge_give_timebase(void)
433 {
434 /* Nothing to do here */
435 }
436
437 /* PowerSurge-style Macs */
438 struct smp_ops_t psurge_smp_ops = {
439 .message_pass = NULL, /* Use smp_muxed_ipi_message_pass */
440 .cause_ipi = smp_psurge_cause_ipi,
441 .cause_nmi_ipi = NULL,
442 .probe = smp_psurge_probe,
443 .kick_cpu = smp_psurge_kick_cpu,
444 .setup_cpu = smp_psurge_setup_cpu,
445 .give_timebase = smp_psurge_give_timebase,
446 .take_timebase = smp_psurge_take_timebase,
447 };
448 #endif /* CONFIG_PPC_PMAC32_PSURGE */
449
450 /*
451 * Core 99 and later support
452 */
453
454
smp_core99_give_timebase(void)455 static void smp_core99_give_timebase(void)
456 {
457 unsigned long flags;
458
459 local_irq_save(flags);
460
461 while(!tb_req)
462 barrier();
463 tb_req = 0;
464 (*pmac_tb_freeze)(1);
465 mb();
466 timebase = get_tb();
467 mb();
468 while (timebase)
469 barrier();
470 mb();
471 (*pmac_tb_freeze)(0);
472 mb();
473
474 local_irq_restore(flags);
475 }
476
477
smp_core99_take_timebase(void)478 static void smp_core99_take_timebase(void)
479 {
480 unsigned long flags;
481
482 local_irq_save(flags);
483
484 tb_req = 1;
485 mb();
486 while (!timebase)
487 barrier();
488 mb();
489 set_tb(timebase >> 32, timebase & 0xffffffff);
490 timebase = 0;
491 mb();
492
493 local_irq_restore(flags);
494 }
495
496 #ifdef CONFIG_PPC64
497 /*
498 * G5s enable/disable the timebase via an i2c-connected clock chip.
499 */
500 static struct pmac_i2c_bus *pmac_tb_clock_chip_host;
501 static u8 pmac_tb_pulsar_addr;
502
smp_core99_cypress_tb_freeze(int freeze)503 static void smp_core99_cypress_tb_freeze(int freeze)
504 {
505 u8 data;
506 int rc;
507
508 /* Strangely, the device-tree says address is 0xd2, but darwin
509 * accesses 0xd0 ...
510 */
511 pmac_i2c_setmode(pmac_tb_clock_chip_host,
512 pmac_i2c_mode_combined);
513 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
514 0xd0 | pmac_i2c_read,
515 1, 0x81, &data, 1);
516 if (rc != 0)
517 goto bail;
518
519 data = (data & 0xf3) | (freeze ? 0x00 : 0x0c);
520
521 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
522 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
523 0xd0 | pmac_i2c_write,
524 1, 0x81, &data, 1);
525
526 bail:
527 if (rc != 0) {
528 printk("Cypress Timebase %s rc: %d\n",
529 freeze ? "freeze" : "unfreeze", rc);
530 panic("Timebase freeze failed !\n");
531 }
532 }
533
534
smp_core99_pulsar_tb_freeze(int freeze)535 static void smp_core99_pulsar_tb_freeze(int freeze)
536 {
537 u8 data;
538 int rc;
539
540 pmac_i2c_setmode(pmac_tb_clock_chip_host,
541 pmac_i2c_mode_combined);
542 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
543 pmac_tb_pulsar_addr | pmac_i2c_read,
544 1, 0x2e, &data, 1);
545 if (rc != 0)
546 goto bail;
547
548 data = (data & 0x88) | (freeze ? 0x11 : 0x22);
549
550 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
551 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
552 pmac_tb_pulsar_addr | pmac_i2c_write,
553 1, 0x2e, &data, 1);
554 bail:
555 if (rc != 0) {
556 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n",
557 freeze ? "freeze" : "unfreeze", rc);
558 panic("Timebase freeze failed !\n");
559 }
560 }
561
smp_core99_setup_i2c_hwsync(int ncpus)562 static void __init smp_core99_setup_i2c_hwsync(int ncpus)
563 {
564 struct device_node *cc = NULL;
565 struct device_node *p;
566 const char *name = NULL;
567 const u32 *reg;
568 int ok;
569
570 /* Look for the clock chip */
571 for_each_node_by_name(cc, "i2c-hwclock") {
572 p = of_get_parent(cc);
573 ok = p && of_device_is_compatible(p, "uni-n-i2c");
574 of_node_put(p);
575 if (!ok)
576 continue;
577
578 pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc);
579 if (pmac_tb_clock_chip_host == NULL)
580 continue;
581 reg = of_get_property(cc, "reg", NULL);
582 if (reg == NULL)
583 continue;
584 switch (*reg) {
585 case 0xd2:
586 if (of_device_is_compatible(cc,"pulsar-legacy-slewing")) {
587 pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
588 pmac_tb_pulsar_addr = 0xd2;
589 name = "Pulsar";
590 } else if (of_device_is_compatible(cc, "cy28508")) {
591 pmac_tb_freeze = smp_core99_cypress_tb_freeze;
592 name = "Cypress";
593 }
594 break;
595 case 0xd4:
596 pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
597 pmac_tb_pulsar_addr = 0xd4;
598 name = "Pulsar";
599 break;
600 }
601 if (pmac_tb_freeze != NULL) {
602 of_node_put(cc);
603 break;
604 }
605 }
606 if (pmac_tb_freeze != NULL) {
607 /* Open i2c bus for synchronous access */
608 if (pmac_i2c_open(pmac_tb_clock_chip_host, 1)) {
609 printk(KERN_ERR "Failed top open i2c bus for clock"
610 " sync, fallback to software sync !\n");
611 goto no_i2c_sync;
612 }
613 printk(KERN_INFO "Processor timebase sync using %s i2c clock\n",
614 name);
615 return;
616 }
617 no_i2c_sync:
618 pmac_tb_freeze = NULL;
619 pmac_tb_clock_chip_host = NULL;
620 }
621
622
623
624 /*
625 * Newer G5s uses a platform function
626 */
627
smp_core99_pfunc_tb_freeze(int freeze)628 static void smp_core99_pfunc_tb_freeze(int freeze)
629 {
630 struct device_node *cpus;
631 struct pmf_args args;
632
633 cpus = of_find_node_by_path("/cpus");
634 BUG_ON(cpus == NULL);
635 args.count = 1;
636 args.u[0].v = !freeze;
637 pmf_call_function(cpus, "cpu-timebase", &args);
638 of_node_put(cpus);
639 }
640
641 #else /* CONFIG_PPC64 */
642
643 /*
644 * SMP G4 use a GPIO to enable/disable the timebase.
645 */
646
647 static unsigned int core99_tb_gpio; /* Timebase freeze GPIO */
648
smp_core99_gpio_tb_freeze(int freeze)649 static void smp_core99_gpio_tb_freeze(int freeze)
650 {
651 if (freeze)
652 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4);
653 else
654 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);
655 pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
656 }
657
658
659 #endif /* !CONFIG_PPC64 */
660
core99_init_caches(int cpu)661 static void core99_init_caches(int cpu)
662 {
663 #ifndef CONFIG_PPC64
664 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
665 static long int core99_l2_cache;
666 static long int core99_l3_cache;
667
668 if (!cpu_has_feature(CPU_FTR_L2CR))
669 return;
670
671 if (cpu == 0) {
672 core99_l2_cache = _get_L2CR();
673 printk("CPU0: L2CR is %lx\n", core99_l2_cache);
674 } else {
675 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
676 _set_L2CR(0);
677 _set_L2CR(core99_l2_cache);
678 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
679 }
680
681 if (!cpu_has_feature(CPU_FTR_L3CR))
682 return;
683
684 if (cpu == 0){
685 core99_l3_cache = _get_L3CR();
686 printk("CPU0: L3CR is %lx\n", core99_l3_cache);
687 } else {
688 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
689 _set_L3CR(0);
690 _set_L3CR(core99_l3_cache);
691 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
692 }
693 #endif /* !CONFIG_PPC64 */
694 }
695
smp_core99_setup(int ncpus)696 static void __init smp_core99_setup(int ncpus)
697 {
698 #ifdef CONFIG_PPC64
699
700 /* i2c based HW sync on some G5s */
701 if (of_machine_is_compatible("PowerMac7,2") ||
702 of_machine_is_compatible("PowerMac7,3") ||
703 of_machine_is_compatible("RackMac3,1"))
704 smp_core99_setup_i2c_hwsync(ncpus);
705
706 /* pfunc based HW sync on recent G5s */
707 if (pmac_tb_freeze == NULL) {
708 struct device_node *cpus =
709 of_find_node_by_path("/cpus");
710 if (cpus &&
711 of_property_read_bool(cpus, "platform-cpu-timebase")) {
712 pmac_tb_freeze = smp_core99_pfunc_tb_freeze;
713 printk(KERN_INFO "Processor timebase sync using"
714 " platform function\n");
715 }
716 of_node_put(cpus);
717 }
718
719 #else /* CONFIG_PPC64 */
720
721 /* GPIO based HW sync on ppc32 Core99 */
722 if (pmac_tb_freeze == NULL && !of_machine_is_compatible("MacRISC4")) {
723 struct device_node *cpu;
724 const u32 *tbprop = NULL;
725
726 core99_tb_gpio = KL_GPIO_TB_ENABLE; /* default value */
727 cpu = of_find_node_by_type(NULL, "cpu");
728 if (cpu != NULL) {
729 tbprop = of_get_property(cpu, "timebase-enable", NULL);
730 if (tbprop)
731 core99_tb_gpio = *tbprop;
732 of_node_put(cpu);
733 }
734 pmac_tb_freeze = smp_core99_gpio_tb_freeze;
735 printk(KERN_INFO "Processor timebase sync using"
736 " GPIO 0x%02x\n", core99_tb_gpio);
737 }
738
739 #endif /* CONFIG_PPC64 */
740
741 /* No timebase sync, fallback to software */
742 if (pmac_tb_freeze == NULL) {
743 smp_ops->give_timebase = smp_generic_give_timebase;
744 smp_ops->take_timebase = smp_generic_take_timebase;
745 printk(KERN_INFO "Processor timebase sync using software\n");
746 }
747
748 #ifndef CONFIG_PPC64
749 {
750 int i;
751
752 /* XXX should get this from reg properties */
753 for (i = 1; i < ncpus; ++i)
754 set_hard_smp_processor_id(i, i);
755 }
756 #endif
757
758 /* 32 bits SMP can't NAP */
759 if (!of_machine_is_compatible("MacRISC4"))
760 powersave_nap = 0;
761 }
762
smp_core99_probe(void)763 static void __init smp_core99_probe(void)
764 {
765 struct device_node *cpus;
766 int ncpus = 0;
767
768 if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
769
770 /* Count CPUs in the device-tree */
771 for_each_node_by_type(cpus, "cpu")
772 ++ncpus;
773
774 printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus);
775
776 /* Nothing more to do if less than 2 of them */
777 if (ncpus <= 1)
778 return;
779
780 /* We need to perform some early initialisations before we can start
781 * setting up SMP as we are running before initcalls
782 */
783 pmac_pfunc_base_install();
784 pmac_i2c_init();
785
786 /* Setup various bits like timebase sync method, ability to nap, ... */
787 smp_core99_setup(ncpus);
788
789 /* Install IPIs */
790 mpic_request_ipis();
791
792 /* Collect l2cr and l3cr values from CPU 0 */
793 core99_init_caches(0);
794 }
795
smp_core99_kick_cpu(int nr)796 static int smp_core99_kick_cpu(int nr)
797 {
798 unsigned int save_vector;
799 unsigned long target, flags;
800 unsigned int *vector = (unsigned int *)(PAGE_OFFSET+0x100);
801
802 if (nr < 0 || nr > 3)
803 return -ENOENT;
804
805 if (ppc_md.progress)
806 ppc_md.progress("smp_core99_kick_cpu", 0x346);
807
808 local_irq_save(flags);
809
810 /* Save reset vector */
811 save_vector = *vector;
812
813 /* Setup fake reset vector that does
814 * b __secondary_start_pmac_0 + nr*8
815 */
816 target = (unsigned long) __secondary_start_pmac_0 + nr * 8;
817 patch_branch(vector, target, BRANCH_SET_LINK);
818
819 /* Put some life in our friend */
820 pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
821
822 /* FIXME: We wait a bit for the CPU to take the exception, I should
823 * instead wait for the entry code to set something for me. Well,
824 * ideally, all that crap will be done in prom.c and the CPU left
825 * in a RAM-based wait loop like CHRP.
826 */
827 mdelay(1);
828
829 /* Restore our exception vector */
830 patch_uint(vector, save_vector);
831
832 local_irq_restore(flags);
833 if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
834
835 return 0;
836 }
837
smp_core99_setup_cpu(int cpu_nr)838 static void smp_core99_setup_cpu(int cpu_nr)
839 {
840 /* Setup L2/L3 */
841 if (cpu_nr != 0)
842 core99_init_caches(cpu_nr);
843
844 /* Setup openpic */
845 mpic_setup_this_cpu();
846 }
847
848 #ifdef CONFIG_PPC64
849 #ifdef CONFIG_HOTPLUG_CPU
850 static unsigned int smp_core99_host_open;
851
smp_core99_cpu_prepare(unsigned int cpu)852 static int smp_core99_cpu_prepare(unsigned int cpu)
853 {
854 int rc;
855
856 /* Open i2c bus if it was used for tb sync */
857 if (pmac_tb_clock_chip_host && !smp_core99_host_open) {
858 rc = pmac_i2c_open(pmac_tb_clock_chip_host, 1);
859 if (rc) {
860 pr_err("Failed to open i2c bus for time sync\n");
861 return notifier_from_errno(rc);
862 }
863 smp_core99_host_open = 1;
864 }
865 return 0;
866 }
867
smp_core99_cpu_online(unsigned int cpu)868 static int smp_core99_cpu_online(unsigned int cpu)
869 {
870 /* Close i2c bus if it was used for tb sync */
871 if (pmac_tb_clock_chip_host && smp_core99_host_open) {
872 pmac_i2c_close(pmac_tb_clock_chip_host);
873 smp_core99_host_open = 0;
874 }
875 return 0;
876 }
877 #endif /* CONFIG_HOTPLUG_CPU */
878
smp_core99_bringup_done(void)879 static void __init smp_core99_bringup_done(void)
880 {
881 /* Close i2c bus if it was used for tb sync */
882 if (pmac_tb_clock_chip_host)
883 pmac_i2c_close(pmac_tb_clock_chip_host);
884
885 /* If we didn't start the second CPU, we must take
886 * it off the bus.
887 */
888 if (of_machine_is_compatible("MacRISC4") &&
889 num_online_cpus() < 2) {
890 set_cpu_present(1, false);
891 g5_phy_disable_cpu1();
892 }
893 #ifdef CONFIG_HOTPLUG_CPU
894 cpuhp_setup_state_nocalls(CPUHP_POWERPC_PMAC_PREPARE,
895 "powerpc/pmac:prepare", smp_core99_cpu_prepare,
896 NULL);
897 cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "powerpc/pmac:online",
898 smp_core99_cpu_online, NULL);
899 #endif
900
901 if (ppc_md.progress)
902 ppc_md.progress("smp_core99_bringup_done", 0x349);
903 }
904 #endif /* CONFIG_PPC64 */
905
906 #ifdef CONFIG_HOTPLUG_CPU
907
smp_core99_cpu_disable(void)908 static int smp_core99_cpu_disable(void)
909 {
910 int rc = generic_cpu_disable();
911 if (rc)
912 return rc;
913
914 mpic_cpu_set_priority(0xf);
915
916 cleanup_cpu_mmu_context();
917
918 return 0;
919 }
920
921 #ifdef CONFIG_PPC32
922
pmac_cpu_offline_self(void)923 static void pmac_cpu_offline_self(void)
924 {
925 int cpu = smp_processor_id();
926
927 local_irq_disable();
928 idle_task_exit();
929 pr_debug("CPU%d offline\n", cpu);
930 generic_set_cpu_dead(cpu);
931 smp_wmb();
932 mb();
933 low_cpu_offline_self();
934 }
935
936 #else /* CONFIG_PPC32 */
937
pmac_cpu_offline_self(void)938 static void pmac_cpu_offline_self(void)
939 {
940 int cpu = smp_processor_id();
941
942 local_irq_disable();
943 idle_task_exit();
944
945 /*
946 * turn off as much as possible, we'll be
947 * kicked out as this will only be invoked
948 * on core99 platforms for now ...
949 */
950
951 printk(KERN_INFO "CPU#%d offline\n", cpu);
952 generic_set_cpu_dead(cpu);
953 smp_wmb();
954
955 /*
956 * Re-enable interrupts. The NAP code needs to enable them
957 * anyways, do it now so we deal with the case where one already
958 * happened while soft-disabled.
959 * We shouldn't get any external interrupts, only decrementer, and the
960 * decrementer handler is safe for use on offline CPUs
961 */
962 local_irq_enable();
963
964 while (1) {
965 /* let's not take timer interrupts too often ... */
966 set_dec(0x7fffffff);
967
968 /* Enter NAP mode */
969 power4_idle();
970 }
971 }
972
973 #endif /* else CONFIG_PPC32 */
974 #endif /* CONFIG_HOTPLUG_CPU */
975
976 /* Core99 Macs (dual G4s and G5s) */
977 static struct smp_ops_t core99_smp_ops = {
978 .message_pass = smp_mpic_message_pass,
979 .probe = smp_core99_probe,
980 #ifdef CONFIG_PPC64
981 .bringup_done = smp_core99_bringup_done,
982 #endif
983 .kick_cpu = smp_core99_kick_cpu,
984 .setup_cpu = smp_core99_setup_cpu,
985 .give_timebase = smp_core99_give_timebase,
986 .take_timebase = smp_core99_take_timebase,
987 #if defined(CONFIG_HOTPLUG_CPU)
988 .cpu_disable = smp_core99_cpu_disable,
989 .cpu_die = generic_cpu_die,
990 #endif
991 };
992
pmac_setup_smp(void)993 void __init pmac_setup_smp(void)
994 {
995 struct device_node *np;
996
997 /* Check for Core99 */
998 np = of_find_node_by_name(NULL, "uni-n");
999 if (!np)
1000 np = of_find_node_by_name(NULL, "u3");
1001 if (!np)
1002 np = of_find_node_by_name(NULL, "u4");
1003 if (np) {
1004 of_node_put(np);
1005 smp_ops = &core99_smp_ops;
1006 }
1007 #ifdef CONFIG_PPC_PMAC32_PSURGE
1008 else {
1009 /* We have to set bits in cpu_possible_mask here since the
1010 * secondary CPU(s) aren't in the device tree. Various
1011 * things won't be initialized for CPUs not in the possible
1012 * map, so we really need to fix it up here.
1013 */
1014 int cpu;
1015
1016 for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu)
1017 set_cpu_possible(cpu, true);
1018 smp_ops = &psurge_smp_ops;
1019 }
1020 #endif /* CONFIG_PPC_PMAC32_PSURGE */
1021
1022 #ifdef CONFIG_HOTPLUG_CPU
1023 smp_ops->cpu_offline_self = pmac_cpu_offline_self;
1024 #endif
1025 }
1026
1027
1028