1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 /* 27 * Copyright (c) 2010, Intel Corporation. 28 * All rights reserved. 29 */ 30 31 #ifndef _SYS_PSM_TYPES_H 32 #define _SYS_PSM_TYPES_H 33 34 /* 35 * Platform Specific Module Types 36 */ 37 38 #include <sys/types.h> 39 #include <sys/cpuvar.h> 40 #include <sys/time.h> 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 /* 47 * PSM_OPS definitions 48 */ 49 typedef enum psm_intr_op_e { 50 PSM_INTR_OP_ALLOC_VECTORS = 0, /* 0. Allocate vectors */ 51 PSM_INTR_OP_FREE_VECTORS, /* 1. Free vectors */ 52 PSM_INTR_OP_NAVAIL_VECTORS, /* 2. Get # of available vectors */ 53 PSM_INTR_OP_XLATE_VECTOR, /* 3. Translate vector */ 54 PSM_INTR_OP_GET_PENDING, /* 4. Get pending information */ 55 PSM_INTR_OP_CLEAR_MASK, /* 5. Clear interrupt mask */ 56 PSM_INTR_OP_SET_MASK, /* 6. Set interrupt mask */ 57 PSM_INTR_OP_GET_CAP, /* 7. Get devices's capabilities */ 58 PSM_INTR_OP_SET_CAP, /* 8. Set devices's capabilities */ 59 PSM_INTR_OP_SET_PRI, /* 9. Set the interrupt priority */ 60 PSM_INTR_OP_GET_SHARED, /* 10. Get the shared intr info */ 61 PSM_INTR_OP_CHECK_MSI, /* 11. Chk if device supports MSI */ 62 PSM_INTR_OP_SET_CPU, /* 12. Set vector's CPU */ 63 PSM_INTR_OP_GET_INTR, /* 13. Get vector's info */ 64 PSM_INTR_OP_GRP_SET_CPU, /* 14. Set all device's vectors' CPU */ 65 PSM_INTR_OP_APIC_TYPE /* 15. Returns APIC type */ 66 } psm_intr_op_t; 67 68 /* 69 * PSM_STATE definitions 70 */ 71 typedef enum psm_state_op_e { 72 PSM_STATE_ALLOC = 1, 73 PSM_STATE_FREE, 74 PSM_STATE_SAVE, 75 PSM_STATE_RESTORE 76 } psm_state_op_t; 77 78 typedef struct psm_state_req { 79 psm_state_op_t psr_cmd; 80 union psm_req { 81 /* 82 * PSM_STATE_ALLOC, PSM_STATE_FREE, PSM_STATE_SAVE, 83 * PSM_STATE_RESTORE all use the same struct, 84 * but union for later expansion 85 */ 86 struct { 87 void *psr_state; 88 size_t psr_state_size; 89 } psm_state_req; 90 } req; 91 } psm_state_request_t; 92 93 typedef enum psm_cpu_op_e { 94 PSM_CPU_ADD = 1, 95 PSM_CPU_REMOVE, 96 PSM_CPU_STOP 97 } psm_cpu_op_t; 98 99 typedef struct psm_cpu_request { 100 psm_cpu_op_t pcr_cmd; 101 union { 102 struct { 103 processorid_t cpuid; 104 void *argp; 105 } cpu_add; 106 107 struct { 108 processorid_t cpuid; 109 } cpu_remove; 110 111 struct { 112 processorid_t cpuid; 113 void *ctx; 114 } cpu_stop; 115 } req; 116 } psm_cpu_request_t; 117 118 struct psm_ops { 119 int (*psm_probe)(void); 120 121 void (*psm_softinit)(void); 122 void (*psm_picinit)(void); 123 int (*psm_intr_enter)(int ipl, int *vectorp); 124 void (*psm_intr_exit)(int ipl, int irqno); 125 void (*psm_setspl)(int ipl); 126 int (*psm_addspl)(int irqno, int ipl, int min_ipl, int max_ipl); 127 int (*psm_delspl)(int irqno, int ipl, int min_ipl, int max_ipl); 128 int (*psm_disable_intr)(processorid_t cpun); 129 void (*psm_enable_intr)(processorid_t cpun); 130 int (*psm_softlvl_to_irq)(int ipl); 131 void (*psm_set_softintr)(int ipl); 132 void (*psm_set_idlecpu)(processorid_t cpun); 133 void (*psm_unset_idlecpu)(processorid_t cpun); 134 135 #if defined(PSMI_1_3) || defined(PSMI_1_4) || defined(PSMI_1_5) || \ 136 defined(PSMI_1_6) || defined(PSMI_1_7) 137 int (*psm_clkinit)(int hertz); 138 #else 139 void (*psm_clkinit)(int hertz); 140 #endif 141 142 int (*psm_get_clockirq)(int ipl); 143 void (*psm_hrtimeinit)(void); 144 hrtime_t (*psm_gethrtime)(void); 145 146 processorid_t (*psm_get_next_processorid)(processorid_t cpu_id); 147 #if defined(PSMI_1_5) || defined(PSMI_1_6) || defined(PSMI_1_7) 148 int (*psm_cpu_start)(processorid_t cpun, caddr_t ctxt); 149 #else 150 void (*psm_cpu_start)(processorid_t cpun, caddr_t rm_code); 151 #endif 152 int (*psm_post_cpu_start)(void); 153 #if defined(PSMI_1_2) || defined(PSMI_1_3) || defined(PSMI_1_4) || \ 154 defined(PSMI_1_5) || defined(PSMI_1_6) || defined(PSMI_1_7) 155 void (*psm_shutdown)(int cmd, int fcn); 156 #else 157 void (*psm_shutdown)(void); 158 #endif 159 int (*psm_get_ipivect)(int ipl, int type); 160 void (*psm_send_ipi)(processorid_t cpun, int ipl); 161 162 int (*psm_translate_irq)(dev_info_t *dip, int irqno); 163 164 #if defined(PSMI_1_2) || defined(PSMI_1_3) || defined(PSMI_1_4) 165 int (*psm_tod_get)(todinfo_t *tod); 166 int (*psm_tod_set)(todinfo_t *tod); 167 #endif 168 void (*psm_notify_error)(int level, char *errmsg); 169 #if defined(PSMI_1_2) || defined(PSMI_1_3) || defined(PSMI_1_4) || \ 170 defined(PSMI_1_5) || defined(PSMI_1_6) || defined(PSMI_1_7) 171 void (*psm_notify_func)(int msg); 172 #endif 173 #if defined(PSMI_1_3) || defined(PSMI_1_4) || defined(PSMI_1_5) || \ 174 defined(PSMI_1_6) || defined(PSMI_1_7) 175 void (*psm_timer_reprogram)(hrtime_t time); 176 void (*psm_timer_enable)(void); 177 void (*psm_timer_disable)(void); 178 void (*psm_post_cyclic_setup)(void *arg); 179 #endif 180 #if defined(PSMI_1_4) || defined(PSMI_1_5) || defined(PSMI_1_6) || \ 181 defined(PSMI_1_7) 182 void (*psm_preshutdown)(int cmd, int fcn); 183 #endif 184 #if defined(PSMI_1_5) || defined(PSMI_1_6) || defined(PSMI_1_7) 185 int (*psm_intr_ops)(dev_info_t *dip, ddi_intr_handle_impl_t *handle, 186 psm_intr_op_t op, int *result); 187 #endif 188 #if defined(PSMI_1_6) || defined(PSMI_1_7) 189 int (*psm_state)(psm_state_request_t *request); 190 #endif 191 #if defined(PSMI_1_7) 192 int (*psm_cpu_ops)(psm_cpu_request_t *reqp); 193 #endif 194 }; 195 196 197 struct psm_info { 198 ushort_t p_version; 199 ushort_t p_owner; 200 struct psm_ops *p_ops; 201 char *p_mach_idstring; /* machine identification string */ 202 char *p_mach_desc; /* machine descriptions */ 203 }; 204 205 /* 206 * version 207 * 0x86vm where v = (version no. - 1) and m = (minor no. + 1) 208 * i.e. psmi 1.0 has v=0 and m=1, psmi 1.1 has v=0 and m=2 209 * also, 0x86 in the high byte is the signature of the psmi 210 */ 211 #define PSM_INFO_VER01 0x8601 212 #define PSM_INFO_VER01_1 0x8602 213 #define PSM_INFO_VER01_2 0x8603 214 #define PSM_INFO_VER01_3 0x8604 215 #define PSM_INFO_VER01_4 0x8605 216 #define PSM_INFO_VER01_5 0x8606 217 #define PSM_INFO_VER01_6 0x8607 218 #define PSM_INFO_VER01_7 0x8608 219 #define PSM_INFO_VER01_X (PSM_INFO_VER01_1 & 0xFFF0) /* ver 1.X */ 220 221 /* 222 * owner field definitions 223 */ 224 #define PSM_OWN_SYS_DEFAULT 0x0001 225 #define PSM_OWN_EXCLUSIVE 0x0002 226 #define PSM_OWN_OVERRIDE 0x0003 227 228 #define PSM_NULL_INFO -1 229 230 /* 231 * Arg to psm_notify_func 232 */ 233 #define PSM_DEBUG_ENTER 1 234 #define PSM_DEBUG_EXIT 2 235 #define PSM_PANIC_ENTER 3 236 237 /* 238 * Soft-level to interrupt vector 239 */ 240 #define PSM_SV_SOFTWARE -1 241 #define PSM_SV_MIXED -2 242 243 /* 244 * Inter-processor interrupt type 245 */ 246 #define PSM_INTR_IPI_HI 0x01 247 #define PSM_INTR_IPI_LO 0x02 248 #define PSM_INTR_POKE 0x03 249 250 /* 251 * Get INTR flags 252 */ 253 #define PSMGI_CPU_USER_BOUND 0x80000000 /* user requested bind if set */ 254 #define PSMGI_CPU_FLAGS 0x80000000 /* all possible flags */ 255 256 /* 257 * return code 258 */ 259 #define PSM_SUCCESS DDI_SUCCESS 260 #define PSM_FAILURE DDI_FAILURE 261 262 #define PSM_INVALID_IPL 0 263 #define PSM_INVALID_CPU -1 264 265 266 struct psm_ops_ver01 { 267 int (*psm_probe)(void); 268 269 void (*psm_softinit)(void); 270 void (*psm_picinit)(void); 271 int (*psm_intr_enter)(int ipl, int *vectorp); 272 void (*psm_intr_exit)(int ipl, int irqno); 273 void (*psm_setspl)(int ipl); 274 int (*psm_addspl)(int irqno, int ipl, int min_ipl, int max_ipl); 275 int (*psm_delspl)(int irqno, int ipl, int min_ipl, int max_ipl); 276 int (*psm_disable_intr)(processorid_t cpun); 277 void (*psm_enable_intr)(processorid_t cpun); 278 int (*psm_softlvl_to_irq)(int ipl); 279 void (*psm_set_softintr)(int ipl); 280 void (*psm_set_idlecpu)(processorid_t cpun); 281 void (*psm_unset_idlecpu)(processorid_t cpun); 282 283 void (*psm_clkinit)(int hertz); 284 int (*psm_get_clockirq)(int ipl); 285 void (*psm_hrtimeinit)(void); 286 hrtime_t (*psm_gethrtime)(void); 287 288 processorid_t (*psm_get_next_processorid)(processorid_t cpu_id); 289 void (*psm_cpu_start)(processorid_t cpun, caddr_t rm_code); 290 int (*psm_post_cpu_start)(void); 291 void (*psm_shutdown)(void); 292 int (*psm_get_ipivect)(int ipl, int type); 293 void (*psm_send_ipi)(processorid_t cpun, int ipl); 294 }; 295 296 #ifdef __cplusplus 297 } 298 #endif 299 300 #endif /* _SYS_PSM_TYPES_H */ 301