xref: /illumos-gate/usr/src/uts/i86pc/sys/psm_types.h (revision 918e0d92ec24e67f572737a68faf135dc6409d26)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 /*
27  * Copyright (c) 2010, Intel Corporation.
28  * All rights reserved.
29  * Copyright 2018 Joyent, Inc.
30  */
31 
32 #ifndef	_SYS_PSM_TYPES_H
33 #define	_SYS_PSM_TYPES_H
34 
35 /*
36  * Platform Specific Module Types
37  */
38 
39 #include <sys/types.h>
40 #include <sys/cpuvar.h>
41 #include <sys/time.h>
42 
43 #ifdef	__cplusplus
44 extern "C" {
45 #endif
46 
47 /*
48  * PSM_OPS definitions
49  */
50 typedef enum psm_intr_op_e {
51 	PSM_INTR_OP_ALLOC_VECTORS = 0,	/* 0.  Allocate vectors */
52 	PSM_INTR_OP_FREE_VECTORS,	/* 1.  Free vectors */
53 	PSM_INTR_OP_NAVAIL_VECTORS,	/* 2.  Get # of available vectors */
54 	PSM_INTR_OP_XLATE_VECTOR,	/* 3.  Translate vector */
55 	PSM_INTR_OP_GET_PENDING,	/* 4.  Get pending information */
56 	PSM_INTR_OP_CLEAR_MASK,		/* 5.  Clear interrupt mask */
57 	PSM_INTR_OP_SET_MASK,		/* 6.  Set interrupt mask */
58 	PSM_INTR_OP_GET_CAP,		/* 7.  Get devices's capabilities */
59 	PSM_INTR_OP_SET_CAP,		/* 8.  Set devices's capabilities */
60 	PSM_INTR_OP_SET_PRI,		/* 9.  Set the interrupt priority */
61 	PSM_INTR_OP_GET_SHARED,		/* 10. Get the shared intr info */
62 	PSM_INTR_OP_CHECK_MSI,		/* 11. Chk if device supports MSI */
63 	PSM_INTR_OP_SET_CPU,		/* 12. Set vector's CPU */
64 	PSM_INTR_OP_GET_INTR,		/* 13. Get vector's info */
65 	PSM_INTR_OP_GRP_SET_CPU,	/* 14. Set all device's vectors' CPU */
66 	PSM_INTR_OP_APIC_TYPE		/* 15. Returns APIC type */
67 } psm_intr_op_t;
68 
69 /*
70  * PSM_STATE definitions
71  */
72 typedef enum psm_state_op_e {
73 	PSM_STATE_ALLOC = 1,
74 	PSM_STATE_FREE,
75 	PSM_STATE_SAVE,
76 	PSM_STATE_RESTORE
77 } psm_state_op_t;
78 
79 typedef struct psm_state_req {
80 	psm_state_op_t psr_cmd;
81 	union psm_req {
82 		/*
83 		 * PSM_STATE_ALLOC, PSM_STATE_FREE, PSM_STATE_SAVE,
84 		 * PSM_STATE_RESTORE all use the same struct,
85 		 * but union for later expansion
86 		 */
87 		struct {
88 			void *psr_state;
89 			size_t psr_state_size;
90 		} psm_state_req;
91 	} req;
92 } psm_state_request_t;
93 
94 typedef enum psm_cpu_op_e {
95 	PSM_CPU_ADD = 1,
96 	PSM_CPU_REMOVE,
97 	PSM_CPU_STOP
98 } psm_cpu_op_t;
99 
100 typedef struct psm_cpu_request {
101 	psm_cpu_op_t pcr_cmd;
102 	union {
103 		struct {
104 			processorid_t cpuid;
105 			void *argp;
106 		} cpu_add;
107 
108 		struct {
109 			processorid_t cpuid;
110 		} cpu_remove;
111 
112 		struct {
113 			processorid_t cpuid;
114 			void *ctx;
115 		} cpu_stop;
116 	} req;
117 } psm_cpu_request_t;
118 
119 struct	psm_ops {
120 	int	(*psm_probe)(void);
121 
122 	void	(*psm_softinit)(void);
123 	void	(*psm_picinit)(void);
124 	int	(*psm_intr_enter)(int ipl, int *vectorp);
125 	void	(*psm_intr_exit)(int ipl, int irqno);
126 	void	(*psm_setspl)(int ipl);
127 	int	(*psm_addspl)(int irqno, int ipl, int min_ipl, int max_ipl);
128 	int	(*psm_delspl)(int irqno, int ipl, int min_ipl, int max_ipl);
129 	int	(*psm_disable_intr)(processorid_t cpun);
130 	void	(*psm_enable_intr)(processorid_t cpun);
131 	int	(*psm_softlvl_to_irq)(int ipl);
132 	void	(*psm_set_softintr)(int ipl);
133 	void	(*psm_set_idlecpu)(processorid_t cpun);
134 	void	(*psm_unset_idlecpu)(processorid_t cpun);
135 
136 #if defined(PSMI_1_3) || defined(PSMI_1_4) || defined(PSMI_1_5) || \
137     defined(PSMI_1_6) || defined(PSMI_1_7)
138 	int	(*psm_clkinit)(int hertz);
139 #else
140 	void	(*psm_clkinit)(int hertz);
141 #endif
142 
143 	int	(*psm_get_clockirq)(int ipl);
144 	void	(*psm_hrtimeinit)(void);
145 	hrtime_t (*psm_gethrtime)(void);
146 
147 	processorid_t (*psm_get_next_processorid)(processorid_t cpu_id);
148 #if defined(PSMI_1_5) || defined(PSMI_1_6) || defined(PSMI_1_7)
149 	int	(*psm_cpu_start)(processorid_t cpun, caddr_t ctxt);
150 #else
151 	void	(*psm_cpu_start)(processorid_t cpun, caddr_t rm_code);
152 #endif
153 	int	(*psm_post_cpu_start)(void);
154 #if defined(PSMI_1_2) || defined(PSMI_1_3) || defined(PSMI_1_4) || \
155     defined(PSMI_1_5) || defined(PSMI_1_6) || defined(PSMI_1_7)
156 	void	(*psm_shutdown)(int cmd, int fcn);
157 #else
158 	void	(*psm_shutdown)(void);
159 #endif
160 	int	(*psm_get_ipivect)(int ipl, int type);
161 	void	(*psm_send_ipi)(processorid_t cpun, int ipl);
162 
163 	int	(*psm_translate_irq)(dev_info_t *dip, int irqno);
164 
165 #if defined(PSMI_1_2) || defined(PSMI_1_3) || defined(PSMI_1_4)
166 	int	(*psm_tod_get)(todinfo_t *tod);
167 	int	(*psm_tod_set)(todinfo_t *tod);
168 #endif
169 	void	(*psm_notify_error)(int level, char *errmsg);
170 #if defined(PSMI_1_2) || defined(PSMI_1_3) || defined(PSMI_1_4) || \
171     defined(PSMI_1_5) || defined(PSMI_1_6) || defined(PSMI_1_7)
172 	void	(*psm_notify_func)(int msg);
173 #endif
174 #if defined(PSMI_1_3) || defined(PSMI_1_4) || defined(PSMI_1_5) || \
175     defined(PSMI_1_6) || defined(PSMI_1_7)
176 	void	(*psm_timer_reprogram)(hrtime_t time);
177 	void	(*psm_timer_enable)(void);
178 	void	(*psm_timer_disable)(void);
179 	void	(*psm_post_cyclic_setup)(void *arg);
180 #endif
181 #if defined(PSMI_1_4) || defined(PSMI_1_5) || defined(PSMI_1_6) || \
182     defined(PSMI_1_7)
183 	void	(*psm_preshutdown)(int cmd, int fcn);
184 #endif
185 #if defined(PSMI_1_5) || defined(PSMI_1_6) || defined(PSMI_1_7)
186 	int	(*psm_intr_ops)(dev_info_t *dip, ddi_intr_handle_impl_t *handle,
187 		    psm_intr_op_t op, int *result);
188 #endif
189 #if defined(PSMI_1_6) || defined(PSMI_1_7)
190 	int	(*psm_state)(psm_state_request_t *request);
191 #endif
192 #if defined(PSMI_1_7)
193 	int	(*psm_cpu_ops)(psm_cpu_request_t *reqp);
194 
195 	int	(*psm_get_pir_ipivect)(void);
196 	void	(*psm_send_pir_ipi)(processorid_t cpu);
197 	void	(*psm_cmci_setup)(processorid_t cpu, boolean_t);
198 #endif
199 };
200 
201 
202 struct psm_info {
203 	ushort_t p_version;
204 	ushort_t p_owner;
205 	struct	psm_ops	*p_ops;
206 	char	*p_mach_idstring;	/* machine identification string */
207 	char	*p_mach_desc;		/* machine descriptions		 */
208 };
209 
210 /*
211  * version
212  * 0x86vm where v = (version no. - 1) and m = (minor no. + 1)
213  * i.e. psmi 1.0 has v=0 and m=1, psmi 1.1 has v=0 and m=2
214  * also, 0x86 in the high byte is the signature of the psmi
215  */
216 #define	PSM_INFO_VER01		0x8601
217 #define	PSM_INFO_VER01_1	0x8602
218 #define	PSM_INFO_VER01_2	0x8603
219 #define	PSM_INFO_VER01_3	0x8604
220 #define	PSM_INFO_VER01_4	0x8605
221 #define	PSM_INFO_VER01_5	0x8606
222 #define	PSM_INFO_VER01_6	0x8607
223 #define	PSM_INFO_VER01_7	0x8608
224 #define	PSM_INFO_VER01_X	(PSM_INFO_VER01_1 & 0xFFF0)	/* ver 1.X */
225 
226 /*
227  *	owner field definitions
228  */
229 #define	PSM_OWN_SYS_DEFAULT	0x0001
230 #define	PSM_OWN_EXCLUSIVE	0x0002
231 #define	PSM_OWN_OVERRIDE	0x0003
232 
233 #define	PSM_NULL_INFO		-1
234 
235 /*
236  *	Arg to psm_notify_func
237  */
238 #define	PSM_DEBUG_ENTER		1
239 #define	PSM_DEBUG_EXIT		2
240 #define	PSM_PANIC_ENTER		3
241 
242 /*
243  *	Soft-level to interrupt vector
244  */
245 #define	PSM_SV_SOFTWARE		-1
246 #define	PSM_SV_MIXED		-2
247 
248 /*
249  *	Inter-processor interrupt type
250  */
251 #define	PSM_INTR_IPI_HI		0x01
252 #define	PSM_INTR_IPI_LO		0x02
253 #define	PSM_INTR_POKE		0x03
254 
255 /*
256  *	Get INTR flags
257  */
258 #define	PSMGI_CPU_USER_BOUND	0x80000000 /* user requested bind if set */
259 #define	PSMGI_CPU_FLAGS		0x80000000 /* all possible flags */
260 
261 /*
262  *	return code
263  */
264 #define	PSM_SUCCESS		DDI_SUCCESS
265 #define	PSM_FAILURE		DDI_FAILURE
266 
267 #define	PSM_INVALID_IPL		0
268 #define	PSM_INVALID_CPU		-1
269 
270 
271 struct	psm_ops_ver01 {
272 	int	(*psm_probe)(void);
273 
274 	void	(*psm_softinit)(void);
275 	void	(*psm_picinit)(void);
276 	int	(*psm_intr_enter)(int ipl, int *vectorp);
277 	void	(*psm_intr_exit)(int ipl, int irqno);
278 	void	(*psm_setspl)(int ipl);
279 	int	(*psm_addspl)(int irqno, int ipl, int min_ipl, int max_ipl);
280 	int	(*psm_delspl)(int irqno, int ipl, int min_ipl, int max_ipl);
281 	int	(*psm_disable_intr)(processorid_t cpun);
282 	void	(*psm_enable_intr)(processorid_t cpun);
283 	int	(*psm_softlvl_to_irq)(int ipl);
284 	void	(*psm_set_softintr)(int ipl);
285 	void	(*psm_set_idlecpu)(processorid_t cpun);
286 	void	(*psm_unset_idlecpu)(processorid_t cpun);
287 
288 	void	(*psm_clkinit)(int hertz);
289 	int	(*psm_get_clockirq)(int ipl);
290 	void	(*psm_hrtimeinit)(void);
291 	hrtime_t (*psm_gethrtime)(void);
292 
293 	processorid_t (*psm_get_next_processorid)(processorid_t cpu_id);
294 	void	(*psm_cpu_start)(processorid_t cpun, caddr_t rm_code);
295 	int	(*psm_post_cpu_start)(void);
296 	void	(*psm_shutdown)(void);
297 	int	(*psm_get_ipivect)(int ipl, int type);
298 	void	(*psm_send_ipi)(processorid_t cpun, int ipl);
299 };
300 
301 #ifdef	__cplusplus
302 }
303 #endif
304 
305 #endif	/* _SYS_PSM_TYPES_H */
306