1 /*-
2 * Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26
27 #ifndef _PQI_DEFINES_H
28 #define _PQI_DEFINES_H
29
30 #define SIS_POLL_WAIT
31 #define DEVICE_HINT
32
33 #ifndef CT_ASSERT
34 /* If the OS hasn't specified a preferred compile time assert, create one */
35 #if !defined(__C_ASSERT__)
36 #define CT_ASSERT(e) extern char __assert_test_case[1 - (2*(!(e)))]
37 #else
38 #define CT_ASSERT(e) typedef char __C_ASSERT__[(e)?1:-1]
39 #endif
40 #endif
41 #define PQI_STATUS_FAILURE -1
42 #define PQI_STATUS_TIMEOUT -2
43 #define PQI_STATUS_QFULL -3
44 #define PQI_STATUS_SUCCESS 0
45
46 #define BITS_PER_BYTE 8
47 #define PQI_VENDOR_GENERAL_CONFIG_TABLE_UPDATE 0
48 #define PQI_VENDOR_GENERAL_HOST_MEMORY_UPDATE 1
49 #define PQI_REQUEST_HEADER_LENGTH 4
50
51 /* Maximum timeout for internal command completion */
52 #define TIMEOUT_INFINITE ((uint32_t) (-1))
53 #define PQISRC_CMD_TIMEOUT TIMEOUT_INFINITE
54 #define PQISRC_PASSTHROUGH_CMD_TIMEOUT PQISRC_CMD_TIMEOUT
55 /* Delay in milli seconds */
56 #define PQISRC_TMF_TIMEOUT (OS_TMF_TIMEOUT_SEC * 1000)
57 /* Delay in micro seconds */
58 #define PQISRC_PENDING_IO_TIMEOUT_USEC 30000000 /* 30 seconds */
59
60 /* If want to disable atomic operations on device active io, then set to zero */
61 #define PQISRC_DEVICE_IO_COUNTER 1
62
63 /* #define SHARE_EVENT_QUEUE_FOR_IO 1 */
64
65 #define INVALID_ELEM 0xffff
66 #ifndef MIN
67 #define MIN(a,b) ((a) < (b) ? (a) : (b))
68 #endif
69
70 #ifndef MAX
71 #define MAX(a,b) ((a) > (b) ? (a) : (b))
72 #endif
73
74 /* defines for stream detection */
75 #define TICKS ticks
76
77 #ifndef INT_MAX
78 #define INT_MAX 0x7FFFFFFF
79 #endif
80
81 #define PQISRC_ROUND_UP(x, y) (((x) + (y) - 1) / (y) * (y))
82 #define PQISRC_ROUND_DOWN(x, y) (((x) / (y)) * (y))
83 #define PQISRC_DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
84
85 #if !defined(offsetofend)
86 #define offsetofend(TYPE, MEMBER) \
87 (offsetof(TYPE, MEMBER) + sizeof(((TYPE *)0)->MEMBER))
88 #endif
89
90 #define ALIGN_BOUNDARY(a, n) { \
91 if (a % n) \
92 a = a + (n - a % n); \
93 }
94
95 /* Busy wait timeout on a condition */
96 #define COND_BUSYWAIT(cond, timeout /* in millisecond */) { \
97 if (!(cond)) { \
98 while (timeout) { \
99 OS_BUSYWAIT(1000); \
100 if (cond) \
101 break; \
102 timeout--; \
103 } \
104 } \
105 }
106
107 /* Wait timeout on a condition*/
108 #define COND_WAIT(cond, timeout /* in millisecond */) { \
109 if (!(cond)) { \
110 while (timeout) { \
111 OS_SLEEP(1000); \
112 if (cond) \
113 break; \
114 timeout--; \
115 } \
116 } \
117 }
118
119 #define FILL_QUEUE_ARRAY_ADDR(q,virt,dma) { \
120 q->array_virt_addr = virt; \
121 q->array_dma_addr = dma; \
122 }
123
124 #define true 1
125 #define false 0
126
127 enum INTR_TYPE {
128 LOCK_INTR,
129 LOCK_SLEEP
130 };
131
132 #define LOCKNAME_SIZE 32
133
134 #define INTR_TYPE_NONE 0x0
135 #define INTR_TYPE_FIXED 0x1
136 #define INTR_TYPE_MSI 0x2
137 #define INTR_TYPE_MSIX 0x4
138 #define SIS_ENABLE_MSIX 0x40
139 #define SIS_ENABLE_INTX 0x80
140 #define PQISRC_LEGACY_INTX_MASK 0x1
141
142 #define DMA_TO_VIRT(mem) ((mem)->virt_addr)
143 #define DMA_PHYS_LOW(mem) (((mem)->dma_addr) & 0x00000000ffffffff)
144 #define DMA_PHYS_HIGH(mem) ((((mem)->dma_addr) & 0xffffffff00000000) >> 32)
145
146 typedef enum IO_PATH {
147 UNKNOWN_PATH,
148 AIO_PATH,
149 RAID_PATH
150 }IO_PATH_T;
151
152 typedef enum device_type
153 {
154 DISK_DEVICE,
155 TAPE_DEVICE,
156 ROM_DEVICE = 5,
157 SES_DEVICE,
158 CONTROLLER_DEVICE,
159 MEDIUM_CHANGER_DEVICE,
160 RAID_DEVICE = 0x0c,
161 ENCLOSURE_DEVICE,
162 ZBC_DEVICE = 0x14
163 } device_type_t;
164
165 typedef enum controller_state {
166 PQI_UP_RUNNING,
167 PQI_BUS_RESET,
168 }controller_state_t;
169
170
171 #define PQISRC_MAX_MSIX_SUPPORTED 64
172
173 /* SIS Specific */
174 #define PQISRC_INIT_STRUCT_REVISION 9
175 #define PQISRC_SECTOR_SIZE 512
176 #define PQISRC_BLK_SIZE PQISRC_SECTOR_SIZE
177 #define PQISRC_DEFAULT_DMA_ALIGN 4
178 #define PQISRC_DMA_ALIGN_MASK (PQISRC_DEFAULT_DMA_ALIGN - 1)
179 #define PQISRC_ERR_BUF_DMA_ALIGN 32
180 #define PQISRC_ERR_BUF_ELEM_SIZE MAX(sizeof(raid_path_error_info_elem_t),sizeof(aio_path_error_info_elem_t))
181 #define PQISRC_INIT_STRUCT_DMA_ALIGN 16
182
183 #define SIS_CMD_GET_ADAPTER_PROPERTIES 0x19
184 #define SIS_CMD_GET_COMM_PREFERRED_SETTINGS 0x26
185 #define SIS_CMD_GET_PQI_CAPABILITIES 0x3000
186 #define SIS_CMD_INIT_BASE_STRUCT_ADDRESS 0x1b
187
188 #define SIS_SUPPORT_EXT_OPT 0x00800000
189 #define SIS_SUPPORT_PQI 0x00000004
190 #define SIS_SUPPORT_PQI_RESET_QUIESCE 0x00000008
191
192 #define SIS_PQI_RESET_QUIESCE 0x1000000
193
194 #define SIS_STATUS_OK_TIMEOUT 120000 /* in milli sec, 5 sec */
195
196 #define SIS_CMD_COMPLETE_TIMEOUT 30000 /* in milli sec, 30 secs */
197 #define SIS_POLL_START_WAIT_TIME 20000 /* in micro sec, 20 milli sec */
198 #define SIS_DB_BIT_CLEAR_TIMEOUT_CNT 120000 /* 500usec * 120000 = 60 sec */
199
200 #define SIS_ENABLE_TIMEOUT 3000
201 #define REENABLE_SIS 0x1
202 #define TRIGGER_NMI_SIS 0x800000
203 /*SIS Register status defines */
204
205 #define PQI_CTRL_KERNEL_UP_AND_RUNNING 0x80
206 #define PQI_CTRL_KERNEL_PANIC 0x100
207
208 #define SIS_CTL_TO_HOST_DB_DISABLE_ALL 0xFFFFFFFF
209 #define SIS_CTL_TO_HOST_DB_CLEAR 0x00001000
210 #define SIS_CMD_SUBMIT 0x00000200 /* Bit 9 */
211 #define SIS_CMD_COMPLETE 0x00001000 /* Bit 12 */
212 #define SIS_CMD_STATUS_SUCCESS 0x1
213
214 /* PQI specific */
215
216 /* defines */
217 #define PQISRC_PQI_REG_OFFSET 0x4000
218
219
220 /* Number of Queues this driver compile can potentially support */
221 #define PQISRC_MAX_SUPPORTED_OP_IB_Q 128
222 #define PQISRC_MAX_SUPPORTED_OP_RAID_IB_Q (PQISRC_MAX_SUPPORTED_OP_IB_Q / 2)
223 #define PQISRC_MAX_SUPPORTED_OP_AIO_IB_Q (PQISRC_MAX_SUPPORTED_OP_RAID_IB_Q)
224 #define PQISRC_MAX_SUPPORTED_OP_OB_Q 64
225
226
227 /* PQI Capability maxes (from controller) */
228 #define PQISRC_MAX_ELEMENTS 8192
229 #define PQISRC_OP_MIN_ELEM_SIZE 1 /* 16 bytes */
230 #define PQISRC_OP_MAX_ELEM_SIZE 8 /* 8 * 16 = 128 bytes */
231 #define PQISRC_MAX_SPANNING_IU_LENGTH 1152
232 #define PQISRC_MAX_OUTSTANDING_REQ 4096
233 /* #define PQISRC_MAX_OP_IB_QUEUE_ELEM_NUM (PQISRC_MAX_OUTSTANDING_REQ / PQISRC_MAX_SUPPORTED_OP_IB_Q) */
234 /* #define PQISRC_MAX_OP_OB_QUEUE_ELEM_NUM PQISRC_MAX_OUTSTANDING_REQ */
235 /* #define PQISRC_MIN_OP_OB_QUEUE_ELEM_NUM 2 */
236
237 #ifdef DEVICE_HINT
238 #define PQISRC_MIN_OUTSTANDING_REQ (PQI_RESERVED_IO_SLOTS_CNT + OS_MIN_OUTSTANDING_REQ)
239 #endif
240
241
242
243 /* Queue IDs Enumeration */
244 #define PQI_ADMIN_IB_QUEUE_ID 0
245 #define PQI_ADMIN_OB_QUEUE_ID 0
246 #define PQI_MIN_OP_IB_QUEUE_ID 1
247 #define PQI_OP_EVENT_QUEUE_ID 1
248 #define PQI_MIN_OP_OB_QUEUE_ID 2
249
250
251 /* PQI IU Element Sizes */
252 #define PQISRC_ADMIN_IBQ_ELEM_SIZE_BYTES 64
253 #define PQISRC_ADMIN_OBQ_ELEM_SIZE_BYTES 64
254 #define PQISRC_OP_IBQ_ELEM_SIZE_BYTES 128
255 #define PQISRC_OP_OBQ_ELEM_SIZE_BYTES 16
256 #define PQISRC_EVENT_Q_ELEM_SIZE_BYTES 32
257
258
259 /* Number of elements this driver compile will potentially use */
260 #define PQISRC_MAX_ADMIN_IB_QUEUE_ELEM_NUM 16
261 #define PQISRC_MAX_ADMIN_OB_QUEUE_ELEM_NUM 16
262 #define PQISRC_MAX_EVENT_QUEUE_ELEM_NUM 32
263 #define PQISRC_MAX_SPANNING_ELEMS 9
264
265 /* setting maximums for adv aio */
266 #define PQISRC_MAX_AIO_RAID5_OR_6_WRITE (8*1024) /* 8 KiB */
267 #define PQISRC_MAX_AIO_RAID1_OR_10_WRITE_2DRV 0x0000 /* No Limit */
268 #define PQISRC_MAX_AIO_RAID1_OR_10_WRITE_3DRV 0x0000 /* No Limit */
269 #define PQISRC_MAX_AIO_NVME_CRYPTO (32*1024) /* 32 KiB */
270 #define PQISRC_MAX_AIO_NO_LIMIT 0x0000 /* No Limit */
271 #define PQISRC_MAX_AIO_RW_XFER_SAS_SATA_CRYPTO 0x0000 /* No Limit */
272 #define PQISRC_MAX_AIO_RW_XFER_NVME_CRYPTO (32*1024)
273
274 #define SENSE_FEATURES_CRYPTO_OFFSET offsetof(bmic_sense_feature_page_io_aio_subpage_t, max_aio_rw_xfer_crypto_sas_sata)
275 #define MINIMUM_AIO_SUBPAGE_LENGTH \
276 (offsetofend(bmic_sense_feature_page_io_aio_subpage_t, \
277 max_aio_write_raid1_10_3drv) - \
278 (sizeof(((bmic_sense_feature_page_io_aio_subpage_t *)0)->header)))
279
280 /* Not used or useful yet */
281 /* #define PQISRC_INTR_COALSC_GRAN 0 */
282 /* #define PQISRC_PROTO_BIT_MASK 0 */
283 /* #define PQISRC_SGL_SUPPORTED_BIT_MASK 0 */
284
285 #define PQISRC_MAX_SUPPORTED_MIRRORS 3
286 /* PQI Registers state status */
287
288 #define PQI_RESET_ACTION_RESET 0x1
289 #define PQI_RESET_ACTION_COMPLETED 0x2
290 #define PQI_RESET_TYPE_NO_RESET 0x0
291 #define PQI_RESET_TYPE_SOFT_RESET 0x1
292 #define PQI_RESET_TYPE_FIRM_RESET 0x2
293 #define PQI_RESET_TYPE_HARD_RESET 0x3
294
295 #define PQI_RESET_POLL_INTERVAL 100000 /*100 msec*/
296
297 enum pqisrc_ctrl_mode{
298 CTRL_SIS_MODE = 0,
299 CTRL_PQI_MODE
300 };
301
302 /* PQI device performing internal initialization (e.g., POST). */
303 #define PQI_DEV_STATE_POWER_ON_AND_RESET 0x0
304 /* Upon entry to this state PQI device initialization begins. */
305 #define PQI_DEV_STATE_PQI_STATUS_AVAILABLE 0x1
306 /* PQI device Standard registers are available to the driver. */
307 #define PQI_DEV_STATE_ALL_REGISTERS_READY 0x2
308 /* PQI device is initialized and ready to process any PCI transactions. */
309 #define PQI_DEV_STATE_ADMIN_QUEUE_PAIR_READY 0x3
310 /* The PQI Device Error register indicates the error. */
311 #define PQI_DEV_STATE_ERROR 0x4
312
313 #define PQI_DEV_STATE_AT_INIT ( PQI_DEV_STATE_PQI_STATUS_AVAILABLE | \
314 PQI_DEV_STATE_ALL_REGISTERS_READY | \
315 PQI_DEV_STATE_ADMIN_QUEUE_PAIR_READY )
316
317 #define PQISRC_PQI_DEVICE_SIGNATURE "PQI DREG"
318
319 #define PQI_ADDR_ALIGN_MASK_4K 0xFFF/* lsb 12 bits */
320 #define PQI_ADDR_ALIGN_MASK_1K 0x3FF/* lsb 10 bits */
321 #define PQI_ADDR_ALIGN_MASK_64 0x3F /* lsb 6 bits */
322 #define PQI_ADDR_ALIGN_MASK_4 0x3 /* lsb 2 bits */
323 #define PQI_ADDR_ALIGN 4096
324 #define PQI_ADDR_ALIGN_MASK PQI_ADDR_ALIGN_MASK_4K
325
326
327 #define PQI_FORCE_IQ_ELEMENTS 32 /* 4096/128 = 32 (see PQISRC_OP_IBQ_ELEM_SIZE_BYTES) */
328 #define PQI_FORCE_OQ_ELEMENTS 256 /* 4096/16 = 256 (see PQISRC_OP_OBQ_ELEM_SIZE_BYTES) */
329
330 #define PQI_CI_PI_ALIGN 64
331 #define PQI_CI_PI_ALIGN_MASK PQI_ADDR_ALIGN_MASK_64
332
333 #define PQISRC_PQIMODE_READY_TIMEOUT (30 * 1000 ) /* 30 secs */
334 #define PQISRC_MODE_READY_POLL_INTERVAL 1000 /* 1 msec */
335
336 #define PRINT_PQI_SIGNATURE(sign) { int i = 0; \
337 char si[9]; \
338 for(i=0;i<8;i++) \
339 si[i] = *((char *)&(sign)+i); \
340 si[i] = '\0'; \
341 DBG_INFO("Signature is %s",si); \
342 }
343 #define PQI_CONF_TABLE_MAX_LEN ((uint16_t)~0)
344 #define PQI_CONF_TABLE_SIGNATURE "CFGTABLE"
345
346 /* PQI configuration table section IDs */
347 #define PQI_CONF_TABLE_ALL_SECTIONS (-1)
348 #define PQI_CONF_TABLE_SECTION_GENERAL_INFO 0
349 #define PQI_CONF_TABLE_SECTION_FIRMWARE_FEATURES 1
350 #define PQI_CONF_TABLE_SECTION_FIRMWARE_ERRATA 2
351 #define PQI_CONF_TABLE_SECTION_DEBUG 3
352 #define PQI_CONF_TABLE_SECTION_HEARTBEAT 4
353 #define PQI_CONF_TABLE_SOFT_RESET 5
354
355 /* PQI feature bits as defined in PQI_SPEC.doc */
356 #define PQI_FIRMWARE_FEATURE_OFA 0
357 #define PQI_FIRMWARE_FEATURE_SMP 1
358 #define PQI_FIRMWARE_FEATURE_MAX_KNOWN_FEATURE 2
359 #define PQI_FIRMWARE_FEATURE_RAID_0_READ_BYPASS 3
360 #define PQI_FIRMWARE_FEATURE_RAID_1_READ_BYPASS 4
361 #define PQI_FIRMWARE_FEATURE_RAID_5_READ_BYPASS 5
362 #define PQI_FIRMWARE_FEATURE_RAID_6_READ_BYPASS 6
363 #define PQI_FIRMWARE_FEATURE_RAID_0_WRITE_BYPASS 7
364 #define PQI_FIRMWARE_FEATURE_RAID_1_WRITE_BYPASS 8
365 #define PQI_FIRMWARE_FEATURE_RAID_5_WRITE_BYPASS 9
366 #define PQI_FIRMWARE_FEATURE_RAID_6_WRITE_BYPASS 10
367 #define PQI_FIRMWARE_FEATURE_SOFT_RESET_HANDSHAKE 11
368 #define PQI_FIRMWARE_FEATURE_UNIQUE_SATA_WWN 12
369 #define PQI_FIRMWARE_FEATURE_RAID_IU_TIMEOUT 13
370 #define PQI_FIRMWARE_FEATURE_TMF_IU_TIMEOUT 14
371 #define PQI_FIRMWARE_FEATURE_MAXIMUM 14
372 #define PQI_FIRMWARE_FEATURE_PAGE83_IDENTIFIER_FOR_RPL_WWID 16
373
374 #define CTRLR_HEARTBEAT_CNT(softs) LE_64(PCI_MEM_GET64(softs, softs->heartbeat_counter_abs_addr, softs->heartbeat_counter_off))
375 #define PQI_HEARTBEAT_TIMEOUT_SEC (10) /* 10 sec interval */
376 #define PQI_HOST_WELLNESS_TIMEOUT_SEC (24*3600)
377
378 /* pqi-2r00a table 36 */
379 #define PQI_ADMIN_QUEUE_MSIX_DISABLE (0x80000000)
380 #define PQI_ADMIN_QUEUE_MSIX_ENABLE (0 << 31)
381
382 #define PQI_ADMIN_QUEUE_CONF_FUNC_CREATE_Q_PAIR 0x01
383 #define PQI_ADMIN_QUEUE_CONF_FUNC_DEL_Q_PAIR 0x02
384 #define PQI_ADMIN_QUEUE_CONF_FUNC_STATUS_IDLE 0x00
385 #define PQISRC_ADMIN_QUEUE_CREATE_TIMEOUT 1000 /* in miLLI sec, 1 sec, 100 ms is standard */
386 #define PQISRC_ADMIN_QUEUE_DELETE_TIMEOUT 100 /* 100 ms is standard */
387 #define PQISRC_ADMIN_CMD_RESP_TIMEOUT 3000 /* 3 sec */
388 #define PQISRC_RAIDPATH_CMD_TIMEOUT 30000 /* 30 sec */
389
390 #define REPORT_PQI_DEV_CAP_DATA_BUF_SIZE sizeof(pqi_dev_cap_t)
391 #define REPORT_MANUFACTURER_INFO_DATA_BUF_SIZE 0x80 /* Data buffer size specified in bytes 0-1 of data buffer. 128 bytes. */
392 /* PQI IUs */
393 /* Admin IU request length not including header. */
394 #define PQI_STANDARD_IU_LENGTH 0x003C /* 60 bytes. */
395 #define PQI_IU_TYPE_GENERAL_ADMIN_REQUEST 0x60
396 #define PQI_IU_TYPE_GENERAL_ADMIN_RESPONSE 0xe0
397
398 /* PQI / Vendor specific IU */
399 #define PQI_FUNCTION_REPORT_DEV_CAP 0x00
400 #define PQI_REQUEST_IU_RAID_TASK_MANAGEMENT 0x13
401 #define PQI_IU_TYPE_RAID_PATH_IO_REQUEST 0x14
402 #define PQI_IU_TYPE_AIO_PATH_IO_REQUEST 0x15
403 #define PQI_REQUEST_IU_AIO_TASK_MANAGEMENT 0x16
404 #define PQI_IU_TYPE_RAID5_WRITE_BYPASS_REQUEST 0x18
405 #define PQI_IU_TYPE_RAID6_WRITE_BYPASS_REQUEST 0x19
406 #define PQI_IU_TYPE_RAID1_WRITE_BYPASS_REQUEST 0x1A
407 #define PQI_REQUEST_IU_AIO_BYPASS_TASK_MGMT 0x20
408 #define PQI_REQUEST_IU_GENERAL_ADMIN 0x60
409 #define PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG 0x72
410 #define PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG 0x73
411 #define PQI_REQUEST_IU_VENDOR_GENERAL 0x75
412 #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81
413 #define PQI_RESPONSE_IU_TASK_MANAGEMENT 0x93
414 #define PQI_RESPONSE_IU_GENERAL_ADMIN 0xe0
415
416 #define PQI_RESPONSE_IU_RAID_PATH_IO_SUCCESS 0xf0
417 #define PQI_RESPONSE_IU_AIO_PATH_IO_SUCCESS 0xf1
418 #define PQI_RESPONSE_IU_RAID_PATH_IO_ERROR 0xf2
419 #define PQI_RESPONSE_IU_AIO_PATH_IO_ERROR 0xf3
420 #define PQI_RESPONSE_IU_AIO_PATH_IS_OFF 0xf4
421 #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6
422 #define PQI_RESPONSE_IU_VENDOR_GENERAL 0xf7
423 #define PQI_REQUEST_HEADER_LENGTH 4
424 #define PQI_FUNCTION_CREATE_OPERATIONAL_IQ 0x10
425 #define PQI_FUNCTION_CREATE_OPERATIONAL_OQ 0x11
426 #define PQI_FUNCTION_DELETE_OPERATIONAL_IQ 0x12
427 #define PQI_FUNCTION_DELETE_OPERATIONAL_OQ 0x13
428 #define PQI_FUNCTION_CHANGE_OPERATIONAL_IQ_PROP 0x14
429 #define PQI_CHANGE_OP_IQ_PROP_ASSIGN_AIO 1
430
431 #define PQI_DEFAULT_IB_QUEUE 0
432 #define PQI_VENDOR_GENERAL_CONFIG_TABLE_UPDATE 0
433
434 #define PQI_VENDOR_RESPONSE_IU_SUCCESS 0
435 #define PQI_VENDOR_RESPONSE_IU_UNSUCCESS 1
436 #define PQI_VENDOR_RESPONSE_IU_INVALID_PARAM 2
437 #define PQI_VENDOR_RESPONSE_IU_INSUFF_RESRC 3
438
439 /* Interface macros */
440
441 #define GET_FW_STATUS(softs) \
442 (PCI_MEM_GET32(softs, &softs->ioa_reg->scratchpad3_fw_status, LEGACY_SIS_OMR))
443
444 #define SIS_IS_KERNEL_PANIC(softs) \
445 (GET_FW_STATUS(softs) & PQI_CTRL_KERNEL_PANIC)
446
447 #define SIS_IS_KERNEL_UP(softs) \
448 (GET_FW_STATUS(softs) & PQI_CTRL_KERNEL_UP_AND_RUNNING)
449
450 #define PQI_GET_CTRL_MODE(softs) \
451 (PCI_MEM_GET32(softs, &softs->ioa_reg->scratchpad0, LEGACY_SIS_SCR0))
452
453 #define PQI_SAVE_CTRL_MODE(softs, mode) { \
454 PCI_MEM_PUT32(softs, &softs->ioa_reg->scratchpad0, LEGACY_SIS_SCR0, mode); \
455 OS_SLEEP(1000); \
456 }
457
458 #define LEGACY_SIS_SCR_REG_LENGTH 4
459 #define LEGACY_SIS_SCR1 LEGACY_SIS_SCR0 + LEGACY_SIS_SCR_REG_LENGTH
460 #define PQI_GET_CTRL_TYPE(softs) \
461 ((PCI_MEM_GET32(softs, &softs->ioa_reg->scratchpad1, LEGACY_SIS_SCR1)) \
462 & 0x0000FFFF)
463
464 /* smart raid-hba pqi functional spec, scratchpad register 1 spec */
465 #define PQI_CTRL_PRODUCT_ID_GEN1 0x0000
466 #define PQI_CTRL_PRODUCT_ID_GEN2_REV_A 0x0007
467 #define PQI_CTRL_PRODUCT_ID_GEN2_REV_B 0x0107
468
469 #define PQISRC_MAX_TARGETID 1024
470 #define PQISRC_MAX_TARGETLUN 64
471
472 /* Vendor specific IU Type for Event config Cmds */
473 #define PQI_REQUEST_IU_REPORT_EVENT_CONFIG 0x72
474 #define PQI_REQUEST_IU_SET_EVENT_CONFIG 0x73
475 #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6
476
477
478 #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81
479 #define PQI_MANAGEMENT_CMD_RESP_TIMEOUT 3000
480 #define PQISRC_EVENT_ACK_RESP_TIMEOUT 1000
481
482
483 /* Supported Event types by controller */
484
485 #define PQI_NUM_SUPPORTED_EVENTS 6
486
487 #define PQI_EVENT_TYPE_HOTPLUG 0x1
488 #define PQI_EVENT_TYPE_HARDWARE 0x2
489 #define PQI_EVENT_TYPE_PHYSICAL_DEVICE 0x4
490 #define PQI_EVENT_TYPE_LOGICAL_DEVICE 0x5
491 #define PQI_EVENT_TYPE_AIO_STATE_CHANGE 0xfd
492 #define PQI_EVENT_TYPE_AIO_CONFIG_CHANGE 0xfe
493
494 /* for indexing into the pending_events[] field of struct pqisrc_softstate */
495 #define PQI_EVENT_HOTPLUG 0
496 #define PQI_EVENT_HARDWARE 1
497 #define PQI_EVENT_PHYSICAL_DEVICE 2
498 #define PQI_EVENT_LOGICAL_DEVICE 3
499 #define PQI_EVENT_AIO_STATE_CHANGE 4
500 #define PQI_EVENT_AIO_CONFIG_CHANGE 5
501
502
503
504 /* Device flags */
505 #define PQISRC_DFLAG_VALID (1 << 0)
506 #define PQISRC_DFLAG_CONFIGURING (1 << 1)
507
508 #define MAX_EMBEDDED_SG_IN_FIRST_IU_DEFAULT 4
509 #define MAX_EMBEDDED_SG_IN_FIRST_IU_RAID56_AIO 3
510 #define MAX_EMBEDDED_SG_IN_IU 8
511 #define SG_FLAG_LAST 0x40000000
512 #define SG_FLAG_CHAIN 0x80000000
513
514 #define IN_PQI_RESET(softs) (softs->ctlr_state & PQI_BUS_RESET)
515 #define DEV_GONE(dev) (!dev || (dev->invalid == true))
516 #define IS_AIO_PATH(dev) (dev->aio_enabled)
517 #define IS_RAID_PATH(dev) (!dev->aio_enabled)
518
519 #define DEVICE_RESET(dvp) (dvp->reset_in_progress)
520
521 /* SOP data direction flags */
522 #define SOP_DATA_DIR_UNKNOWN 0xFF
523 #define SOP_DATA_DIR_NONE 0x00
524 #define SOP_DATA_DIR_FROM_DEVICE 0x01
525 #define SOP_DATA_DIR_TO_DEVICE 0x02
526 #define SOP_DATA_DIR_BIDIRECTIONAL 0x03
527 #define SOP_PARTIAL_DATA_BUFFER 0x04
528
529 #define PQISRC_DMA_VALID (1 << 0)
530 #define PQISRC_CMD_NO_INTR (1 << 1)
531
532 #define SOP_TASK_ATTRIBUTE_SIMPLE 0
533 #define SOP_TASK_ATTRIBUTE_HEAD_OF_QUEUE 1
534 #define SOP_TASK_ATTRIBUTE_ORDERED 2
535 #define SOP_TASK_ATTRIBUTE_ACA 4
536
537 #define SOP_TASK_MANAGEMENT_FUNCTION_COMPLETE 0x0
538 #define SOP_TASK_MANAGEMENT_FUNCTION_REJECTED 0x4
539 #define SOP_TASK_MANAGEMENT_FUNCTION_FAILED 0x5
540 #define SOP_TASK_MANAGEMENT_FUNCTION_SUCCEEDED 0x8
541 #define SOP_TASK_MANAGEMENT_FUNCTION_ABORT_TASK 0x01
542 #define SOP_TASK_MANAGEMENT_FUNCTION_ABORT_TASK_SET 0x02
543 #define SOP_TASK_MANAGEMENT_LUN_RESET 0x8
544
545
546 /* Additional CDB bytes */
547 #define PQI_ADDITIONAL_CDB_BYTES_0 0 /* 16 byte CDB */
548 #define PQI_ADDITIONAL_CDB_BYTES_4 1 /* 20 byte CDB */
549 #define PQI_ADDITIONAL_CDB_BYTES_8 2 /* 24 byte CDB */
550 #define PQI_ADDITIONAL_CDB_BYTES_12 3 /* 28 byte CDB */
551 #define PQI_ADDITIONAL_CDB_BYTES_16 4 /* 32 byte CDB */
552
553 #define PQI_PROTOCOL_SOP 0x0
554
555 #define PQI_AIO_STATUS_GOOD 0x0
556 #define PQI_AIO_STATUS_CHECK_CONDITION 0x2
557 #define PQI_AIO_STATUS_CONDITION_MET 0x4
558 #define PQI_AIO_STATUS_DEVICE_BUSY 0x8
559 #define PQI_AIO_STATUS_INT_GOOD 0x10
560 #define PQI_AIO_STATUS_INT_COND_MET 0x14
561 #define PQI_AIO_STATUS_RESERV_CONFLICT 0x18
562 #define PQI_AIO_STATUS_CMD_TERMINATED 0x22
563 #define PQI_AIO_STATUS_QUEUE_FULL 0x28
564 #define PQI_AIO_STATUS_TASK_ABORTED 0x40
565 #define PQI_AIO_STATUS_UNDERRUN 0x51
566 #define PQI_AIO_STATUS_OVERRUN 0x75
567 /* Status when Target Failure */
568 #define PQI_AIO_STATUS_IO_ERROR 0x1
569 #define PQI_AIO_STATUS_IO_ABORTED 0x2
570 #define PQI_AIO_STATUS_IO_NO_DEVICE 0x3
571 #define PQI_AIO_STATUS_INVALID_DEVICE 0x4
572 #define PQI_AIO_STATUS_AIO_PATH_DISABLED 0xe
573
574 /* Service Response */
575 #define PQI_AIO_SERV_RESPONSE_COMPLETE 0
576 #define PQI_AIO_SERV_RESPONSE_FAILURE 1
577 #define PQI_AIO_SERV_RESPONSE_TMF_COMPLETE 2
578 #define PQI_AIO_SERV_RESPONSE_TMF_SUCCEEDED 3
579 #define PQI_AIO_SERV_RESPONSE_TMF_REJECTED 4
580 #define PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN 5
581
582 #define PQI_TMF_WAIT_DELAY 10000000 /* 10 seconds */
583
584 #define PQI_RAID_STATUS_GOOD PQI_AIO_STATUS_GOOD
585 #define PQI_RAID_STATUS_CHECK_CONDITION PQI_AIO_STATUS_CHECK_CONDITION
586 #define PQI_RAID_STATUS_CONDITION_MET PQI_AIO_STATUS_CONDITION_MET
587 #define PQI_RAID_STATUS_DEVICE_BUSY PQI_AIO_STATUS_DEVICE_BUSY
588 #define PQI_RAID_STATUS_INT_GOOD PQI_AIO_STATUS_INT_GOOD
589 #define PQI_RAID_STATUS_INT_COND_MET PQI_AIO_STATUS_INT_COND_MET
590 #define PQI_RAID_STATUS_RESERV_CONFLICT PQI_AIO_STATUS_RESERV_CONFLICT
591 #define PQI_RAID_STATUS_CMD_TERMINATED PQI_AIO_STATUS_CMD_TERMINATED
592 #define PQI_RAID_STATUS_QUEUE_FULL PQI_AIO_STATUS_QUEUE_FULL
593 #define PQI_RAID_STATUS_TASK_ABORTED PQI_AIO_STATUS_TASK_ABORTED
594 #define PQI_RAID_STATUS_UNDERRUN PQI_AIO_STATUS_UNDERRUN
595 #define PQI_RAID_STATUS_OVERRUN PQI_AIO_STATUS_OVERRUN
596
597 #define NUM_STREAMS_PER_LUN 8
598
599 /* VPD inquiry pages */
600 #define SCSI_VPD_SUPPORTED_PAGES 0x0 /* standard page */
601 #define SCSI_VPD_DEVICE_ID 0x83 /* standard page */
602 #define SA_VPD_PHYS_DEVICE_ID 0xc0 /* vendor-specific page */
603 #define SA_VPD_LV_DEVICE_GEOMETRY 0xc1 /* vendor-specific page */
604 #define SA_VPD_LV_IOACCEL_STATUS 0xc2 /* vendor-specific page */
605 #define SA_VPD_LV_STATUS 0xc3 /* vendor-specific page */
606
607 #define VPD_PAGE (1 << 8)
608
609
610 /* logical volume states */
611 #define SA_LV_OK 0x0
612 #define SA_LV_FAILED 0x1
613 #define SA_LV_NOT_CONFIGURED 0x2
614 #define SA_LV_DEGRADED 0x3
615 #define SA_LV_READY_FOR_RECOVERY 0x4
616 #define SA_LV_UNDERGOING_RECOVERY 0x5
617 #define SA_LV_WRONG_PHYSICAL_DRIVE_REPLACED 0x6
618 #define SA_LV_PHYSICAL_DRIVE_CONNECTION_PROBLEM 0x7
619 #define SA_LV_HARDWARE_OVERHEATING 0x8
620 #define SA_LV_HARDWARE_HAS_OVERHEATED 0x9
621 #define SA_LV_UNDERGOING_EXPANSION 0xA
622 #define SA_LV_NOT_AVAILABLE 0xb
623 #define SA_LV_QUEUED_FOR_EXPANSION 0xc
624 #define SA_LV_DISABLED_SCSI_ID_CONFLICT 0xd
625 #define SA_LV_EJECTED 0xe
626 #define SA_LV_UNDERGOING_ERASE 0xf
627 #define SA_LV_UNDERGOING_RPI 0x12
628 #define SA_LV_PENDING_RPI 0x13
629 #define SA_LV_ENCRYPTED_NO_KEY 0x14
630 #define SA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER 0x15
631 #define SA_LV_UNDERGOING_ENCRYPTION 0x16
632 #define SA_LV_UNDERGOING_ENCRYPTION_REKEYING 0x17
633 #define SA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 0x18
634 #define SA_LV_PENDING_ENCRYPTION 0x19
635 #define SA_LV_PENDING_ENCRYPTION_REKEYING 0x1a
636 #define SA_LV_STATUS_VPD_UNSUPPORTED 0xff
637
638
639 /* constants for flags field of ciss_vpd_logical_volume_status */
640 #define SA_LV_FLAGS_NO_HOST_IO 0x1 /* volume not available for */
641
642 /*
643 * assume worst case: SATA queue depth of 31 minus 4 internal firmware commands
644 */
645 #define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 27
646
647 /* 0 = no limit */
648 #define PQI_LOGICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 0
649 #define PQI_LOG_EXT_QUEUE_DEPTH_ENABLED 0x20
650 #define PQI_LOG_EXT_QUEUE_ENABLE 0x56
651 #define MAX_RAW_M256_QDEPTH 32512
652 #define MAX_RAW_M16_QDEPTH 2032
653 #define PQI_PTRAID_UPDATE_ON_RESCAN_LUNS 0x80000000
654
655 #define RAID_CTLR_LUNID ((uint8_t *) "\0\0\0\0\0\0\0\0")
656
657 /* SCSI Cmds @todo: move SCMD_READ_6, etc. into library */
658 #define SCSI_INQUIRY 0x12
659 #define SCSI_MODE_SENSE 0x1a
660 #define SCSI_REPORT_LUNS 0xa0
661 #define SCSI_LOG_SENSE 0x4d
662 #define SCSI_ATA_PASSTHRU16 0x85
663
664 #define PQISRC_INQUIRY_TIMEOUT 30
665
666 #define SA_INQUIRY 0x12
667 #define SA_REPORT_LOG 0xc2 /* Report Logical LUNs */
668 #define SA_REPORT_PHYS 0xc3 /* Report Physical LUNs */
669 #define SA_CISS_READ 0xc0
670 #define SA_GET_RAID_MAP 0xc8
671
672 #define SCSI_SENSE_RESPONSE_70 0x70
673 #define SCSI_SENSE_RESPONSE_71 0x71
674 #define SCSI_SENSE_RESPONSE_72 0x72
675 #define SCSI_SENSE_RESPONSE_73 0x73
676
677 #define SA_REPORT_LOG_EXTENDED 0x1
678 #define SA_REPORT_PHYS_EXTENDED 0x2
679
680 #define GET_SCSI_SNO(cmd) (cmd->cmdId.serialNumber)
681
682 #define REPORT_LUN_DEV_FLAG_AIO_ENABLED 0x8
683 #define PQI_MAX_TRANSFER_SIZE (4 * 1024U * 1024U)
684 #define RAID_MAP_MAX_ENTRIES 1024
685 #define RAID_MAP_ENCRYPTION_ENABLED 0x1
686 #define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 27
687
688 #define ASC_LUN_NOT_READY 0x4
689 #define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x4
690 #define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x2
691
692
693 #define OBDR_SIG_OFFSET 43
694 #define OBDR_TAPE_SIG "$DR-10"
695 #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
696 #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
697
698
699 #define IOACCEL_STATUS_BYTE 4
700 #define OFFLOAD_CONFIGURED_BIT 0x1
701 #define OFFLOAD_ENABLED_BIT 0x2
702
703 #define PQI_RAID_DATA_IN_OUT_GOOD 0x0
704 #define PQI_RAID_DATA_IN_OUT_UNDERFLOW 0x1
705 #define PQI_RAID_DATA_IN_OUT_BUFFER_ERROR 0x40
706 #define PQI_RAID_DATA_IN_OUT_BUFFER_OVERFLOW 0x41
707 #define PQI_RAID_DATA_IN_OUT_BUFFER_OVERFLOW_DESCRIPTOR_AREA 0x42
708 #define PQI_RAID_DATA_IN_OUT_BUFFER_OVERFLOW_BRIDGE 0x43
709 #define PQI_RAID_DATA_IN_OUT_PCIE_FABRIC_ERROR 0x60
710 #define PQI_RAID_DATA_IN_OUT_PCIE_COMPLETION_TIMEOUT 0x61
711 #define PQI_RAID_DATA_IN_OUT_PCIE_COMPLETER_ABORT_RECEIVED 0x62
712 #define PQI_RAID_DATA_IN_OUT_PCIE_POISONED_MEMORY_READ 0x63
713 #define PQI_RAID_DATA_IN_OUT_PCIE_ECRC_CHECK_FAILED 0x64
714 #define PQI_RAID_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST 0x65
715 #define PQI_RAID_DATA_IN_OUT_PCIE_ACS_VIOLATION 0x66
716 #define PQI_RAID_DATA_IN_OUT_PCIE_TLP_PREFIX_BLOCKED 0x67
717 #define PQI_RAID_DATA_IN_OUT_ERROR 0xf0
718 #define PQI_RAID_DATA_IN_OUT_PROTOCOL_ERROR 0xf1
719 #define PQI_RAID_DATA_IN_OUT_HARDWARE_ERROR 0xf2
720 #define PQI_RAID_DATA_IN_OUT_UNSOLICITED_ABORT 0xf3
721 #define PQI_RAID_DATA_IN_OUT_ABORTED 0xf4
722 #define PQI_RAID_DATA_IN_OUT_TIMEOUT 0xf5
723
724
725 #define PQI_PHYSICAL_DEVICE_BUS 0
726 #define PQI_RAID_VOLUME_BUS 1
727 #define PQI_HBA_BUS 2
728 #define PQI_EXTERNAL_RAID_VOLUME_BUS 3
729 #define PQI_MAX_BUS PQI_EXTERNAL_RAID_VOLUME_BUS
730
731 #define TEST_UNIT_READY 0x00
732 #define SCSI_VPD_HEADER_LENGTH 64
733
734
735 #define PQI_MAX_MULTILUN 256
736 #define PQI_MAX_LOGICALS 64
737 #define PQI_MAX_PHYSICALS 1024
738 #define PQI_MAX_DEVICES (PQI_MAX_LOGICALS + PQI_MAX_PHYSICALS + 1) /* 1 for controller device entry */
739 #define PQI_MAX_EXT_TARGETS 32
740
741 #define PQI_CTLR_INDEX 0
742 #define PQI_PD_INDEX(t) (t + PQI_MAX_LOGICALS)
743
744 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
745 #define MAX_TARGET_DEVICES 1024
746 #define MAX_TARGET_BIT 1025
747 #define SLOT_AVAILABLE false
748 #define SLOT_TAKEN true
749
750 #define PQI_NO_MEM 2
751
752 typedef enum pqisrc_device_status {
753 DEVICE_NOT_FOUND,
754 DEVICE_CHANGED,
755 DEVICE_UNCHANGED,
756 DEVICE_IN_REMOVE,
757 } device_status_t;
758
759 #define SA_RAID_0 0
760 #define SA_RAID_4 1
761 #define SA_RAID_1 2 /* also used for RAID 10 */
762 #define SA_RAID_5 3 /* also used for RAID 50 */
763 #define SA_RAID_51 4
764 #define SA_RAID_6 5 /* also used for RAID 60 */
765 #define SA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
766 #define SA_RAID_MAX SA_RAID_ADM
767 #define SA_RAID_UNKNOWN 0xff
768
769 #define BIT0 (1 << 0)
770 #define BIT1 (1 << 1)
771 #define BIT2 (1 << 2)
772 #define BIT3 (1 << 3)
773
774 #define BITS_PER_BYTE 8
775
776
777 /* Vendor Specific (BMIC) Op Code */
778 #define BMIC_READ 0x26
779 #define BMIC_WRITE 0x27
780 #define IS_BMIC_OPCODE(opcode) (opcode == BMIC_READ || opcode == BMIC_WRITE)
781 /* BMIC commands */
782 #define BMIC_IDENTIFY_CONTROLLER 0x11
783 #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15
784 #define BMIC_SENSE_FEATURE 0x61
785 #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64
786 #define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66
787 #define BMIC_WRITE_HOST_WELLNESS 0xa5
788 #define BMIC_CACHE_FLUSH 0xc2
789 #define BMIC_SET_DIAGS_OPTIONS 0xf4
790 #define BMIC_SENSE_DIAGS_OPTIONS 0xf5
791 #define BMIC_FLASH_FIRMWARE 0xf7
792
793 /* Sense Feature Pages/Subpages */
794 #define IO_SENSE_FEATURES_PAGE 0x08
795 #define SENSE_FEATURES_AIO_SUBPAGE 0x02
796
797 #define MASKED_DEVICE(lunid) ((lunid)[3] & 0xC0)
798 #define BMIC_GET_LEVEL_2_BUS(lunid) ((lunid)[7] & 0x3F)
799 #define BMIC_GET_LEVEL_TWO_TARGET(lunid) ((lunid)[6])
800 #define BMIC_GET_DRIVE_NUMBER(lunid) \
801 (((BMIC_GET_LEVEL_2_BUS((lunid)) - 1) << 8) + \
802 BMIC_GET_LEVEL_TWO_TARGET((lunid)))
803 #define NON_DISK_PHYS_DEV(rle) \
804 (((reportlun_ext_entry_t *)(rle))->device_flags & 0x1)
805
806 #define NO_TIMEOUT ((unsigned long) -1)
807
808 #define BMIC_DEVICE_TYPE_SATA 0x1
809
810 /* No of IO slots required for internal requests */
811 #define PQI_RESERVED_IO_SLOTS_SYNC_REQUESTS 3
812 #define PQI_RESERVED_IO_SLOTS_TMF 1
813 #define PQI_RESERVED_IO_SLOTS_CNT (PQI_NUM_SUPPORTED_EVENTS + \
814 PQI_RESERVED_IO_SLOTS_TMF + \
815 PQI_RESERVED_IO_SLOTS_SYNC_REQUESTS)
816
817 /* Defines for counter flags */
818 #define COUNTER_FLAG_CLEAR_COUNTS 0x0001
819 #define COUNTER_FLAG_ONLY_NON_ZERO 0x0002
820
821 /* Defines for print flags */
822 #define PRINT_FLAG_HDR_COLUMN 0x0001
823
824
825 /* Function-specific debug flags */
826 #if 0
827 #define DEBUG_AIO /* show AIO eligibility, IU, etc. (very spammy!) */
828 #define DEBUG_AIO_LOCATOR /* show AIO row/column etc. calc. */
829 #define DEBUG_RAID_MAP /* show AIO raid map content from FW */
830 #endif
831
GET_LE16(const uint8_t * p)832 static inline uint16_t GET_LE16(const uint8_t *p)
833 {
834 return p[0] | p[1] << 8;
835 }
836
GET_LE32(const uint8_t * p)837 static inline uint32_t GET_LE32(const uint8_t *p)
838 {
839 return p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24;
840 }
841
GET_LE64(const uint8_t * p)842 static inline uint64_t GET_LE64(const uint8_t *p)
843 {
844 return (((uint64_t)GET_LE32(p + 4) << 32) |
845 GET_LE32(p));
846 }
847
GET_BE16(const uint8_t * p)848 static inline uint16_t GET_BE16(const uint8_t *p)
849 {
850 return p[0] << 8 | p[1];
851 }
852
GET_BE32(const uint8_t * p)853 static inline uint32_t GET_BE32(const uint8_t *p)
854 {
855 return p[0] << 24 | p[1] << 16 | p[2] << 8 | p[3];
856 }
857
GET_BE64(const uint8_t * p)858 static inline uint64_t GET_BE64(const uint8_t *p)
859 {
860 return (((uint64_t)GET_BE32(p) << 32) |
861 GET_BE32(p + 4));
862 }
863
PUT_BE16(uint16_t val,uint8_t * p)864 static inline void PUT_BE16(uint16_t val, uint8_t *p)
865 {
866 *p++ = val >> 8;
867 *p++ = val;
868 }
869
PUT_BE32(uint32_t val,uint8_t * p)870 static inline void PUT_BE32(uint32_t val, uint8_t *p)
871 {
872 PUT_BE16(val >> 16, p);
873 PUT_BE16(val, p + 2);
874 }
875
PUT_BE64(uint64_t val,uint8_t * p)876 static inline void PUT_BE64(uint64_t val, uint8_t *p)
877 {
878 PUT_BE32(val >> 32, p);
879 PUT_BE32(val, p + 4);
880 }
881
882
883 /* Calculates percentage of val vs total, i.e. 20 out of 100 --> 20% */
CALC_PERCENT_TOTAL(uint64_t val,uint64_t total)884 static inline uint64_t CALC_PERCENT_TOTAL(uint64_t val, uint64_t total)
885 {
886 uint64_t percent = 0;
887 if (total)
888 percent = (val * 100) / total;
889 return percent;
890 }
891
892 /* Calculates percentage of a vs b, i.e. 50 vs 100 -> 50/150 -> 33% */
893 #define CALC_PERCENT_VS(a, b) (CALC_PERCENT_TOTAL(a, (a+b)))
894
895 #define STREAM_DETECTION "stream_disable"
896 #define SATA_UNIQUE_WWN "sata_unique_wwn_disable"
897 #define AIO_RAID1_WRITE_BYPASS "aio_raid1_write_disable"
898 #define AIO_RAID5_WRITE_BYPASS "aio_raid5_write_disable"
899 #define AIO_RAID6_WRITE_BYPASS "aio_raid6_write_disable"
900 #define ADAPTER_QUEUE_DEPTH "queue_depth"
901 #define SCATTER_GATHER_COUNT "sg_count"
902 #define QUEUE_COUNT "queue_count"
903
904 #define OS_ATTRIBUTE_PACKED __attribute__((__packed__))
905 #define OS_ATTRIBUTE_ALIGNED(n) __attribute__((aligned(n)))
906
907
908 /* Management Interface */
909 #define CCISS_IOC_MAGIC 'C'
910 #define SMARTPQI_IOCTL_BASE 'M'
911 #define CCISS_GETDRIVVER _IOWR(SMARTPQI_IOCTL_BASE, 0, driver_info)
912 #define CCISS_GETPCIINFO _IOWR(SMARTPQI_IOCTL_BASE, 1, pqi_pci_info_t)
913 #define SMARTPQI_PASS_THRU _IOWR(SMARTPQI_IOCTL_BASE, 2, IOCTL_Command_struct)
914 #define CCISS_PASSTHRU _IOWR('C', 210, IOCTL_Command_struct)
915 #define CCISS_REGNEWD _IO(CCISS_IOC_MAGIC, 14)
916
917 /*IOCTL pci_info structure */
918 typedef struct pqi_pci_info
919 {
920 unsigned char bus;
921 unsigned char dev_fn;
922 unsigned short domain;
923 uint32_t board_id;
924 uint32_t chip_id;
925 }pqi_pci_info_t;
926
927 typedef struct _driver_info
928 {
929 unsigned char major_version;
930 unsigned long minor_version;
931 unsigned char release_version;
932 unsigned long build_revision;
933 unsigned long max_targets;
934 unsigned long max_io;
935 unsigned long max_transfer_length;
936 }driver_info, *pdriver_info;
937
938 typedef uint8_t *passthru_buf_type_t;
939
940 #define PQISRC_DRIVER_MAJOR __FreeBSD__
941 #define PQISRC_DRIVER_MINOR 4410
942 #define PQISRC_DRIVER_RELEASE 0
943 #define PQISRC_DRIVER_REVISION 2005
944
945 #define STR(s) # s
946 #define PQISRC_VERSION(a, b, c, d) STR(a.b.c-d)
947 #define PQISRC_DRIVER_VERSION PQISRC_VERSION(PQISRC_DRIVER_MAJOR, \
948 PQISRC_DRIVER_MINOR, \
949 PQISRC_DRIVER_RELEASE, \
950 PQISRC_DRIVER_REVISION)
951
952 /* End Management interface */
953
954 #ifdef ASSERT
955 #undef ASSERT
956 #endif
957
958 /*
959 *os_atomic64_cas--
960 *
961 *Atomically read, compare, and conditionally write.
962 *i.e. compare and swap.
963 *retval True On Success
964 *retval False On Failure
965 *
966 */
967 static inline boolean_t
os_atomic64_cas(volatile uint64_t * var,uint64_t old_val,uint64_t new_val)968 os_atomic64_cas(volatile uint64_t* var, uint64_t old_val, uint64_t new_val)
969 {
970 return (atomic_cmpset_64(var, old_val, new_val));
971 }
972
973 #define ASSERT(cond) {\
974 if (!(cond)) { \
975 printf("Assertion failed at file %s line %d\n",__FILE__,__LINE__); \
976 } \
977 }
978
979 /* Atomic */
980 typedef volatile uint64_t OS_ATOMIC64_T;
981 #define OS_ATOMIC64_READ(p) atomic_load_acq_64(p)
982 #define OS_ATOMIC64_INIT(p,val) atomic_store_rel_64(p, val)
983
984 /* 64-bit post atomic increment and decrement operations on value in pointer.*/
985 #define OS_ATOMIC64_DEC(p) (atomic_fetchadd_64(p, -1) - 1)
986 #define OS_ATOMIC64_INC(p) (atomic_fetchadd_64(p, 1) + 1)
987
988
989 #define PQI_MAX_MSIX 64 /* vectors */
990 #define PQI_MSI_CTX_SIZE sizeof(pqi_intr_ctx)+1
991 #define IS_POLLING_REQUIRED(softs) if (cold) {\
992 pqisrc_process_event_intr_src(softs, 0);\
993 pqisrc_process_response_queue(softs, 1);\
994 }
995
996 #define OS_GET_TASK_ATTR(rcb) os_get_task_attr(rcb)
997 #define OS_FW_HEARTBEAT_TIMER_INTERVAL (5)
998
999 typedef struct PCI_ACC_HANDLE {
1000 bus_space_tag_t pqi_btag;
1001 bus_space_handle_t pqi_bhandle;
1002 } PCI_ACC_HANDLE_T;
1003
1004 /*
1005 * Legacy SIS Register definitions for the Adaptec PMC SRC/SRCv/smartraid adapters.
1006 */
1007 /* accessible via BAR0 */
1008 #define LEGACY_SIS_IOAR 0x18 /* IOA->host interrupt register */
1009 #define LEGACY_SIS_IDBR 0x20 /* inbound doorbell register */
1010 #define LEGACY_SIS_IISR 0x24 /* inbound interrupt status register */
1011 #define LEGACY_SIS_OIMR 0x34 /* outbound interrupt mask register */
1012 #define LEGACY_SIS_ODBR_R 0x9c /* outbound doorbell register read */
1013 #define LEGACY_SIS_ODBR_C 0xa0 /* outbound doorbell register clear */
1014
1015 #define LEGACY_SIS_SCR0 0xb0 /* scratchpad 0 */
1016 #define LEGACY_SIS_OMR 0xbc /* outbound message register */
1017 #define LEGACY_SIS_IQUE64_L 0xc0 /* inbound queue address 64-bit (low) */
1018 #define LEGACY_SIS_IQUE64_H 0xc4 /* inbound queue address 64-bit (high)*/
1019 #define LEGACY_SIS_ODBR_MSI 0xc8 /* MSI register for sync./AIF */
1020 #define LEGACY_SIS_IQN_L 0xd0 /* inbound queue native mode (low) */
1021 #define LEGACY_SIS_IQN_H 0xd4 /* inbound queue native mode (high)*/
1022 #define LEGACY_SIS_MAILBOX 0x7fc60 /* mailbox (20 bytes) */
1023 #define LEGACY_SIS_SRCV_MAILBOX 0x1000 /* mailbox (20 bytes) */
1024 #define LEGACY_SIS_SRCV_OFFSET_MAILBOX_7 0x101C /* mailbox 7 register offset */
1025
1026 #define LEGACY_SIS_ODR_SHIFT 12 /* outbound doorbell shift */
1027 #define LEGACY_SIS_IDR_SHIFT 9 /* inbound doorbell shift */
1028
1029
1030 /*
1031 * PQI Register definitions for the smartraid adapters
1032 */
1033 /* accessible via BAR0 */
1034 #define PQI_SIGNATURE 0x4000
1035 #define PQI_ADMINQ_CONFIG 0x4008
1036 #define PQI_ADMINQ_CAP 0x4010
1037 #define PQI_LEGACY_INTR_STATUS 0x4018
1038 #define PQI_LEGACY_INTR_MASK_SET 0x401C
1039 #define PQI_LEGACY_INTR_MASK_CLR 0x4020
1040 #define PQI_DEV_STATUS 0x4040
1041 #define PQI_ADMIN_IBQ_PI_OFFSET 0x4048
1042 #define PQI_ADMIN_OBQ_CI_OFFSET 0x4050
1043 #define PQI_ADMIN_IBQ_ELEM_ARRAY_ADDR 0x4058
1044 #define PQI_ADMIN_OBQ_ELEM_ARRAY_ADDR 0x4060
1045 #define PQI_ADMIN_IBQ_CI_ADDR 0x4068
1046 #define PQI_ADMIN_OBQ_PI_ADDR 0x4070
1047 #define PQI_ADMINQ_PARAM 0x4078
1048 #define PQI_DEV_ERR 0x4080
1049 #define PQI_DEV_ERR_DETAILS 0x4088
1050 #define PQI_DEV_RESET 0x4090
1051 #define PQI_POWER_ACTION 0x4094
1052
1053 /* Busy wait micro seconds */
1054 #define OS_BUSYWAIT(x) DELAY(x)
1055 #define OS_SLEEP(timeout) \
1056 DELAY(timeout);
1057
1058 /* TMF request timeout is 600 Sec */
1059 #define OS_TMF_TIMEOUT_SEC (10 * 60)
1060
1061 #define LE_16(x) htole16(x)
1062 #define LE_32(x) htole32(x)
1063 #define LE_64(x) htole64(x)
1064 #define BE_16(x) htobe16(x)
1065 #define BE_32(x) htobe32(x)
1066 #define BE_64(x) htobe64(x)
1067
1068 #define PQI_HWIF_SRCV 0
1069 #define PQI_HWIF_UNKNOWN -1
1070
1071
1072 #define SMART_STATE_SUSPEND (1<<0)
1073 #define SMART_STATE_UNUSED0 (1<<1)
1074 #define SMART_STATE_INTERRUPTS_ON (1<<2)
1075 #define SMART_STATE_AIF_SLEEPER (1<<3)
1076 #define SMART_STATE_RESET (1<<4)
1077
1078 #define PQI_FLAG_BUSY (1<<0)
1079 #define PQI_MSI_ENABLED (1<<1)
1080 #define PQI_SIM_REGISTERED (1<<2)
1081 #define PQI_MTX_INIT (1<<3)
1082
1083
1084 #define PQI_CMD_MAPPED (1<<2)
1085
1086 /* Interrupt context to get oq_id */
1087 typedef struct pqi_intr_ctx {
1088 int oq_id;
1089 device_t pqi_dev;
1090 }pqi_intr_ctx_t;
1091
1092 typedef uint8_t os_dev_info_t;
1093
1094 typedef struct OS_SPECIFIC {
1095 device_t pqi_dev;
1096 struct resource *pqi_regs_res0; /* reg. if. window */
1097 int pqi_regs_rid0; /* resource ID */
1098 bus_dma_tag_t pqi_parent_dmat; /* parent DMA tag */
1099 bus_dma_tag_t pqi_buffer_dmat;
1100
1101 /* controller hardware interface */
1102 int pqi_hwif;
1103 struct resource *pqi_irq[PQI_MAX_MSIX]; /* interrupt */
1104 int pqi_irq_rid[PQI_MAX_MSIX];
1105 void *intrcookie[PQI_MAX_MSIX];
1106 bool intr_registered[PQI_MAX_MSIX];
1107 bool msi_enabled; /* MSI/MSI-X enabled */
1108 pqi_intr_ctx_t *msi_ctx;
1109 int oq_id;
1110 int pqi_state;
1111 uint32_t pqi_flags;
1112 struct mtx cam_lock;
1113 struct mtx map_lock;
1114 int mtx_init;
1115 int sim_registered;
1116 struct cam_devq *devq;
1117 struct cam_sim *sim;
1118 struct cam_path *path;
1119 struct task event_task;
1120 struct cdev *cdev;
1121 struct callout wellness_periodic; /* periodic event handling */
1122 struct callout heartbeat_timeout_id; /* heart beat event handling */
1123 } OS_SPECIFIC_T;
1124
1125
1126 typedef struct device_hints {
1127 uint8_t stream_status: 1;
1128 uint8_t sata_unique_wwn_status: 1;
1129 uint8_t aio_raid1_write_status: 1;
1130 uint8_t aio_raid5_write_status: 1;
1131 uint8_t aio_raid6_write_status: 1;
1132 uint32_t queue_depth;
1133 uint32_t sg_segments;
1134 uint32_t cpu_count;
1135 } device_hint;
1136
1137 typedef bus_addr_t dma_addr_t;
1138
1139
1140 /* Register access macros */
1141 #define PCI_MEM_GET32( _softs, _absaddr, _offset ) \
1142 bus_space_read_4(_softs->pci_mem_handle.pqi_btag, \
1143 _softs->pci_mem_handle.pqi_bhandle, _offset)
1144
1145
1146 #if defined(__i386__)
1147 #define PCI_MEM_GET64( _softs, _absaddr, _offset ) ({ \
1148 (uint64_t)bus_space_read_4(_softs->pci_mem_handle.pqi_btag, \
1149 _softs->pci_mem_handle.pqi_bhandle, _offset) + \
1150 ((uint64_t)bus_space_read_4(_softs->pci_mem_handle.pqi_btag, \
1151 _softs->pci_mem_handle.pqi_bhandle, _offset + 4) << 32); \
1152 })
1153 #else
1154 #define PCI_MEM_GET64(_softs, _absaddr, _offset ) \
1155 bus_space_read_8(_softs->pci_mem_handle.pqi_btag, \
1156 _softs->pci_mem_handle.pqi_bhandle, _offset)
1157 #endif
1158
1159 #define PCI_MEM_PUT32( _softs, _absaddr, _offset, _val ) \
1160 bus_space_write_4(_softs->pci_mem_handle.pqi_btag, \
1161 _softs->pci_mem_handle.pqi_bhandle, _offset, _val)
1162
1163 #if defined(__i386__)
1164 #define PCI_MEM_PUT64( _softs, _absaddr, _offset, _val ) \
1165 bus_space_write_4(_softs->pci_mem_handle.pqi_btag, \
1166 _softs->pci_mem_handle.pqi_bhandle, _offset, _val); \
1167 bus_space_write_4(_softs->pci_mem_handle.pqi_btag, \
1168 _softs->pci_mem_handle.pqi_bhandle, _offset + 4, _val >> 32);
1169 #else
1170 #define PCI_MEM_PUT64( _softs, _absaddr, _offset, _val ) \
1171 bus_space_write_8(_softs->pci_mem_handle.pqi_btag, \
1172 _softs->pci_mem_handle.pqi_bhandle, _offset, _val)
1173 #endif
1174
1175
1176 #define PCI_MEM_GET_BUF(_softs, _absaddr, _offset, buf, size) \
1177 bus_space_read_region_1(_softs->pci_mem_handle.pqi_btag,\
1178 _softs->pci_mem_handle.pqi_bhandle, _offset, buf, size)
1179
1180 /* Lock */
1181 typedef struct mtx OS_LOCK_T;
1182 typedef struct sema OS_SEMA_LOCK_T;
1183
1184 #define OS_PQILOCK_T OS_LOCK_T
1185
1186 #define OS_ACQUIRE_SPINLOCK(_lock) mtx_lock_spin(_lock)
1187 #define OS_RELEASE_SPINLOCK(_lock) mtx_unlock_spin(_lock)
1188
1189 #define OS_INIT_PQILOCK(_softs,_lock,_lockname) os_init_spinlock(_softs,_lock,_lockname)
1190 #define OS_UNINIT_PQILOCK(_lock) os_uninit_spinlock(_lock)
1191
1192 #define PQI_LOCK(_lock) OS_ACQUIRE_SPINLOCK(_lock)
1193 #define PQI_UNLOCK(_lock) OS_RELEASE_SPINLOCK(_lock)
1194
1195 #define OS_GET_CDBP(rcb) ((rcb->cm_ccb->ccb_h.flags & CAM_CDB_POINTER) ? rcb->cm_ccb->csio.cdb_io.cdb_ptr : rcb->cm_ccb->csio.cdb_io.cdb_bytes)
1196 #define GET_SCSI_BUFFLEN(rcb) (rcb->cm_ccb->csio.dxfer_len)
1197 #define IS_OS_SCSICMD(rcb) (rcb && !rcb->tm_req && rcb->cm_ccb)
1198
1199 #define OS_GET_IO_QINDEX(softs,rcb) curcpu % softs->num_op_obq
1200 #define OS_GET_IO_RESP_QID(softs,rcb) (softs->op_ob_q[(OS_GET_IO_QINDEX(softs,rcb))].q_id)
1201 #define OS_GET_IO_REQ_QINDEX(softs,rcb) OS_GET_IO_QINDEX(softs,rcb)
1202 #define OS_GET_TMF_RESP_QID OS_GET_IO_RESP_QID
1203 #define OS_GET_TMF_REQ_QINDEX OS_GET_IO_REQ_QINDEX
1204
1205 /* check request type */
1206 #define is_internal_req(rcb) (!(rcb->cm_ccb))
1207
1208 #define os_io_memcpy(dest, src, len) memcpy(dest, src, len)
1209
1210 /* sg elements addr, len, flags */
1211 #define OS_GET_IO_SG_COUNT(rcb) rcb->nseg
1212 #define OS_GET_IO_SG_ADDR(rcb,i) rcb->sgt[i].addr
1213 #define OS_GET_IO_SG_LEN(rcb,i) rcb->sgt[i].len
1214
1215 /* scsi commands used in pqilib for RAID bypass*/
1216 #define SCMD_READ_6 READ_6
1217 #define SCMD_WRITE_6 WRITE_6
1218 #define SCMD_READ_10 READ_10
1219 #define SCMD_WRITE_10 WRITE_10
1220 #define SCMD_READ_12 READ_12
1221 #define SCMD_WRITE_12 WRITE_12
1222 #define SCMD_READ_16 READ_16
1223 #define SCMD_WRITE_16 WRITE_16
1224
1225 /* FreeBSD status macros */
1226 #define BSD_SUCCESS 0
1227 #define DEVICE_HINT_SUCCESS 0
1228
1229 /* Min outstanding commands that driver can register with CAM layer.*/
1230 #define OS_MIN_OUTSTANDING_REQ 6
1231 #define BSD_MIN_SG_SEGMENTS 16
1232
1233 #define DISABLE_ERR_RESP_VERBOSE 1
1234
1235 /* Debug facility */
1236
1237 #define PQISRC_FLAGS_MASK 0x0000ffff
1238 #define PQISRC_FLAGS_INIT 0x00000001
1239 #define PQISRC_FLAGS_INFO 0x00000002
1240 #define PQISRC_FLAGS_FUNC 0x00000004
1241 #define PQISRC_FLAGS_TRACEIO 0x00000008
1242 #define PQISRC_FLAGS_DISC 0x00000010
1243 #define PQISRC_FLAGS_WARN 0x00000020
1244 #define PQISRC_FLAGS_ERROR 0x00000040
1245 #define PQISRC_FLAGS_NOTE 0x00000080
1246
1247 #define PQISRC_LOG_LEVEL (PQISRC_FLAGS_WARN | PQISRC_FLAGS_ERROR | PQISRC_FLAGS_NOTE)
1248
1249 static int logging_level = PQISRC_LOG_LEVEL;
1250
1251 #define DBG_INIT(fmt,args...) \
1252 do { \
1253 if (logging_level & PQISRC_FLAGS_INIT) { \
1254 printf("[INIT]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \
1255 } \
1256 }while(0);
1257
1258 #define DBG_INFO(fmt,args...) \
1259 do { \
1260 if (logging_level & PQISRC_FLAGS_INFO) { \
1261 printf("[INFO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \
1262 } \
1263 }while(0);
1264
1265 #define DBG_FUNC(fmt,args...) \
1266 do { \
1267 if (logging_level & PQISRC_FLAGS_FUNC) { \
1268 printf("[FUNC]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \
1269 } \
1270 }while(0);
1271
1272 #define DBG_DISC(fmt,args...) \
1273 do { \
1274 if (logging_level & PQISRC_FLAGS_DISC) { \
1275 printf("[DISC]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \
1276 } \
1277 }while(0);
1278
1279 #define DBG_TRACEIO(fmt,args...) \
1280 do { \
1281 if (logging_level & PQISRC_FLAGS_TRACEIO) { \
1282 printf("[TRACEIO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \
1283 } \
1284 }while(0);
1285
1286 #define DBG_WARN(fmt,args...) \
1287 do { \
1288 if (logging_level & PQISRC_FLAGS_WARN) { \
1289 printf("[WARN]:[%u:%u.%u][CPU %d][%s][%d]:"fmt,softs->bus_id,softs->device_id,softs->func_id,curcpu,__func__,__LINE__,##args);\
1290 } \
1291 }while(0);
1292
1293 #define DBG_ERR(fmt,args...) \
1294 do { \
1295 if (logging_level & PQISRC_FLAGS_ERROR) { \
1296 printf("[ERROR]::[%u:%u.%u][CPU %d][%s][%d]:"fmt,softs->bus_id,softs->device_id,softs->func_id,curcpu,__func__,__LINE__,##args); \
1297 } \
1298 }while(0);
1299 #define DBG_ERR_NO_SOFTS(fmt,args...) \
1300 do { \
1301 if (logging_level & PQISRC_FLAGS_ERROR) { \
1302 printf("[ERROR]::[CPU %d][%s][%d]:"fmt,curcpu,__func__,__LINE__,##args); \
1303 } \
1304 }while(0);
1305 #define DBG_IO(fmt,args...) \
1306 do { \
1307 if (logging_level & PQISRC_FLAGS_TRACEIO) { \
1308 printf("[IO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \
1309 } \
1310 }while(0);
1311
1312 #define DBG_ERR_BTL(device,fmt,args...) \
1313 do { \
1314 if (logging_level & PQISRC_FLAGS_ERROR) { \
1315 printf("[ERROR]::[%u:%u.%u][%d,%d,%d][CPU %d][%s][%d]:"fmt, softs->bus_id, softs->device_id, softs->func_id, device->bus, device->target, device->lun,curcpu,__func__,__LINE__,##args); \
1316 } \
1317 }while(0);
1318
1319 #define DBG_WARN_BTL(device,fmt,args...) \
1320 do { \
1321 if (logging_level & PQISRC_FLAGS_WARN) { \
1322 printf("[WARN]:[%u:%u.%u][%d,%d,%d][CPU %d][%s][%d]:"fmt, softs->bus_id, softs->device_id, softs->func_id, device->bus, device->target, device->lun,curcpu,__func__,__LINE__,##args);\
1323 } \
1324 }while(0);
1325
1326 #define DBG_NOTE(fmt,args...) \
1327 do { \
1328 if (logging_level & PQISRC_FLAGS_NOTE) { \
1329 printf("[NOTE]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \
1330 } \
1331 }while(0);
1332
1333 #endif /* _PQI_DEFINES_H */
1334