1 //===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides PowerPC specific target descriptions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H 14 #define LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H 15 16 // GCC #defines PPC on Linux but we use it as our namespace name 17 #undef PPC 18 19 #include "llvm/MC/MCRegisterInfo.h" 20 #include "llvm/Support/MathExtras.h" 21 #include <cstdint> 22 #include <memory> 23 24 namespace llvm { 25 26 class MCAsmBackend; 27 class MCCodeEmitter; 28 class MCContext; 29 class MCInstrDesc; 30 class MCInstrInfo; 31 class MCObjectTargetWriter; 32 class MCRegisterInfo; 33 class MCSubtargetInfo; 34 class MCTargetOptions; 35 class Target; 36 37 namespace PPC { 38 /// stripRegisterPrefix - This method strips the character prefix from a 39 /// register name so that only the number is left. Used by for linux asm. 40 const char *stripRegisterPrefix(const char *RegName); 41 42 /// getRegNumForOperand - some operands use different numbering schemes 43 /// for the same registers. For example, a VSX instruction may have any of 44 /// vs0-vs63 allocated whereas an Altivec instruction could only have 45 /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual 46 /// register number needed for the opcode/operand number combination. 47 /// The operand number argument will be useful when we need to extend this 48 /// to instructions that use both Altivec and VSX numbering (for different 49 /// operands). 50 unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, 51 unsigned OpNo); 52 53 } // namespace PPC 54 55 MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII, 56 MCContext &Ctx); 57 58 MCAsmBackend *createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI, 59 const MCRegisterInfo &MRI, 60 const MCTargetOptions &Options); 61 62 /// Construct an PPC ELF object writer. 63 std::unique_ptr<MCObjectTargetWriter> createPPCELFObjectWriter(bool Is64Bit, 64 uint8_t OSABI); 65 /// Construct a PPC Mach-O object writer. 66 std::unique_ptr<MCObjectTargetWriter> 67 createPPCMachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype); 68 69 /// Construct a PPC XCOFF object writer. 70 std::unique_ptr<MCObjectTargetWriter> createPPCXCOFFObjectWriter(bool Is64Bit); 71 72 /// Returns true iff Val consists of one contiguous run of 1s with any number of 73 /// 0s on either side. The 1s are allowed to wrap from LSB to MSB, so 74 /// 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is not, 75 /// since all 1s are not contiguous. 76 static inline bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) { 77 if (!Val) 78 return false; 79 80 if (isShiftedMask_32(Val)) { 81 // look for the first non-zero bit 82 MB = llvm::countl_zero(Val); 83 // look for the first zero bit after the run of ones 84 ME = llvm::countl_zero((Val - 1) ^ Val); 85 return true; 86 } else { 87 Val = ~Val; // invert mask 88 if (isShiftedMask_32(Val)) { 89 // effectively look for the first zero bit 90 ME = llvm::countl_zero(Val) - 1; 91 // effectively look for the first one bit after the run of zeros 92 MB = llvm::countl_zero((Val - 1) ^ Val) + 1; 93 return true; 94 } 95 } 96 // no run present 97 return false; 98 } 99 100 static inline bool isRunOfOnes64(uint64_t Val, unsigned &MB, unsigned &ME) { 101 if (!Val) 102 return false; 103 104 if (isShiftedMask_64(Val)) { 105 // look for the first non-zero bit 106 MB = llvm::countl_zero(Val); 107 // look for the first zero bit after the run of ones 108 ME = llvm::countl_zero((Val - 1) ^ Val); 109 return true; 110 } else { 111 Val = ~Val; // invert mask 112 if (isShiftedMask_64(Val)) { 113 // effectively look for the first zero bit 114 ME = llvm::countl_zero(Val) - 1; 115 // effectively look for the first one bit after the run of zeros 116 MB = llvm::countl_zero((Val - 1) ^ Val) + 1; 117 return true; 118 } 119 } 120 // no run present 121 return false; 122 } 123 124 /// PPCII - This namespace holds all of the PowerPC target-specific 125 /// per-instruction flags. These must match the corresponding definitions in 126 /// PPC.td and PPCInstrFormats.td. 127 namespace PPCII { 128 enum { 129 // PPC970 Instruction Flags. These flags describe the characteristics of the 130 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 131 // raw machine instructions. 132 133 /// PPC970_First - This instruction starts a new dispatch group, so it will 134 /// always be the first one in the group. 135 PPC970_First = 0x1, 136 137 /// PPC970_Single - This instruction starts a new dispatch group and 138 /// terminates it, so it will be the sole instruction in the group. 139 PPC970_Single = 0x2, 140 141 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 142 /// two dispatch pipes to be available to issue. 143 PPC970_Cracked = 0x4, 144 145 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 146 /// an instruction is issued to. 147 PPC970_Shift = 3, 148 PPC970_Mask = 0x07 << PPC970_Shift 149 }; 150 enum PPC970_Unit { 151 /// These are the various PPC970 execution unit pipelines. Each instruction 152 /// is one of these. 153 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 154 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 155 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 156 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 157 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 158 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 159 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 160 PPC970_BRU = 7 << PPC970_Shift // Branch Unit 161 }; 162 163 enum { 164 /// Shift count to bypass PPC970 flags 165 NewDef_Shift = 6, 166 167 /// This instruction is an X-Form memory operation. 168 XFormMemOp = 0x1 << NewDef_Shift, 169 /// This instruction is prefixed. 170 Prefixed = 0x1 << (NewDef_Shift + 1), 171 /// This instruction produced a sign extended result. 172 SExt32To64 = 0x1 << (NewDef_Shift + 2), 173 /// This instruction produced a zero extended result. 174 ZExt32To64 = 0x1 << (NewDef_Shift + 3) 175 }; 176 } // end namespace PPCII 177 178 } // end namespace llvm 179 180 // Defines symbolic names for PowerPC registers. This defines a mapping from 181 // register name to register number. 182 // 183 #define GET_REGINFO_ENUM 184 #include "PPCGenRegisterInfo.inc" 185 186 // Defines symbolic names for the PowerPC instructions. 187 // 188 #define GET_INSTRINFO_ENUM 189 #define GET_INSTRINFO_SCHED_ENUM 190 #define GET_INSTRINFO_MC_HELPER_DECLS 191 #include "PPCGenInstrInfo.inc" 192 193 #define GET_SUBTARGETINFO_ENUM 194 #include "PPCGenSubtargetInfo.inc" 195 196 #define PPC_REGS0_7(X) \ 197 { \ 198 X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \ 199 } 200 201 #define PPC_REGS0_31(X) \ 202 { \ 203 X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \ 204 X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \ 205 X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \ 206 } 207 208 #define PPC_REGS_EVEN0_30(X) \ 209 { \ 210 X##0, X##2, X##4, X##6, X##8, X##10, X##12, X##14, X##16, X##18, X##20, \ 211 X##22, X##24, X##26, X##28, X##30 \ 212 } 213 214 #define PPC_REGS0_63(X) \ 215 { \ 216 X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \ 217 X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \ 218 X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31, \ 219 X##32, X##33, X##34, X##35, X##36, X##37, X##38, X##39, X##40, X##41, \ 220 X##42, X##43, X##44, X##45, X##46, X##47, X##48, X##49, X##50, X##51, \ 221 X##52, X##53, X##54, X##55, X##56, X##57, X##58, X##59, X##60, X##61, \ 222 X##62, X##63 \ 223 } 224 225 #define PPC_REGS_NO0_31(Z, X) \ 226 { \ 227 Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \ 228 X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \ 229 X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \ 230 } 231 232 #define PPC_REGS_LO_HI(LO, HI) \ 233 { \ 234 LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, LO##8, LO##9, \ 235 LO##10, LO##11, LO##12, LO##13, LO##14, LO##15, LO##16, LO##17, \ 236 LO##18, LO##19, LO##20, LO##21, LO##22, LO##23, LO##24, LO##25, \ 237 LO##26, LO##27, LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, HI##2, \ 238 HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, HI##10, HI##11, \ 239 HI##12, HI##13, HI##14, HI##15, HI##16, HI##17, HI##18, HI##19, \ 240 HI##20, HI##21, HI##22, HI##23, HI##24, HI##25, HI##26, HI##27, \ 241 HI##28, HI##29, HI##30, HI##31 \ 242 } 243 244 #define PPC_REGS0_7(X) \ 245 { \ 246 X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \ 247 } 248 249 #define PPC_REGS0_3(X) \ 250 { \ 251 X##0, X##1, X##2, X##3 \ 252 } 253 254 using llvm::MCPhysReg; 255 256 #define DEFINE_PPC_REGCLASSES \ 257 static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \ 258 static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \ 259 static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \ 260 static const MCPhysReg FpRegs[16] = PPC_REGS_EVEN0_30(PPC::Fpair); \ 261 static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC::VSRp); \ 262 static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \ 263 static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF); \ 264 static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \ 265 static const MCPhysReg RRegsNoR0[32] = PPC_REGS_NO0_31(PPC::ZERO, PPC::R); \ 266 static const MCPhysReg XRegsNoX0[32] = PPC_REGS_NO0_31(PPC::ZERO8, PPC::X); \ 267 static const MCPhysReg VSRegs[64] = PPC_REGS_LO_HI(PPC::VSL, PPC::V); \ 268 static const MCPhysReg VSFRegs[64] = PPC_REGS_LO_HI(PPC::F, PPC::VF); \ 269 static const MCPhysReg VSSRegs[64] = PPC_REGS_LO_HI(PPC::F, PPC::VF); \ 270 static const MCPhysReg CRBITRegs[32] = { \ 271 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, PPC::CR1LT, PPC::CR1GT, \ 272 PPC::CR1EQ, PPC::CR1UN, PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, \ 273 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, PPC::CR4LT, PPC::CR4GT, \ 274 PPC::CR4EQ, PPC::CR4UN, PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, \ 275 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, \ 276 PPC::CR7EQ, PPC::CR7UN}; \ 277 static const MCPhysReg CRRegs[8] = PPC_REGS0_7(PPC::CR); \ 278 static const MCPhysReg ACCRegs[8] = PPC_REGS0_7(PPC::ACC); \ 279 static const MCPhysReg WACCRegs[8] = PPC_REGS0_7(PPC::WACC); \ 280 static const MCPhysReg WACC_HIRegs[8] = PPC_REGS0_7(PPC::WACC_HI); \ 281 static const MCPhysReg DMRROWpRegs[32] = PPC_REGS0_31(PPC::DMRROWp); \ 282 static const MCPhysReg DMRROWRegs[64] = PPC_REGS0_63(PPC::DMRROW); \ 283 static const MCPhysReg DMRRegs[8] = PPC_REGS0_7(PPC::DMR); \ 284 static const MCPhysReg DMRpRegs[4] = PPC_REGS0_3(PPC::DMRp); 285 286 namespace llvm { 287 namespace PPC { 288 static inline bool isVFRegister(unsigned Reg) { 289 return Reg >= PPC::VF0 && Reg <= PPC::VF31; 290 } 291 292 static inline bool isVRRegister(unsigned Reg) { 293 return Reg >= PPC::V0 && Reg <= PPC::V31; 294 } 295 } // namespace PPC 296 } // namespace llvm 297 298 #endif // LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H 299