1 #ifndef __devinfo_h__ 2 #define __devinfo_h__ 3 4 #include "mac_drv_info.h" 5 6 /**************************************************************************** 7 * Shared HW configuration * 8 ****************************************************************************/ 9 #define PIN_CFG_NA 0x00000000 10 #define PIN_CFG_GPIO0_P0 0x00000001 11 #define PIN_CFG_GPIO1_P0 0x00000002 12 #define PIN_CFG_GPIO2_P0 0x00000003 13 #define PIN_CFG_GPIO3_P0 0x00000004 14 #define PIN_CFG_GPIO0_P1 0x00000005 15 #define PIN_CFG_GPIO1_P1 0x00000006 16 #define PIN_CFG_GPIO2_P1 0x00000007 17 #define PIN_CFG_GPIO3_P1 0x00000008 18 #define PIN_CFG_EPIO0 0x00000009 19 #define PIN_CFG_EPIO1 0x0000000a 20 #define PIN_CFG_EPIO2 0x0000000b 21 #define PIN_CFG_EPIO3 0x0000000c 22 #define PIN_CFG_EPIO4 0x0000000d 23 #define PIN_CFG_EPIO5 0x0000000e 24 #define PIN_CFG_EPIO6 0x0000000f 25 #define PIN_CFG_EPIO7 0x00000010 26 #define PIN_CFG_EPIO8 0x00000011 27 #define PIN_CFG_EPIO9 0x00000012 28 #define PIN_CFG_EPIO10 0x00000013 29 #define PIN_CFG_EPIO11 0x00000014 30 #define PIN_CFG_EPIO12 0x00000015 31 #define PIN_CFG_EPIO13 0x00000016 32 #define PIN_CFG_EPIO14 0x00000017 33 #define PIN_CFG_EPIO15 0x00000018 34 #define PIN_CFG_EPIO16 0x00000019 35 #define PIN_CFG_EPIO17 0x0000001a 36 #define PIN_CFG_EPIO18 0x0000001b 37 #define PIN_CFG_EPIO19 0x0000001c 38 #define PIN_CFG_EPIO20 0x0000001d 39 #define PIN_CFG_EPIO21 0x0000001e 40 #define PIN_CFG_EPIO22 0x0000001f 41 #define PIN_CFG_EPIO23 0x00000020 42 #define PIN_CFG_EPIO24 0x00000021 43 #define PIN_CFG_EPIO25 0x00000022 44 #define PIN_CFG_EPIO26 0x00000023 45 #define PIN_CFG_EPIO27 0x00000024 46 #define PIN_CFG_EPIO28 0x00000025 47 #define PIN_CFG_EPIO29 0x00000026 48 #define PIN_CFG_EPIO30 0x00000027 49 #define PIN_CFG_EPIO31 0x00000028 50 51 /* EPIO definition */ 52 #define EPIO_CFG_NA 0x00000000 53 #define EPIO_CFG_EPIO0 0x00000001 54 #define EPIO_CFG_EPIO1 0x00000002 55 #define EPIO_CFG_EPIO2 0x00000003 56 #define EPIO_CFG_EPIO3 0x00000004 57 #define EPIO_CFG_EPIO4 0x00000005 58 #define EPIO_CFG_EPIO5 0x00000006 59 #define EPIO_CFG_EPIO6 0x00000007 60 #define EPIO_CFG_EPIO7 0x00000008 61 #define EPIO_CFG_EPIO8 0x00000009 62 #define EPIO_CFG_EPIO9 0x0000000a 63 #define EPIO_CFG_EPIO10 0x0000000b 64 #define EPIO_CFG_EPIO11 0x0000000c 65 #define EPIO_CFG_EPIO12 0x0000000d 66 #define EPIO_CFG_EPIO13 0x0000000e 67 #define EPIO_CFG_EPIO14 0x0000000f 68 #define EPIO_CFG_EPIO15 0x00000010 69 #define EPIO_CFG_EPIO16 0x00000011 70 #define EPIO_CFG_EPIO17 0x00000012 71 #define EPIO_CFG_EPIO18 0x00000013 72 #define EPIO_CFG_EPIO19 0x00000014 73 #define EPIO_CFG_EPIO20 0x00000015 74 #define EPIO_CFG_EPIO21 0x00000016 75 #define EPIO_CFG_EPIO22 0x00000017 76 #define EPIO_CFG_EPIO23 0x00000018 77 #define EPIO_CFG_EPIO24 0x00000019 78 #define EPIO_CFG_EPIO25 0x0000001a 79 #define EPIO_CFG_EPIO26 0x0000001b 80 #define EPIO_CFG_EPIO27 0x0000001c 81 #define EPIO_CFG_EPIO28 0x0000001d 82 #define EPIO_CFG_EPIO29 0x0000001e 83 #define EPIO_CFG_EPIO30 0x0000001f 84 #define EPIO_CFG_EPIO31 0x00000020 85 86 struct mac_addr { 87 u32 upper; 88 u32 lower; 89 }; 90 91 92 93 struct shared_hw_cfg { /* NVRAM Offset */ 94 /* Up to 16 bytes of NULL-terminated string */ 95 u8 part_num[16]; /* 0x104 */ 96 97 u32 config; /* 0x114 */ 98 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 99 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 100 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 101 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 102 103 #define SHARED_HW_CFG_PORT_SWAP 0x00000004 104 105 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 106 107 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 108 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 109 110 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 111 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 112 /* Whatever MFW found in NVM 113 (if multiple found, priority order is: NC-SI, UMP, IPMI) */ 114 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 115 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 116 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 117 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 118 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI 119 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 120 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 121 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI 122 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 123 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 124 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP 125 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 126 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 127 128 /* Adjust the PCIe G2 Tx amplitude driver for all Tx lanes. For 129 backwards compatibility, value of 0 is disabling this feature. 130 That means that though 0 is a valid value, it cannot be 131 configured. */ 132 #define SHARED_HW_CFG_G2_TX_DRIVE_MASK 0x0000F000 133 #define SHARED_HW_CFG_G2_TX_DRIVE_SHIFT 12 134 135 #define SHARED_HW_CFG_LED_MODE_MASK 0x000F0000 136 #define SHARED_HW_CFG_LED_MODE_SHIFT 16 137 #define SHARED_HW_CFG_LED_MAC1 0x00000000 138 #define SHARED_HW_CFG_LED_PHY1 0x00010000 139 #define SHARED_HW_CFG_LED_PHY2 0x00020000 140 #define SHARED_HW_CFG_LED_PHY3 0x00030000 141 #define SHARED_HW_CFG_LED_MAC2 0x00040000 142 #define SHARED_HW_CFG_LED_PHY4 0x00050000 143 #define SHARED_HW_CFG_LED_PHY5 0x00060000 144 #define SHARED_HW_CFG_LED_PHY6 0x00070000 145 #define SHARED_HW_CFG_LED_MAC3 0x00080000 146 #define SHARED_HW_CFG_LED_PHY7 0x00090000 147 #define SHARED_HW_CFG_LED_PHY9 0x000a0000 148 #define SHARED_HW_CFG_LED_PHY11 0x000b0000 149 #define SHARED_HW_CFG_LED_MAC4 0x000c0000 150 #define SHARED_HW_CFG_LED_PHY8 0x000d0000 151 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 152 #define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000 153 154 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 155 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 156 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 157 158 #define SHARED_HW_CFG_ATC_MASK 0x80000000 159 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 160 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 161 162 u32 config2; /* 0x118 */ 163 164 #define SHARED_HW_CFG_PCIE_GEN2_MASK 0x00000100 165 #define SHARED_HW_CFG_PCIE_GEN2_SHIFT 8 166 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 167 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 168 169 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 170 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 171 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 172 173 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 174 175 176 177 /* Output low when PERST is asserted */ 178 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 179 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 180 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 181 182 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 183 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 184 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 185 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 186 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 187 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 188 189 /* The fan failure mechanism is usually related to the PHY type 190 since the power consumption of the board is determined by the PHY. 191 Currently, fan is required for most designs with SFX7101, BCM8727 192 and BCM8481. If a fan is not required for a board which uses one 193 of those PHYs, this field should be set to "Disabled". If a fan is 194 required for a different PHY type, this option should be set to 195 "Enabled". The fan failure indication is expected on SPIO5 */ 196 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 197 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 198 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 199 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 200 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 201 202 /* ASPM Power Management support */ 203 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 204 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 205 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 206 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 207 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 208 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 209 210 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register 211 tl_control_0 (register 0x2800) */ 212 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 213 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 214 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 215 216 217 /* Set the MDC/MDIO access for the first external phy */ 218 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 219 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 220 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 221 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 222 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 223 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 224 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 225 226 /* Set the MDC/MDIO access for the second external phy */ 227 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 228 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 229 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 230 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 231 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 232 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 233 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 234 235 /* Max number of PF MSIX vectors */ 236 u32 config_3; /* 0x11C */ 237 #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK 0x0000007F 238 #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT 0 239 240 /* This field extends the mf mode chosen in nvm cfg #73 (as we ran 241 out of bits) */ 242 #define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK 0x00000F00 243 #define SHARED_HW_CFG_EXTENDED_MF_MODE_SHIFT 8 244 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5 0x00000000 245 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0 0x00000100 246 247 u32 ump_nc_si_config; /* 0x120 */ 248 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 249 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 250 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 251 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 252 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 253 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 254 255 /* Reserved bits: 226-230 */ 256 257 /* The output pin template BSC_SEL which selects the I2C for this 258 port in the I2C Mux */ 259 u32 board; /* 0x124 */ 260 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F 261 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 262 263 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 264 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 265 /* Use the PIN_CFG_XXX defines on top */ 266 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000 267 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 268 269 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000 270 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 271 272 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000 273 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 274 275 u32 wc_lane_config; /* 0x128 */ 276 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 277 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 278 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b 279 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 280 #define SHARED_HW_CFG_LANE_SWAP_CFG_31200213 0x000027d8 281 #define SHARED_HW_CFG_LANE_SWAP_CFG_02133120 0x0000d827 282 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b 283 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 284 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 285 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 286 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 287 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 288 289 /* TX lane Polarity swap */ 290 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 291 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 292 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 293 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 294 /* TX lane Polarity swap */ 295 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 296 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 297 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 298 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 299 300 /* Selects the port layout of the board */ 301 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 302 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 303 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 304 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 305 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 306 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 307 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 308 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 309 }; 310 311 312 /**************************************************************************** 313 * Port HW configuration * 314 ****************************************************************************/ 315 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ 316 317 u32 pci_id; 318 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000FFFF 319 #define PORT_HW_CFG_PCI_DEVICE_ID_SHIFT 0 320 321 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xFFFF0000 322 #define PORT_HW_CFG_PCI_VENDOR_ID_SHIFT 16 323 324 u32 pci_sub_id; 325 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000FFFF 326 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_SHIFT 0 327 328 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xFFFF0000 329 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_SHIFT 16 330 331 u32 power_dissipated; 332 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000FF 333 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 334 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000FF00 335 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 336 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00FF0000 337 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 338 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xFF000000 339 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 340 341 u32 power_consumed; 342 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000FF 343 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 344 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000FF00 345 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 346 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00FF0000 347 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 348 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xFF000000 349 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 350 351 u32 mac_upper; 352 u32 mac_lower; /* 0x140 */ 353 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000FFFF 354 #define PORT_HW_CFG_UPPERMAC_SHIFT 0 355 356 357 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */ 358 u32 iscsi_mac_lower; 359 360 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */ 361 u32 rdma_mac_lower; 362 363 u32 serdes_config; 364 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF 365 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 366 367 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000 368 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 369 370 371 /* Default values: 2P-64, 4P-32 */ 372 u32 reserved; 373 374 u32 vf_config; /* 0x15C */ 375 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 376 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 377 378 u32 mf_pci_id; /* 0x160 */ 379 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF 380 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 381 382 /* Controls the TX laser of the SFP+ module */ 383 u32 sfp_ctrl; /* 0x164 */ 384 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF 385 #define PORT_HW_CFG_TX_LASER_SHIFT 0 386 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 387 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 388 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 389 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 390 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 391 392 /* Controls the fault module LED of the SFP+ */ 393 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 394 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 395 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 396 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 397 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 398 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 399 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 400 401 /* The output pin TX_DIS that controls the TX laser of the SFP+ 402 module. Use the PIN_CFG_XXX defines on top */ 403 u32 e3_sfp_ctrl; /* 0x168 */ 404 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF 405 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 406 407 /* The output pin for SFPP_TYPE which turns on the Fault module LED */ 408 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 409 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 410 411 /* The input pin MOD_ABS that indicates whether SFP+ module is 412 present or not. Use the PIN_CFG_XXX defines on top */ 413 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 414 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 415 416 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ 417 module. Use the PIN_CFG_XXX defines on top */ 418 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 419 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 420 421 /* 422 * The input pin which signals module transmit fault. Use the 423 * PIN_CFG_XXX defines on top 424 */ 425 u32 e3_cmn_pin_cfg; /* 0x16C */ 426 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF 427 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 428 429 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on 430 top */ 431 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 432 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 433 434 /* 435 * The output pin which powers down the PHY. Use the PIN_CFG_XXX 436 * defines on top 437 */ 438 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 439 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 440 441 /* The output pin values BSC_SEL which selects the I2C for this port 442 in the I2C Mux */ 443 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 444 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 445 446 447 /* 448 * The input pin I_FAULT which indicate over-current has occurred. 449 * Use the PIN_CFG_XXX defines on top 450 */ 451 u32 e3_cmn_pin_cfg1; /* 0x170 */ 452 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF 453 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 454 455 /* pause on host ring */ 456 u32 generic_features; /* 0x174 */ 457 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001 458 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0 459 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000 460 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001 461 462 /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2 463 * LOM recommended and tested value is 0xBEB2. Using a different 464 * value means using a value not tested by BRCM 465 */ 466 u32 sfi_tap_values; /* 0x178 */ 467 #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF 468 #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0 469 470 /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested 471 * value is 0x2. LOM recommended and tested value is 0x2. Using a 472 * different value means using a value not tested by BRCM 473 */ 474 #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000 475 #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16 476 477 u32 reserved0[5]; /* 0x17c */ 478 479 u32 aeu_int_mask; /* 0x190 */ 480 481 u32 media_type; /* 0x194 */ 482 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF 483 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 484 485 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 486 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 487 488 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 489 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 490 491 /* 4 times 16 bits for all 4 lanes. In case external PHY is present 492 (not direct mode), those values will not take effect on the 4 XGXS 493 lanes. For some external PHYs (such as 8706 and 8726) the values 494 will be used to configure the external PHY in those cases, not 495 all 4 values are needed. */ 496 u16 xgxs_config_rx[4]; /* 0x198 */ 497 u16 xgxs_config_tx[4]; /* 0x1A0 */ 498 499 500 /* For storing FCOE mac on shared memory */ 501 u32 fcoe_fip_mac_upper; 502 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff 503 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 504 u32 fcoe_fip_mac_lower; 505 506 u32 fcoe_wwn_port_name_upper; 507 u32 fcoe_wwn_port_name_lower; 508 509 u32 fcoe_wwn_node_name_upper; 510 u32 fcoe_wwn_node_name_lower; 511 512 /* wwpn for npiv enabled */ 513 u32 wwpn_for_npiv_config; /* 0x1C0 */ 514 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_MASK 0x00000001 515 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_SHIFT 0 516 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_DISABLED 0x00000000 517 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_ENABLED 0x00000001 518 519 /* wwpn for npiv valid addresses */ 520 u32 wwpn_for_npiv_valid_addresses; /* 0x1C4 */ 521 #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_MASK 0x0000FFFF 522 #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_SHIFT 0 523 524 struct mac_addr wwpn_for_niv_macs[16]; 525 526 /* Reserved bits: 2272-2336 For storing FCOE mac on shared memory */ 527 u32 Reserved1[14]; 528 529 u32 pf_allocation; /* 0x280 */ 530 /* number of vfs per PF, if 0 - sriov disabled */ 531 #define PORT_HW_CFG_NUMBER_OF_VFS_MASK 0x000000FF 532 #define PORT_HW_CFG_NUMBER_OF_VFS_SHIFT 0 533 534 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default), 535 84833 only */ 536 u32 xgbt_phy_cfg; /* 0x284 */ 537 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF 538 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 539 540 u32 default_cfg; /* 0x288 */ 541 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 542 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 543 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 544 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 545 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 546 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 547 548 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C 549 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 550 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 551 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 552 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 553 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c 554 555 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 556 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 557 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 558 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 559 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 560 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 561 562 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 563 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 564 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 565 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 566 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 567 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 568 569 /* When KR link is required to be set to force which is not 570 KR-compliant, this parameter determine what is the trigger for it. 571 When GPIO is selected, low input will force the speed. Currently 572 default speed is 1G. In the future, it may be widen to select the 573 forced speed in with another parameter. Note when force-1G is 574 enabled, it override option 56: Link Speed option. */ 575 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 576 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 577 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 578 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 579 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 580 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 581 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 582 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 583 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 584 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 585 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 586 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 587 /* Enable to determine with which GPIO to reset the external phy */ 588 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 589 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 590 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 591 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 592 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 593 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 594 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 595 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 596 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 597 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 598 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 599 600 /* Enable BAM on KR */ 601 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 602 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 603 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 604 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 605 606 /* Enable Common Mode Sense */ 607 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 608 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 609 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 610 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 611 612 /* Determine the Serdes electrical interface */ 613 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 614 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 615 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 616 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 617 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 618 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 619 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 620 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 621 622 /* SFP+ main TAP and post TAP volumes */ 623 #define PORT_HW_CFG_TAP_LEVELS_MASK 0x70000000 624 #define PORT_HW_CFG_TAP_LEVELS_SHIFT 28 625 #define PORT_HW_CFG_TAP_LEVELS_POST_15_MAIN_43 0x00000000 626 #define PORT_HW_CFG_TAP_LEVELS_POST_14_MAIN_44 0x10000000 627 #define PORT_HW_CFG_TAP_LEVELS_POST_13_MAIN_45 0x20000000 628 #define PORT_HW_CFG_TAP_LEVELS_POST_12_MAIN_46 0x30000000 629 #define PORT_HW_CFG_TAP_LEVELS_POST_11_MAIN_47 0x40000000 630 #define PORT_HW_CFG_TAP_LEVELS_POST_10_MAIN_48 0x50000000 631 632 u32 speed_capability_mask2; /* 0x28C */ 633 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF 634 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 635 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 636 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF 0x00000002 637 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004 638 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 639 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 640 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G 0x00000020 641 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 642 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 643 644 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 645 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 646 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 647 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_HALF 0x00020000 648 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_HALF 0x00040000 649 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 650 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 651 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_5G 0x00200000 652 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 653 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 654 655 656 /* In the case where two media types (e.g. copper and fiber) are 657 present and electrically active at the same time, PHY Selection 658 will determine which of the two PHYs will be designated as the 659 Active PHY and used for a connection to the network. */ 660 u32 multi_phy_config; /* 0x290 */ 661 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 662 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 663 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 664 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 665 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 666 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 667 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 668 669 /* When enabled, all second phy nvram parameters will be swapped 670 with the first phy parameters */ 671 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 672 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 673 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 674 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 675 676 677 /* Address of the second external phy */ 678 u32 external_phy_config2; /* 0x294 */ 679 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF 680 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 681 682 /* The second XGXS external PHY type */ 683 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 684 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 685 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 686 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 687 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 688 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 689 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 690 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 691 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 692 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 693 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 694 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 695 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 696 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 697 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 698 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 699 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00 700 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 701 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000 702 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100 703 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 704 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 705 706 707 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as 708 8706, 8726 and 8727) not all 4 values are needed. */ 709 u16 xgxs_config2_rx[4]; /* 0x296 */ 710 u16 xgxs_config2_tx[4]; /* 0x2A0 */ 711 712 u32 lane_config; 713 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 714 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 715 /* AN and forced */ 716 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b 717 /* forced only */ 718 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 719 /* forced only */ 720 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 721 /* forced only */ 722 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 723 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 724 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 725 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 726 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 727 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000C000 728 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 729 730 /* Indicate whether to swap the external phy polarity */ 731 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 732 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 733 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 734 735 736 u32 external_phy_config; 737 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000FF 738 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 739 740 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000FF00 741 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 742 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 743 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 744 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 745 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 746 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 747 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 748 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 749 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 750 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 751 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 752 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 753 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 754 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00 755 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 756 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00 757 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 758 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000 759 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100 760 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 761 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 762 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 763 764 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00FF0000 765 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 766 767 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xFF000000 768 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 769 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 770 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 771 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 772 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 773 774 u32 speed_capability_mask; 775 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000FFFF 776 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 777 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 778 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 779 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 780 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 781 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 782 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 783 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 784 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 785 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 786 787 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xFFFF0000 788 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 789 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 790 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 791 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 792 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 793 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 794 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 795 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 796 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 797 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 798 799 /* A place to hold the original MAC address as a backup */ 800 u32 backup_mac_upper; /* 0x2B4 */ 801 u32 backup_mac_lower; /* 0x2B8 */ 802 803 }; 804 805 806 /**************************************************************************** 807 * Shared Feature configuration * 808 ****************************************************************************/ 809 struct shared_feat_cfg { /* NVRAM Offset */ 810 811 u32 config; /* 0x450 */ 812 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 813 814 /* Use NVRAM values instead of HW default values */ 815 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ 816 0x00000002 817 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ 818 0x00000000 819 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ 820 0x00000002 821 822 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 823 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 824 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 825 826 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 827 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 828 829 /* Override the OTP back to single function mode. When using GPIO, 830 high means only SF, 0 is according to CLP configuration */ 831 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 832 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 833 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 834 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 835 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 836 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 837 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400 838 #define SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE 0x00000500 839 #define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE 0x00000600 840 #define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE 0x00000700 841 842 /* Act as if the FCoE license is invalid */ 843 #define SHARED_FEAT_CFG_PREVENT_FCOE 0x00001000 844 845 /* Force FLR capability to all ports */ 846 #define SHARED_FEAT_CFG_FORCE_FLR_CAPABILITY 0x00002000 847 848 /* Act as if the iSCSI license is invalid */ 849 #define SHARED_FEAT_CFG_PREVENT_ISCSI_MASK 0x00004000 850 #define SHARED_FEAT_CFG_PREVENT_ISCSI_SHIFT 14 851 #define SHARED_FEAT_CFG_PREVENT_ISCSI_DISABLED 0x00000000 852 #define SHARED_FEAT_CFG_PREVENT_ISCSI_ENABLED 0x00004000 853 854 /* The interval in seconds between sending LLDP packets. Set to zero 855 to disable the feature */ 856 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00FF0000 857 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 858 859 /* The assigned device type ID for LLDP usage */ 860 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xFF000000 861 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 862 863 }; 864 865 866 /**************************************************************************** 867 * Port Feature configuration * 868 ****************************************************************************/ 869 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ 870 871 u32 config; 872 #define PORT_FEAT_CFG_BAR1_SIZE_MASK 0x0000000F 873 #define PORT_FEAT_CFG_BAR1_SIZE_SHIFT 0 874 #define PORT_FEAT_CFG_BAR1_SIZE_DISABLED 0x00000000 875 #define PORT_FEAT_CFG_BAR1_SIZE_64K 0x00000001 876 #define PORT_FEAT_CFG_BAR1_SIZE_128K 0x00000002 877 #define PORT_FEAT_CFG_BAR1_SIZE_256K 0x00000003 878 #define PORT_FEAT_CFG_BAR1_SIZE_512K 0x00000004 879 #define PORT_FEAT_CFG_BAR1_SIZE_1M 0x00000005 880 #define PORT_FEAT_CFG_BAR1_SIZE_2M 0x00000006 881 #define PORT_FEAT_CFG_BAR1_SIZE_4M 0x00000007 882 #define PORT_FEAT_CFG_BAR1_SIZE_8M 0x00000008 883 #define PORT_FEAT_CFG_BAR1_SIZE_16M 0x00000009 884 #define PORT_FEAT_CFG_BAR1_SIZE_32M 0x0000000a 885 #define PORT_FEAT_CFG_BAR1_SIZE_64M 0x0000000b 886 #define PORT_FEAT_CFG_BAR1_SIZE_128M 0x0000000c 887 #define PORT_FEAT_CFG_BAR1_SIZE_256M 0x0000000d 888 #define PORT_FEAT_CFG_BAR1_SIZE_512M 0x0000000e 889 #define PORT_FEAT_CFG_BAR1_SIZE_1G 0x0000000f 890 #define PORT_FEAT_CFG_BAR2_SIZE_MASK 0x000000F0 891 #define PORT_FEAT_CFG_BAR2_SIZE_SHIFT 4 892 #define PORT_FEAT_CFG_BAR2_SIZE_DISABLED 0x00000000 893 #define PORT_FEAT_CFG_BAR2_SIZE_64K 0x00000010 894 #define PORT_FEAT_CFG_BAR2_SIZE_128K 0x00000020 895 #define PORT_FEAT_CFG_BAR2_SIZE_256K 0x00000030 896 #define PORT_FEAT_CFG_BAR2_SIZE_512K 0x00000040 897 #define PORT_FEAT_CFG_BAR2_SIZE_1M 0x00000050 898 #define PORT_FEAT_CFG_BAR2_SIZE_2M 0x00000060 899 #define PORT_FEAT_CFG_BAR2_SIZE_4M 0x00000070 900 #define PORT_FEAT_CFG_BAR2_SIZE_8M 0x00000080 901 #define PORT_FEAT_CFG_BAR2_SIZE_16M 0x00000090 902 #define PORT_FEAT_CFG_BAR2_SIZE_32M 0x000000a0 903 #define PORT_FEAT_CFG_BAR2_SIZE_64M 0x000000b0 904 #define PORT_FEAT_CFG_BAR2_SIZE_128M 0x000000c0 905 #define PORT_FEAT_CFG_BAR2_SIZE_256M 0x000000d0 906 #define PORT_FEAT_CFG_BAR2_SIZE_512M 0x000000e0 907 #define PORT_FEAT_CFG_BAR2_SIZE_1G 0x000000f0 908 909 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 910 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 911 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 912 913 #define PORT_FEAT_CFG_AUTOGREEEN_MASK 0x00000200 914 #define PORT_FEAT_CFG_AUTOGREEEN_SHIFT 9 915 #define PORT_FEAT_CFG_AUTOGREEEN_DISABLED 0x00000000 916 #define PORT_FEAT_CFG_AUTOGREEEN_ENABLED 0x00000200 917 918 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00 919 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_SHIFT 10 920 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_DEFAULT 0x00000000 921 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400 922 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800 923 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH 0x00000c00 924 925 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 926 #define PORT_FEATURE_EN_SIZE_SHIFT 24 927 #define PORT_FEATURE_WOL_ENABLED 0x01000000 928 #define PORT_FEATURE_MBA_ENABLED 0x02000000 929 #define PORT_FEATURE_MFW_ENABLED 0x04000000 930 931 /* Advertise expansion ROM even if MBA is disabled */ 932 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 933 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 934 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 935 936 /* Check the optic vendor via i2c against a list of approved modules 937 in a separate nvram image */ 938 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000 939 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 940 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ 941 0x00000000 942 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ 943 0x20000000 944 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 945 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 946 947 u32 wol_config; 948 /* Default is used when driver sets to "auto" mode */ 949 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 950 951 u32 mba_config; 952 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 953 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 954 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 955 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 956 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 957 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 958 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 959 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 960 961 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 962 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 963 964 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 965 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 966 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 967 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 968 969 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000FF000 970 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 971 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 972 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 973 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 974 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 975 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 976 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 977 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 978 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 979 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 980 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 981 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 982 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 983 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 984 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 985 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 986 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 987 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00F00000 988 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 989 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 990 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 991 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 992 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 993 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 994 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 995 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3C000000 996 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 997 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 998 #define PORT_FEATURE_MBA_LINK_SPEED_10M_HALF 0x04000000 999 #define PORT_FEATURE_MBA_LINK_SPEED_10M_FULL 0x08000000 1000 #define PORT_FEATURE_MBA_LINK_SPEED_100M_HALF 0x0c000000 1001 #define PORT_FEATURE_MBA_LINK_SPEED_100M_FULL 0x10000000 1002 #define PORT_FEATURE_MBA_LINK_SPEED_1G 0x14000000 1003 #define PORT_FEATURE_MBA_LINK_SPEED_2_5G 0x18000000 1004 #define PORT_FEATURE_MBA_LINK_SPEED_10G 0x1c000000 1005 #define PORT_FEATURE_MBA_LINK_SPEED_20G 0x20000000 1006 1007 u32 Reserved0; /* 0x460 */ 1008 1009 u32 mba_vlan_cfg; 1010 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000FFFF 1011 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 1012 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 1013 #define PORT_FEATUTE_BOFM_CFGD_EN 0x00020000 1014 #define PORT_FEATURE_BOFM_CFGD_FTGT 0x00040000 1015 #define PORT_FEATURE_BOFM_CFGD_VEN 0x00080000 1016 1017 u32 Reserved1; 1018 u32 smbus_config; 1019 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe 1020 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 1021 1022 u32 vf_config; 1023 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000F 1024 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 1025 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 1026 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 1027 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 1028 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 1029 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 1030 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 1031 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 1032 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 1033 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 1034 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 1035 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a 1036 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b 1037 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c 1038 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d 1039 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e 1040 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f 1041 1042 u32 link_config; /* Used as HW defaults for the driver */ 1043 1044 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 1045 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 1046 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 1047 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 1048 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 1049 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 1050 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 1051 #define PORT_FEATURE_FLOW_CONTROL_SAFC_RX 0x00000500 1052 #define PORT_FEATURE_FLOW_CONTROL_SAFC_TX 0x00000600 1053 #define PORT_FEATURE_FLOW_CONTROL_SAFC_BOTH 0x00000700 1054 1055 #define PORT_FEATURE_LINK_SPEED_MASK 0x000F0000 1056 #define PORT_FEATURE_LINK_SPEED_SHIFT 16 1057 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 1058 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00010000 1059 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00020000 1060 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 1061 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 1062 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 1063 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 1064 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 1065 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 1066 1067 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 1068 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 1069 /* (forced) low speed switch (< 10G) */ 1070 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 1071 /* (forced) high speed switch (>= 10G) */ 1072 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 1073 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 1074 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 1075 1076 1077 1078 1079 /* The default for MCP link configuration, 1080 uses the same defines as link_config */ 1081 u32 mfw_wol_link_cfg; 1082 1083 /* The default for the driver of the second external phy, 1084 uses the same defines as link_config */ 1085 u32 link_config2; /* 0x47C */ 1086 1087 /* The default for MCP of the second external phy, 1088 uses the same defines as link_config */ 1089 u32 mfw_wol_link_cfg2; /* 0x480 */ 1090 1091 1092 1093 1094 /* EEE power saving mode */ 1095 u32 eee_power_mode; /* 0x484 */ 1096 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF 1097 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0 1098 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000 1099 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001 1100 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002 1101 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003 1102 1103 1104 u32 Reserved2[16]; /* 0x488 */ 1105 }; 1106 1107 /**************************************************************************** 1108 * Device Information * 1109 ****************************************************************************/ 1110 struct shm_dev_info { /* size */ 1111 1112 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 1113 1114 struct shared_hw_cfg shared_hw_config; /* 40 */ 1115 1116 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ 1117 1118 struct shared_feat_cfg shared_feature_config; /* 4 */ 1119 1120 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ 1121 1122 }; 1123 1124 struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */ 1125 1126 /* Threshold in celcius to start using the fan */ 1127 u32 temperature_monitor1; /* 0x4000 */ 1128 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_MASK 0x0000007F 1129 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_SHIFT 0 1130 1131 /* Threshold in celcius to shut down the board */ 1132 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_MASK 0x00007F00 1133 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_SHIFT 8 1134 1135 /* EPIO of fan temperature status */ 1136 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_MASK 0x00FF0000 1137 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_SHIFT 16 1138 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_NA 0x00000000 1139 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO0 0x00010000 1140 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO1 0x00020000 1141 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO2 0x00030000 1142 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO3 0x00040000 1143 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO4 0x00050000 1144 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO5 0x00060000 1145 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO6 0x00070000 1146 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO7 0x00080000 1147 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO8 0x00090000 1148 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO9 0x000a0000 1149 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO10 0x000b0000 1150 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO11 0x000c0000 1151 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO12 0x000d0000 1152 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO13 0x000e0000 1153 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO14 0x000f0000 1154 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO15 0x00100000 1155 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO16 0x00110000 1156 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO17 0x00120000 1157 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO18 0x00130000 1158 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO19 0x00140000 1159 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO20 0x00150000 1160 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO21 0x00160000 1161 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO22 0x00170000 1162 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO23 0x00180000 1163 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO24 0x00190000 1164 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO25 0x001a0000 1165 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO26 0x001b0000 1166 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO27 0x001c0000 1167 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO28 0x001d0000 1168 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO29 0x001e0000 1169 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO30 0x001f0000 1170 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO31 0x00200000 1171 1172 /* EPIO of shut down temperature status */ 1173 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_MASK 0xFF000000 1174 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_SHIFT 24 1175 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_NA 0x00000000 1176 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO0 0x01000000 1177 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO1 0x02000000 1178 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO2 0x03000000 1179 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO3 0x04000000 1180 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO4 0x05000000 1181 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO5 0x06000000 1182 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO6 0x07000000 1183 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO7 0x08000000 1184 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO8 0x09000000 1185 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO9 0x0a000000 1186 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO10 0x0b000000 1187 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO11 0x0c000000 1188 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO12 0x0d000000 1189 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO13 0x0e000000 1190 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO14 0x0f000000 1191 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO15 0x10000000 1192 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO16 0x11000000 1193 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO17 0x12000000 1194 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO18 0x13000000 1195 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO19 0x14000000 1196 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO20 0x15000000 1197 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO21 0x16000000 1198 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO22 0x17000000 1199 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO23 0x18000000 1200 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO24 0x19000000 1201 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO25 0x1a000000 1202 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO26 0x1b000000 1203 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO27 0x1c000000 1204 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO28 0x1d000000 1205 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO29 0x1e000000 1206 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO30 0x1f000000 1207 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO31 0x20000000 1208 1209 1210 /* EPIO of shut down temperature status */ 1211 u32 temperature_monitor2; /* 0x4004 */ 1212 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK 0x0000FFFF 1213 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT 0 1214 1215 1216 /* MFW flavor to be used */ 1217 u32 mfw_cfg; /* 0x4008 */ 1218 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_MASK 0x000000FF 1219 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_SHIFT 0 1220 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_NA 0x00000000 1221 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_A 0x00000001 1222 1223 /* Should NIC data query remain enabled upon last drv unload */ 1224 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_MASK 0x00000100 1225 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_SHIFT 8 1226 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000 1227 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED 0x00000100 1228 1229 /* Hide DCBX feature in CCM/BACS menus */ 1230 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK 0x00010000 1231 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_SHIFT 16 1232 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_DISABLED 0x00000000 1233 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_ENABLED 0x00010000 1234 1235 u32 smbus_config; /* 0x400C */ 1236 #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_MASK 0x000000FF 1237 #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_SHIFT 0 1238 1239 /* Switching regulator loop gain */ 1240 u32 board_cfg; /* 0x4010 */ 1241 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_MASK 0x0000000F 1242 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_SHIFT 0 1243 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_HW_DEFAULT 0x00000000 1244 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X2 0x00000008 1245 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X4 0x00000009 1246 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X8 0x0000000a 1247 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X16 0x0000000b 1248 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV8 0x0000000c 1249 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV4 0x0000000d 1250 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV2 0x0000000e 1251 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X1 0x0000000f 1252 1253 /* whether shadow swim feature is supported */ 1254 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_MASK 0x00000100 1255 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_SHIFT 8 1256 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_DISABLED 0x00000000 1257 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_ENABLED 0x00000100 1258 1259 /* whether to show/hide SRIOV menu in CCM */ 1260 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_MASK 0x00000200 1261 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_SHIFT 9 1262 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU 0x00000000 1263 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU 0x00000200 1264 1265 /* Overide PCIE revision ID when enabled the, 1266 revision ID will set to B1=='0x11' */ 1267 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_MASK 0x00000400 1268 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_SHIFT 10 1269 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_DISABLED 0x00000000 1270 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_ENABLED 0x00000400 1271 1272 /* Bypass slicer offset tuning */ 1273 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_MASK 0x00000800 1274 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_SHIFT 11 1275 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_DISABLED 0x00000000 1276 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_ENABLED 0x00000800 1277 /* Control Revision ID */ 1278 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_MASK 0x00003000 1279 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_SHIFT 12 1280 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_PRESERVE 0x00000000 1281 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_ACTUAL 0x00001000 1282 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B0 0x00002000 1283 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B1 0x00003000 1284 /* Threshold in celcius for max continuous operation */ 1285 u32 temperature_report; /* 0x4014 */ 1286 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK 0x0000007F 1287 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_SHIFT 0 1288 1289 /* Threshold in celcius for sensor caution */ 1290 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_MASK 0x00007F00 1291 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_SHIFT 8 1292 1293 /* wwn node prefix to be used (unless value is 0) */ 1294 u32 wwn_prefix; /* 0x4018 */ 1295 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_MASK 0x000000FF 1296 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_SHIFT 0 1297 1298 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_MASK 0x0000FF00 1299 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_SHIFT 8 1300 1301 /* wwn port prefix to be used (unless value is 0) */ 1302 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_MASK 0x00FF0000 1303 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_SHIFT 16 1304 1305 /* wwn port prefix to be used (unless value is 0) */ 1306 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_MASK 0xFF000000 1307 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_SHIFT 24 1308 1309 /* General debug nvm cfg */ 1310 u32 dbg_cfg_flags; /* 0x401C */ 1311 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_MASK 0x000FFFFF 1312 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SHIFT 0 1313 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ENABLE 0x00000001 1314 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_EN_SIGDET_FILTER 0x00000002 1315 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_LP_TX_PRESET7 0x00000004 1316 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_TX_ANA_DEFAULT 0x00000008 1317 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_PLL_ANA_DEFAULT 0x00000010 1318 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_G1PLL_RETUNE 0x00000020 1319 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_RX_ANA_DEFAULT 0x00000040 1320 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_SERDES_RX_CLK 0x00000080 1321 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_RX_LP_EIEOS 0x00000100 1322 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FINALIZE_UCODE 0x00000200 1323 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_HOLDOFF_REQ 0x00000400 1324 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_OVERRIDE 0x00000800 1325 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GP_PORG_UC_RESET 0x00001000 1326 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SUPPRESS_COMPEN_EVT 0x00002000 1327 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ADJ_TXEQ_P0_P1 0x00004000 1328 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_G3_PLL_RETUNE 0x00008000 1329 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_MAC_PHY_CTL8 0x00010000 1330 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_MAC_G3_FRM_ERR 0x00020000 1331 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI 0x00040000 1332 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA 0x00080000 1333 1334 /* Debug signet rx threshold */ 1335 u32 dbg_rx_sigdet_threshold; /* 0x4020 */ 1336 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK 0x00000007 1337 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_SHIFT 0 1338 1339 /* Enable IFFE feature */ 1340 u32 iffe_features; /* 0x4024 */ 1341 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_MASK 0x00000001 1342 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_SHIFT 0 1343 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_DISABLED 0x00000000 1344 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_ENABLED 0x00000001 1345 1346 /* Allowable port enablement (bitmask for ports 3-1) */ 1347 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_MASK 0x0000000E 1348 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_SHIFT 1 1349 1350 /* Allow iSCSI offload override */ 1351 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_MASK 0x00000010 1352 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_SHIFT 4 1353 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_DISABLED 0x00000000 1354 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_ENABLED 0x00000010 1355 1356 /* Allow FCoE offload override */ 1357 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_MASK 0x00000020 1358 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_SHIFT 5 1359 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_DISABLED 0x00000000 1360 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_ENABLED 0x00000020 1361 1362 /* Tie to adaptor */ 1363 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_MASK 0x00008000 1364 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_SHIFT 15 1365 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_DISABLED 0x00000000 1366 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_ENABLED 0x00008000 1367 1368 /* Currently enabled port(s) (bitmask for ports 3-1) */ 1369 u32 current_iffe_mask; /* 0x4028 */ 1370 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_MASK 0x0000000E 1371 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_SHIFT 1 1372 1373 /* Current iSCSI offload */ 1374 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_MASK 0x00000010 1375 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_SHIFT 4 1376 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_DISABLED 0x00000000 1377 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_ENABLED 0x00000010 1378 1379 /* Current FCoE offload */ 1380 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_MASK 0x00000020 1381 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_SHIFT 5 1382 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_DISABLED 0x00000000 1383 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_ENABLED 0x00000020 1384 1385 /* FW set this pin to "0" (assert) these signal if either of its MAC 1386 * or PHY specific threshold values is exceeded. 1387 * Values are standard GPIO/EPIO pins. 1388 */ 1389 u32 threshold_pin; /* 0x402C */ 1390 #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_MASK 0x000000FF 1391 #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_SHIFT 0 1392 #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_MASK 0x0000FF00 1393 #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_SHIFT 8 1394 #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_MASK 0x00FF0000 1395 #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_SHIFT 16 1396 1397 /* MAC die temperature threshold in Celsius. */ 1398 u32 mac_threshold_val; /* 0x4030 */ 1399 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_MASK 0x000000FF 1400 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_SHIFT 0 1401 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_MASK 0x0000FF00 1402 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_SHIFT 8 1403 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_MASK 0x00FF0000 1404 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_SHIFT 16 1405 1406 /* PHY die temperature threshold in Celsius. */ 1407 u32 phy_threshold_val; /* 0x4034 */ 1408 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_MASK 0x000000FF 1409 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_SHIFT 0 1410 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_MASK 0x0000FF00 1411 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_SHIFT 8 1412 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_MASK 0x00FF0000 1413 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_SHIFT 16 1414 1415 /* External pins to communicate with host. 1416 * Values are standard GPIO/EPIO pins. 1417 */ 1418 u32 host_pin; /* 0x4038 */ 1419 #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_MASK 0x000000FF 1420 #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_SHIFT 0 1421 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_MASK 0x0000FF00 1422 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_SHIFT 8 1423 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_MASK 0x00FF0000 1424 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_SHIFT 16 1425 #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK 0xFF000000 1426 #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_SHIFT 24 1427 }; 1428 1429 #endif 1430