1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003-2008, Joseph Koshy 5 * Copyright (c) 2007 The FreeBSD Foundation 6 * All rights reserved. 7 * 8 * Portions of this software were developed by A. Joseph Koshy under 9 * sponsorship from the FreeBSD Foundation and Google, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #ifndef _SYS_PMC_H_ 34 #define _SYS_PMC_H_ 35 36 #include <dev/hwpmc/pmc_events.h> 37 #include <sys/proc.h> 38 #include <sys/counter.h> 39 #include <machine/pmc_mdep.h> 40 #include <machine/profile.h> 41 #ifdef _KERNEL 42 #include <sys/epoch.h> 43 #include <ck_queue.h> 44 #endif 45 46 #define PMC_MODULE_NAME "hwpmc" 47 #define PMC_NAME_MAX 64 /* HW counter name size */ 48 #define PMC_CLASS_MAX 8 /* max #classes of PMCs per-system */ 49 50 /* 51 * Kernel<->userland API version number [MMmmpppp] 52 * 53 * Major numbers are to be incremented when an incompatible change to 54 * the ABI occurs that older clients will not be able to handle. 55 * 56 * Minor numbers are incremented when a backwards compatible change 57 * occurs that allows older correct programs to run unchanged. For 58 * example, when support for a new PMC type is added. 59 * 60 * The patch version is incremented for every bug fix. 61 */ 62 #define PMC_VERSION_MAJOR 0x0A 63 #define PMC_VERSION_MINOR 0x01 64 #define PMC_VERSION_PATCH 0x0000 65 66 #define PMC_VERSION (PMC_VERSION_MAJOR << 24 | \ 67 PMC_VERSION_MINOR << 16 | PMC_VERSION_PATCH) 68 69 #define PMC_CPUID_LEN 64 70 /* cpu model name for pmu lookup */ 71 extern char pmc_cpuid[PMC_CPUID_LEN]; 72 73 /* 74 * Kinds of CPUs known. 75 * 76 * We keep track of CPU variants that need to be distinguished in 77 * some way for PMC operations. CPU names are grouped by manufacturer 78 * and numbered sparsely in order to minimize changes to the ABI involved 79 * when new CPUs are added. 80 * 81 * Please keep the pmc(3) manual page in sync with this list. 82 */ 83 #define __PMC_CPUS() \ 84 __PMC_CPU(AMD_K8, 0x01, "AMD K8") \ 85 __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \ 86 __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \ 87 __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \ 88 __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \ 89 __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \ 90 __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \ 91 __PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \ 92 __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \ 93 __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \ 94 __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \ 95 __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \ 96 __PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \ 97 __PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \ 98 __PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \ 99 __PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \ 100 __PMC_CPU(INTEL_BROADWELL, 0x96, "Intel Broadwell") \ 101 __PMC_CPU(INTEL_BROADWELL_XEON, 0x97, "Intel Broadwell Xeon") \ 102 __PMC_CPU(INTEL_SKYLAKE, 0x98, "Intel Skylake") \ 103 __PMC_CPU(INTEL_SKYLAKE_XEON, 0x99, "Intel Skylake Xeon") \ 104 __PMC_CPU(INTEL_ATOM_GOLDMONT, 0x9A, "Intel Atom Goldmont") \ 105 __PMC_CPU(INTEL_ICELAKE, 0x9B, "Intel Icelake") \ 106 __PMC_CPU(INTEL_ICELAKE_XEON, 0x9C, "Intel Icelake Xeon") \ 107 __PMC_CPU(INTEL_ALDERLAKE, 0x9D, "Intel Alderlake") \ 108 __PMC_CPU(INTEL_ATOM_GOLDMONT_P, 0x9E, "Intel Atom Goldmont Plus") \ 109 __PMC_CPU(INTEL_ATOM_TREMONT, 0x9F, "Intel Atom Tremont") \ 110 __PMC_CPU(INTEL_EMERALD_RAPIDS, 0xA0, "Intel Emerald Rapids") \ 111 __PMC_CPU(INTEL_ALDERLAKEN, 0xA1, "Intel AlderlakeN") \ 112 __PMC_CPU(INTEL_GRANITE_RAPIDS, 0xA2, "Intel Granite Rapids") \ 113 __PMC_CPU(INTEL_METEOR_LAKE, 0xA3, "Intel Meteorlake") \ 114 __PMC_CPU(INTEL_SAPPHIRE_RAPIDS, 0xA4, "Intel Sapphire Rapids") \ 115 __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \ 116 __PMC_CPU(PPC_E500, 0x340, "PowerPC e500 Core") \ 117 __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \ 118 __PMC_CPU(PPC_POWER8, 0x390, "IBM POWER8") \ 119 __PMC_CPU(GENERIC, 0x400, "Generic") \ 120 __PMC_CPU(ARMV7_CORTEX_A5, 0x500, "ARMv7 Cortex A5") \ 121 __PMC_CPU(ARMV7_CORTEX_A7, 0x501, "ARMv7 Cortex A7") \ 122 __PMC_CPU(ARMV7_CORTEX_A8, 0x502, "ARMv7 Cortex A8") \ 123 __PMC_CPU(ARMV7_CORTEX_A9, 0x503, "ARMv7 Cortex A9") \ 124 __PMC_CPU(ARMV7_CORTEX_A15, 0x504, "ARMv7 Cortex A15") \ 125 __PMC_CPU(ARMV7_CORTEX_A17, 0x505, "ARMv7 Cortex A17") \ 126 __PMC_CPU(ARMV8_CORTEX_A53, 0x600, "ARMv8 Cortex A53") \ 127 __PMC_CPU(ARMV8_CORTEX_A57, 0x601, "ARMv8 Cortex A57") \ 128 __PMC_CPU(ARMV8_CORTEX_A76, 0x602, "ARMv8 Cortex A76") 129 130 enum pmc_cputype { 131 #undef __PMC_CPU 132 #define __PMC_CPU(S,V,D) PMC_CPU_##S = V, 133 __PMC_CPUS() 134 }; 135 136 #define PMC_CPU_FIRST PMC_CPU_AMD_K8 137 #define PMC_CPU_LAST PMC_CPU_ARMV8_CORTEX_A76 138 139 /* 140 * Classes of PMCs 141 */ 142 #define __PMC_CLASSES() \ 143 __PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \ 144 __PMC_CLASS(K8, 0x02, "AMD K8 performance counters") \ 145 __PMC_CLASS(IBS, 0x03, "AMD IBS performance counters") \ 146 __PMC_CLASS(IAF, 0x06, "Intel Core2/Atom, fixed function") \ 147 __PMC_CLASS(IAP, 0x07, "Intel Core...Atom, programmable") \ 148 __PMC_CLASS(UCF, 0x08, "Intel Uncore fixed function") \ 149 __PMC_CLASS(UCP, 0x09, "Intel Uncore programmable") \ 150 __PMC_CLASS(PPC7450, 0x0D, "Motorola MPC7450 class") \ 151 __PMC_CLASS(PPC970, 0x0E, "IBM PowerPC 970 class") \ 152 __PMC_CLASS(SOFT, 0x0F, "Software events") \ 153 __PMC_CLASS(ARMV7, 0x10, "ARMv7") \ 154 __PMC_CLASS(ARMV8, 0x11, "ARMv8") \ 155 __PMC_CLASS(E500, 0x13, "Freescale e500 class") \ 156 __PMC_CLASS(POWER8, 0x15, "IBM POWER8 class") \ 157 __PMC_CLASS(DMC620_PMU_CD2, 0x16, "ARM DMC620 Memory Controller PMU CLKDIV2") \ 158 __PMC_CLASS(DMC620_PMU_C, 0x17, "ARM DMC620 Memory Controller PMU CLK") \ 159 __PMC_CLASS(CMN600_PMU, 0x18, "Arm CoreLink CMN600 Coherent Mesh Network PMU") 160 161 enum pmc_class { 162 #undef __PMC_CLASS 163 #define __PMC_CLASS(S,V,D) PMC_CLASS_##S = V, 164 __PMC_CLASSES() 165 }; 166 167 #define PMC_CLASS_FIRST PMC_CLASS_TSC 168 #define PMC_CLASS_LAST PMC_CLASS_CMN600_PMU 169 170 /* 171 * A PMC can be in the following states: 172 * 173 * Hardware states: 174 * DISABLED -- administratively prohibited from being used. 175 * FREE -- HW available for use 176 * Software states: 177 * ALLOCATED -- allocated 178 * STOPPED -- allocated, but not counting events 179 * RUNNING -- allocated, and in operation; 'pm_runcount' 180 * holds the number of CPUs using this PMC at 181 * a given instant 182 * DELETED -- being destroyed 183 */ 184 185 #define __PMC_HWSTATES() \ 186 __PMC_STATE(DISABLED) \ 187 __PMC_STATE(FREE) 188 189 #define __PMC_SWSTATES() \ 190 __PMC_STATE(ALLOCATED) \ 191 __PMC_STATE(STOPPED) \ 192 __PMC_STATE(RUNNING) \ 193 __PMC_STATE(DELETED) 194 195 #define __PMC_STATES() \ 196 __PMC_HWSTATES() \ 197 __PMC_SWSTATES() 198 199 enum pmc_state { 200 #undef __PMC_STATE 201 #define __PMC_STATE(S) PMC_STATE_##S, 202 __PMC_STATES() 203 __PMC_STATE(MAX) 204 }; 205 206 #define PMC_STATE_FIRST PMC_STATE_DISABLED 207 #define PMC_STATE_LAST PMC_STATE_DELETED 208 209 /* 210 * An allocated PMC may used as a 'global' counter or as a 211 * 'thread-private' one. Each such mode of use can be in either 212 * statistical sampling mode or in counting mode. Thus a PMC in use 213 * 214 * SS i.e., SYSTEM STATISTICAL -- system-wide statistical profiling 215 * SC i.e., SYSTEM COUNTER -- system-wide counting mode 216 * TS i.e., THREAD STATISTICAL -- thread virtual, statistical profiling 217 * TC i.e., THREAD COUNTER -- thread virtual, counting mode 218 * 219 * Statistical profiling modes rely on the PMC periodically delivering 220 * a interrupt to the CPU (when the configured number of events have 221 * been measured), so the PMC must have the ability to generate 222 * interrupts. 223 * 224 * In counting modes, the PMC counts its configured events, with the 225 * value of the PMC being read whenever needed by its owner process. 226 * 227 * The thread specific modes "virtualize" the PMCs -- the PMCs appear 228 * to be thread private and count events only when the profiled thread 229 * actually executes on the CPU. 230 * 231 * The system-wide "global" modes keep the PMCs running all the time 232 * and are used to measure the behaviour of the whole system. 233 */ 234 235 #define __PMC_MODES() \ 236 __PMC_MODE(SS, 0) \ 237 __PMC_MODE(SC, 1) \ 238 __PMC_MODE(TS, 2) \ 239 __PMC_MODE(TC, 3) 240 241 enum pmc_mode { 242 #undef __PMC_MODE 243 #define __PMC_MODE(M,N) PMC_MODE_##M = N, 244 __PMC_MODES() 245 }; 246 247 #define PMC_MODE_FIRST PMC_MODE_SS 248 #define PMC_MODE_LAST PMC_MODE_TC 249 250 #define PMC_IS_COUNTING_MODE(mode) \ 251 ((mode) == PMC_MODE_SC || (mode) == PMC_MODE_TC) 252 #define PMC_IS_SYSTEM_MODE(mode) \ 253 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_SC) 254 #define PMC_IS_SAMPLING_MODE(mode) \ 255 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_TS) 256 #define PMC_IS_VIRTUAL_MODE(mode) \ 257 ((mode) == PMC_MODE_TS || (mode) == PMC_MODE_TC) 258 259 /* 260 * PMC row disposition 261 */ 262 263 #define __PMC_DISPOSITIONS(N) \ 264 __PMC_DISP(STANDALONE) /* global/disabled counters */ \ 265 __PMC_DISP(FREE) /* free/available */ \ 266 __PMC_DISP(THREAD) /* thread-virtual PMCs */ \ 267 __PMC_DISP(UNKNOWN) /* sentinel */ 268 269 enum pmc_disp { 270 #undef __PMC_DISP 271 #define __PMC_DISP(D) PMC_DISP_##D , 272 __PMC_DISPOSITIONS() 273 }; 274 275 #define PMC_DISP_FIRST PMC_DISP_STANDALONE 276 #define PMC_DISP_LAST PMC_DISP_THREAD 277 278 /* 279 * Counter capabilities 280 * 281 * __PMC_CAPS(NAME, VALUE, DESCRIPTION) 282 */ 283 284 #define __PMC_CAPS() \ 285 __PMC_CAP(INTERRUPT, 0, "generate interrupts") \ 286 __PMC_CAP(USER, 1, "count user-mode events") \ 287 __PMC_CAP(SYSTEM, 2, "count system-mode events") \ 288 __PMC_CAP(EDGE, 3, "do edge detection of events") \ 289 __PMC_CAP(THRESHOLD, 4, "ignore events below a threshold") \ 290 __PMC_CAP(READ, 5, "read PMC counter") \ 291 __PMC_CAP(WRITE, 6, "reprogram PMC counter") \ 292 __PMC_CAP(INVERT, 7, "invert comparison sense") \ 293 __PMC_CAP(QUALIFIER, 8, "further qualify monitored events") \ 294 __PMC_CAP(PRECISE, 9, "perform precise sampling") \ 295 __PMC_CAP(TAGGING, 10, "tag upstream events") \ 296 __PMC_CAP(CASCADE, 11, "cascade counters") \ 297 __PMC_CAP(SYSWIDE, 12, "system wide counter") \ 298 __PMC_CAP(DOMWIDE, 13, "NUMA domain wide counter") 299 300 enum pmc_caps 301 { 302 #undef __PMC_CAP 303 #define __PMC_CAP(NAME, VALUE, DESCR) PMC_CAP_##NAME = (1 << VALUE) , 304 __PMC_CAPS() 305 }; 306 307 #define PMC_CAP_FIRST PMC_CAP_INTERRUPT 308 #define PMC_CAP_LAST PMC_CAP_DOMWIDE 309 310 /* 311 * PMC Event Numbers 312 * 313 * These are generated from the definitions in "dev/hwpmc/pmc_events.h". 314 */ 315 316 enum pmc_event { 317 #undef __PMC_EV 318 #undef __PMC_EV_BLOCK 319 #define __PMC_EV_BLOCK(C,V) PMC_EV_ ## C ## __BLOCK_START = (V) - 1 , 320 #define __PMC_EV(C,N) PMC_EV_ ## C ## _ ## N , 321 __PMC_EVENTS() 322 }; 323 324 /* 325 * PMC SYSCALL INTERFACE 326 */ 327 328 /* 329 * "PMC_OPS" -- these are the commands recognized by the kernel 330 * module, and are used when performing a system call from userland. 331 */ 332 #define __PMC_OPS() \ 333 __PMC_OP(CONFIGURELOG, "Set log file") \ 334 __PMC_OP(FLUSHLOG, "Flush log file") \ 335 __PMC_OP(GETCPUINFO, "Get system CPU information") \ 336 __PMC_OP(GETDRIVERSTATS, "Get driver statistics") \ 337 __PMC_OP(GETMODULEVERSION, "Get module version") \ 338 __PMC_OP(GETPMCINFO, "Get per-cpu PMC information") \ 339 __PMC_OP(PMCADMIN, "Set PMC state") \ 340 __PMC_OP(PMCALLOCATE, "Allocate and configure a PMC") \ 341 __PMC_OP(PMCATTACH, "Attach a PMC to a process") \ 342 __PMC_OP(PMCDETACH, "Detach a PMC from a process") \ 343 __PMC_OP(PMCGETMSR, "Get a PMC's hardware address") \ 344 __PMC_OP(PMCRELEASE, "Release a PMC") \ 345 __PMC_OP(PMCRW, "Read/Set a PMC") \ 346 __PMC_OP(PMCSETCOUNT, "Set initial count/sampling rate") \ 347 __PMC_OP(PMCSTART, "Start a PMC") \ 348 __PMC_OP(PMCSTOP, "Stop a PMC") \ 349 __PMC_OP(WRITELOG, "Write a cookie to the log file") \ 350 __PMC_OP(CLOSELOG, "Close log file") \ 351 __PMC_OP(GETDYNEVENTINFO, "Get dynamic events list") \ 352 __PMC_OP(GETCAPS, "Get capabilities") 353 354 enum pmc_ops { 355 #undef __PMC_OP 356 #define __PMC_OP(N, D) PMC_OP_##N, 357 __PMC_OPS() 358 }; 359 360 /* 361 * Flags used in operations on PMCs. 362 */ 363 364 #define PMC_F_UNUSED1 0x00000001 /* unused */ 365 #define PMC_F_DESCENDANTS 0x00000002 /*OP ALLOCATE track descendants */ 366 #define PMC_F_LOG_PROCCSW 0x00000004 /*OP ALLOCATE track ctx switches */ 367 #define PMC_F_LOG_PROCEXIT 0x00000008 /*OP ALLOCATE log proc exits */ 368 #define PMC_F_NEWVALUE 0x00000010 /*OP RW write new value */ 369 #define PMC_F_OLDVALUE 0x00000020 /*OP RW get old value */ 370 371 /* V2 API */ 372 #define PMC_F_CALLCHAIN 0x00000080 /*OP ALLOCATE capture callchains */ 373 #define PMC_F_USERCALLCHAIN 0x00000100 /*OP ALLOCATE use userspace stack */ 374 375 /* V10 API */ 376 #define PMC_F_EV_PMU 0x00000200 /* 377 * OP ALLOCATE: pm_ev has special 378 * userspace meaning; counter 379 * configuration is communicated 380 * through class-dependent fields 381 */ 382 383 /* internal flags */ 384 #define PMC_F_ATTACHED_TO_OWNER 0x00010000 /*attached to owner*/ 385 #define PMC_F_NEEDS_LOGFILE 0x00020000 /*needs log file */ 386 #define PMC_F_ATTACH_DONE 0x00040000 /*attached at least once */ 387 388 #define PMC_CALLCHAIN_DEPTH_MAX 512 389 390 #define PMC_CC_F_USERSPACE 0x01 /*userspace callchain*/ 391 #define PMC_CC_F_MULTIPART 0x02 /*multipart data*/ 392 393 /* 394 * Cookies used to denote allocated PMCs, and the values of PMCs. 395 */ 396 397 typedef uint32_t pmc_id_t; 398 typedef uint64_t pmc_value_t; 399 400 #define PMC_ID_INVALID (~ (pmc_id_t) 0) 401 402 /* 403 * PMC IDs have the following format: 404 * 405 * +-----------------------+-------+-----------+ 406 * | CPU | PMC MODE | CLASS | ROW INDEX | 407 * +-----------------------+-------+-----------+ 408 * 409 * where CPU is 12 bits, MODE 4, CLASS 8, and ROW INDEX 8 Field 'CPU' 410 * is set to the requested CPU for system-wide PMCs or PMC_CPU_ANY for 411 * process-mode PMCs. Field 'PMC MODE' is the allocated PMC mode. 412 * Field 'PMC CLASS' is the class of the PMC. Field 'ROW INDEX' is the 413 * row index for the PMC. 414 * 415 * The 'ROW INDEX' ranges over 0..NWPMCS where NHWPMCS is the total 416 * number of hardware PMCs on this cpu. 417 */ 418 419 #define PMC_ID_TO_ROWINDEX(ID) ((ID) & 0xFF) 420 #define PMC_ID_TO_CLASS(ID) (((ID) & 0xFF00) >> 8) 421 #define PMC_ID_TO_MODE(ID) (((ID) & 0xF0000) >> 16) 422 #define PMC_ID_TO_CPU(ID) (((ID) & 0xFFF00000) >> 20) 423 #define PMC_ID_MAKE_ID(CPU,MODE,CLASS,ROWINDEX) \ 424 ((((CPU) & 0xFFF) << 20) | (((MODE) & 0xF) << 16) | \ 425 (((CLASS) & 0xFF) << 8) | ((ROWINDEX) & 0xFF)) 426 427 /* 428 * Data structures for system calls supported by the pmc driver. 429 */ 430 431 /* 432 * OP PMCALLOCATE 433 * 434 * Allocate a PMC on the named CPU. 435 */ 436 437 #define PMC_CPU_ANY ~0 438 439 struct pmc_op_pmcallocate { 440 uint32_t pm_caps; /* PMC_CAP_* */ 441 uint32_t pm_cpu; /* CPU number or PMC_CPU_ANY */ 442 enum pmc_class pm_class; /* class of PMC desired */ 443 enum pmc_event pm_ev; /* [enum pmc_event] desired */ 444 uint32_t pm_flags; /* additional modifiers PMC_F_* */ 445 enum pmc_mode pm_mode; /* desired mode */ 446 pmc_id_t pm_pmcid; /* [return] process pmc id */ 447 pmc_value_t pm_count; /* initial/sample count */ 448 449 union pmc_md_op_pmcallocate pm_md; /* MD layer extensions */ 450 }; 451 452 /* 453 * OP PMCADMIN 454 * 455 * Set the administrative state (i.e., whether enabled or disabled) of 456 * a PMC 'pm_pmc' on CPU 'pm_cpu'. Note that 'pm_pmc' specifies an 457 * absolute PMC number and need not have been first allocated by the 458 * calling process. 459 */ 460 461 struct pmc_op_pmcadmin { 462 int pm_cpu; /* CPU# */ 463 uint32_t pm_flags; /* flags */ 464 int pm_pmc; /* PMC# */ 465 enum pmc_state pm_state; /* desired state */ 466 }; 467 468 /* 469 * OP PMCATTACH / OP PMCDETACH 470 * 471 * Attach/detach a PMC and a process. 472 */ 473 474 struct pmc_op_pmcattach { 475 pmc_id_t pm_pmc; /* PMC to attach to */ 476 pid_t pm_pid; /* target process */ 477 }; 478 479 /* 480 * OP PMCSETCOUNT 481 * 482 * Set the sampling rate (i.e., the reload count) for statistical counters. 483 * 'pm_pmcid' need to have been previously allocated using PMCALLOCATE. 484 */ 485 486 struct pmc_op_pmcsetcount { 487 pmc_value_t pm_count; /* initial/sample count */ 488 pmc_id_t pm_pmcid; /* PMC id to set */ 489 }; 490 491 /* 492 * OP PMCRW 493 * 494 * Read the value of a PMC named by 'pm_pmcid'. 'pm_pmcid' needs 495 * to have been previously allocated using PMCALLOCATE. 496 */ 497 498 struct pmc_op_pmcrw { 499 uint32_t pm_flags; /* PMC_F_{OLD,NEW}VALUE*/ 500 pmc_id_t pm_pmcid; /* pmc id */ 501 pmc_value_t pm_value; /* new&returned value */ 502 }; 503 504 /* 505 * OP GETPMCINFO 506 * 507 * retrieve PMC state for a named CPU. The caller is expected to 508 * allocate 'npmc' * 'struct pmc_info' bytes of space for the return 509 * values. 510 */ 511 512 struct pmc_info { 513 char pm_name[PMC_NAME_MAX]; /* pmc name */ 514 enum pmc_class pm_class; /* enum pmc_class */ 515 int pm_enabled; /* whether enabled */ 516 enum pmc_disp pm_rowdisp; /* FREE, THREAD or STANDLONE */ 517 pid_t pm_ownerpid; /* owner, or -1 */ 518 enum pmc_mode pm_mode; /* current mode [enum pmc_mode] */ 519 enum pmc_event pm_event; /* current event */ 520 uint32_t pm_flags; /* current flags */ 521 pmc_value_t pm_reloadcount; /* sampling counters only */ 522 }; 523 524 struct pmc_op_getpmcinfo { 525 int32_t pm_cpu; /* 0 <= cpu < mp_maxid */ 526 struct pmc_info pm_pmcs[]; /* space for 'npmc' structures */ 527 }; 528 529 /* 530 * OP GETCPUINFO 531 * 532 * Retrieve system CPU information. 533 */ 534 535 struct pmc_classinfo { 536 enum pmc_class pm_class; /* class id */ 537 uint32_t pm_caps; /* counter capabilities */ 538 uint32_t pm_width; /* width of the PMC */ 539 uint32_t pm_num; /* number of PMCs in class */ 540 }; 541 542 struct pmc_op_getcpuinfo { 543 enum pmc_cputype pm_cputype; /* what kind of CPU */ 544 uint32_t pm_ncpu; /* max CPU number */ 545 uint32_t pm_npmc; /* #PMCs per CPU */ 546 uint32_t pm_nclass; /* #classes of PMCs */ 547 struct pmc_classinfo pm_classes[PMC_CLASS_MAX]; 548 }; 549 550 /* 551 * OP CONFIGURELOG 552 * 553 * Configure a log file for writing system-wide statistics to. 554 */ 555 556 struct pmc_op_configurelog { 557 int pm_flags; 558 int pm_logfd; /* logfile fd (or -1) */ 559 }; 560 561 /* 562 * OP GETDRIVERSTATS 563 * 564 * Retrieve pmc(4) driver-wide statistics. 565 */ 566 #ifdef _KERNEL 567 struct pmc_driverstats { 568 counter_u64_t pm_intr_ignored; /* #interrupts ignored */ 569 counter_u64_t pm_intr_processed; /* #interrupts processed */ 570 counter_u64_t pm_intr_bufferfull; /* #interrupts with ENOSPC */ 571 counter_u64_t pm_syscalls; /* #syscalls */ 572 counter_u64_t pm_syscall_errors; /* #syscalls with errors */ 573 counter_u64_t pm_buffer_requests; /* #buffer requests */ 574 counter_u64_t pm_buffer_requests_failed; /* #failed buffer requests */ 575 counter_u64_t pm_log_sweeps; /* #sample buffer processing 576 passes */ 577 counter_u64_t pm_merges; /* merged k+u */ 578 counter_u64_t pm_overwrites; /* UR overwrites */ 579 }; 580 #endif 581 582 struct pmc_op_getdriverstats { 583 unsigned int pm_intr_ignored; /* #interrupts ignored */ 584 unsigned int pm_intr_processed; /* #interrupts processed */ 585 unsigned int pm_intr_bufferfull; /* #interrupts with ENOSPC */ 586 unsigned int pm_syscalls; /* #syscalls */ 587 unsigned int pm_syscall_errors; /* #syscalls with errors */ 588 unsigned int pm_buffer_requests; /* #buffer requests */ 589 unsigned int pm_buffer_requests_failed; /* #failed buffer requests */ 590 unsigned int pm_log_sweeps; /* #sample buffer processing 591 passes */ 592 }; 593 594 /* 595 * OP RELEASE / OP START / OP STOP 596 * 597 * Simple operations on a PMC id. 598 */ 599 600 struct pmc_op_simple { 601 pmc_id_t pm_pmcid; 602 }; 603 604 /* 605 * OP WRITELOG 606 * 607 * Flush the current log buffer and write 4 bytes of user data to it. 608 */ 609 610 struct pmc_op_writelog { 611 uint32_t pm_userdata; 612 }; 613 614 /* 615 * OP GETMSR 616 * 617 * Retrieve the machine specific address associated with the allocated 618 * PMC. This number can be used subsequently with a read-performance-counter 619 * instruction. 620 */ 621 622 struct pmc_op_getmsr { 623 uint32_t pm_msr; /* machine specific address */ 624 pmc_id_t pm_pmcid; /* allocated pmc id */ 625 }; 626 627 /* 628 * OP GETDYNEVENTINFO 629 * 630 * Retrieve a PMC dynamic class events list. 631 */ 632 633 struct pmc_dyn_event_descr { 634 char pm_ev_name[PMC_NAME_MAX]; 635 enum pmc_event pm_ev_code; 636 }; 637 638 struct pmc_op_getdyneventinfo { 639 enum pmc_class pm_class; 640 unsigned int pm_nevent; 641 struct pmc_dyn_event_descr pm_events[PMC_EV_DYN_COUNT]; 642 }; 643 644 /* 645 * OP GETCAPS 646 * 647 * Retrieve the PMC capabilties flags for this type of counter. 648 */ 649 650 struct pmc_op_caps { 651 pmc_id_t pm_pmcid; /* allocated pmc id */ 652 uint32_t pm_caps; /* capabilities */ 653 }; 654 655 #ifdef _KERNEL 656 657 #include <sys/malloc.h> 658 #include <sys/sysctl.h> 659 #include <sys/_cpuset.h> 660 661 #include <machine/frame.h> 662 663 #define PMC_HASH_SIZE 1024 664 #define PMC_MTXPOOL_SIZE 2048 665 #define PMC_LOG_BUFFER_SIZE 256 666 #define PMC_LOG_BUFFER_SIZE_MAX (16 * 1024) 667 #define PMC_NLOGBUFFERS_PCPU 32 668 #define PMC_NLOGBUFFERS_PCPU_MEM_MAX (32 * 1024) 669 #define PMC_NSAMPLES 256 670 #define PMC_CALLCHAIN_DEPTH 128 671 #define PMC_THREADLIST_MAX 128 672 673 #define PMC_SYSCTL_NAME_PREFIX "kern." PMC_MODULE_NAME "." 674 675 /* 676 * Locking keys 677 * 678 * (b) - pmc_bufferlist_mtx (spin lock) 679 * (k) - pmc_kthread_mtx (sleep lock) 680 * (o) - po->po_mtx (spin lock) 681 * (g) - global_epoch_preempt (epoch) 682 * (p) - pmc_sx (sx) 683 */ 684 685 /* 686 * PMC commands 687 */ 688 689 struct pmc_syscall_args { 690 register_t pmop_code; /* one of PMC_OP_* */ 691 void *pmop_data; /* syscall parameter */ 692 }; 693 694 /* 695 * Interface to processor specific s1tuff 696 */ 697 698 /* 699 * struct pmc_descr 700 * 701 * Machine independent (i.e., the common parts) of a human readable 702 * PMC description. 703 */ 704 705 struct pmc_descr { 706 char pd_name[PMC_NAME_MAX]; /* name */ 707 uint32_t pd_caps; /* capabilities */ 708 enum pmc_class pd_class; /* class of the PMC */ 709 uint32_t pd_width; /* width in bits */ 710 }; 711 712 /* 713 * struct pmc_target 714 * 715 * This structure records all the target processes associated with a 716 * PMC. 717 */ 718 719 struct pmc_target { 720 LIST_ENTRY(pmc_target) pt_next; 721 struct pmc_process *pt_process; /* target descriptor */ 722 }; 723 724 /* 725 * struct pmc 726 * 727 * Describes each allocated PMC. 728 * 729 * Each PMC has precisely one owner, namely the process that allocated 730 * the PMC. 731 * 732 * A PMC may be attached to multiple target processes. The 733 * 'pm_targets' field links all the target processes being monitored 734 * by this PMC. 735 * 736 * The 'pm_savedvalue' field is protected by a mutex. 737 * 738 * On a multi-cpu machine, multiple target threads associated with a 739 * process-virtual PMC could be concurrently executing on different 740 * CPUs. The 'pm_runcount' field is atomically incremented every time 741 * the PMC gets scheduled on a CPU and atomically decremented when it 742 * get descheduled. Deletion of a PMC is only permitted when this 743 * field is '0'. 744 * 745 */ 746 struct pmc_pcpu_state { 747 uint32_t pps_overflowcnt; /* count overflow interrupts */ 748 uint8_t pps_stalled; 749 uint8_t pps_cpustate; 750 } __aligned(CACHE_LINE_SIZE); 751 struct pmc { 752 LIST_HEAD(,pmc_target) pm_targets; /* list of target processes */ 753 LIST_ENTRY(pmc) pm_next; /* owner's list */ 754 755 /* 756 * System-wide PMCs are allocated on a CPU and are not moved 757 * around. For system-wide PMCs we record the CPU the PMC was 758 * allocated on in the 'CPU' field of the pmc ID. 759 * 760 * Virtual PMCs run on whichever CPU is currently executing 761 * their targets' threads. For these PMCs we need to save 762 * their current PMC counter values when they are taken off 763 * CPU. 764 */ 765 766 union { 767 pmc_value_t pm_savedvalue; /* Virtual PMCS */ 768 } pm_gv; 769 770 /* 771 * For sampling mode PMCs, we keep track of the PMC's "reload 772 * count", which is the counter value to be loaded in when 773 * arming the PMC for the next counting session. For counting 774 * modes on PMCs that are read-only (e.g., the x86 TSC), we 775 * keep track of the initial value at the start of 776 * counting-mode operation. 777 */ 778 779 union { 780 pmc_value_t pm_reloadcount; /* sampling PMC modes */ 781 pmc_value_t pm_initial; /* counting PMC modes */ 782 } pm_sc; 783 784 struct pmc_pcpu_state *pm_pcpu_state; 785 volatile cpuset_t pm_cpustate; /* CPUs where PMC should be active */ 786 uint32_t pm_caps; /* PMC capabilities */ 787 enum pmc_event pm_event; /* event being measured */ 788 uint32_t pm_flags; /* additional flags PMC_F_... */ 789 struct pmc_owner *pm_owner; /* owner thread state */ 790 counter_u64_t pm_runcount; /* #cpus currently on */ 791 enum pmc_state pm_state; /* current PMC state */ 792 793 /* 794 * The PMC ID field encodes the row-index for the PMC, its 795 * mode, class and the CPU# associated with the PMC. 796 */ 797 798 pmc_id_t pm_id; /* allocated PMC id */ 799 enum pmc_class pm_class; 800 801 /* md extensions */ 802 union pmc_md_pmc pm_md; 803 }; 804 805 /* 806 * Accessor macros for 'struct pmc' 807 */ 808 809 #define PMC_TO_MODE(P) PMC_ID_TO_MODE((P)->pm_id) 810 #define PMC_TO_CLASS(P) PMC_ID_TO_CLASS((P)->pm_id) 811 #define PMC_TO_ROWINDEX(P) PMC_ID_TO_ROWINDEX((P)->pm_id) 812 #define PMC_TO_CPU(P) PMC_ID_TO_CPU((P)->pm_id) 813 814 /* 815 * struct pmc_threadpmcstate 816 * 817 * Record per-PMC, per-thread state. 818 */ 819 struct pmc_threadpmcstate { 820 pmc_value_t pt_pmcval; /* per-thread reload count */ 821 }; 822 823 /* 824 * struct pmc_thread 825 * 826 * Record a 'target' thread being profiled. 827 */ 828 struct pmc_thread { 829 LIST_ENTRY(pmc_thread) pt_next; /* linked list */ 830 struct thread *pt_td; /* target thread */ 831 struct pmc_threadpmcstate pt_pmcs[]; /* per-PMC state */ 832 }; 833 834 /* 835 * struct pmc_process 836 * 837 * Record a 'target' process being profiled. 838 * 839 * The target process being profiled could be different from the owner 840 * process which allocated the PMCs. Each target process descriptor 841 * is associated with NHWPMC 'struct pmc *' pointers. Each PMC at a 842 * given hardware row-index 'n' will use slot 'n' of the 'pp_pmcs[]' 843 * array. The size of this structure is thus PMC architecture 844 * dependent. 845 * 846 */ 847 848 struct pmc_targetstate { 849 struct pmc *pp_pmc; /* target PMC */ 850 pmc_value_t pp_pmcval; /* per-process value */ 851 }; 852 853 struct pmc_process { 854 LIST_ENTRY(pmc_process) pp_next; /* hash chain */ 855 LIST_HEAD(,pmc_thread) pp_tds; /* list of threads */ 856 struct mtx *pp_tdslock; /* lock on pp_tds thread list */ 857 int pp_refcnt; /* reference count */ 858 uint32_t pp_flags; /* flags PMC_PP_* */ 859 struct proc *pp_proc; /* target process */ 860 struct pmc_targetstate pp_pmcs[]; /* NHWPMCs */ 861 }; 862 863 #define PMC_PP_ENABLE_MSR_ACCESS 0x00000001 864 865 /* 866 * struct pmc_owner 867 * 868 * We associate a PMC with an 'owner' process. 869 * 870 * A process can be associated with 0..NCPUS*NHWPMC PMCs during its 871 * lifetime, where NCPUS is the numbers of CPUS in the system and 872 * NHWPMC is the number of hardware PMCs per CPU. These are 873 * maintained in the list headed by the 'po_pmcs' to save on space. 874 * 875 */ 876 877 struct pmc_owner { 878 LIST_ENTRY(pmc_owner) po_next; /* hash chain */ 879 CK_LIST_ENTRY(pmc_owner) po_ssnext; /* (g/p) list of SS PMC owners */ 880 LIST_HEAD(, pmc) po_pmcs; /* owned PMC list */ 881 TAILQ_HEAD(, pmclog_buffer) po_logbuffers; /* (o) logbuffer list */ 882 struct mtx po_mtx; /* spin lock for (o) */ 883 struct proc *po_owner; /* owner proc */ 884 uint32_t po_flags; /* (k) flags PMC_PO_* */ 885 struct proc *po_kthread; /* (k) helper kthread */ 886 struct file *po_file; /* file reference */ 887 int po_error; /* recorded error */ 888 short po_sscount; /* # SS PMCs owned */ 889 short po_logprocmaps; /* global mappings done */ 890 struct pmclog_buffer *po_curbuf[MAXCPU]; /* current log buffer */ 891 }; 892 893 #define PMC_PO_OWNS_LOGFILE 0x00000001 /* has a log file */ 894 #define PMC_PO_SHUTDOWN 0x00000010 /* in the process of shutdown */ 895 #define PMC_PO_INITIAL_MAPPINGS_DONE 0x00000020 896 897 /* 898 * struct pmc_hw -- describe the state of the PMC hardware 899 * 900 * When in use, a HW PMC is associated with one allocated 'struct pmc' 901 * pointed to by field 'phw_pmc'. When inactive, this field is NULL. 902 * 903 * On an SMP box, one or more HW PMC's in process virtual mode with 904 * the same 'phw_pmc' could be executing on different CPUs. In order 905 * to handle this case correctly, we need to ensure that only 906 * incremental counts get added to the saved value in the associated 907 * 'struct pmc'. The 'phw_save' field is used to keep the saved PMC 908 * value at the time the hardware is started during this context 909 * switch (i.e., the difference between the new (hardware) count and 910 * the saved count is atomically added to the count field in 'struct 911 * pmc' at context switch time). 912 * 913 */ 914 915 struct pmc_hw { 916 uint32_t phw_state; /* see PHW_* macros below */ 917 struct pmc *phw_pmc; /* current thread PMC */ 918 }; 919 920 #define PMC_PHW_RI_MASK 0x000000FF 921 #define PMC_PHW_CPU_SHIFT 8 922 #define PMC_PHW_CPU_MASK 0x0000FF00 923 #define PMC_PHW_FLAGS_SHIFT 16 924 #define PMC_PHW_FLAGS_MASK 0xFFFF0000 925 926 #define PMC_PHW_INDEX_TO_STATE(ri) ((ri) & PMC_PHW_RI_MASK) 927 #define PMC_PHW_STATE_TO_INDEX(state) ((state) & PMC_PHW_RI_MASK) 928 #define PMC_PHW_CPU_TO_STATE(cpu) (((cpu) << PMC_PHW_CPU_SHIFT) & \ 929 PMC_PHW_CPU_MASK) 930 #define PMC_PHW_STATE_TO_CPU(state) (((state) & PMC_PHW_CPU_MASK) >> \ 931 PMC_PHW_CPU_SHIFT) 932 #define PMC_PHW_FLAGS_TO_STATE(flags) (((flags) << PMC_PHW_FLAGS_SHIFT) & \ 933 PMC_PHW_FLAGS_MASK) 934 #define PMC_PHW_STATE_TO_FLAGS(state) (((state) & PMC_PHW_FLAGS_MASK) >> \ 935 PMC_PHW_FLAGS_SHIFT) 936 #define PMC_PHW_FLAG_IS_ENABLED (PMC_PHW_FLAGS_TO_STATE(0x01)) 937 #define PMC_PHW_FLAG_IS_SHAREABLE (PMC_PHW_FLAGS_TO_STATE(0x02)) 938 939 /* 940 * struct pmc_sample 941 * 942 * Space for N (tunable) PC samples and associated control data. 943 */ 944 945 struct pmc_sample { 946 uint16_t ps_nsamples; /* callchain depth */ 947 uint16_t ps_nsamples_actual; 948 uint16_t ps_cpu; /* cpu number */ 949 uint16_t ps_flags; /* other flags */ 950 lwpid_t ps_tid; /* thread id */ 951 pid_t ps_pid; /* process PID or -1 */ 952 int ps_ticks; /* ticks at sample time */ 953 /* pad */ 954 struct thread *ps_td; /* which thread */ 955 struct pmc *ps_pmc; /* interrupting PMC */ 956 uintptr_t *ps_pc; /* (const) callchain start */ 957 uint64_t ps_tsc; /* tsc value */ 958 }; 959 960 #define PMC_SAMPLE_FREE ((uint16_t) 0) 961 #define PMC_USER_CALLCHAIN_PENDING ((uint16_t) 0xFFFF) 962 963 struct pmc_samplebuffer { 964 volatile uint64_t ps_prodidx; /* producer index */ 965 volatile uint64_t ps_considx; /* consumer index */ 966 uintptr_t *ps_callchains; /* all saved call chains */ 967 struct pmc_sample ps_samples[]; /* array of sample entries */ 968 }; 969 970 #define PMC_CONS_SAMPLE(psb) \ 971 (&(psb)->ps_samples[(psb)->ps_considx & pmc_sample_mask]) 972 973 #define PMC_CONS_SAMPLE_OFF(psb, off) \ 974 (&(psb)->ps_samples[(off) & pmc_sample_mask]) 975 976 #define PMC_PROD_SAMPLE(psb) \ 977 (&(psb)->ps_samples[(psb)->ps_prodidx & pmc_sample_mask]) 978 979 980 /* 981 * struct pmc_multipart 982 * 983 * Multipart payload 984 */ 985 struct pmc_multipart { 986 char pl_type; 987 char pl_length; 988 uint64_t pl_mpdata[10]; 989 }; 990 991 /* 992 * struct pmc_cpustate 993 * 994 * A CPU is modelled as a collection of HW PMCs with space for additional 995 * flags. 996 */ 997 998 struct pmc_cpu { 999 uint32_t pc_state; /* physical cpu number + flags */ 1000 struct pmc_samplebuffer *pc_sb[3]; /* space for samples */ 1001 struct pmc_hw *pc_hwpmcs[]; /* 'npmc' pointers */ 1002 }; 1003 1004 #define PMC_PCPU_CPU_MASK 0x000000FF 1005 #define PMC_PCPU_FLAGS_MASK 0xFFFFFF00 1006 #define PMC_PCPU_FLAGS_SHIFT 8 1007 #define PMC_PCPU_STATE_TO_CPU(S) ((S) & PMC_PCPU_CPU_MASK) 1008 #define PMC_PCPU_STATE_TO_FLAGS(S) (((S) & PMC_PCPU_FLAGS_MASK) >> PMC_PCPU_FLAGS_SHIFT) 1009 #define PMC_PCPU_FLAGS_TO_STATE(F) (((F) << PMC_PCPU_FLAGS_SHIFT) & PMC_PCPU_FLAGS_MASK) 1010 #define PMC_PCPU_CPU_TO_STATE(C) ((C) & PMC_PCPU_CPU_MASK) 1011 #define PMC_PCPU_FLAG_HTT (PMC_PCPU_FLAGS_TO_STATE(0x1)) 1012 1013 /* 1014 * struct pmc_binding 1015 * 1016 * CPU binding information. 1017 */ 1018 1019 struct pmc_binding { 1020 int pb_bound; /* is bound? */ 1021 int pb_cpu; /* if so, to which CPU */ 1022 u_char pb_priority; /* Thread active priority. */ 1023 }; 1024 1025 struct pmc_mdep; 1026 1027 /* 1028 * struct pmc_classdep 1029 * 1030 * PMC class-dependent operations. 1031 */ 1032 struct pmc_classdep { 1033 uint32_t pcd_caps; /* class capabilities */ 1034 enum pmc_class pcd_class; /* class id */ 1035 int pcd_num; /* number of PMCs */ 1036 int pcd_ri; /* row index of the first PMC in class */ 1037 int pcd_width; /* width of the PMC */ 1038 1039 /* configuring/reading/writing the hardware PMCs */ 1040 int (*pcd_config_pmc)(int _cpu, int _ri, struct pmc *_pm); 1041 int (*pcd_get_config)(int _cpu, int _ri, struct pmc **_ppm); 1042 int (*pcd_read_pmc)(int _cpu, int _ri, struct pmc *_pm, 1043 pmc_value_t *_value); 1044 int (*pcd_write_pmc)(int _cpu, int _ri, struct pmc *_pm, 1045 pmc_value_t _value); 1046 1047 /* pmc allocation/release */ 1048 int (*pcd_allocate_pmc)(int _cpu, int _ri, struct pmc *_t, 1049 const struct pmc_op_pmcallocate *_a); 1050 int (*pcd_release_pmc)(int _cpu, int _ri, struct pmc *_pm); 1051 1052 /* starting and stopping PMCs */ 1053 int (*pcd_start_pmc)(int _cpu, int _ri, struct pmc *_pm); 1054 int (*pcd_stop_pmc)(int _cpu, int _ri, struct pmc *_pm); 1055 1056 /* description */ 1057 int (*pcd_describe)(int _cpu, int _ri, struct pmc_info *_pi, 1058 struct pmc **_ppmc); 1059 int (*pcd_get_caps)(int _ri, uint32_t *_caps); 1060 1061 /* class-dependent initialization & finalization */ 1062 int (*pcd_pcpu_init)(struct pmc_mdep *_md, int _cpu); 1063 int (*pcd_pcpu_fini)(struct pmc_mdep *_md, int _cpu); 1064 1065 /* machine-specific interface */ 1066 int (*pcd_get_msr)(int _ri, uint32_t *_msr); 1067 }; 1068 1069 /* 1070 * struct pmc_mdep 1071 * 1072 * Machine dependent bits needed per CPU type. 1073 */ 1074 1075 struct pmc_mdep { 1076 uint32_t pmd_cputype; /* from enum pmc_cputype */ 1077 uint32_t pmd_npmc; /* number of PMCs per CPU */ 1078 uint32_t pmd_nclass; /* number of PMC classes present */ 1079 1080 /* 1081 * Machine dependent methods. 1082 */ 1083 1084 /* thread context switch in/out */ 1085 int (*pmd_switch_in)(struct pmc_cpu *_p, struct pmc_process *_pp); 1086 int (*pmd_switch_out)(struct pmc_cpu *_p, struct pmc_process *_pp); 1087 1088 /* handle a PMC interrupt */ 1089 int (*pmd_intr)(struct trapframe *_tf); 1090 1091 /* 1092 * PMC class dependent information. 1093 */ 1094 struct pmc_classdep pmd_classdep[]; 1095 }; 1096 1097 /* 1098 * Per-CPU state. This is an array of 'mp_ncpu' pointers 1099 * to struct pmc_cpu descriptors. 1100 */ 1101 1102 extern struct pmc_cpu **pmc_pcpu; 1103 1104 /* driver statistics */ 1105 extern struct pmc_driverstats pmc_stats; 1106 1107 #if defined(HWPMC_DEBUG) 1108 1109 /* HWPMC_DEBUG without KTR will compile but is a no-op. */ 1110 #if !defined(KTR) || !defined(KTR_COMPILE) || ((KTR_COMPILE & KTR_SUBSYS) == 0) 1111 #error "HWPMC_DEBUG requires KTR and KTR_COMPILE=KTR_SUBSYS -- see ktr(4)" 1112 #endif 1113 1114 #include <sys/ktr.h> 1115 1116 #define __pmcdbg_used /* unused variable annotation */ 1117 1118 /* 1119 * Debug flags, major flag groups. 1120 * 1121 * Please keep the DEBUGGING section of the hwpmc(4) man page in sync. 1122 */ 1123 struct pmc_debugflags { 1124 int pdb_CPU; 1125 int pdb_CSW; 1126 int pdb_LOG; 1127 int pdb_MDP; 1128 int pdb_MOD; 1129 int pdb_OWN; 1130 int pdb_PMC; 1131 int pdb_PRC; 1132 int pdb_SAM; 1133 }; 1134 1135 extern struct pmc_debugflags pmc_debugflags; 1136 1137 #define KTR_PMC KTR_SUBSYS 1138 1139 #define PMC_DEBUG_STRSIZE 128 1140 #define PMC_DEBUG_DEFAULT_FLAGS { 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1141 1142 #define PMCDBG0(M, N, L, F) do { \ 1143 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1144 CTR0(KTR_PMC, #M ":" #N ":" #L ": " F); \ 1145 } while (0) 1146 #define PMCDBG1(M, N, L, F, p1) do { \ 1147 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1148 CTR1(KTR_PMC, #M ":" #N ":" #L ": " F, p1); \ 1149 } while (0) 1150 #define PMCDBG2(M, N, L, F, p1, p2) do { \ 1151 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1152 CTR2(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2); \ 1153 } while (0) 1154 #define PMCDBG3(M, N, L, F, p1, p2, p3) do { \ 1155 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1156 CTR3(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3); \ 1157 } while (0) 1158 #define PMCDBG4(M, N, L, F, p1, p2, p3, p4) do { \ 1159 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1160 CTR4(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4);\ 1161 } while (0) 1162 #define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) do { \ 1163 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1164 CTR5(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \ 1165 p5); \ 1166 } while (0) 1167 #define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) do { \ 1168 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1169 CTR6(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \ 1170 p5, p6); \ 1171 } while (0) 1172 1173 /* Major numbers */ 1174 #define PMC_DEBUG_MAJ_CPU 0 /* cpu switches */ 1175 #define PMC_DEBUG_MAJ_CSW 1 /* context switches */ 1176 #define PMC_DEBUG_MAJ_LOG 2 /* logging */ 1177 #define PMC_DEBUG_MAJ_MDP 3 /* machine dependent */ 1178 #define PMC_DEBUG_MAJ_MOD 4 /* misc module infrastructure */ 1179 #define PMC_DEBUG_MAJ_OWN 5 /* owner */ 1180 #define PMC_DEBUG_MAJ_PMC 6 /* pmc management */ 1181 #define PMC_DEBUG_MAJ_PRC 7 /* processes */ 1182 #define PMC_DEBUG_MAJ_SAM 8 /* sampling */ 1183 1184 /* Minor numbers */ 1185 1186 /* Common (8 bits) */ 1187 #define PMC_DEBUG_MIN_ALL 0 /* allocation */ 1188 #define PMC_DEBUG_MIN_REL 1 /* release */ 1189 #define PMC_DEBUG_MIN_OPS 2 /* ops: start, stop, ... */ 1190 #define PMC_DEBUG_MIN_INI 3 /* init */ 1191 #define PMC_DEBUG_MIN_FND 4 /* find */ 1192 1193 /* MODULE */ 1194 #define PMC_DEBUG_MIN_PMH 14 /* pmc_hook */ 1195 #define PMC_DEBUG_MIN_PMS 15 /* pmc_syscall */ 1196 1197 /* OWN */ 1198 #define PMC_DEBUG_MIN_ORM 8 /* owner remove */ 1199 #define PMC_DEBUG_MIN_OMR 9 /* owner maybe remove */ 1200 1201 /* PROCESSES */ 1202 #define PMC_DEBUG_MIN_TLK 8 /* link target */ 1203 #define PMC_DEBUG_MIN_TUL 9 /* unlink target */ 1204 #define PMC_DEBUG_MIN_EXT 10 /* process exit */ 1205 #define PMC_DEBUG_MIN_EXC 11 /* process exec */ 1206 #define PMC_DEBUG_MIN_FRK 12 /* process fork */ 1207 #define PMC_DEBUG_MIN_ATT 13 /* attach/detach */ 1208 #define PMC_DEBUG_MIN_SIG 14 /* signalling */ 1209 1210 /* CONTEXT SWITCHES */ 1211 #define PMC_DEBUG_MIN_SWI 8 /* switch in */ 1212 #define PMC_DEBUG_MIN_SWO 9 /* switch out */ 1213 1214 /* PMC */ 1215 #define PMC_DEBUG_MIN_REG 8 /* pmc register */ 1216 #define PMC_DEBUG_MIN_ALR 9 /* allocate row */ 1217 1218 /* MACHINE DEPENDENT LAYER */ 1219 #define PMC_DEBUG_MIN_REA 8 /* read */ 1220 #define PMC_DEBUG_MIN_WRI 9 /* write */ 1221 #define PMC_DEBUG_MIN_CFG 10 /* config */ 1222 #define PMC_DEBUG_MIN_STA 11 /* start */ 1223 #define PMC_DEBUG_MIN_STO 12 /* stop */ 1224 #define PMC_DEBUG_MIN_INT 13 /* interrupts */ 1225 1226 /* CPU */ 1227 #define PMC_DEBUG_MIN_BND 8 /* bind */ 1228 #define PMC_DEBUG_MIN_SEL 9 /* select */ 1229 1230 /* LOG */ 1231 #define PMC_DEBUG_MIN_GTB 8 /* get buf */ 1232 #define PMC_DEBUG_MIN_SIO 9 /* schedule i/o */ 1233 #define PMC_DEBUG_MIN_FLS 10 /* flush */ 1234 #define PMC_DEBUG_MIN_SAM 11 /* sample */ 1235 #define PMC_DEBUG_MIN_CLO 12 /* close */ 1236 1237 #else 1238 #define __pmcdbg_used __unused 1239 #define PMCDBG0(M, N, L, F) /* nothing */ 1240 #define PMCDBG1(M, N, L, F, p1) 1241 #define PMCDBG2(M, N, L, F, p1, p2) 1242 #define PMCDBG3(M, N, L, F, p1, p2, p3) 1243 #define PMCDBG4(M, N, L, F, p1, p2, p3, p4) 1244 #define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) 1245 #define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) 1246 #endif 1247 1248 /* declare a dedicated memory pool */ 1249 MALLOC_DECLARE(M_PMC); 1250 1251 /* 1252 * Functions 1253 */ 1254 1255 struct pmc_mdep *pmc_md_initialize(void); /* MD init function */ 1256 void pmc_md_finalize(struct pmc_mdep *_md); /* MD fini function */ 1257 int pmc_getrowdisp(int _ri); 1258 int pmc_process_interrupt_mp(int _ring, struct pmc *_pm, 1259 struct trapframe *_tf, struct pmc_multipart *mp); 1260 int pmc_process_interrupt(int _ring, struct pmc *_pm, 1261 struct trapframe *_tf); 1262 int pmc_save_kernel_callchain(uintptr_t *_cc, int _maxsamples, 1263 struct trapframe *_tf); 1264 int pmc_save_user_callchain(uintptr_t *_cc, int _maxsamples, 1265 struct trapframe *_tf); 1266 void pmc_restore_cpu_binding(struct pmc_binding *pb); 1267 void pmc_save_cpu_binding(struct pmc_binding *pb); 1268 void pmc_select_cpu(int cpu); 1269 struct pmc_mdep *pmc_mdep_alloc(int nclasses); 1270 void pmc_mdep_free(struct pmc_mdep *md); 1271 uint64_t pmc_rdtsc(void); 1272 #endif /* _KERNEL */ 1273 #endif /* _SYS_PMC_H_ */ 1274