1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 /* 25 * PMC 8x6G register definitions 26 */ 27 #ifndef _PMCS_REG_H 28 #define _PMCS_REG_H 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* 34 * PCI Constants 35 */ 36 #define PMCS_VENDOR_ID 0x11F8 37 #define PMCS_DEVICE_ID 0x8001 38 39 #define PMCS_PM8001_REV_A 0 40 #define PMCS_PM8001_REV_B 1 41 #define PMCS_PM8001_REV_C 2 42 43 #define PMCS_REGSET_0 1 44 #define PMCS_REGSET_1 2 45 #define PMCS_REGSET_2 3 46 #define PMCS_REGSET_3 4 47 48 49 /* 50 * PCIe BARs - 4 64KB memory regions 51 * 52 * BAR0-1 64KiB 53 * BAR2-3 64KiB 54 * BAR4 64KiB 55 * BAR5 64KiB 56 */ 57 58 /* 59 * The PMC 8x6G registers are defined by BARs in PCIe space. 60 * 61 * Four memory region BARS are used. 62 * 63 * The first is for the Messaging Unit. 64 * 65 * The second 64KiB region contains the PCS/PMA registers and some of the 66 * Top-Level registers. 67 * 68 * The third 64KiB region is a 64KiB window on the rest of the chip registers 69 * which can be shifted by writing a register in the second region. 70 * 71 * The fourth 64KiB region is for the message passing area. 72 */ 73 74 /* 75 * Messaging Unit Register Offsets 76 */ 77 #define PMCS_MSGU_IBDB 0x04 /* Inbound Doorbell */ 78 #define PMCS_MSGU_IBDB_CLEAR 0x20 /* InBound Doorbell Clear */ 79 #define PMCS_MSGU_OBDB 0x3c /* OutBound Doorbell */ 80 #define PMCS_MSGU_OBDB_CLEAR 0x40 /* OutBound Doorbell Clear */ 81 #define PMCS_MSGU_SCRATCH0 0x44 /* Scratchpad 0 */ 82 #define PMCS_MSGU_SCRATCH1 0x48 /* Scratchpad 1 */ 83 #define PMCS_MSGU_SCRATCH2 0x4C /* Scratchpad 2 */ 84 #define PMCS_MSGU_SCRATCH3 0x50 /* Scratchpad 3 */ 85 #define PMCS_MSGU_HOST_SCRATCH0 0x54 /* Host Scratchpad 0 */ 86 #define PMCS_MSGU_HOST_SCRATCH1 0x58 /* Host Scratchpad 1 */ 87 #define PMCS_MSGU_HOST_SCRATCH2 0x5C /* Host Scratchpad 2 */ 88 #define PMCS_MSGU_HOST_SCRATCH3 0x60 /* Host Scratchpad 3 */ 89 #define PMCS_MSGU_HOST_SCRATCH4 0x64 /* Host Scratchpad 4 */ 90 #define PMCS_MSGU_HOST_SCRATCH5 0x68 /* Host Scratchpad 5 */ 91 #define PMCS_MSGU_HOST_SCRATCH6 0x6C /* Host Scratchpad 6 */ 92 #define PMCS_MSGU_HOST_SCRATCH7 0x70 /* Host Scratchpad 7 */ 93 #define PMCS_MSGU_OBDB_MASK 0x74 /* Outbound Doorbell Mask */ 94 95 /* 96 * Inbound Doorbell and Doorbell Clear Definitions 97 * NB: The Doorbell Clear register is only used on RevA/8000 parts. 98 */ 99 #define PMCS_MSGU_IBDB_MPIIU 0x08 /* Initiate Unfreeze */ 100 #define PMCS_MSGU_IBDB_MPIIF 0x04 /* Initiate Freeze */ 101 #define PMCS_MSGU_IBDB_MPICTU 0x02 /* Initiate MPI Termination */ 102 #define PMCS_MSGU_IBDB_MPIINI 0x01 /* Initiate MPI */ 103 104 /* 105 * Outbound Doorbell and Doorbell Clear Register 106 * 107 * The Doorbell Clear register is only used on RevA/8000 parts. 108 * 109 * Each bit of the ODR is mapped 1-to-1 to a MSI or MSI-X vector 110 * table entry. There are 32 MSI and 16 MSI-X entries. The top 111 * 16 bits are mapped to the low 16 bits for MSI-X. For legacy 112 * INT-X, any bit will generate a host interrupt. 113 * 114 * Each bit in the Outbound Doorbell Clear is used to clear the 115 * corresponding bit in the ODR. For INT-X it also then deasserts 116 * any interrupt condition. 117 */ 118 #define PMCS_MSI_INTS 32 119 #define PMCS_MSIX_INTS 16 120 121 /* 122 * Scratchpad 0 Definitions 123 * 124 * When the AAP is ready state (see Scratchpad 1), bits 31:26 is the offset 125 * within PCIe space for another BAR that, when mapped, will point to a region 126 * that conains the MPI Configuration table (the offset of which is in bits 127 * 25:0 of this register) 128 * 129 * When the AAP is in error state, this register contains additional error 130 * information. 131 */ 132 #define PMCS_MSGU_MPI_BAR_SHIFT 26 133 #define PMCS_MSGU_MPI_OFFSET_MASK ((1 << PMCS_MSGU_MPI_BAR_SHIFT) - 1) 134 135 /* 136 * Scratchpad 1 Definitions 137 * 138 * The bottom two bits are the AAP state of the 8x6G. 139 * 140 * When the AAP is in error state, bits 31:10 contain the error indicator. 141 * 142 */ 143 #define PMCS_MSGU_AAP_STATE_MASK 0x03 144 #define PMCS_MSGU_AAP_STATE_POR 0 145 #define PMCS_MSGU_AAP_STATE_SOFT_RESET 1 146 #define PMCS_MSGU_AAP_STATE_ERROR 2 147 #define PMCS_MSGU_AAP_STATE_READY 3 148 #define PMCS_MSGU_AAP_SFR_PROGRESS 0x04 149 #define PMCS_MSGU_AAP_ERROR_MASK 0xfffffc00 150 151 /* 152 * Scratchpad 2 Definitions 153 * 154 * Bits 31:10 contain error information if the IOP is in error state. 155 */ 156 #define PMCS_MSGU_IOP_STATE_MASK 0x03 157 #define PMCS_MSGU_IOP_STATE_POR 0 158 #define PMCS_MSGU_IOP_STATE_SOFT_RESET 1 159 #define PMCS_MSGU_IOP_STATE_ERROR 2 160 #define PMCS_MSGU_IOP_STATE_READY 3 161 162 #define PMCS_MSGU_HOST_SOFT_RESET_READY 0x04 163 #define PMCS_MSGU_CPU_SOFT_RESET_READY 0x08 164 165 /* 166 * Scratchpad 3 Definitions 167 * 168 * Contains additional error information if the IOP is in error state 169 * (see Scratchpad 2) 170 */ 171 172 /* 173 * Host Scratchpad 0 174 * Soft Reset Signature 175 */ 176 #define HST_SFT_RESET_SIG 0x252ACBCD 177 178 /* 179 * Host Scratchpad 1 180 * 181 * This is a bit mask for freeze or unfreeze operations for IQs 0..31 182 */ 183 184 /* 185 * Host Scratchpad 2 186 * 187 * This is a bit mask for freeze or unfreeze operations for IQs 32..63 188 */ 189 190 /* 191 * Outbound Doorbell Mask Register 192 * 193 * Each bit set here masks bits and interrupt assertion for the corresponding 194 * bit (and vector) in the ODR. 195 */ 196 197 /* 198 * GSM Registers 199 */ 200 #define GSM_BASE_MASK 0x00ffff 201 #define NMI_EN_VPE0_IOP 0x60418 202 #define NMI_EN_VPE0_AAP1 0x70418 203 #define RB6_ACCESS 0x6A80C0 204 #define GSM_CFG_AND_RESET 0x700000 205 #define RAM_ECC_DOUBLE_ERROR_INDICATOR 0x700018 206 #define READ_ADR_PARITY_CHK_EN 0x700038 207 #define WRITE_ADR_PARITY_CHK_EN 0x700040 208 #define WRITE_DATA_PARITY_CHK_EN 0x700048 209 #define READ_ADR_PARITY_ERROR_INDICATOR 0x700058 210 #define WRITE_ADR_PARITY_ERROR_INDICATOR 0x700060 211 #define WRITE_DATA_PARITY_ERROR_INDICATOR 0x700068 212 213 #define GSM_FLASH_BASE_UPPER 0x18 214 #define GSM_FLASH_BASE 0x40000000 215 #define GSM_FLASH_ILA GSM_FLASH_BASE 216 #define GSM_FLASH_IMG_FLAGS (GSM_FLASH_BASE + 0x400000) 217 218 #define PMCS_IMG_FLAG_A 0x01 219 220 /* 221 * GSM Share Memory, IO Status Table and Ring Buffer 222 */ 223 #define GSM_SM_BLKSZ 0x10000 224 #define GSM_SM_BASE 0x400000 225 #define IO_STATUS_TABLE_BASE 0x640000 226 #define RING_BUF_STORAGE_0 0x680000 227 #define RING_BUF_STORAGE_1 0x690000 228 #define RING_BUF_PTR_ACC_BASE 0x6A0000 229 230 #define IO_STATUS_TABLE_BLKNM 0x4 231 #define GSM_SM_BLKNM 0x10 232 #define RING_BUF_PTR_OFF 0x1000 233 #define RING_BUF_PTR_SIZE 0xFF8 234 #define RING_BUF_ACC_OFF 0x8000 235 #define RING_BUF_ACC_SIZE 0xFF8 236 237 /* 238 * GSM Configuration and Reset Bits 239 */ 240 #define MST_XCBI_SW_RSTB (1 << 14) 241 #define COM_SLV_SW_RSTB (1 << 13) 242 #define QSSP_SW_RSTB (1 << 12) 243 #define RAAE_SW_RSTB (1 << 11) 244 #define RB_1_SW_RSTB (1 << 9) 245 #define SM_SW_RSTB (1 << 8) 246 247 #define COHERENCY_GAP_SHIFT 4 248 #define COHERENCY_GAP_MASK 0xf0 249 #define COHERENCY_GAP_DEFAULT (8 << COHERENCY_GAP_SHIFT) 250 251 #define COHERENCY_MODE (1 << 3) 252 #define RB_WSTRB_ERRCHK_EN (1 << 2) 253 #define RAAE_PORT2_EN (1 << 1) 254 #define GSM_WCI_MODE (1 << 0) 255 #define PMCS_SOFT_RESET_BITS \ 256 (COM_SLV_SW_RSTB|QSSP_SW_RSTB|RAAE_SW_RSTB|RB_1_SW_RSTB|SM_SW_RSTB) 257 258 #define RB6_NMI_SIGNATURE 0x00001234 259 260 /* 261 * PMCS PCI Configuration Registers 262 */ 263 #define PMCS_PCI_PMC 0x40 264 #define PMCS_PCI_PMCSR 0x44 265 #define PMCS_PCI_MSI 0x50 266 #define PMCS_PCI_MAL 0x54 267 #define PMCS_PCI_MAU 0x58 268 #define PMCS_PCI_MD 0x5C 269 #define PMCS_PCI_PCIE 0x70 270 #define PMCS_PCI_DEV_CAP 0x74 271 #define PMCS_PCI_DEV_CTRL 0x78 272 #define PMCS_PCI_LINK_CAP 0x7C 273 #define PMCS_PCI_LINK_CTRL 0x80 274 #define PMCS_PCI_MSIX_CAP 0xAC 275 #define PMCS_PCI_TBL_OFFSET 0xB0 276 #define PMCS_PCI_PBA_OFFSET 0xB4 277 #define PMCS_PCI_PCIE_CAP_HD 0x100 278 #define PMCS_PCI_UE_STAT 0x104 279 #define PMCS_PCI_UE_MASK 0x108 280 #define PMCS_PCI_UE_SEV 0x10C 281 #define PMCS_PCI_CE_STAT 0x110 282 #define PMCS_PCI_CE_MASK 0x114 283 #define PMCS_PCI_ADV_ERR_CTRL 0x118 284 #define PMCS_PCI_HD_LOG_DW 0x11C 285 286 /* 287 * Top Level Registers 288 */ 289 /* these registers are in MEMBASE-III */ 290 #define PMCS_SPC_RESET 0x0 291 #define PMCS_SPC_BOOT_STRAP 0x8 292 #define PMCS_SPC_DEVICE_ID 0x20 293 #define PMCS_DEVICE_REVISION 0x24 294 /* these registers are in MEMBASE-II */ 295 #define PMCS_EVENT_INT_ENABLE 0x3040 296 #define PMCS_EVENT_INT_STAT 0x3044 297 #define PMCS_ERROR_INT_ENABLE 0x3048 298 #define PMCS_ERROR_INT_STAT 0x304C 299 #define PMCS_AXI_TRANS 0x3258 300 #define PMCS_AXI_TRANS_UPPER 0x3268 301 #define PMCS_OBDB_AUTO_CLR 0x335C 302 #define PMCS_INT_COALESCING_TIMER 0x33C0 303 #define PMCS_INT_COALESCING_CONTROL 0x33C4 304 305 306 /* 307 * Chip Reset Register Bits (PMCS_SPC_RESET) 308 * 309 * NB: all bits are inverted. That is, the normal state is '1'. 310 * When '0' is set, the action is taken. 311 */ 312 #define PMCS_SPC_HARD_RESET 0x00 313 #define PMCS_SPC_HARD_RESET_CLR 0xffffffff 314 315 316 #define SW_DEVICE_RSTB (1 << 31) 317 #define PCIE_PC_SXCBI_ARESETN (1 << 26) 318 #define PMIC_CORE_RSTB (1 << 25) 319 #define PMIC_SXCBI_ARESETN (1 << 24) 320 #define LMS_SXCBI_ARESETN (1 << 23) 321 #define PCS_SXCBI_ARESETN (1 << 22) 322 #define PCIE_SFT_RSTB (1 << 21) 323 #define PCIE_PWR_RSTB (1 << 20) 324 #define PCIE_AL_SXCBI_ARESETN (1 << 19) 325 #define BDMA_SXCBI_ARESETN (1 << 18) 326 #define BDMA_CORE_RSTB (1 << 17) 327 #define DDR2_RSTB (1 << 16) 328 #define GSM_RSTB (1 << 8) 329 #define PCS_RSTB (1 << 7) 330 #define PCS_LM_RSTB (1 << 6) 331 #define PCS_AAP2_SS_RSTB (1 << 5) 332 #define PCS_AAP1_SS_RSTB (1 << 4) 333 #define PCS_IOP_SS_RSTB (1 << 3) 334 #define PCS_SPBC_RSTB (1 << 2) 335 #define RAAE_RSTB (1 << 1) 336 #define OSSP_RSTB (1 << 0) 337 338 339 /* 340 * Timer Enables Register 341 */ 342 #define PMCS_TENABLE_WINDOW_OFFSET 0x30000 343 #define PMCS_TENABLE_BASE 0x0209C 344 #define PMCS_TENABLE_MULTIPLIER 0x04000 345 346 /* 347 * Special register (MEMBASE-III) for Step 5.5 in soft reset sequence to set 348 * GPIO into tri-state mode (temporary workaround for 1.07.xx beta firmware) 349 */ 350 #define PMCS_GPIO_TRISTATE_MODE_ADDR 0x9010C 351 #define PMCS_GPIO_TSMODE_BIT0 (1 << 0) 352 #define PMCS_GPIO_TSMODE_BIT1 (1 << 1) 353 354 /* 355 * SAS/SATA PHY Layer Registers 356 * These are in MEMBASE-III (i.e. in GSM space) 357 */ 358 #define OPEN_RETRY_INTERVAL(phy) \ 359 (phy < 4) ? (0x330B4 + (0x4000 * (phy))) : \ 360 (0x430B4 + (0x4000 * (phy - 4))) 361 362 #define OPEN_RETRY_INTERVAL_DEF 20 363 #define OPEN_RETRY_INTERVAL_MAX 0x7FFF 364 365 /* 366 * Register Access Inline Functions 367 */ 368 uint32_t pmcs_rd_msgunit(pmcs_hw_t *, uint32_t); 369 uint32_t pmcs_rd_gsm_reg(pmcs_hw_t *, uint8_t, uint32_t); 370 uint32_t pmcs_rd_topunit(pmcs_hw_t *, uint32_t); 371 uint32_t pmcs_rd_mpi_tbl(pmcs_hw_t *, uint32_t); 372 uint32_t pmcs_rd_gst_tbl(pmcs_hw_t *, uint32_t); 373 uint32_t pmcs_rd_iqc_tbl(pmcs_hw_t *, uint32_t); 374 uint32_t pmcs_rd_oqc_tbl(pmcs_hw_t *, uint32_t); 375 uint32_t pmcs_rd_iqci(pmcs_hw_t *, uint32_t); 376 uint32_t pmcs_rd_iqpi(pmcs_hw_t *, uint32_t); 377 uint32_t pmcs_rd_oqci(pmcs_hw_t *, uint32_t); 378 uint32_t pmcs_rd_oqpi(pmcs_hw_t *, uint32_t); 379 380 void pmcs_wr_msgunit(pmcs_hw_t *, uint32_t, uint32_t); 381 void pmcs_wr_gsm_reg(pmcs_hw_t *, uint32_t, uint32_t); 382 void pmcs_wr_topunit(pmcs_hw_t *, uint32_t, uint32_t); 383 void pmcs_wr_mpi_tbl(pmcs_hw_t *, uint32_t, uint32_t); 384 void pmcs_wr_gst_tbl(pmcs_hw_t *, uint32_t, uint32_t); 385 void pmcs_wr_iqc_tbl(pmcs_hw_t *, uint32_t, uint32_t); 386 void pmcs_wr_oqc_tbl(pmcs_hw_t *, uint32_t, uint32_t); 387 void pmcs_wr_iqci(pmcs_hw_t *, uint32_t, uint32_t); 388 void pmcs_wr_iqpi(pmcs_hw_t *, uint32_t, uint32_t); 389 void pmcs_wr_oqci(pmcs_hw_t *, uint32_t, uint32_t); 390 void pmcs_wr_oqpi(pmcs_hw_t *, uint32_t, uint32_t); 391 392 #ifdef __cplusplus 393 } 394 #endif 395 #endif /* _PMCS_REG_H */ 396