1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2021 NXP
4 */
5
6 #include <linux/bitfield.h>
7 #include <linux/clk-provider.h>
8 #include <linux/err.h>
9 #include <linux/export.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/slab.h>
13 #include <asm/div64.h>
14
15 #include "clk.h"
16
17 #define PLL_CTRL 0x0
18 #define HW_CTRL_SEL BIT(16)
19 #define CLKMUX_BYPASS BIT(2)
20 #define CLKMUX_EN BIT(1)
21 #define POWERUP_MASK BIT(0)
22
23 #define PLL_ANA_PRG 0x10
24 #define PLL_SPREAD_SPECTRUM 0x30
25
26 #define PLL_NUMERATOR 0x40
27 #define PLL_MFN_MASK GENMASK(31, 2)
28
29 #define PLL_DENOMINATOR 0x50
30 #define PLL_MFD_MASK GENMASK(29, 0)
31
32 #define PLL_DIV 0x60
33 #define PLL_MFI_MASK GENMASK(24, 16)
34 #define PLL_RDIV_MASK GENMASK(15, 13)
35 #define PLL_ODIV_MASK GENMASK(7, 0)
36
37 #define PLL_DFS_CTRL(x) (0x70 + (x) * 0x10)
38
39 #define PLL_STATUS 0xF0
40 #define LOCK_STATUS BIT(0)
41
42 #define DFS_STATUS 0xF4
43
44 #define LOCK_TIMEOUT_US 200
45
46 #define PLL_FRACN_GP(_rate, _mfi, _mfn, _mfd, _rdiv, _odiv) \
47 { \
48 .rate = (_rate), \
49 .mfi = (_mfi), \
50 .mfn = (_mfn), \
51 .mfd = (_mfd), \
52 .rdiv = (_rdiv), \
53 .odiv = (_odiv), \
54 }
55
56 #define PLL_FRACN_GP_INTEGER(_rate, _mfi, _rdiv, _odiv) \
57 { \
58 .rate = (_rate), \
59 .mfi = (_mfi), \
60 .mfn = 0, \
61 .mfd = 0, \
62 .rdiv = (_rdiv), \
63 .odiv = (_odiv), \
64 }
65
66 struct clk_fracn_gppll {
67 struct clk_hw hw;
68 void __iomem *base;
69 const struct imx_fracn_gppll_rate_table *rate_table;
70 int rate_count;
71 u32 flags;
72 };
73
74 /*
75 * Fvco = (Fref / rdiv) * (MFI + MFN / MFD)
76 * Fout = Fvco / odiv
77 * The (Fref / rdiv) should be in range 20MHz to 40MHz
78 * The Fvco should be in range 2.5Ghz to 5Ghz
79 */
80 static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
81 PLL_FRACN_GP(1039500000U, 173, 25, 100, 1, 4),
82 PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6),
83 PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
84 PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
85 PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8),
86 PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
87 PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
88 PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
89 PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
90 PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
91 PLL_FRACN_GP(332600000U, 138, 584, 1000, 0, 10),
92 PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12),
93 PLL_FRACN_GP(241900000U, 201, 584, 1000, 0, 20),
94 };
95
96 struct imx_fracn_gppll_clk imx_fracn_gppll = {
97 .rate_table = fracn_tbl,
98 .rate_count = ARRAY_SIZE(fracn_tbl),
99 };
100 EXPORT_SYMBOL_GPL(imx_fracn_gppll);
101
102 /*
103 * Fvco = (Fref / rdiv) * MFI
104 * Fout = Fvco / odiv
105 * The (Fref / rdiv) should be in range 20MHz to 40MHz
106 * The Fvco should be in range 2.5Ghz to 5Ghz
107 */
108 static const struct imx_fracn_gppll_rate_table int_tbl[] = {
109 PLL_FRACN_GP_INTEGER(1700000000U, 141, 1, 2),
110 PLL_FRACN_GP_INTEGER(1400000000U, 175, 1, 3),
111 PLL_FRACN_GP_INTEGER(900000000U, 150, 1, 4),
112 PLL_FRACN_GP_INTEGER(800000000U, 200, 1, 6),
113 };
114
115 struct imx_fracn_gppll_clk imx_fracn_gppll_integer = {
116 .rate_table = int_tbl,
117 .rate_count = ARRAY_SIZE(int_tbl),
118 };
119 EXPORT_SYMBOL_GPL(imx_fracn_gppll_integer);
120
to_clk_fracn_gppll(struct clk_hw * hw)121 static inline struct clk_fracn_gppll *to_clk_fracn_gppll(struct clk_hw *hw)
122 {
123 return container_of(hw, struct clk_fracn_gppll, hw);
124 }
125
126 static const struct imx_fracn_gppll_rate_table *
imx_get_pll_settings(struct clk_fracn_gppll * pll,unsigned long rate)127 imx_get_pll_settings(struct clk_fracn_gppll *pll, unsigned long rate)
128 {
129 const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
130 int i;
131
132 for (i = 0; i < pll->rate_count; i++)
133 if (rate == rate_table[i].rate)
134 return &rate_table[i];
135
136 return NULL;
137 }
138
clk_fracn_gppll_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)139 static int clk_fracn_gppll_determine_rate(struct clk_hw *hw,
140 struct clk_rate_request *req)
141 {
142 struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
143 const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
144 int i;
145
146 /* Assuming rate_table is in descending order */
147 for (i = 0; i < pll->rate_count; i++)
148 if (req->rate >= rate_table[i].rate) {
149 req->rate = rate_table[i].rate;
150
151 return 0;
152 }
153
154 /* return minimum supported value */
155 req->rate = rate_table[pll->rate_count - 1].rate;
156
157 return 0;
158 }
159
clk_fracn_gppll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)160 static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
161 {
162 struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
163 const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
164 u32 pll_numerator, pll_denominator, pll_div;
165 u32 mfi, mfn, mfd, rdiv, odiv;
166 u64 fvco = parent_rate;
167 long rate = 0;
168 int i;
169
170 pll_numerator = readl_relaxed(pll->base + PLL_NUMERATOR);
171 mfn = FIELD_GET(PLL_MFN_MASK, pll_numerator);
172
173 pll_denominator = readl_relaxed(pll->base + PLL_DENOMINATOR);
174 mfd = FIELD_GET(PLL_MFD_MASK, pll_denominator);
175
176 pll_div = readl_relaxed(pll->base + PLL_DIV);
177 mfi = FIELD_GET(PLL_MFI_MASK, pll_div);
178
179 rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div);
180 odiv = FIELD_GET(PLL_ODIV_MASK, pll_div);
181
182 /*
183 * Sometimes, the recalculated rate has deviation due to
184 * the frac part. So find the accurate pll rate from the table
185 * first, if no match rate in the table, use the rate calculated
186 * from the equation below.
187 */
188 for (i = 0; i < pll->rate_count; i++) {
189 if (rate_table[i].mfn == mfn && rate_table[i].mfi == mfi &&
190 rate_table[i].mfd == mfd && rate_table[i].rdiv == rdiv &&
191 rate_table[i].odiv == odiv)
192 rate = rate_table[i].rate;
193 }
194
195 if (rate)
196 return (unsigned long)rate;
197
198 if (!rdiv)
199 rdiv = rdiv + 1;
200
201 switch (odiv) {
202 case 0:
203 odiv = 2;
204 break;
205 case 1:
206 odiv = 3;
207 break;
208 default:
209 break;
210 }
211
212 if (pll->flags & CLK_FRACN_GPPLL_INTEGER) {
213 /* Fvco = (Fref / rdiv) * MFI */
214 fvco = fvco * mfi;
215 do_div(fvco, rdiv * odiv);
216 } else {
217 /* Fvco = (Fref / rdiv) * (MFI + MFN / MFD) */
218 fvco = fvco * mfi * mfd + fvco * mfn;
219 do_div(fvco, mfd * rdiv * odiv);
220 }
221
222 return (unsigned long)fvco;
223 }
224
clk_fracn_gppll_wait_lock(struct clk_fracn_gppll * pll)225 static int clk_fracn_gppll_wait_lock(struct clk_fracn_gppll *pll)
226 {
227 u32 val;
228
229 return readl_poll_timeout(pll->base + PLL_STATUS, val,
230 val & LOCK_STATUS, 0, LOCK_TIMEOUT_US);
231 }
232
clk_fracn_gppll_set_rate(struct clk_hw * hw,unsigned long drate,unsigned long prate)233 static int clk_fracn_gppll_set_rate(struct clk_hw *hw, unsigned long drate,
234 unsigned long prate)
235 {
236 struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
237 const struct imx_fracn_gppll_rate_table *rate;
238 u32 tmp, pll_div, ana_mfn;
239 int ret;
240
241 rate = imx_get_pll_settings(pll, drate);
242
243 /* Hardware control select disable. PLL is control by register */
244 tmp = readl_relaxed(pll->base + PLL_CTRL);
245 tmp &= ~HW_CTRL_SEL;
246 writel_relaxed(tmp, pll->base + PLL_CTRL);
247
248 /* Disable output */
249 tmp = readl_relaxed(pll->base + PLL_CTRL);
250 tmp &= ~CLKMUX_EN;
251 writel_relaxed(tmp, pll->base + PLL_CTRL);
252
253 /* Power Down */
254 tmp &= ~POWERUP_MASK;
255 writel_relaxed(tmp, pll->base + PLL_CTRL);
256
257 /* Disable BYPASS */
258 tmp &= ~CLKMUX_BYPASS;
259 writel_relaxed(tmp, pll->base + PLL_CTRL);
260
261 pll_div = FIELD_PREP(PLL_RDIV_MASK, rate->rdiv) | rate->odiv |
262 FIELD_PREP(PLL_MFI_MASK, rate->mfi);
263 writel_relaxed(pll_div, pll->base + PLL_DIV);
264 readl(pll->base + PLL_DIV);
265 if (pll->flags & CLK_FRACN_GPPLL_FRACN) {
266 writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR);
267 writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUMERATOR);
268 readl(pll->base + PLL_NUMERATOR);
269 }
270
271 /* Wait for 5us according to fracn mode pll doc */
272 udelay(5);
273
274 /* Enable Powerup */
275 tmp |= POWERUP_MASK;
276 writel_relaxed(tmp, pll->base + PLL_CTRL);
277 readl(pll->base + PLL_CTRL);
278
279 /* Wait Lock */
280 ret = clk_fracn_gppll_wait_lock(pll);
281 if (ret)
282 return ret;
283
284 /* Enable output */
285 tmp |= CLKMUX_EN;
286 writel_relaxed(tmp, pll->base + PLL_CTRL);
287
288 ana_mfn = readl_relaxed(pll->base + PLL_STATUS);
289 ana_mfn = FIELD_GET(PLL_MFN_MASK, ana_mfn);
290
291 WARN(ana_mfn != rate->mfn, "ana_mfn != rate->mfn\n");
292
293 return 0;
294 }
295
clk_fracn_gppll_prepare(struct clk_hw * hw)296 static int clk_fracn_gppll_prepare(struct clk_hw *hw)
297 {
298 struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
299 u32 val;
300 int ret;
301
302 val = readl_relaxed(pll->base + PLL_CTRL);
303 if (val & POWERUP_MASK)
304 return 0;
305
306 if (pll->flags & CLK_FRACN_GPPLL_FRACN)
307 writel_relaxed(readl_relaxed(pll->base + PLL_NUMERATOR),
308 pll->base + PLL_NUMERATOR);
309
310 val |= CLKMUX_BYPASS;
311 writel_relaxed(val, pll->base + PLL_CTRL);
312
313 val |= POWERUP_MASK;
314 writel_relaxed(val, pll->base + PLL_CTRL);
315 readl(pll->base + PLL_CTRL);
316
317 ret = clk_fracn_gppll_wait_lock(pll);
318 if (ret)
319 return ret;
320
321 val |= CLKMUX_EN;
322 writel_relaxed(val, pll->base + PLL_CTRL);
323
324 val &= ~CLKMUX_BYPASS;
325 writel_relaxed(val, pll->base + PLL_CTRL);
326
327 return 0;
328 }
329
clk_fracn_gppll_is_prepared(struct clk_hw * hw)330 static int clk_fracn_gppll_is_prepared(struct clk_hw *hw)
331 {
332 struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
333 u32 val;
334
335 val = readl_relaxed(pll->base + PLL_CTRL);
336
337 return (val & POWERUP_MASK) ? 1 : 0;
338 }
339
clk_fracn_gppll_unprepare(struct clk_hw * hw)340 static void clk_fracn_gppll_unprepare(struct clk_hw *hw)
341 {
342 struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
343 u32 val;
344
345 val = readl_relaxed(pll->base + PLL_CTRL);
346 val &= ~POWERUP_MASK;
347 writel_relaxed(val, pll->base + PLL_CTRL);
348 }
349
350 static const struct clk_ops clk_fracn_gppll_ops = {
351 .prepare = clk_fracn_gppll_prepare,
352 .unprepare = clk_fracn_gppll_unprepare,
353 .is_prepared = clk_fracn_gppll_is_prepared,
354 .recalc_rate = clk_fracn_gppll_recalc_rate,
355 .determine_rate = clk_fracn_gppll_determine_rate,
356 .set_rate = clk_fracn_gppll_set_rate,
357 };
358
_imx_clk_fracn_gppll(const char * name,const char * parent_name,void __iomem * base,const struct imx_fracn_gppll_clk * pll_clk,u32 pll_flags)359 static struct clk_hw *_imx_clk_fracn_gppll(const char *name, const char *parent_name,
360 void __iomem *base,
361 const struct imx_fracn_gppll_clk *pll_clk,
362 u32 pll_flags)
363 {
364 struct clk_fracn_gppll *pll;
365 struct clk_hw *hw;
366 struct clk_init_data init;
367 int ret;
368
369 pll = kzalloc_obj(*pll);
370 if (!pll)
371 return ERR_PTR(-ENOMEM);
372
373 init.name = name;
374 init.flags = pll_clk->flags;
375 init.parent_names = &parent_name;
376 init.num_parents = 1;
377 init.ops = &clk_fracn_gppll_ops;
378
379 pll->base = base;
380 pll->hw.init = &init;
381 pll->rate_table = pll_clk->rate_table;
382 pll->rate_count = pll_clk->rate_count;
383 pll->flags = pll_flags;
384
385 hw = &pll->hw;
386
387 ret = clk_hw_register(NULL, hw);
388 if (ret) {
389 pr_err("%s: failed to register pll %s %d\n", __func__, name, ret);
390 kfree(pll);
391 return ERR_PTR(ret);
392 }
393
394 return hw;
395 }
396
imx_clk_fracn_gppll(const char * name,const char * parent_name,void __iomem * base,const struct imx_fracn_gppll_clk * pll_clk)397 struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base,
398 const struct imx_fracn_gppll_clk *pll_clk)
399 {
400 return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_FRACN);
401 }
402 EXPORT_SYMBOL_GPL(imx_clk_fracn_gppll);
403
imx_clk_fracn_gppll_integer(const char * name,const char * parent_name,void __iomem * base,const struct imx_fracn_gppll_clk * pll_clk)404 struct clk_hw *imx_clk_fracn_gppll_integer(const char *name, const char *parent_name,
405 void __iomem *base,
406 const struct imx_fracn_gppll_clk *pll_clk)
407 {
408 return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_INTEGER);
409 }
410 EXPORT_SYMBOL_GPL(imx_clk_fracn_gppll_integer);
411