1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #include "i915_reg_defs.h" 29 #include "display/intel_display_reg_defs.h" 30 31 /** 32 * DOC: The i915 register macro definition style guide 33 * 34 * Follow the style described here for new macros, and while changing existing 35 * macros. Do **not** mass change existing definitions just to update the style. 36 * 37 * File Layout 38 * ~~~~~~~~~~~ 39 * 40 * Keep helper macros near the top. For example, _PIPE() and friends. 41 * 42 * Prefix macros that generally should not be used outside of this file with 43 * underscore '_'. For example, _PIPE() and friends, single instances of 44 * registers that are defined solely for the use by function-like macros. 45 * 46 * Avoid using the underscore prefixed macros outside of this file. There are 47 * exceptions, but keep them to a minimum. 48 * 49 * There are two basic types of register definitions: Single registers and 50 * register groups. Register groups are registers which have two or more 51 * instances, for example one per pipe, port, transcoder, etc. Register groups 52 * should be defined using function-like macros. 53 * 54 * For single registers, define the register offset first, followed by register 55 * contents. 56 * 57 * For register groups, define the register instance offsets first, prefixed 58 * with underscore, followed by a function-like macro choosing the right 59 * instance based on the parameter, followed by register contents. 60 * 61 * Define the register contents (i.e. bit and bit field macros) from most 62 * significant to least significant bit. Indent the register content macros 63 * using two extra spaces between ``#define`` and the macro name. 64 * 65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents 66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already 67 * shifted in place, so they can be directly OR'd together. For convenience, 68 * function-like macros may be used to define bit fields, but do note that the 69 * macros may be needed to read as well as write the register contents. 70 * 71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. 72 * 73 * Group the register and its contents together without blank lines, separate 74 * from other registers and their contents with one blank line. 75 * 76 * Indent macro values from macro names using TABs. Align values vertically. Use 77 * braces in macro values as needed to avoid unintended precedence after macro 78 * substitution. Use spaces in macro values according to kernel coding 79 * style. Use lower case in hexadecimal values. 80 * 81 * Naming 82 * ~~~~~~ 83 * 84 * Try to name registers according to the specs. If the register name changes in 85 * the specs from platform to another, stick to the original name. 86 * 87 * Try to reuse existing register macro definitions. Only add new macros for 88 * new register offsets, or when the register contents have changed enough to 89 * warrant a full redefinition. 90 * 91 * When a register macro changes for a new platform, prefix the new macro using 92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The 93 * prefix signifies the start platform/generation using the register. 94 * 95 * When a bit (field) macro changes or gets added for a new platform, while 96 * retaining the existing register macro, add a platform acronym or generation 97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``. 98 * 99 * Examples 100 * ~~~~~~~~ 101 * 102 * (Note that the values in the example are indented using spaces instead of 103 * TABs to avoid misalignment in generated documentation. Use TABs in the 104 * definitions.):: 105 * 106 * #define _FOO_A 0xf000 107 * #define _FOO_B 0xf001 108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) 109 * #define FOO_ENABLE REG_BIT(31) 110 * #define FOO_MODE_MASK REG_GENMASK(19, 16) 111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) 112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) 113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) 114 * 115 * #define BAR _MMIO(0xb000) 116 * #define GEN8_BAR _MMIO(0xb888) 117 */ 118 119 #define GU_CNTL_PROTECTED _MMIO(0x10100C) 120 #define DEPRESENT REG_BIT(9) 121 122 #define GU_CNTL _MMIO(0x101010) 123 #define LMEM_INIT REG_BIT(7) 124 #define DRIVERFLR REG_BIT(31) 125 #define GU_DEBUG _MMIO(0x101018) 126 #define DRIVERFLR_STATUS REG_BIT(31) 127 128 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) 129 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) 130 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) 131 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) 132 #define GEN6_STOLEN_RESERVED_1M (0 << 4) 133 #define GEN6_STOLEN_RESERVED_512K (1 << 4) 134 #define GEN6_STOLEN_RESERVED_256K (2 << 4) 135 #define GEN6_STOLEN_RESERVED_128K (3 << 4) 136 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) 137 #define GEN7_STOLEN_RESERVED_1M (0 << 5) 138 #define GEN7_STOLEN_RESERVED_256K (1 << 5) 139 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) 140 #define GEN8_STOLEN_RESERVED_1M (0 << 7) 141 #define GEN8_STOLEN_RESERVED_2M (1 << 7) 142 #define GEN8_STOLEN_RESERVED_4M (2 << 7) 143 #define GEN8_STOLEN_RESERVED_8M (3 << 7) 144 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0) 145 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20) 146 147 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 148 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 149 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) 150 151 /* 152 * Reset registers 153 */ 154 #define DEBUG_RESET_I830 _MMIO(0x6070) 155 #define DEBUG_RESET_FULL (1 << 7) 156 #define DEBUG_RESET_RENDER (1 << 8) 157 #define DEBUG_RESET_DISPLAY (1 << 9) 158 159 /* 160 * IOSF sideband 161 */ 162 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) 163 #define IOSF_DEVFN_SHIFT 24 164 #define IOSF_OPCODE_SHIFT 16 165 #define IOSF_PORT_SHIFT 8 166 #define IOSF_BYTE_ENABLES_SHIFT 4 167 #define IOSF_BAR_SHIFT 1 168 #define IOSF_SB_BUSY (1 << 0) 169 #define IOSF_PORT_BUNIT 0x03 170 #define IOSF_PORT_PUNIT 0x04 171 #define IOSF_PORT_NC 0x11 172 #define IOSF_PORT_DPIO 0x12 173 #define IOSF_PORT_GPIO_NC 0x13 174 #define IOSF_PORT_CCK 0x14 175 #define IOSF_PORT_DPIO_2 0x1a 176 #define IOSF_PORT_FLISDSI 0x1b 177 #define IOSF_PORT_GPIO_SC 0x48 178 #define IOSF_PORT_GPIO_SUS 0xa8 179 #define IOSF_PORT_CCU 0xa9 180 #define CHV_IOSF_PORT_GPIO_N 0x13 181 #define CHV_IOSF_PORT_GPIO_SE 0x48 182 #define CHV_IOSF_PORT_GPIO_E 0xa8 183 #define CHV_IOSF_PORT_GPIO_SW 0xb2 184 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) 185 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) 186 187 /* DPIO registers */ 188 #define DPIO_DEVFN 0 189 190 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) 191 #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */ 192 #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */ 193 #define DPIO_SFR_BYPASS (1 << 1) 194 #define DPIO_CMNRST (1 << 0) 195 196 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) 197 #define MIPIO_RST_CTRL (1 << 2) 198 199 #define _BXT_PHY_CTL_DDI_A 0x64C00 200 #define _BXT_PHY_CTL_DDI_B 0x64C10 201 #define _BXT_PHY_CTL_DDI_C 0x64C20 202 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) 203 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) 204 #define BXT_PHY_LANE_ENABLED (1 << 8) 205 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ 206 _BXT_PHY_CTL_DDI_B) 207 208 #define _PHY_CTL_FAMILY_DDI 0x64C90 209 #define _PHY_CTL_FAMILY_EDP 0x64C80 210 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 211 #define COMMON_RESET_DIS (1 << 31) 212 #define BXT_PHY_CTL_FAMILY(phy) \ 213 _MMIO(_PICK_EVEN_2RANGES(phy, 1, \ 214 _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI, \ 215 _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C)) 216 217 /* UAIMI scratch pad register 1 */ 218 #define UAIMI_SPR1 _MMIO(0x4F074) 219 /* SKL VccIO mask */ 220 #define SKL_VCCIO_MASK 0x1 221 /* SKL balance leg register */ 222 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) 223 /* I_boost values */ 224 #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) 225 #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) 226 /* Balance leg disable bits */ 227 #define BALANCE_LEG_DISABLE_SHIFT 23 228 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) 229 230 /* 231 * Fence registers 232 * [0-7] @ 0x2000 gen2,gen3 233 * [8-15] @ 0x3000 945,g33,pnv 234 * 235 * [0-15] @ 0x3000 gen4,gen5 236 * 237 * [0-15] @ 0x100000 gen6,vlv,chv 238 * [0-31] @ 0x100000 gen7+ 239 */ 240 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) 241 #define I830_FENCE_START_MASK 0x07f80000 242 #define I830_FENCE_TILING_Y_SHIFT 12 243 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 244 #define I830_FENCE_PITCH_SHIFT 4 245 #define I830_FENCE_REG_VALID (1 << 0) 246 #define I915_FENCE_MAX_PITCH_VAL 4 247 #define I830_FENCE_MAX_PITCH_VAL 6 248 #define I830_FENCE_MAX_SIZE_VAL (1 << 8) 249 250 #define I915_FENCE_START_MASK 0x0ff00000 251 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 252 253 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) 254 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) 255 #define I965_FENCE_PITCH_SHIFT 2 256 #define I965_FENCE_TILING_Y_SHIFT 1 257 #define I965_FENCE_REG_VALID (1 << 0) 258 #define I965_FENCE_MAX_PITCH_VAL 0x0400 259 260 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) 261 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) 262 #define GEN6_FENCE_PITCH_SHIFT 32 263 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 264 265 266 /* control register for cpu gtt access */ 267 #define TILECTL _MMIO(0x101000) 268 #define TILECTL_SWZCTL (1 << 0) 269 #define TILECTL_TLBPF (1 << 1) 270 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 271 #define TILECTL_BACKSNOOP_DIS (1 << 3) 272 273 /* 274 * Instruction and interrupt control regs 275 */ 276 #define PGTBL_CTL _MMIO(0x02020) 277 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 278 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 279 #define PGTBL_ER _MMIO(0x02024) 280 #define PRB0_BASE (0x2030 - 0x30) 281 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */ 282 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */ 283 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */ 284 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */ 285 #define SRB2_BASE (0x2120 - 0x30) /* 830 */ 286 #define SRB3_BASE (0x2130 - 0x30) /* 830 */ 287 #define RENDER_RING_BASE 0x02000 288 #define BSD_RING_BASE 0x04000 289 #define GEN6_BSD_RING_BASE 0x12000 290 #define GEN8_BSD2_RING_BASE 0x1c000 291 #define GEN11_BSD_RING_BASE 0x1c0000 292 #define GEN11_BSD2_RING_BASE 0x1c4000 293 #define GEN11_BSD3_RING_BASE 0x1d0000 294 #define GEN11_BSD4_RING_BASE 0x1d4000 295 #define XEHP_BSD5_RING_BASE 0x1e0000 296 #define XEHP_BSD6_RING_BASE 0x1e4000 297 #define XEHP_BSD7_RING_BASE 0x1f0000 298 #define XEHP_BSD8_RING_BASE 0x1f4000 299 #define VEBOX_RING_BASE 0x1a000 300 #define GEN11_VEBOX_RING_BASE 0x1c8000 301 #define GEN11_VEBOX2_RING_BASE 0x1d8000 302 #define XEHP_VEBOX3_RING_BASE 0x1e8000 303 #define XEHP_VEBOX4_RING_BASE 0x1f8000 304 #define MTL_GSC_RING_BASE 0x11a000 305 #define GEN12_COMPUTE0_RING_BASE 0x1a000 306 #define GEN12_COMPUTE1_RING_BASE 0x1c000 307 #define GEN12_COMPUTE2_RING_BASE 0x1e000 308 #define GEN12_COMPUTE3_RING_BASE 0x26000 309 #define BLT_RING_BASE 0x22000 310 #define XEHPC_BCS1_RING_BASE 0x3e0000 311 #define XEHPC_BCS2_RING_BASE 0x3e2000 312 #define XEHPC_BCS3_RING_BASE 0x3e4000 313 #define XEHPC_BCS4_RING_BASE 0x3e6000 314 #define XEHPC_BCS5_RING_BASE 0x3e8000 315 #define XEHPC_BCS6_RING_BASE 0x3ea000 316 #define XEHPC_BCS7_RING_BASE 0x3ec000 317 #define XEHPC_BCS8_RING_BASE 0x3ee000 318 #define DG1_GSC_HECI1_BASE 0x00258000 319 #define DG1_GSC_HECI2_BASE 0x00259000 320 #define DG2_GSC_HECI1_BASE 0x00373000 321 #define DG2_GSC_HECI2_BASE 0x00374000 322 #define MTL_GSC_HECI1_BASE 0x00116000 323 #define MTL_GSC_HECI2_BASE 0x00117000 324 325 #define HECI_H_CSR(base) _MMIO((base) + 0x4) 326 #define HECI_H_CSR_IE REG_BIT(0) 327 #define HECI_H_CSR_IS REG_BIT(1) 328 #define HECI_H_CSR_IG REG_BIT(2) 329 #define HECI_H_CSR_RDY REG_BIT(3) 330 #define HECI_H_CSR_RST REG_BIT(4) 331 332 #define HECI_H_GS1(base) _MMIO((base) + 0xc4c) 333 #define HECI_H_GS1_ER_PREP REG_BIT(0) 334 335 /* 336 * The FWSTS register values are FW defined and can be different between 337 * HECI1 and HECI2 338 */ 339 #define HECI_FWSTS1 0xc40 340 #define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0) 341 #define HECI1_FWSTS1_CURRENT_STATE_RESET 0 342 #define HECI1_FWSTS1_PROXY_STATE_NORMAL 5 343 #define HECI1_FWSTS1_INIT_COMPLETE REG_BIT(9) 344 #define HECI_FWSTS2 0xc48 345 #define HECI_FWSTS3 0xc60 346 #define HECI_FWSTS4 0xc64 347 #define HECI_FWSTS5 0xc68 348 #define HECI1_FWSTS5_HUC_AUTH_DONE (1 << 19) 349 #define HECI_FWSTS6 0xc6c 350 351 /* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */ 352 #define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \ 353 HECI_FWSTS1, \ 354 HECI_FWSTS2, \ 355 HECI_FWSTS3, \ 356 HECI_FWSTS4, \ 357 HECI_FWSTS5, \ 358 HECI_FWSTS6)) 359 360 #define HSW_GTT_CACHE_EN _MMIO(0x4024) 361 #define GTT_CACHE_EN_ALL 0xF0007FFF 362 #define GEN7_WR_WATERMARK _MMIO(0x4028) 363 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) 364 #define ARB_MODE _MMIO(0x4030) 365 #define ARB_MODE_SWIZZLE_SNB (1 << 4) 366 #define ARB_MODE_SWIZZLE_IVB (1 << 5) 367 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) 368 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) 369 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 370 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) 371 #define GEN7_LRA_LIMITS_REG_NUM 13 372 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) 373 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) 374 375 #define ILK_GTT_FAULT _MMIO(0x44040) /* ilk/snb */ 376 #define GTT_FAULT_INVALID_GTT_PTE (1 << 7) 377 #define GTT_FAULT_INVALID_PTE_DATA (1 << 6) 378 #define GTT_FAULT_CURSOR_B_FAULT (1 << 5) 379 #define GTT_FAULT_CURSOR_A_FAULT (1 << 4) 380 #define GTT_FAULT_SPRITE_B_FAULT (1 << 3) 381 #define GTT_FAULT_SPRITE_A_FAULT (1 << 2) 382 #define GTT_FAULT_PRIMARY_B_FAULT (1 << 1) 383 #define GTT_FAULT_PRIMARY_A_FAULT (1 << 0) 384 385 #define GEN7_ERR_INT _MMIO(0x44040) 386 #define ERR_INT_POISON (1 << 31) 387 #define ERR_INT_INVALID_GTT_PTE (1 << 29) 388 #define ERR_INT_INVALID_PTE_DATA (1 << 28) 389 #define ERR_INT_SPRITE_C_FAULT (1 << 23) 390 #define ERR_INT_PRIMARY_C_FAULT (1 << 22) 391 #define ERR_INT_CURSOR_C_FAULT (1 << 21) 392 #define ERR_INT_SPRITE_B_FAULT (1 << 20) 393 #define ERR_INT_PRIMARY_B_FAULT (1 << 19) 394 #define ERR_INT_CURSOR_B_FAULT (1 << 18) 395 #define ERR_INT_SPRITE_A_FAULT (1 << 17) 396 #define ERR_INT_PRIMARY_A_FAULT (1 << 16) 397 #define ERR_INT_CURSOR_A_FAULT (1 << 15) 398 #define ERR_INT_MMIO_UNCLAIMED (1 << 13) 399 #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) 400 #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) 401 #define ERR_INT_PIPE_CRC_DONE_B (1 << 5) 402 #define ERR_INT_FIFO_UNDERRUN_B (1 << 3) 403 #define ERR_INT_PIPE_CRC_DONE_A (1 << 2) 404 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3)) 405 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) 406 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 407 408 #define FPGA_DBG _MMIO(0x42300) 409 #define FPGA_DBG_RM_NOCLAIM REG_BIT(31) 410 411 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) 412 #define CLAIM_ER_CLR REG_BIT(31) 413 #define CLAIM_ER_OVERFLOW REG_BIT(16) 414 #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0) 415 416 #define DERRMR _MMIO(0x44050) 417 /* Note that HBLANK events are reserved on bdw+ */ 418 #define DERRMR_PIPEA_SCANLINE (1 << 0) 419 #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1) 420 #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2) 421 #define DERRMR_PIPEA_VBLANK (1 << 3) 422 #define DERRMR_PIPEA_HBLANK (1 << 5) 423 #define DERRMR_PIPEB_SCANLINE (1 << 8) 424 #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9) 425 #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10) 426 #define DERRMR_PIPEB_VBLANK (1 << 11) 427 #define DERRMR_PIPEB_HBLANK (1 << 13) 428 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 429 #define DERRMR_PIPEC_SCANLINE (1 << 14) 430 #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15) 431 #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20) 432 #define DERRMR_PIPEC_VBLANK (1 << 21) 433 #define DERRMR_PIPEC_HBLANK (1 << 22) 434 435 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) 436 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) 437 #define SCPD0 _MMIO(0x209c) /* 915+ only */ 438 #define SCPD_FBC_IGNORE_3D (1 << 6) 439 #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5) 440 #define GEN2_IER _MMIO(0x20a0) 441 #define GEN2_IIR _MMIO(0x20a4) 442 #define GEN2_IMR _MMIO(0x20a8) 443 #define GEN2_ISR _MMIO(0x20ac) 444 445 #define GEN2_IRQ_REGS I915_IRQ_REGS(GEN2_IMR, \ 446 GEN2_IER, \ 447 GEN2_IIR) 448 449 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) 450 #define GINT_DIS (1 << 22) 451 #define GCFG_DIS (1 << 8) 452 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) 453 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 454 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 455 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 456 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 457 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 458 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 459 #define VLV_PCBR_ADDR_SHIFT 12 460 461 #define VLV_IRQ_REGS I915_IRQ_REGS(VLV_IMR, \ 462 VLV_IER, \ 463 VLV_IIR) 464 465 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */ 466 #define EIR _MMIO(0x20b0) 467 #define EMR _MMIO(0x20b4) 468 #define ESR _MMIO(0x20b8) 469 #define GM45_ERROR_PAGE_TABLE (1 << 5) 470 #define GM45_ERROR_MEM_PRIV (1 << 4) 471 #define I915_ERROR_PAGE_TABLE (1 << 4) 472 #define GM45_ERROR_CP_PRIV (1 << 3) 473 #define I915_ERROR_MEMORY_REFRESH (1 << 1) 474 #define I915_ERROR_INSTRUCTION (1 << 0) 475 476 #define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR) 477 478 #define VLV_EIR _MMIO(VLV_DISPLAY_BASE + 0x20b0) 479 #define VLV_EMR _MMIO(VLV_DISPLAY_BASE + 0x20b4) 480 #define VLV_ESR _MMIO(VLV_DISPLAY_BASE + 0x20b8) 481 #define VLV_ERROR_GUNIT_TLB_DATA (1 << 6) 482 #define VLV_ERROR_GUNIT_TLB_PTE (1 << 5) 483 #define VLV_ERROR_PAGE_TABLE (1 << 4) 484 #define VLV_ERROR_CLAIM (1 << 0) 485 486 #define VLV_ERROR_REGS I915_ERROR_REGS(VLV_EMR, VLV_EIR) 487 488 #define INSTPM _MMIO(0x20c0) 489 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ 490 #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts 491 will not assert AGPBUSY# and will only 492 be delivered when out of C3. */ 493 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ 494 #define INSTPM_TLB_INVALIDATE (1 << 9) 495 #define INSTPM_SYNC_FLUSH (1 << 5) 496 #define MEM_MODE _MMIO(0x20cc) 497 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ 498 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ 499 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */ 500 #define FW_BLC _MMIO(0x20d8) 501 #define FW_BLC2 _MMIO(0x20dc) 502 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ 503 #define FW_BLC_SELF_EN_MASK (1 << 31) 504 #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */ 505 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */ 506 #define MM_BURST_LENGTH 0x00700000 507 #define MM_FIFO_WATERMARK 0x0001F000 508 #define LM_BURST_LENGTH 0x00000700 509 #define LM_FIFO_WATERMARK 0x0000001F 510 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ 511 512 #define _MBUS_ABOX0_CTL 0x45038 513 #define _MBUS_ABOX1_CTL 0x45048 514 #define _MBUS_ABOX2_CTL 0x4504C 515 #define MBUS_ABOX_CTL(x) \ 516 _MMIO(_PICK_EVEN_2RANGES(x, 2, \ 517 _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL, \ 518 _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL)) 519 520 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) 521 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) 522 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) 523 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16) 524 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) 525 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) 526 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) 527 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) 528 529 /* 530 * Make render/texture TLB fetches lower priority than associated data 531 * fetches. This is not turned on by default. 532 */ 533 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 534 535 /* Isoch request wait on GTT enable (Display A/B/C streams). 536 * Make isoch requests stall on the TLB update. May cause 537 * display underruns (test mode only) 538 */ 539 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 540 541 /* Block grant count for isoch requests when block count is 542 * set to a finite value. 543 */ 544 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 545 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 546 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 547 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 548 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 549 550 /* Enable render writes to complete in C2/C3/C4 power states. 551 * If this isn't enabled, render writes are prevented in low 552 * power states. That seems bad to me. 553 */ 554 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 555 556 /* This acknowledges an async flip immediately instead 557 * of waiting for 2TLB fetches. 558 */ 559 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 560 561 /* Enables non-sequential data reads through arbiter 562 */ 563 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 564 565 /* Disable FSB snooping of cacheable write cycles from binner/render 566 * command stream 567 */ 568 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 569 570 /* Arbiter time slice for non-isoch streams */ 571 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 572 #define MI_ARB_TIME_SLICE_1 (0 << 5) 573 #define MI_ARB_TIME_SLICE_2 (1 << 5) 574 #define MI_ARB_TIME_SLICE_4 (2 << 5) 575 #define MI_ARB_TIME_SLICE_6 (3 << 5) 576 #define MI_ARB_TIME_SLICE_8 (4 << 5) 577 #define MI_ARB_TIME_SLICE_10 (5 << 5) 578 #define MI_ARB_TIME_SLICE_14 (6 << 5) 579 #define MI_ARB_TIME_SLICE_16 (7 << 5) 580 581 /* Low priority grace period page size */ 582 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 583 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 584 585 /* Disable display A/B trickle feed */ 586 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 587 588 /* Set display plane priority */ 589 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 590 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 591 592 #define MI_STATE _MMIO(0x20e4) /* gen2 only */ 593 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 594 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 595 596 /* On modern GEN architectures interrupt control consists of two sets 597 * of registers. The first set pertains to the ring generating the 598 * interrupt. The second control is for the functional block generating the 599 * interrupt. These are PM, GT, DE, etc. 600 * 601 * Luckily *knocks on wood* all the ring interrupt bits match up with the 602 * GT interrupt bits, so we don't need to duplicate the defines. 603 * 604 * These defines should cover us well from SNB->HSW with minor exceptions 605 * it can also work on ILK. 606 */ 607 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 608 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 609 #define GT_BLT_USER_INTERRUPT (1 << 22) 610 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 611 #define GT_BSD_USER_INTERRUPT (1 << 12) 612 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 613 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */ 614 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 615 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 616 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 617 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) 618 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 619 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 620 #define GT_RENDER_USER_INTERRUPT (1 << 0) 621 622 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 623 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 624 625 #define GT_PARITY_ERROR(dev_priv) \ 626 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 627 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 628 629 /* These are all the "old" interrupts */ 630 #define ILK_BSD_USER_INTERRUPT (1 << 5) 631 632 #define I915_PM_INTERRUPT (1 << 31) 633 #define I915_ISP_INTERRUPT (1 << 22) 634 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21) 635 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20) 636 #define I915_MIPIC_INTERRUPT (1 << 19) 637 #define I915_MIPIA_INTERRUPT (1 << 18) 638 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18) 639 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17) 640 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16) 641 #define I915_MASTER_ERROR_INTERRUPT (1 << 15) 642 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14) 643 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */ 644 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13) 645 #define I915_HWB_OOM_INTERRUPT (1 << 13) 646 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12) 647 #define I915_SYNC_STATUS_INTERRUPT (1 << 12) 648 #define I915_MISC_INTERRUPT (1 << 11) 649 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11) 650 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10) 651 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10) 652 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9) 653 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9) 654 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8) 655 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8) 656 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7) 657 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6) 658 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5) 659 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4) 660 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3) 661 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2) 662 #define I915_DEBUG_INTERRUPT (1 << 2) 663 #define I915_WINVALID_INTERRUPT (1 << 1) 664 #define I915_USER_INTERRUPT (1 << 1) 665 #define I915_ASLE_INTERRUPT (1 << 0) 666 #define I915_BSD_USER_INTERRUPT (1 << 25) 667 668 #define GEN6_BSD_RNCID _MMIO(0x12198) 669 670 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) 671 #define GEN7_FF_SCHED_MASK 0x0077070 672 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 673 #define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19) 674 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16) 675 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16) 676 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16) 677 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */ 678 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 679 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12) 680 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12) 681 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */ 682 #define GEN7_FF_VS_SCHED_HW (0x0 << 12) 683 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4) 684 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4) 685 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */ 686 #define GEN7_FF_DS_SCHED_HW (0x0 << 4) 687 688 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) 689 #define ILK_FBCQ_DIS REG_BIT(22) 690 #define ILK_PABSTRETCH_DIS REG_BIT(21) 691 #define ILK_SABSTRETCH_DIS REG_BIT(20) 692 #define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20) 693 #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0) 694 #define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1) 695 #define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2) 696 #define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3) 697 #define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18) 698 #define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0) 699 #define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1) 700 #define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2) 701 #define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3) 702 703 #define IPS_CTL _MMIO(0x43408) 704 #define IPS_ENABLE REG_BIT(31) 705 #define IPS_FALSE_COLOR REG_BIT(4) 706 707 /* 708 * Clock control & power management 709 */ 710 #define _DPLL_A 0x6014 711 #define _DPLL_B 0x6018 712 #define _CHV_DPLL_C 0x6030 713 #define DPLL(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \ 714 (pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 715 716 #define VGA0 _MMIO(0x6000) 717 #define VGA1 _MMIO(0x6004) 718 #define VGA_PD _MMIO(0x6010) 719 #define VGA0_PD_P2_DIV_4 (1 << 7) 720 #define VGA0_PD_P1_DIV_2 (1 << 5) 721 #define VGA0_PD_P1_SHIFT 0 722 #define VGA0_PD_P1_MASK (0x1f << 0) 723 #define VGA1_PD_P2_DIV_4 (1 << 15) 724 #define VGA1_PD_P1_DIV_2 (1 << 13) 725 #define VGA1_PD_P1_SHIFT 8 726 #define VGA1_PD_P1_MASK (0x1f << 8) 727 #define DPLL_VCO_ENABLE (1 << 31) 728 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 729 #define DPLL_DVO_2X_MODE (1 << 30) 730 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 731 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 732 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) 733 #define DPLL_VGA_MODE_DIS (1 << 28) 734 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 735 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 736 #define DPLL_MODE_MASK (3 << 26) 737 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 738 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 739 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 740 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 741 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 742 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 743 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 744 #define DPLL_LOCK_VLV (1 << 15) 745 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) 746 #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13) 747 #define DPLL_SSC_REF_CLK_CHV (1 << 13) 748 #define DPLL_PORTC_READY_MASK (0xf << 4) 749 #define DPLL_PORTB_READY_MASK (0xf) 750 751 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 752 753 /* Additional CHV pll/phy registers */ 754 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) 755 #define DPLL_PORTD_READY_MASK (0xf) 756 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) 757 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27)) 758 #define PHY_LDO_DELAY_0NS 0x0 759 #define PHY_LDO_DELAY_200NS 0x1 760 #define PHY_LDO_DELAY_600NS 0x2 761 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23)) 762 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11)) 763 #define PHY_CH_SU_PSR 0x1 764 #define PHY_CH_DEEP_PSR 0x7 765 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2)) 766 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 767 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) 768 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30)) 769 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch)))) 770 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)))) 771 772 /* 773 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 774 * this field (only one bit may be set). 775 */ 776 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 777 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 778 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 779 /* i830, required in DVO non-gang */ 780 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 781 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 782 #define PLL_REF_INPUT_DREFCLK (0 << 13) 783 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 784 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 785 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 786 #define PLL_REF_INPUT_MASK (3 << 13) 787 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 788 /* Ironlake */ 789 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 790 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 791 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9) 792 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 793 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 794 795 /* 796 * Parallel to Serial Load Pulse phase selection. 797 * Selects the phase for the 10X DPLL clock for the PCIe 798 * digital display port. The range is 4 to 13; 10 or more 799 * is just a flip delay. The default is 6 800 */ 801 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 802 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 803 /* 804 * SDVO multiplier for 945G/GM. Not used on 965. 805 */ 806 #define SDVO_MULTIPLIER_MASK 0x000000ff 807 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 808 #define SDVO_MULTIPLIER_SHIFT_VGA 0 809 810 #define _DPLL_A_MD 0x601c 811 #define _DPLL_B_MD 0x6020 812 #define _CHV_DPLL_C_MD 0x603c 813 #define DPLL_MD(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \ 814 (pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 815 816 /* 817 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 818 * 819 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 820 */ 821 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 822 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 823 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 824 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 825 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 826 /* 827 * SDVO/UDI pixel multiplier. 828 * 829 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 830 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 831 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 832 * dummy bytes in the datastream at an increased clock rate, with both sides of 833 * the link knowing how many bytes are fill. 834 * 835 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 836 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 837 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 838 * through an SDVO command. 839 * 840 * This register field has values of multiplication factor minus 1, with 841 * a maximum multiplier of 5 for SDVO. 842 */ 843 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 844 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 845 /* 846 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 847 * This best be set to the default value (3) or the CRT won't work. No, 848 * I don't entirely understand what this does... 849 */ 850 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 851 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 852 853 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) 854 855 #define _FPA0 0x6040 856 #define _FPA1 0x6044 857 #define _FPB0 0x6048 858 #define _FPB1 0x604c 859 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) 860 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) 861 #define FP_N_DIV_MASK 0x003f0000 862 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 863 #define FP_N_DIV_SHIFT 16 864 #define FP_M1_DIV_MASK 0x00003f00 865 #define FP_M1_DIV_SHIFT 8 866 #define FP_M2_DIV_MASK 0x0000003f 867 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 868 #define FP_M2_DIV_SHIFT 0 869 #define DPLL_TEST _MMIO(0x606c) 870 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 871 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 872 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 873 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 874 #define DPLLB_TEST_N_BYPASS (1 << 19) 875 #define DPLLB_TEST_M_BYPASS (1 << 18) 876 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 877 #define DPLLA_TEST_N_BYPASS (1 << 3) 878 #define DPLLA_TEST_M_BYPASS (1 << 2) 879 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 880 #define D_STATE _MMIO(0x6104) 881 #define DSTATE_GFX_RESET_I830 (1 << 6) 882 #define DSTATE_PLL_D3_OFF (1 << 3) 883 #define DSTATE_GFX_CLOCK_GATING (1 << 1) 884 #define DSTATE_DOT_CLOCK_GATING (1 << 0) 885 #define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200) 886 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 887 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 888 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 889 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 890 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 891 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 892 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 893 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */ 894 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 895 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 896 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 897 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 898 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 899 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 900 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 901 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 902 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 903 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 904 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 905 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 906 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 907 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 908 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 909 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 910 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 911 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 912 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 913 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 914 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 915 /* 916 * This bit must be set on the 830 to prevent hangs when turning off the 917 * overlay scaler. 918 */ 919 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 920 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 921 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 922 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 923 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 924 925 #define RENCLK_GATE_D1 _MMIO(0x6204) 926 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 927 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 928 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 929 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 930 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 931 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 932 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 933 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 934 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 935 /* This bit must be unset on 855,865 */ 936 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 937 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 938 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 939 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 940 /* This bit must be set on 855,865. */ 941 # define SV_CLOCK_GATE_DISABLE (1 << 0) 942 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 943 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 944 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 945 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 946 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 947 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 948 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 949 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 950 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 951 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 952 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 953 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 954 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 955 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 956 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 957 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 958 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 959 960 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 961 /* This bit must always be set on 965G/965GM */ 962 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 963 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 964 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 965 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 966 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 967 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 968 /* This bit must always be set on 965G */ 969 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 970 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 971 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 972 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 973 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 974 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 975 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 976 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 977 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 978 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 979 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 980 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 981 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 982 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 983 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 984 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 985 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 986 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 987 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 988 989 #define RENCLK_GATE_D2 _MMIO(0x6208) 990 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 991 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 992 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 993 994 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ 995 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 996 997 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ 998 #define DEUC _MMIO(0x6214) /* CRL only */ 999 1000 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) 1001 #define FW_CSPWRDWNEN (1 << 15) 1002 1003 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) 1004 1005 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) 1006 #define CDCLK_FREQ_SHIFT 4 1007 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 1008 #define CZCLK_FREQ_MASK 0xf 1009 1010 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) 1011 #define PFI_CREDIT_63 (9 << 28) /* chv only */ 1012 #define PFI_CREDIT_31 (8 << 28) /* chv only */ 1013 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ 1014 #define PFI_CREDIT_RESEND (1 << 27) 1015 #define VGA_FAST_MODE_DISABLE (1 << 14) 1016 1017 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) 1018 1019 #define PEG_BAND_GAP_DATA _MMIO(0x14d68) 1020 1021 #define BXT_RP_STATE_CAP _MMIO(0x138170) 1022 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148) 1023 1024 #define MTL_RP_STATE_CAP _MMIO(0x138000) 1025 #define MTL_MEDIAP_STATE_CAP _MMIO(0x138020) 1026 #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0) 1027 #define MTL_RPN_CAP_MASK REG_GENMASK(24, 16) 1028 1029 #define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c) 1030 #define MTL_MPE_FREQUENCY _MMIO(0x13802c) 1031 #define MTL_RPE_MASK REG_GENMASK(8, 0) 1032 1033 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8) 1034 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 1035 #define PROCHOT_MASK REG_BIT(0) 1036 #define THERMAL_LIMIT_MASK REG_BIT(1) 1037 #define RATL_MASK REG_BIT(5) 1038 #define VR_THERMALERT_MASK REG_BIT(6) 1039 #define VR_TDC_MASK REG_BIT(7) 1040 #define POWER_LIMIT_4_MASK REG_BIT(8) 1041 #define POWER_LIMIT_1_MASK REG_BIT(10) 1042 #define POWER_LIMIT_2_MASK REG_BIT(11) 1043 #define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16) 1044 #define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030) 1045 1046 #define CHV_CLK_CTL1 _MMIO(0x101100) 1047 #define VLV_CLK_CTL2 _MMIO(0x101104) 1048 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 1049 1050 /* 1051 * Overlay regs 1052 */ 1053 1054 #define OVADD _MMIO(0x30000) 1055 #define DOVSTA _MMIO(0x30008) 1056 #define OC_BUF (0x3 << 20) 1057 #define OGAMC5 _MMIO(0x30010) 1058 #define OGAMC4 _MMIO(0x30014) 1059 #define OGAMC3 _MMIO(0x30018) 1060 #define OGAMC2 _MMIO(0x3001c) 1061 #define OGAMC1 _MMIO(0x30020) 1062 #define OGAMC0 _MMIO(0x30024) 1063 1064 /* 1065 * GEN9 clock gating regs 1066 */ 1067 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) 1068 #define DARBF_GATING_DIS REG_BIT(27) 1069 #define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15) 1070 #define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14) 1071 #define PWM2_GATING_DIS REG_BIT(14) 1072 #define PWM1_GATING_DIS REG_BIT(13) 1073 1074 #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) 1075 #define TGL_VRH_GATING_DIS REG_BIT(31) 1076 #define DPT_GATING_DIS REG_BIT(22) 1077 1078 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) 1079 #define BXT_GMBUS_GATING_DIS (1 << 14) 1080 1081 #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540) 1082 #define DPCE_GATING_DIS REG_BIT(17) 1083 1084 #define _CLKGATE_DIS_PSL_A 0x46520 1085 #define _CLKGATE_DIS_PSL_B 0x46524 1086 #define _CLKGATE_DIS_PSL_C 0x46528 1087 #define DUPS1_GATING_DIS (1 << 15) 1088 #define DUPS2_GATING_DIS (1 << 19) 1089 #define DUPS3_GATING_DIS (1 << 23) 1090 #define CURSOR_GATING_DIS REG_BIT(28) 1091 #define DPF_GATING_DIS (1 << 10) 1092 #define DPF_RAM_GATING_DIS (1 << 9) 1093 #define DPFR_GATING_DIS (1 << 8) 1094 1095 #define CLKGATE_DIS_PSL(pipe) \ 1096 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) 1097 1098 #define _CLKGATE_DIS_PSL_EXT_A 0x4654C 1099 #define _CLKGATE_DIS_PSL_EXT_B 0x46550 1100 #define PIPEDMC_GATING_DIS REG_BIT(12) 1101 1102 #define CLKGATE_DIS_PSL_EXT(pipe) \ 1103 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B) 1104 1105 /* 1106 * Display engine regs 1107 */ 1108 1109 /* Pipe/transcoder A timing regs */ 1110 #define _TRANS_HTOTAL_A 0x60000 1111 #define _TRANS_HTOTAL_B 0x61000 1112 #define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A) 1113 #define HTOTAL_MASK REG_GENMASK(31, 16) 1114 #define HTOTAL(htotal) REG_FIELD_PREP(HTOTAL_MASK, (htotal)) 1115 #define HACTIVE_MASK REG_GENMASK(15, 0) 1116 #define HACTIVE(hdisplay) REG_FIELD_PREP(HACTIVE_MASK, (hdisplay)) 1117 1118 #define _TRANS_HBLANK_A 0x60004 1119 #define _TRANS_HBLANK_B 0x61004 1120 #define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A) 1121 #define HBLANK_END_MASK REG_GENMASK(31, 16) 1122 #define HBLANK_END(hblank_end) REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end)) 1123 #define HBLANK_START_MASK REG_GENMASK(15, 0) 1124 #define HBLANK_START(hblank_start) REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start)) 1125 1126 #define _TRANS_HSYNC_A 0x60008 1127 #define _TRANS_HSYNC_B 0x61008 1128 #define TRANS_HSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A) 1129 #define HSYNC_END_MASK REG_GENMASK(31, 16) 1130 #define HSYNC_END(hsync_end) REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end)) 1131 #define HSYNC_START_MASK REG_GENMASK(15, 0) 1132 #define HSYNC_START(hsync_start) REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start)) 1133 1134 #define _TRANS_VTOTAL_A 0x6000c 1135 #define _TRANS_VTOTAL_B 0x6100c 1136 #define TRANS_VTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A) 1137 #define VTOTAL_MASK REG_GENMASK(31, 16) 1138 #define VTOTAL(vtotal) REG_FIELD_PREP(VTOTAL_MASK, (vtotal)) 1139 #define VACTIVE_MASK REG_GENMASK(15, 0) 1140 #define VACTIVE(vdisplay) REG_FIELD_PREP(VACTIVE_MASK, (vdisplay)) 1141 1142 #define _TRANS_VBLANK_A 0x60010 1143 #define _TRANS_VBLANK_B 0x61010 1144 #define TRANS_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A) 1145 #define VBLANK_END_MASK REG_GENMASK(31, 16) 1146 #define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end)) 1147 #define VBLANK_START_MASK REG_GENMASK(15, 0) 1148 #define VBLANK_START(vblank_start) REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start)) 1149 1150 #define _TRANS_VSYNC_A 0x60014 1151 #define _TRANS_VSYNC_B 0x61014 1152 #define TRANS_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A) 1153 #define VSYNC_END_MASK REG_GENMASK(31, 16) 1154 #define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end)) 1155 #define VSYNC_START_MASK REG_GENMASK(15, 0) 1156 #define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start)) 1157 1158 #define _PIPEASRC 0x6001c 1159 #define _PIPEBSRC 0x6101c 1160 #define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC) 1161 #define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16) 1162 #define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w)) 1163 #define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0) 1164 #define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h)) 1165 1166 #define _BCLRPAT_A 0x60020 1167 #define _BCLRPAT_B 0x61020 1168 #define BCLRPAT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A) 1169 1170 #define _TRANS_VSYNCSHIFT_A 0x60028 1171 #define _TRANS_VSYNCSHIFT_B 0x61028 1172 #define TRANS_VSYNCSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A) 1173 1174 #define _TRANS_MULT_A 0x6002c 1175 #define _TRANS_MULT_B 0x6102c 1176 #define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A) 1177 1178 /* Hotplug control (945+ only) */ 1179 #define PORT_HOTPLUG_EN(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) 1180 #define PORTB_HOTPLUG_INT_EN (1 << 29) 1181 #define PORTC_HOTPLUG_INT_EN (1 << 28) 1182 #define PORTD_HOTPLUG_INT_EN (1 << 27) 1183 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 1184 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 1185 #define TV_HOTPLUG_INT_EN (1 << 18) 1186 #define CRT_HOTPLUG_INT_EN (1 << 9) 1187 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 1188 PORTC_HOTPLUG_INT_EN | \ 1189 PORTD_HOTPLUG_INT_EN | \ 1190 SDVOC_HOTPLUG_INT_EN | \ 1191 SDVOB_HOTPLUG_INT_EN | \ 1192 CRT_HOTPLUG_INT_EN) 1193 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 1194 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 1195 /* must use period 64 on GM45 according to docs */ 1196 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 1197 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 1198 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 1199 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 1200 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 1201 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 1202 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 1203 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 1204 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 1205 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 1206 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 1207 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 1208 1209 #define PORT_HOTPLUG_STAT(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) 1210 /* HDMI/DP bits are g4x+ */ 1211 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 1212 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 1213 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 1214 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 1215 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 1216 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 1217 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 1218 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 1219 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 1220 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 1221 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 1222 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 1223 /* CRT/TV common between gen3+ */ 1224 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 1225 #define TV_HOTPLUG_INT_STATUS (1 << 10) 1226 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 1227 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 1228 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 1229 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 1230 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 1231 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 1232 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 1233 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 1234 1235 /* SDVO is different across gen3/4 */ 1236 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 1237 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 1238 /* 1239 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 1240 * since reality corrobates that they're the same as on gen3. But keep these 1241 * bits here (and the comment!) to help any other lost wanderers back onto the 1242 * right tracks. 1243 */ 1244 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 1245 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 1246 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 1247 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 1248 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 1249 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 1250 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 1251 PORTB_HOTPLUG_INT_STATUS | \ 1252 PORTC_HOTPLUG_INT_STATUS | \ 1253 PORTD_HOTPLUG_INT_STATUS) 1254 1255 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 1256 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 1257 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 1258 PORTB_HOTPLUG_INT_STATUS | \ 1259 PORTC_HOTPLUG_INT_STATUS | \ 1260 PORTD_HOTPLUG_INT_STATUS) 1261 1262 /* SDVO and HDMI port control. 1263 * The same register may be used for SDVO or HDMI */ 1264 #define _GEN3_SDVOB 0x61140 1265 #define _GEN3_SDVOC 0x61160 1266 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) 1267 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) 1268 #define GEN4_HDMIB GEN3_SDVOB 1269 #define GEN4_HDMIC GEN3_SDVOC 1270 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) 1271 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) 1272 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) 1273 #define PCH_SDVOB _MMIO(0xe1140) 1274 #define PCH_HDMIB PCH_SDVOB 1275 #define PCH_HDMIC _MMIO(0xe1150) 1276 #define PCH_HDMID _MMIO(0xe1160) 1277 1278 #define PORT_DFT_I9XX _MMIO(0x61150) 1279 #define DC_BALANCE_RESET (1 << 25) 1280 #define PORT_DFT2_G4X(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) 1281 #define DC_BALANCE_RESET_VLV (1 << 31) 1282 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) 1283 #define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */ 1284 #define PIPE_B_SCRAMBLE_RESET REG_BIT(1) 1285 #define PIPE_A_SCRAMBLE_RESET REG_BIT(0) 1286 1287 /* Gen 3 SDVO bits: */ 1288 #define SDVO_ENABLE (1 << 31) 1289 #define SDVO_PIPE_SEL_SHIFT 30 1290 #define SDVO_PIPE_SEL_MASK (1 << 30) 1291 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 1292 #define SDVO_STALL_SELECT (1 << 29) 1293 #define SDVO_INTERRUPT_ENABLE (1 << 26) 1294 /* 1295 * 915G/GM SDVO pixel multiplier. 1296 * Programmed value is multiplier - 1, up to 5x. 1297 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 1298 */ 1299 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 1300 #define SDVO_PORT_MULTIPLY_SHIFT 23 1301 #define SDVO_PHASE_SELECT_MASK (15 << 19) 1302 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 1303 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 1304 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 1305 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 1306 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 1307 #define SDVO_DETECTED (1 << 2) 1308 /* Bits to be preserved when writing */ 1309 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 1310 SDVO_INTERRUPT_ENABLE) 1311 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 1312 1313 /* Gen 4 SDVO/HDMI bits: */ 1314 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 1315 #define SDVO_COLOR_FORMAT_MASK (7 << 26) 1316 #define SDVO_ENCODING_SDVO (0 << 10) 1317 #define SDVO_ENCODING_HDMI (2 << 10) 1318 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 1319 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 1320 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 1321 #define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */ 1322 /* VSYNC/HSYNC bits new with 965, default is to be set */ 1323 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 1324 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 1325 1326 /* Gen 5 (IBX) SDVO/HDMI bits: */ 1327 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 1328 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 1329 1330 /* Gen 6 (CPT) SDVO/HDMI bits: */ 1331 #define SDVO_PIPE_SEL_SHIFT_CPT 29 1332 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 1333 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 1334 1335 /* CHV SDVO/HDMI bits: */ 1336 #define SDVO_PIPE_SEL_SHIFT_CHV 24 1337 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 1338 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 1339 1340 /* Video Data Island Packet control */ 1341 #define VIDEO_DIP_DATA _MMIO(0x61178) 1342 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC 1343 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 1344 * of the infoframe structure specified by CEA-861. */ 1345 #define VIDEO_DIP_DATA_SIZE 32 1346 #define VIDEO_DIP_ASYNC_DATA_SIZE 36 1347 #define VIDEO_DIP_GMP_DATA_SIZE 36 1348 #define VIDEO_DIP_VSC_DATA_SIZE 36 1349 #define VIDEO_DIP_PPS_DATA_SIZE 132 1350 #define VIDEO_DIP_CTL _MMIO(0x61170) 1351 /* Pre HSW: */ 1352 #define VIDEO_DIP_ENABLE (1 << 31) 1353 #define VIDEO_DIP_PORT(port) ((port) << 29) 1354 #define VIDEO_DIP_PORT_MASK (3 << 29) 1355 #define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */ 1356 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 1357 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 1358 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */ 1359 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 1360 #define VIDEO_DIP_SELECT_AVI (0 << 19) 1361 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 1362 #define VIDEO_DIP_SELECT_GAMUT (2 << 19) 1363 #define VIDEO_DIP_SELECT_SPD (3 << 19) 1364 #define VIDEO_DIP_SELECT_MASK (3 << 19) 1365 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 1366 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 1367 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 1368 #define VIDEO_DIP_FREQ_MASK (3 << 16) 1369 /* HSW and later: */ 1370 #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28) 1371 #define PSR_VSC_BIT_7_SET (1 << 27) 1372 #define VSC_SELECT_MASK (0x3 << 25) 1373 #define VSC_SELECT_SHIFT 25 1374 #define VSC_DIP_HW_HEA_DATA (0 << 25) 1375 #define VSC_DIP_HW_HEA_SW_DATA (1 << 25) 1376 #define VSC_DIP_HW_DATA_SW_HEA (2 << 25) 1377 #define VSC_DIP_SW_HEA_DATA (3 << 25) 1378 #define VDIP_ENABLE_PPS (1 << 24) 1379 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 1380 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 1381 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 1382 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 1383 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 1384 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 1385 /* ADL and later: */ 1386 #define VIDEO_DIP_ENABLE_AS_ADL REG_BIT(23) 1387 1388 #define PCH_GTC_CTL _MMIO(0xe7000) 1389 #define PCH_GTC_ENABLE (1 << 31) 1390 1391 /* Display Port */ 1392 #define DP_A _MMIO(0x64000) /* eDP */ 1393 #define DP_B _MMIO(0x64100) 1394 #define DP_C _MMIO(0x64200) 1395 #define DP_D _MMIO(0x64300) 1396 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) 1397 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) 1398 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) 1399 #define DP_PORT_EN (1 << 31) 1400 #define DP_PIPE_SEL_SHIFT 30 1401 #define DP_PIPE_SEL_MASK (1 << 30) 1402 #define DP_PIPE_SEL(pipe) ((pipe) << 30) 1403 #define DP_PIPE_SEL_SHIFT_IVB 29 1404 #define DP_PIPE_SEL_MASK_IVB (3 << 29) 1405 #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29) 1406 #define DP_PIPE_SEL_SHIFT_CHV 16 1407 #define DP_PIPE_SEL_MASK_CHV (3 << 16) 1408 #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16) 1409 1410 /* Link training mode - select a suitable mode for each stage */ 1411 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 1412 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 1413 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 1414 #define DP_LINK_TRAIN_OFF (3 << 28) 1415 #define DP_LINK_TRAIN_MASK (3 << 28) 1416 #define DP_LINK_TRAIN_SHIFT 28 1417 1418 /* CPT Link training mode */ 1419 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 1420 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 1421 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 1422 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 1423 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 1424 #define DP_LINK_TRAIN_SHIFT_CPT 8 1425 1426 /* Signal voltages. These are mostly controlled by the other end */ 1427 #define DP_VOLTAGE_0_4 (0 << 25) 1428 #define DP_VOLTAGE_0_6 (1 << 25) 1429 #define DP_VOLTAGE_0_8 (2 << 25) 1430 #define DP_VOLTAGE_1_2 (3 << 25) 1431 #define DP_VOLTAGE_MASK (7 << 25) 1432 #define DP_VOLTAGE_SHIFT 25 1433 1434 /* Signal pre-emphasis levels, like voltages, the other end tells us what 1435 * they want 1436 */ 1437 #define DP_PRE_EMPHASIS_0 (0 << 22) 1438 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 1439 #define DP_PRE_EMPHASIS_6 (2 << 22) 1440 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 1441 #define DP_PRE_EMPHASIS_MASK (7 << 22) 1442 #define DP_PRE_EMPHASIS_SHIFT 22 1443 1444 /* How many wires to use. I guess 3 was too hard */ 1445 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 1446 #define DP_PORT_WIDTH_MASK (7 << 19) 1447 #define DP_PORT_WIDTH_SHIFT 19 1448 1449 /* Mystic DPCD version 1.1 special mode */ 1450 #define DP_ENHANCED_FRAMING (1 << 18) 1451 1452 /* eDP */ 1453 #define DP_PLL_FREQ_270MHZ (0 << 16) 1454 #define DP_PLL_FREQ_162MHZ (1 << 16) 1455 #define DP_PLL_FREQ_MASK (3 << 16) 1456 1457 /* locked once port is enabled */ 1458 #define DP_PORT_REVERSAL (1 << 15) 1459 1460 /* eDP */ 1461 #define DP_PLL_ENABLE (1 << 14) 1462 1463 /* sends the clock on lane 15 of the PEG for debug */ 1464 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 1465 1466 #define DP_SCRAMBLING_DISABLE (1 << 12) 1467 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 1468 1469 /* limit RGB values to avoid confusing TVs */ 1470 #define DP_COLOR_RANGE_16_235 (1 << 8) 1471 1472 /* Turn on the audio link */ 1473 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 1474 1475 /* vs and hs sync polarity */ 1476 #define DP_SYNC_VS_HIGH (1 << 4) 1477 #define DP_SYNC_HS_HIGH (1 << 3) 1478 1479 /* A fantasy */ 1480 #define DP_DETECTED (1 << 2) 1481 1482 /* 1483 * Computing GMCH M and N values for the Display Port link 1484 * 1485 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 1486 * 1487 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 1488 * 1489 * The GMCH value is used internally 1490 * 1491 * bytes_per_pixel is the number of bytes coming out of the plane, 1492 * which is after the LUTs, so we want the bytes for our color format. 1493 * For our current usage, this is always 3, one byte for R, G and B. 1494 */ 1495 #define _PIPEA_DATA_M_G4X 0x70050 1496 #define _PIPEB_DATA_M_G4X 0x71050 1497 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 1498 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 1499 #define TU_SIZE_MASK REG_GENMASK(30, 25) 1500 #define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */ 1501 #define DATA_LINK_M_N_MASK REG_GENMASK(23, 0) 1502 #define DATA_LINK_N_MAX (0x800000) 1503 1504 #define _PIPEA_DATA_N_G4X 0x70054 1505 #define _PIPEB_DATA_N_G4X 0x71054 1506 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 1507 1508 /* 1509 * Computing Link M and N values for the Display Port link 1510 * 1511 * Link M / N = pixel_clock / ls_clk 1512 * 1513 * (the DP spec calls pixel_clock the 'strm_clk') 1514 * 1515 * The Link value is transmitted in the Main Stream 1516 * Attributes and VB-ID. 1517 */ 1518 #define _PIPEA_LINK_M_G4X 0x70060 1519 #define _PIPEB_LINK_M_G4X 0x71060 1520 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 1521 1522 #define _PIPEA_LINK_N_G4X 0x70064 1523 #define _PIPEB_LINK_N_G4X 0x71064 1524 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 1525 1526 /* Pipe A */ 1527 #define _PIPEADSL 0x70000 1528 #define PIPEDSL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEADSL) 1529 #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */ 1530 #define PIPEDSL_LINE_MASK REG_GENMASK(19, 0) 1531 1532 #define _TRANSACONF 0x70008 1533 #define TRANSCONF(dev_priv, trans) _MMIO_PIPE2(dev_priv, (trans), _TRANSACONF) 1534 #define TRANSCONF_ENABLE REG_BIT(31) 1535 #define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */ 1536 #define TRANSCONF_STATE_ENABLE REG_BIT(30) /* i965+ */ 1537 #define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */ 1538 #define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */ 1539 #define TRANSCONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */ 1540 #define TRANSCONF_PIPE_LOCKED REG_BIT(25) 1541 #define TRANSCONF_FORCE_BORDER REG_BIT(25) 1542 #define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */ 1543 #define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */ 1544 #define TRANSCONF_GAMMA_MODE_8BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0) 1545 #define TRANSCONF_GAMMA_MODE_10BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 1) 1546 #define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */ 1547 #define TRANSCONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */ 1548 #define TRANSCONF_GAMMA_MODE(x) REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */ 1549 #define TRANSCONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */ 1550 #define TRANSCONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0) 1551 #define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */ 1552 #define TRANSCONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */ 1553 #define TRANSCONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 6) 1554 #define TRANSCONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */ 1555 /* 1556 * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display, 1557 * DBL=power saving pixel doubling, PF-ID* requires panel fitter 1558 */ 1559 #define TRANSCONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */ 1560 #define TRANSCONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */ 1561 #define TRANSCONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0) 1562 #define TRANSCONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 1) 1563 #define TRANSCONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 3) 1564 #define TRANSCONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */ 1565 #define TRANSCONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */ 1566 #define TRANSCONF_REFRESH_RATE_ALT_ILK REG_BIT(20) 1567 #define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */ 1568 #define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x)) 1569 #define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16) 1570 #define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv only */ 1571 #define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14) 1572 #define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13) 1573 #define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */ 1574 #define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */ 1575 #define TRANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */ 1576 #define TRANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */ 1577 #define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */ 1578 #define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */ 1579 #define TRANSCONF_BPC_8 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0) 1580 #define TRANSCONF_BPC_10 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 1) 1581 #define TRANSCONF_BPC_6 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 2) 1582 #define TRANSCONF_BPC_12 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 3) 1583 #define TRANSCONF_DITHER_EN REG_BIT(4) 1584 #define TRANSCONF_DITHER_TYPE_MASK REG_GENMASK(3, 2) 1585 #define TRANSCONF_DITHER_TYPE_SP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0) 1586 #define TRANSCONF_DITHER_TYPE_ST1 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1) 1587 #define TRANSCONF_DITHER_TYPE_ST2 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2) 1588 #define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3) 1589 #define TRANSCONF_PIXEL_COUNT_SCALING_MASK REG_GENMASK(1, 0) 1590 #define TRANSCONF_PIXEL_COUNT_SCALING_X4 1 1591 1592 #define _PIPEASTAT 0x70024 1593 #define PIPESTAT(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT) 1594 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) 1595 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) 1596 #define PIPE_CRC_ERROR_ENABLE (1UL << 29) 1597 #define PIPE_CRC_DONE_ENABLE (1UL << 28) 1598 #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) 1599 #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) 1600 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) 1601 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) 1602 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) 1603 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) 1604 #define PIPE_DPST_EVENT_ENABLE (1UL << 23) 1605 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) 1606 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) 1607 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) 1608 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20) 1609 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19) 1610 #define PERF_COUNTER_INTERRUPT_EN (1UL << 19) 1611 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */ 1612 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */ 1613 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17) 1614 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) 1615 #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16) 1616 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16) 1617 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15) 1618 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14) 1619 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13) 1620 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12) 1621 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11) 1622 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11) 1623 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10) 1624 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) 1625 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) 1626 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) 1627 #define PIPE_DPST_EVENT_STATUS (1UL << 7) 1628 #define PIPE_A_PSR_STATUS_VLV (1UL << 6) 1629 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) 1630 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) 1631 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4) 1632 #define PIPE_B_PSR_STATUS_VLV (1UL << 3) 1633 #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3) 1634 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */ 1635 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */ 1636 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1) 1637 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) 1638 #define PIPE_HBLANK_INT_STATUS (1UL << 0) 1639 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0) 1640 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 1641 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff 1642 1643 #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */ 1644 #define PIPE_ARB_CTL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A) 1645 #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13) 1646 1647 #define _PIPE_MISC_A 0x70030 1648 #define _PIPE_MISC_B 0x71030 1649 #define PIPE_MISC(pipe) _MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B) 1650 #define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */ 1651 #define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */ 1652 #define PIPE_MISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */ 1653 #define PIPE_MISC_PSR_MASK_PRIMARY_FLIP REG_BIT(23) /* bdw */ 1654 #define PIPE_MISC_PSR_MASK_SPRITE_ENABLE REG_BIT(22) /* bdw */ 1655 #define PIPE_MISC_PSR_MASK_PIPE_REG_WRITE REG_BIT(21) /* skl+ */ 1656 #define PIPE_MISC_PSR_MASK_CURSOR_MOVE REG_BIT(21) /* bdw */ 1657 #define PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT REG_BIT(20) 1658 #define PIPE_MISC_OUTPUT_COLORSPACE_YUV REG_BIT(11) 1659 #define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ 1660 /* 1661 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with 1662 * valid values of: 6, 8, 10 BPC. 1663 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of: 1664 * 6, 8, 10, 12 BPC. 1665 */ 1666 #define PIPE_MISC_BPC_MASK REG_GENMASK(7, 5) 1667 #define PIPE_MISC_BPC_8 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0) 1668 #define PIPE_MISC_BPC_10 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 1) 1669 #define PIPE_MISC_BPC_6 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 2) 1670 #define PIPE_MISC_BPC_12_ADLP REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 4) /* adlp+ */ 1671 #define PIPE_MISC_DITHER_ENABLE REG_BIT(4) 1672 #define PIPE_MISC_DITHER_TYPE_MASK REG_GENMASK(3, 2) 1673 #define PIPE_MISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0) 1674 #define PIPE_MISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 1) 1675 #define PIPE_MISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 2) 1676 #define PIPE_MISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 3) 1677 1678 #define _PIPE_MISC2_A 0x7002C 1679 #define _PIPE_MISC2_B 0x7102C 1680 #define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B) 1681 #define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24) 1682 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80) 1683 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20) 1684 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */ 1685 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id)) 1686 1687 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) 1688 #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29) 1689 #define PIPEB_HLINE_INT_EN REG_BIT(28) 1690 #define PIPEB_VBLANK_INT_EN REG_BIT(27) 1691 #define SPRITED_FLIP_DONE_INT_EN REG_BIT(26) 1692 #define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25) 1693 #define PLANEB_FLIP_DONE_INT_EN REG_BIT(24) 1694 #define PIPE_PSR_INT_EN REG_BIT(22) 1695 #define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21) 1696 #define PIPEA_HLINE_INT_EN REG_BIT(20) 1697 #define PIPEA_VBLANK_INT_EN REG_BIT(19) 1698 #define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18) 1699 #define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17) 1700 #define PLANEA_FLIPDONE_INT_EN REG_BIT(16) 1701 #define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13) 1702 #define PIPEC_HLINE_INT_EN REG_BIT(12) 1703 #define PIPEC_VBLANK_INT_EN REG_BIT(11) 1704 #define SPRITEF_FLIPDONE_INT_EN REG_BIT(10) 1705 #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9) 1706 #define PLANEC_FLIPDONE_INT_EN REG_BIT(8) 1707 1708 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 1709 #define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16) 1710 #define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16) 1711 #define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27) 1712 #define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26) 1713 #define PLANEC_INVALID_GTT_INT_EN REG_BIT(25) 1714 #define CURSORC_INVALID_GTT_INT_EN REG_BIT(24) 1715 #define CURSORB_INVALID_GTT_INT_EN REG_BIT(23) 1716 #define CURSORA_INVALID_GTT_INT_EN REG_BIT(22) 1717 #define SPRITED_INVALID_GTT_INT_EN REG_BIT(21) 1718 #define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20) 1719 #define PLANEB_INVALID_GTT_INT_EN REG_BIT(19) 1720 #define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18) 1721 #define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17) 1722 #define PLANEA_INVALID_GTT_INT_EN REG_BIT(16) 1723 #define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0) 1724 #define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0) 1725 #define SPRITEF_INVALID_GTT_STATUS REG_BIT(11) 1726 #define SPRITEE_INVALID_GTT_STATUS REG_BIT(10) 1727 #define PLANEC_INVALID_GTT_STATUS REG_BIT(9) 1728 #define CURSORC_INVALID_GTT_STATUS REG_BIT(8) 1729 #define CURSORB_INVALID_GTT_STATUS REG_BIT(7) 1730 #define CURSORA_INVALID_GTT_STATUS REG_BIT(6) 1731 #define SPRITED_INVALID_GTT_STATUS REG_BIT(5) 1732 #define SPRITEC_INVALID_GTT_STATUS REG_BIT(4) 1733 #define PLANEB_INVALID_GTT_STATUS REG_BIT(3) 1734 #define SPRITEB_INVALID_GTT_STATUS REG_BIT(2) 1735 #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1) 1736 #define PLANEA_INVALID_GTT_STATUS REG_BIT(0) 1737 1738 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) 1739 #define CBR_PND_DEADLINE_DISABLE (1 << 31) 1740 #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30) 1741 1742 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) 1743 #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */ 1744 1745 /* 1746 * The two pipe frame counter registers are not synchronized, so 1747 * reading a stable value is somewhat tricky. The following code 1748 * should work: 1749 * 1750 * do { 1751 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 1752 * PIPE_FRAME_HIGH_SHIFT; 1753 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 1754 * PIPE_FRAME_LOW_SHIFT); 1755 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 1756 * PIPE_FRAME_HIGH_SHIFT); 1757 * } while (high1 != high2); 1758 * frame = (high1 << 8) | low1; 1759 */ 1760 #define _PIPEAFRAMEHIGH 0x70040 1761 #define PIPEFRAME(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH) 1762 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 1763 #define PIPE_FRAME_HIGH_SHIFT 0 1764 1765 #define _PIPEAFRAMEPIXEL 0x70044 1766 #define PIPEFRAMEPIXEL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL) 1767 #define PIPE_FRAME_LOW_MASK 0xff000000 1768 #define PIPE_FRAME_LOW_SHIFT 24 1769 #define PIPE_PIXEL_MASK 0x00ffffff 1770 #define PIPE_PIXEL_SHIFT 0 1771 1772 /* GM45+ just has to be different */ 1773 #define _PIPEA_FRMCOUNT_G4X 0x70040 1774 #define PIPE_FRMCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X) 1775 1776 #define _PIPEA_FLIPCOUNT_G4X 0x70044 1777 #define PIPE_FLIPCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X) 1778 1779 /* CHV pipe B blender */ 1780 #define _CHV_BLEND_A 0x60a00 1781 #define CHV_BLEND(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A) 1782 #define CHV_BLEND_MASK REG_GENMASK(31, 30) 1783 #define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0) 1784 #define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1) 1785 #define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2) 1786 1787 #define _CHV_CANVAS_A 0x60a04 1788 #define CHV_CANVAS(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A) 1789 #define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20) 1790 #define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10) 1791 #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0) 1792 1793 /* Display/Sprite base address macros */ 1794 #define DISP_BASEADDR_MASK (0xfffff000) 1795 #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK) 1796 #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK) 1797 1798 /* 1799 * VBIOS flags 1800 * gen2: 1801 * [00:06] alm,mgm 1802 * [10:16] all 1803 * [30:32] alm,mgm 1804 * gen3+: 1805 * [00:0f] all 1806 * [10:1f] all 1807 * [30:32] all 1808 */ 1809 #define SWF0(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) 1810 #define SWF1(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) 1811 #define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) 1812 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) 1813 1814 /* VBIOS regs */ 1815 #define VGACNTRL _MMIO(0x71400) 1816 # define VGA_DISP_DISABLE (1 << 31) 1817 # define VGA_2X_MODE (1 << 30) 1818 # define VGA_PIPE_B_SELECT (1 << 29) 1819 1820 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) 1821 1822 /* Ironlake */ 1823 1824 #define CPU_VGACNTRL _MMIO(0x41000) 1825 1826 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) 1827 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 1828 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ 1829 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ 1830 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ 1831 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ 1832 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ 1833 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) 1834 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) 1835 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) 1836 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) 1837 1838 /* refresh rate hardware control */ 1839 #define RR_HW_CTL _MMIO(0x45300) 1840 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 1841 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 1842 1843 #define PCH_3DCGDIS0 _MMIO(0x46020) 1844 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 1845 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 1846 1847 #define PCH_3DCGDIS1 _MMIO(0x46024) 1848 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 1849 1850 #define _PIPEA_DATA_M1 0x60030 1851 #define _PIPEB_DATA_M1 0x61030 1852 #define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1) 1853 1854 #define _PIPEA_DATA_N1 0x60034 1855 #define _PIPEB_DATA_N1 0x61034 1856 #define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1) 1857 1858 #define _PIPEA_DATA_M2 0x60038 1859 #define _PIPEB_DATA_M2 0x61038 1860 #define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2) 1861 1862 #define _PIPEA_DATA_N2 0x6003c 1863 #define _PIPEB_DATA_N2 0x6103c 1864 #define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2) 1865 1866 #define _PIPEA_LINK_M1 0x60040 1867 #define _PIPEB_LINK_M1 0x61040 1868 #define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1) 1869 1870 #define _PIPEA_LINK_N1 0x60044 1871 #define _PIPEB_LINK_N1 0x61044 1872 #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1) 1873 1874 #define _PIPEA_LINK_M2 0x60048 1875 #define _PIPEB_LINK_M2 0x61048 1876 #define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2) 1877 1878 #define _PIPEA_LINK_N2 0x6004c 1879 #define _PIPEB_LINK_N2 0x6104c 1880 #define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2) 1881 1882 /* 1883 * Skylake scalers 1884 */ 1885 #define _ID(id, a, b) _PICK_EVEN(id, a, b) 1886 #define _PS_1A_CTRL 0x68180 1887 #define _PS_2A_CTRL 0x68280 1888 #define _PS_1B_CTRL 0x68980 1889 #define _PS_2B_CTRL 0x68A80 1890 #define _PS_1C_CTRL 0x69180 1891 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ 1892 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ 1893 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) 1894 #define PS_SCALER_EN REG_BIT(31) 1895 #define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */ 1896 #define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0) 1897 #define PS_SCALER_TYPE_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1) 1898 #define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */ 1899 #define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0) 1900 #define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1) 1901 #define SKL_PS_SCALER_MODE_NV12 REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 2) 1902 #define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */ 1903 #define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0) 1904 #define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1) 1905 #define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */ 1906 #define PS_BINDING_MASK REG_GENMASK(27, 25) 1907 #define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0) 1908 #define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1) 1909 #define PS_FILTER_MASK REG_GENMASK(24, 23) 1910 #define PS_FILTER_MEDIUM REG_FIELD_PREP(PS_FILTER_MASK, 0) 1911 #define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1) 1912 #define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2) 1913 #define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3) 1914 #define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */ 1915 #define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0) 1916 #define PS_ADAPTIVE_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1) 1917 #define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */ 1918 #define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */ 1919 #define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */ 1920 #define PS_VERT3TAP REG_BIT(21) /* skl/bxt */ 1921 #define PS_VERT_INT_INVERT_FIELD REG_BIT(20) 1922 #define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */ 1923 #define PS_PWRUP_PROGRESS REG_BIT(17) 1924 #define PS_V_FILTER_BYPASS REG_BIT(8) 1925 #define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */ 1926 #define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */ 1927 #define PS_VADAPT_MODE_LEAST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0) 1928 #define PS_VADAPT_MODE_MOD_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 1) 1929 #define PS_VADAPT_MODE_MOST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 3) 1930 #define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */ 1931 #define PS_BINDING_Y_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1) 1932 #define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */ 1933 #define PS_Y_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_VERT_FILTER_SELECT_MASK, (set)) 1934 #define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */ 1935 #define PS_Y_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_HORZ_FILTER_SELECT_MASK, (set)) 1936 #define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */ 1937 #define PS_UV_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_VERT_FILTER_SELECT_MASK, (set)) 1938 #define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */ 1939 #define PS_UV_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_HORZ_FILTER_SELECT_MASK, (set)) 1940 1941 #define _PS_PWR_GATE_1A 0x68160 1942 #define _PS_PWR_GATE_2A 0x68260 1943 #define _PS_PWR_GATE_1B 0x68960 1944 #define _PS_PWR_GATE_2B 0x68A60 1945 #define _PS_PWR_GATE_1C 0x69160 1946 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ 1947 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ 1948 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) 1949 #define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31) 1950 #define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3) 1951 #define PS_PWR_GATE_SETTLING_TIME_32 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0) 1952 #define PS_PWR_GATE_SETTLING_TIME_64 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 1) 1953 #define PS_PWR_GATE_SETTLING_TIME_96 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 2) 1954 #define PS_PWR_GATE_SETTLING_TIME_128 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 3) 1955 #define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0) 1956 #define PS_PWR_GATE_SLPEN_8 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0) 1957 #define PS_PWR_GATE_SLPEN_16 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 1) 1958 #define PS_PWR_GATE_SLPEN_24 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 2) 1959 #define PS_PWR_GATE_SLPEN_32 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 3) 1960 1961 #define _PS_WIN_POS_1A 0x68170 1962 #define _PS_WIN_POS_2A 0x68270 1963 #define _PS_WIN_POS_1B 0x68970 1964 #define _PS_WIN_POS_2B 0x68A70 1965 #define _PS_WIN_POS_1C 0x69170 1966 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ 1967 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ 1968 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) 1969 #define PS_WIN_XPOS_MASK REG_GENMASK(31, 16) 1970 #define PS_WIN_XPOS(x) REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x)) 1971 #define PS_WIN_YPOS_MASK REG_GENMASK(15, 0) 1972 #define PS_WIN_YPOS(y) REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y)) 1973 1974 #define _PS_WIN_SZ_1A 0x68174 1975 #define _PS_WIN_SZ_2A 0x68274 1976 #define _PS_WIN_SZ_1B 0x68974 1977 #define _PS_WIN_SZ_2B 0x68A74 1978 #define _PS_WIN_SZ_1C 0x69174 1979 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ 1980 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ 1981 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) 1982 #define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16) 1983 #define PS_WIN_XSIZE(w) REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w)) 1984 #define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0) 1985 #define PS_WIN_YSIZE(h) REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h)) 1986 1987 #define _PS_VSCALE_1A 0x68184 1988 #define _PS_VSCALE_2A 0x68284 1989 #define _PS_VSCALE_1B 0x68984 1990 #define _PS_VSCALE_2B 0x68A84 1991 #define _PS_VSCALE_1C 0x69184 1992 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ 1993 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ 1994 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) 1995 1996 #define _PS_HSCALE_1A 0x68190 1997 #define _PS_HSCALE_2A 0x68290 1998 #define _PS_HSCALE_1B 0x68990 1999 #define _PS_HSCALE_2B 0x68A90 2000 #define _PS_HSCALE_1C 0x69190 2001 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ 2002 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ 2003 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) 2004 2005 #define _PS_VPHASE_1A 0x68188 2006 #define _PS_VPHASE_2A 0x68288 2007 #define _PS_VPHASE_1B 0x68988 2008 #define _PS_VPHASE_2B 0x68A88 2009 #define _PS_VPHASE_1C 0x69188 2010 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ 2011 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ 2012 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) 2013 #define PS_Y_PHASE_MASK REG_GENMASK(31, 16) 2014 #define PS_Y_PHASE(x) REG_FIELD_PREP(PS_Y_PHASE_MASK, (x)) 2015 #define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0) 2016 #define PS_UV_RGB_PHASE(x) REG_FIELD_PREP(PS_UV_RGB_PHASE_MASK, (x)) 2017 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */ 2018 #define PS_PHASE_TRIP (1 << 0) 2019 2020 #define _PS_HPHASE_1A 0x68194 2021 #define _PS_HPHASE_2A 0x68294 2022 #define _PS_HPHASE_1B 0x68994 2023 #define _PS_HPHASE_2B 0x68A94 2024 #define _PS_HPHASE_1C 0x69194 2025 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ 2026 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ 2027 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) 2028 2029 #define _PS_ECC_STAT_1A 0x681D0 2030 #define _PS_ECC_STAT_2A 0x682D0 2031 #define _PS_ECC_STAT_1B 0x689D0 2032 #define _PS_ECC_STAT_2B 0x68AD0 2033 #define _PS_ECC_STAT_1C 0x691D0 2034 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ 2035 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ 2036 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) 2037 2038 #define _PS_COEF_SET0_INDEX_1A 0x68198 2039 #define _PS_COEF_SET0_INDEX_2A 0x68298 2040 #define _PS_COEF_SET0_INDEX_1B 0x68998 2041 #define _PS_COEF_SET0_INDEX_2B 0x68A98 2042 #define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 2043 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \ 2044 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8) 2045 #define PS_COEF_INDEX_AUTO_INC REG_BIT(10) 2046 2047 #define _PS_COEF_SET0_DATA_1A 0x6819C 2048 #define _PS_COEF_SET0_DATA_2A 0x6829C 2049 #define _PS_COEF_SET0_DATA_1B 0x6899C 2050 #define _PS_COEF_SET0_DATA_2B 0x68A9C 2051 #define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 2052 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \ 2053 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8) 2054 2055 /* Display Internal Timeout Register */ 2056 #define RM_TIMEOUT _MMIO(0x42060) 2057 #define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0) 2058 #define MMIO_TIMEOUT_US(us) ((us) << 0) 2059 2060 /* interrupts */ 2061 #define DE_MASTER_IRQ_CONTROL (1 << 31) 2062 #define DE_SPRITEB_FLIP_DONE (1 << 29) 2063 #define DE_SPRITEA_FLIP_DONE (1 << 28) 2064 #define DE_PLANEB_FLIP_DONE (1 << 27) 2065 #define DE_PLANEA_FLIP_DONE (1 << 26) 2066 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 2067 #define DE_PCU_EVENT (1 << 25) 2068 #define DE_GTT_FAULT (1 << 24) 2069 #define DE_POISON (1 << 23) 2070 #define DE_PERFORM_COUNTER (1 << 22) 2071 #define DE_PCH_EVENT (1 << 21) 2072 #define DE_AUX_CHANNEL_A (1 << 20) 2073 #define DE_DP_A_HOTPLUG (1 << 19) 2074 #define DE_GSE (1 << 18) 2075 #define DE_PIPEB_VBLANK (1 << 15) 2076 #define DE_PIPEB_EVEN_FIELD (1 << 14) 2077 #define DE_PIPEB_ODD_FIELD (1 << 13) 2078 #define DE_PIPEB_LINE_COMPARE (1 << 12) 2079 #define DE_PIPEB_VSYNC (1 << 11) 2080 #define DE_PIPEB_CRC_DONE (1 << 10) 2081 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 2082 #define DE_PIPEA_VBLANK (1 << 7) 2083 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe))) 2084 #define DE_PIPEA_EVEN_FIELD (1 << 6) 2085 #define DE_PIPEA_ODD_FIELD (1 << 5) 2086 #define DE_PIPEA_LINE_COMPARE (1 << 4) 2087 #define DE_PIPEA_VSYNC (1 << 3) 2088 #define DE_PIPEA_CRC_DONE (1 << 2) 2089 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe))) 2090 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 2091 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) 2092 2093 /* More Ivybridge lolz */ 2094 #define DE_ERR_INT_IVB (1 << 30) 2095 #define DE_GSE_IVB (1 << 29) 2096 #define DE_PCH_EVENT_IVB (1 << 28) 2097 #define DE_DP_A_HOTPLUG_IVB (1 << 27) 2098 #define DE_AUX_CHANNEL_A_IVB (1 << 26) 2099 #define DE_EDP_PSR_INT_HSW (1 << 19) 2100 #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14) 2101 #define DE_PLANEC_FLIP_DONE_IVB (1 << 13) 2102 #define DE_PIPEC_VBLANK_IVB (1 << 10) 2103 #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9) 2104 #define DE_PLANEB_FLIP_DONE_IVB (1 << 8) 2105 #define DE_PIPEB_VBLANK_IVB (1 << 5) 2106 #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4) 2107 #define DE_PLANEA_FLIP_DONE_IVB (1 << 3) 2108 #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane))) 2109 #define DE_PIPEA_VBLANK_IVB (1 << 0) 2110 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) 2111 2112 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 2113 #define MASTER_INTERRUPT_ENABLE (1 << 31) 2114 2115 #define DEISR _MMIO(0x44000) 2116 #define DEIMR _MMIO(0x44004) 2117 #define DEIIR _MMIO(0x44008) 2118 #define DEIER _MMIO(0x4400c) 2119 2120 #define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \ 2121 DEIER, \ 2122 DEIIR) 2123 2124 #define GTISR _MMIO(0x44010) 2125 #define GTIMR _MMIO(0x44014) 2126 #define GTIIR _MMIO(0x44018) 2127 #define GTIER _MMIO(0x4401c) 2128 2129 #define GT_IRQ_REGS I915_IRQ_REGS(GTIMR, \ 2130 GTIER, \ 2131 GTIIR) 2132 2133 #define GEN8_MASTER_IRQ _MMIO(0x44200) 2134 #define GEN8_MASTER_IRQ_CONTROL (1 << 31) 2135 #define GEN8_PCU_IRQ (1 << 30) 2136 #define GEN8_DE_PCH_IRQ (1 << 23) 2137 #define GEN8_DE_MISC_IRQ (1 << 22) 2138 #define GEN8_DE_PORT_IRQ (1 << 20) 2139 #define GEN8_DE_PIPE_C_IRQ (1 << 18) 2140 #define GEN8_DE_PIPE_B_IRQ (1 << 17) 2141 #define GEN8_DE_PIPE_A_IRQ (1 << 16) 2142 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) 2143 #define GEN8_GT_VECS_IRQ (1 << 6) 2144 #define GEN8_GT_GUC_IRQ (1 << 5) 2145 #define GEN8_GT_PM_IRQ (1 << 4) 2146 #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ 2147 #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ 2148 #define GEN8_GT_BCS_IRQ (1 << 1) 2149 #define GEN8_GT_RCS_IRQ (1 << 0) 2150 2151 #define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c) 2152 2153 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) 2154 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) 2155 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) 2156 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) 2157 2158 #define GEN8_GT_IRQ_REGS(which) I915_IRQ_REGS(GEN8_GT_IMR(which), \ 2159 GEN8_GT_IER(which), \ 2160 GEN8_GT_IIR(which)) 2161 2162 #define GEN8_RCS_IRQ_SHIFT 0 2163 #define GEN8_BCS_IRQ_SHIFT 16 2164 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */ 2165 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */ 2166 #define GEN8_VECS_IRQ_SHIFT 0 2167 #define GEN8_WD_IRQ_SHIFT 16 2168 2169 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) 2170 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) 2171 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) 2172 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) 2173 #define GEN8_PIPE_FIFO_UNDERRUN REG_BIT(31) 2174 #define GEN8_PIPE_CDCLK_CRC_ERROR REG_BIT(29) 2175 #define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28) 2176 #define GEN12_PIPEDMC_INTERRUPT REG_BIT(26) /* tgl+ */ 2177 #define GEN12_PIPEDMC_FAULT REG_BIT(25) /* tgl+ */ 2178 #define MTL_PIPEDMC_ATS_FAULT REG_BIT(24) /* mtl+ */ 2179 #define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */ 2180 #define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */ 2181 #define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */ 2182 #define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */ 2183 #define MTL_PLANE_ATS_FAULT REG_BIT(18) /* mtl+ */ 2184 #define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */ 2185 #define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */ 2186 #define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */ 2187 #define GEN12_DSB_2_INT REG_BIT(15) /* tgl+ */ 2188 #define GEN12_DSB_1_INT REG_BIT(14) /* tgl+ */ 2189 #define GEN12_DSB_0_INT REG_BIT(13) /* tgl+ */ 2190 #define GEN12_DSB_INT(dsb_id) REG_BIT(13 + (dsb_id)) 2191 #define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */ 2192 #define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */ 2193 #define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */ 2194 #define GEN9_PIPE_PLANE3_FAULT REG_BIT(9) /* skl+ */ 2195 #define GEN8_PIPE_SPRITE_FAULT REG_BIT(9) /* bdw */ 2196 #define GEN9_PIPE_PLANE2_FAULT REG_BIT(8) /* skl+ */ 2197 #define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) /* bdw */ 2198 #define GEN9_PIPE_PLANE1_FAULT REG_BIT(7) /* skl+ */ 2199 #define GEN9_PIPE_PLANE4_FLIP_DONE REG_BIT(6) /* skl+ */ 2200 #define GEN9_PIPE_PLANE3_FLIP_DONE REG_BIT(5) /* skl+ */ 2201 #define GEN8_PIPE_SPRITE_FLIP_DONE REG_BIT(5) /* bdw */ 2202 #define GEN9_PIPE_PLANE2_FLIP_DONE REG_BIT(4) /* skl+ */ 2203 #define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */ 2204 #define GEN9_PIPE_PLANE1_FLIP_DONE REG_BIT(3) /* skl+ */ 2205 #define GEN9_PIPE_PLANE_FLIP_DONE(plane_id) \ 2206 REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) + (plane_id)) /* skl+ */ 2207 #define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2) 2208 #define GEN8_PIPE_VSYNC REG_BIT(1) 2209 #define GEN8_PIPE_VBLANK REG_BIT(0) 2210 2211 #define GEN8_DE_PIPE_IRQ_REGS(pipe) I915_IRQ_REGS(GEN8_DE_PIPE_IMR(pipe), \ 2212 GEN8_DE_PIPE_IER(pipe), \ 2213 GEN8_DE_PIPE_IIR(pipe)) 2214 2215 #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A) 2216 #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1) 2217 2218 #define GEN8_DE_PORT_ISR _MMIO(0x44440) 2219 #define GEN8_DE_PORT_IMR _MMIO(0x44444) 2220 #define GEN8_DE_PORT_IIR _MMIO(0x44448) 2221 #define GEN8_DE_PORT_IER _MMIO(0x4444c) 2222 #define DSI1_NON_TE (1 << 31) 2223 #define DSI0_NON_TE (1 << 30) 2224 #define ICL_AUX_CHANNEL_E (1 << 29) 2225 #define ICL_AUX_CHANNEL_F (1 << 28) 2226 #define GEN9_AUX_CHANNEL_D (1 << 27) 2227 #define GEN9_AUX_CHANNEL_C (1 << 26) 2228 #define GEN9_AUX_CHANNEL_B (1 << 25) 2229 #define DSI1_TE (1 << 24) 2230 #define DSI0_TE (1 << 23) 2231 #define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin)) 2232 #define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \ 2233 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \ 2234 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) 2235 #define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) 2236 #define BXT_DE_PORT_GMBUS (1 << 1) 2237 #define GEN8_AUX_CHANNEL_A (1 << 0) 2238 #define TGL_DE_PORT_AUX_USBC6 REG_BIT(13) 2239 #define XELPD_DE_PORT_AUX_DDIE REG_BIT(13) 2240 #define TGL_DE_PORT_AUX_USBC5 REG_BIT(12) 2241 #define XELPD_DE_PORT_AUX_DDID REG_BIT(12) 2242 #define TGL_DE_PORT_AUX_USBC4 REG_BIT(11) 2243 #define TGL_DE_PORT_AUX_USBC3 REG_BIT(10) 2244 #define TGL_DE_PORT_AUX_USBC2 REG_BIT(9) 2245 #define TGL_DE_PORT_AUX_USBC1 REG_BIT(8) 2246 #define TGL_DE_PORT_AUX_DDIC REG_BIT(2) 2247 #define TGL_DE_PORT_AUX_DDIB REG_BIT(1) 2248 #define TGL_DE_PORT_AUX_DDIA REG_BIT(0) 2249 2250 #define GEN8_DE_PORT_IRQ_REGS I915_IRQ_REGS(GEN8_DE_PORT_IMR, \ 2251 GEN8_DE_PORT_IER, \ 2252 GEN8_DE_PORT_IIR) 2253 2254 #define GEN8_DE_MISC_ISR _MMIO(0x44460) 2255 #define GEN8_DE_MISC_IMR _MMIO(0x44464) 2256 #define GEN8_DE_MISC_IIR _MMIO(0x44468) 2257 #define GEN8_DE_MISC_IER _MMIO(0x4446c) 2258 #define XELPDP_RM_TIMEOUT REG_BIT(29) 2259 #define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27) 2260 #define GEN8_DE_MISC_GSE REG_BIT(27) 2261 #define GEN8_DE_EDP_PSR REG_BIT(19) 2262 #define XELPDP_PMDEMAND_RSP REG_BIT(3) 2263 #define XE2LPD_DBUF_OVERLAP_DETECTED REG_BIT(1) 2264 2265 #define GEN8_DE_MISC_IRQ_REGS I915_IRQ_REGS(GEN8_DE_MISC_IMR, \ 2266 GEN8_DE_MISC_IER, \ 2267 GEN8_DE_MISC_IIR) 2268 2269 #define GEN8_PCU_ISR _MMIO(0x444e0) 2270 #define GEN8_PCU_IMR _MMIO(0x444e4) 2271 #define GEN8_PCU_IIR _MMIO(0x444e8) 2272 #define GEN8_PCU_IER _MMIO(0x444ec) 2273 2274 #define GEN8_PCU_IRQ_REGS I915_IRQ_REGS(GEN8_PCU_IMR, \ 2275 GEN8_PCU_IER, \ 2276 GEN8_PCU_IIR) 2277 2278 #define GEN11_GU_MISC_ISR _MMIO(0x444f0) 2279 #define GEN11_GU_MISC_IMR _MMIO(0x444f4) 2280 #define GEN11_GU_MISC_IIR _MMIO(0x444f8) 2281 #define GEN11_GU_MISC_IER _MMIO(0x444fc) 2282 #define GEN11_GU_MISC_GSE (1 << 27) 2283 2284 #define GEN11_GU_MISC_IRQ_REGS I915_IRQ_REGS(GEN11_GU_MISC_IMR, \ 2285 GEN11_GU_MISC_IER, \ 2286 GEN11_GU_MISC_IIR) 2287 2288 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) 2289 #define GEN11_MASTER_IRQ (1 << 31) 2290 #define GEN11_PCU_IRQ (1 << 30) 2291 #define GEN11_GU_MISC_IRQ (1 << 29) 2292 #define GEN11_DISPLAY_IRQ (1 << 16) 2293 #define GEN11_GT_DW_IRQ(x) (1 << (x)) 2294 #define GEN11_GT_DW1_IRQ (1 << 1) 2295 #define GEN11_GT_DW0_IRQ (1 << 0) 2296 2297 #define DG1_MSTR_TILE_INTR _MMIO(0x190008) 2298 #define DG1_MSTR_IRQ REG_BIT(31) 2299 #define DG1_MSTR_TILE(t) REG_BIT(t) 2300 2301 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) 2302 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) 2303 #define GEN11_AUDIO_CODEC_IRQ (1 << 24) 2304 #define GEN11_DE_PCH_IRQ (1 << 23) 2305 #define GEN11_DE_MISC_IRQ (1 << 22) 2306 #define GEN11_DE_HPD_IRQ (1 << 21) 2307 #define GEN11_DE_PORT_IRQ (1 << 20) 2308 #define GEN11_DE_PIPE_C (1 << 18) 2309 #define GEN11_DE_PIPE_B (1 << 17) 2310 #define GEN11_DE_PIPE_A (1 << 16) 2311 2312 #define GEN11_DE_HPD_ISR _MMIO(0x44470) 2313 #define GEN11_DE_HPD_IMR _MMIO(0x44474) 2314 #define GEN11_DE_HPD_IIR _MMIO(0x44478) 2315 #define GEN11_DE_HPD_IER _MMIO(0x4447c) 2316 #define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) 2317 #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \ 2318 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \ 2319 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \ 2320 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \ 2321 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \ 2322 GEN11_TC_HOTPLUG(HPD_PORT_TC1)) 2323 #define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) 2324 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \ 2325 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \ 2326 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \ 2327 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \ 2328 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \ 2329 GEN11_TBT_HOTPLUG(HPD_PORT_TC1)) 2330 2331 #define GEN11_DE_HPD_IRQ_REGS I915_IRQ_REGS(GEN11_DE_HPD_IMR, \ 2332 GEN11_DE_HPD_IER, \ 2333 GEN11_DE_HPD_IIR) 2334 2335 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) 2336 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) 2337 #define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 2338 #define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 2339 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 2340 #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4)) 2341 2342 #define PICAINTERRUPT_ISR _MMIO(0x16FE50) 2343 #define PICAINTERRUPT_IMR _MMIO(0x16FE54) 2344 #define PICAINTERRUPT_IIR _MMIO(0x16FE58) 2345 #define PICAINTERRUPT_IER _MMIO(0x16FE5C) 2346 #define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) 2347 #define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16) 2348 #define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin)) 2349 #define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8) 2350 #define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 + _HPD_PIN_DDI(hpd_pin)) 2351 #define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6) 2352 #define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) 2353 #define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0) 2354 2355 #define PICAINTERRUPT_IRQ_REGS I915_IRQ_REGS(PICAINTERRUPT_IMR, \ 2356 PICAINTERRUPT_IER, \ 2357 PICAINTERRUPT_IIR) 2358 2359 #define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200)) 2360 #define XELPDP_TBT_HOTPLUG_ENABLE REG_BIT(6) 2361 #define XELPDP_TBT_HPD_LONG_DETECT REG_BIT(5) 2362 #define XELPDP_TBT_HPD_SHORT_DETECT REG_BIT(4) 2363 #define XELPDP_DP_ALT_HOTPLUG_ENABLE REG_BIT(2) 2364 #define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1) 2365 #define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0) 2366 2367 #define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword)) 2368 #define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16) 2369 #define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12) 2370 #define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8) 2371 #define XE3_PMDEMAND_PIPES_MASK REG_GENMASK(7, 4) 2372 #define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6) 2373 #define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4) 2374 #define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0) 2375 2376 #define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31) 2377 #define XELPDP_PMDEMAND_CDCLK_FREQ_MASK REG_GENMASK(30, 20) 2378 #define XELPDP_PMDEMAND_DDICLK_FREQ_MASK REG_GENMASK(18, 8) 2379 #define XELPDP_PMDEMAND_SCALERS_MASK REG_GENMASK(6, 4) 2380 #define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0) 2381 2382 #define GEN12_DCPR_STATUS_1 _MMIO(0x46440) 2383 #define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26) 2384 2385 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) 2386 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 2387 #define ILK_ELPIN_409_SELECT REG_BIT(25) 2388 #define ILK_DPARB_GATE REG_BIT(22) 2389 #define ILK_VSDPFD_FULL REG_BIT(21) 2390 2391 #define FUSE_STRAP _MMIO(0x42014) 2392 #define ILK_INTERNAL_GRAPHICS_DISABLE REG_BIT(31) 2393 #define ILK_INTERNAL_DISPLAY_DISABLE REG_BIT(30) 2394 #define ILK_DISPLAY_DEBUG_DISABLE REG_BIT(29) 2395 #define IVB_PIPE_C_DISABLE REG_BIT(28) 2396 #define ILK_HDCP_DISABLE REG_BIT(25) 2397 #define ILK_eDP_A_DISABLE REG_BIT(24) 2398 #define HSW_CDCLK_LIMIT REG_BIT(24) 2399 #define ILK_DESKTOP REG_BIT(23) 2400 #define HSW_CPU_SSC_ENABLE REG_BIT(21) 2401 2402 #define FUSE_STRAP3 _MMIO(0x42020) 2403 #define HSW_REF_CLK_SELECT REG_BIT(1) 2404 2405 #define ILK_DSPCLK_GATE_D _MMIO(0x42020) 2406 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE REG_BIT(28) 2407 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE REG_BIT(9) 2408 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE REG_BIT(8) 2409 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE REG_BIT(7) 2410 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE REG_BIT(5) 2411 2412 #define IVB_CHICKEN3 _MMIO(0x4200c) 2413 #define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE REG_BIT(5) 2414 #define CHICKEN3_DGMG_DONE_FIX_DISABLE REG_BIT(2) 2415 2416 #define CHICKEN_PAR1_1 _MMIO(0x42080) 2417 #define IGNORE_KVMR_PIPE_A REG_BIT(23) 2418 #define KBL_ARB_FILL_SPARE_22 REG_BIT(22) 2419 #define DIS_RAM_BYPASS_PSR2_MAN_TRACK REG_BIT(16) 2420 #define SKL_DE_COMPRESSED_HASH_MODE REG_BIT(15) 2421 #define HSW_MASK_VBL_TO_PIPE_IN_SRD REG_BIT(15) /* hsw/bdw */ 2422 #define FORCE_ARB_IDLE_PLANES REG_BIT(14) 2423 #define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3) 2424 #define IGNORE_PSR2_HW_TRACKING REG_BIT(1) 2425 2426 #define CHICKEN_PAR2_1 _MMIO(0x42090) 2427 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14) 2428 2429 #define CHICKEN_MISC_2 _MMIO(0x42084) 2430 #define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */ 2431 #define BMG_DARB_HALF_BLK_END_BURST REG_BIT(27) 2432 #define KBL_ARB_FILL_SPARE_14 REG_BIT(14) 2433 #define KBL_ARB_FILL_SPARE_13 REG_BIT(13) 2434 #define GLK_CL2_PWR_DOWN REG_BIT(12) 2435 #define GLK_CL1_PWR_DOWN REG_BIT(11) 2436 #define GLK_CL0_PWR_DOWN REG_BIT(10) 2437 2438 #define CHICKEN_MISC_3 _MMIO(0x42088) 2439 #define DP_MST_DPT_DPTP_ALIGN_WA(trans) REG_BIT(9 + (trans) - TRANSCODER_A) 2440 #define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A) 2441 #define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A) 2442 2443 #define CHICKEN_MISC_4 _MMIO(0x4208c) 2444 #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13) 2445 #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0) 2446 #define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x)) 2447 2448 #define _CHICKEN_PIPESL_1_A 0x420b0 2449 #define _CHICKEN_PIPESL_1_B 0x420b4 2450 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 2451 #define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27) 2452 #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0) 2453 #define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1) 2454 #define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2) 2455 #define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3) 2456 #define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25) 2457 #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0) 2458 #define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1) 2459 #define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2) 2460 #define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3) 2461 #define HSW_FBCQ_DIS REG_BIT(22) 2462 #define HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */ 2463 #define SKL_PSR_MASK_PLANE_FLIP REG_BIT(11) /* skl+ */ 2464 #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0) 2465 #define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0) 2466 #define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1) 2467 #define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2) 2468 #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3) 2469 #define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */ 2470 2471 #define _CHICKEN_TRANS_A 0x420c0 2472 #define _CHICKEN_TRANS_B 0x420c4 2473 #define _CHICKEN_TRANS_C 0x420c8 2474 #define _CHICKEN_TRANS_EDP 0x420cc 2475 #define _CHICKEN_TRANS_D 0x420d8 2476 #define _CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ 2477 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ 2478 [TRANSCODER_A] = _CHICKEN_TRANS_A, \ 2479 [TRANSCODER_B] = _CHICKEN_TRANS_B, \ 2480 [TRANSCODER_C] = _CHICKEN_TRANS_C, \ 2481 [TRANSCODER_D] = _CHICKEN_TRANS_D)) 2482 #define _MTL_CHICKEN_TRANS_A 0x604e0 2483 #define _MTL_CHICKEN_TRANS_B 0x614e0 2484 #define _MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \ 2485 _MTL_CHICKEN_TRANS_A, \ 2486 _MTL_CHICKEN_TRANS_B) 2487 #define CHICKEN_TRANS(display, trans) (DISPLAY_VER(display) >= 14 ? _MTL_CHICKEN_TRANS(trans) : _CHICKEN_TRANS(trans)) 2488 #define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* tgl+ */ 2489 #define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */ 2490 #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) 2491 #define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x) 2492 #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */ 2493 #define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23) 2494 #define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19) 2495 #define ADLP_1_BASED_X_GRANULARITY REG_BIT(18) 2496 #define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18) 2497 #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */ 2498 #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */ 2499 #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15) 2500 #define DP_FEC_BS_JITTER_WA REG_BIT(15) 2501 #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) 2502 #define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4) 2503 #define HDCP_LINE_REKEY_DISABLE REG_BIT(0) 2504 2505 #define DISP_ARB_CTL _MMIO(0x45000) 2506 #define DISP_FBC_MEMORY_WAKE REG_BIT(31) 2507 #define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13) 2508 #define DISP_FBC_WM_DIS REG_BIT(15) 2509 2510 #define DISP_ARB_CTL2 _MMIO(0x45004) 2511 #define DISP_DATA_PARTITION_5_6 REG_BIT(6) 2512 #define DISP_IPC_ENABLE REG_BIT(3) 2513 2514 #define GEN7_MSG_CTL _MMIO(0x45010) 2515 #define WAIT_FOR_PCH_RESET_ACK (1 << 1) 2516 #define WAIT_FOR_PCH_FLR_ACK (1 << 0) 2517 2518 #define _BW_BUDDY0_CTL 0x45130 2519 #define _BW_BUDDY1_CTL 0x45140 2520 #define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ 2521 _BW_BUDDY0_CTL, \ 2522 _BW_BUDDY1_CTL)) 2523 #define BW_BUDDY_DISABLE REG_BIT(31) 2524 #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) 2525 #define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x) 2526 2527 #define _BW_BUDDY0_PAGE_MASK 0x45134 2528 #define _BW_BUDDY1_PAGE_MASK 0x45144 2529 #define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ 2530 _BW_BUDDY0_PAGE_MASK, \ 2531 _BW_BUDDY1_PAGE_MASK)) 2532 2533 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) 2534 #define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6) 2535 #define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4) 2536 2537 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 2538 #define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31) 2539 #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) 2540 #define _LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25) 2541 #define _LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24) 2542 #define _LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23) 2543 #define LATENCY_REPORTING_REMOVED(pipe) _PICK((pipe), \ 2544 _LATENCY_REPORTING_REMOVED_PIPE_A, \ 2545 _LATENCY_REPORTING_REMOVED_PIPE_B, \ 2546 _LATENCY_REPORTING_REMOVED_PIPE_C, \ 2547 _LATENCY_REPORTING_REMOVED_PIPE_D) 2548 #define ICL_DELAY_PMRSP REG_BIT(22) 2549 #define DISABLE_FLR_SRC REG_BIT(15) 2550 #define MASK_WAKEMEM REG_BIT(13) 2551 #define DDI_CLOCK_REG_ACCESS REG_BIT(7) 2552 2553 #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434) 2554 #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27) 2555 #define DCPR_MASK_LPMODE REG_BIT(26) 2556 #define DCPR_SEND_RESP_IMM REG_BIT(25) 2557 #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24) 2558 2559 #define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438) 2560 #define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19) 2561 2562 #define SKL_DFSM _MMIO(0x51000) 2563 #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27) 2564 #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) 2565 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) 2566 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) 2567 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) 2568 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) 2569 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) 2570 #define ICL_DFSM_DMC_DISABLE (1 << 23) 2571 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) 2572 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) 2573 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) 2574 #define TGL_DFSM_PIPE_D_DISABLE (1 << 22) 2575 #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7) 2576 #define XE2LPD_DFSM_DBUF_OVERLAP_DISABLE (1 << 3) 2577 2578 #define XE2LPD_DE_CAP _MMIO(0x41100) 2579 #define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30) 2580 #define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28) 2581 #define XE2LPD_DE_CAP_DSC_REMOVED 1 2582 #define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26) 2583 #define XE2LPD_DE_CAP_SCALER_SINGLE 1 2584 2585 #define SKL_DSSM _MMIO(0x51004) 2586 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) 2587 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) 2588 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) 2589 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) 2590 2591 #define GMD_ID_DISPLAY _MMIO(0x510a0) 2592 #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22) 2593 #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14) 2594 #define GMD_ID_STEP REG_GENMASK(5, 0) 2595 2596 /*GEN11 chicken */ 2597 #define _PIPEA_CHICKEN 0x70038 2598 #define _PIPEB_CHICKEN 0x71038 2599 #define _PIPEC_CHICKEN 0x72038 2600 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ 2601 _PIPEB_CHICKEN) 2602 #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30) 2603 #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30) 2604 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15) 2605 #define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12) 2606 #define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7) 2607 2608 /* PCH */ 2609 2610 #define PCH_DISPLAY_BASE 0xc0000u 2611 2612 /* south display engine interrupt: IBX */ 2613 #define SDE_AUDIO_POWER_D (1 << 27) 2614 #define SDE_AUDIO_POWER_C (1 << 26) 2615 #define SDE_AUDIO_POWER_B (1 << 25) 2616 #define SDE_AUDIO_POWER_SHIFT (25) 2617 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 2618 #define SDE_GMBUS (1 << 24) 2619 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 2620 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 2621 #define SDE_AUDIO_HDCP_MASK (3 << 22) 2622 #define SDE_AUDIO_TRANSB (1 << 21) 2623 #define SDE_AUDIO_TRANSA (1 << 20) 2624 #define SDE_AUDIO_TRANS_MASK (3 << 20) 2625 #define SDE_POISON (1 << 19) 2626 /* 18 reserved */ 2627 #define SDE_FDI_RXB (1 << 17) 2628 #define SDE_FDI_RXA (1 << 16) 2629 #define SDE_FDI_MASK (3 << 16) 2630 #define SDE_AUXD (1 << 15) 2631 #define SDE_AUXC (1 << 14) 2632 #define SDE_AUXB (1 << 13) 2633 #define SDE_AUX_MASK (7 << 13) 2634 /* 12 reserved */ 2635 #define SDE_CRT_HOTPLUG (1 << 11) 2636 #define SDE_PORTD_HOTPLUG (1 << 10) 2637 #define SDE_PORTC_HOTPLUG (1 << 9) 2638 #define SDE_PORTB_HOTPLUG (1 << 8) 2639 #define SDE_SDVOB_HOTPLUG (1 << 6) 2640 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 2641 SDE_SDVOB_HOTPLUG | \ 2642 SDE_PORTB_HOTPLUG | \ 2643 SDE_PORTC_HOTPLUG | \ 2644 SDE_PORTD_HOTPLUG) 2645 #define SDE_TRANSB_CRC_DONE (1 << 5) 2646 #define SDE_TRANSB_CRC_ERR (1 << 4) 2647 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 2648 #define SDE_TRANSA_CRC_DONE (1 << 2) 2649 #define SDE_TRANSA_CRC_ERR (1 << 1) 2650 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 2651 #define SDE_TRANS_MASK (0x3f) 2652 2653 /* south display engine interrupt: CPT - CNP */ 2654 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 2655 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 2656 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 2657 #define SDE_AUDIO_POWER_SHIFT_CPT 29 2658 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 2659 #define SDE_AUXD_CPT (1 << 27) 2660 #define SDE_AUXC_CPT (1 << 26) 2661 #define SDE_AUXB_CPT (1 << 25) 2662 #define SDE_AUX_MASK_CPT (7 << 25) 2663 #define SDE_PORTE_HOTPLUG_SPT (1 << 25) 2664 #define SDE_PORTA_HOTPLUG_SPT (1 << 24) 2665 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 2666 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 2667 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 2668 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 2669 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 2670 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 2671 SDE_SDVOB_HOTPLUG_CPT | \ 2672 SDE_PORTD_HOTPLUG_CPT | \ 2673 SDE_PORTC_HOTPLUG_CPT | \ 2674 SDE_PORTB_HOTPLUG_CPT) 2675 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ 2676 SDE_PORTD_HOTPLUG_CPT | \ 2677 SDE_PORTC_HOTPLUG_CPT | \ 2678 SDE_PORTB_HOTPLUG_CPT | \ 2679 SDE_PORTA_HOTPLUG_SPT) 2680 #define SDE_GMBUS_CPT (1 << 17) 2681 #define SDE_ERROR_CPT (1 << 16) 2682 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 2683 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 2684 #define SDE_FDI_RXC_CPT (1 << 8) 2685 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 2686 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 2687 #define SDE_FDI_RXB_CPT (1 << 4) 2688 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 2689 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 2690 #define SDE_FDI_RXA_CPT (1 << 0) 2691 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 2692 SDE_AUDIO_CP_REQ_B_CPT | \ 2693 SDE_AUDIO_CP_REQ_A_CPT) 2694 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 2695 SDE_AUDIO_CP_CHG_B_CPT | \ 2696 SDE_AUDIO_CP_CHG_A_CPT) 2697 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 2698 SDE_FDI_RXB_CPT | \ 2699 SDE_FDI_RXA_CPT) 2700 2701 /* south display engine interrupt: ICP/TGP/MTP */ 2702 #define SDE_PICAINTERRUPT REG_BIT(31) 2703 #define SDE_GMBUS_ICP (1 << 23) 2704 #define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin)) 2705 #define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */ 2706 #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin)) 2707 #define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \ 2708 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \ 2709 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \ 2710 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A)) 2711 #define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \ 2712 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \ 2713 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \ 2714 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \ 2715 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \ 2716 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1)) 2717 2718 #define SDEISR _MMIO(0xc4000) 2719 #define SDEIMR _MMIO(0xc4004) 2720 #define SDEIIR _MMIO(0xc4008) 2721 #define SDEIER _MMIO(0xc400c) 2722 2723 #define SDE_IRQ_REGS I915_IRQ_REGS(SDEIMR, \ 2724 SDEIER, \ 2725 SDEIIR) 2726 2727 #define SERR_INT _MMIO(0xc4040) 2728 #define SERR_INT_POISON (1 << 31) 2729 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 2730 2731 /* digital port hotplug */ 2732 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ 2733 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ 2734 #define BXT_DDIA_HPD_INVERT (1 << 27) 2735 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ 2736 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ 2737 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ 2738 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ 2739 #define PORTD_HOTPLUG_ENABLE (1 << 20) 2740 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ 2741 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ 2742 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ 2743 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ 2744 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ 2745 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) 2746 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 2747 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 2748 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 2749 #define PORTC_HOTPLUG_ENABLE (1 << 12) 2750 #define BXT_DDIC_HPD_INVERT (1 << 11) 2751 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ 2752 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ 2753 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ 2754 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ 2755 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ 2756 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) 2757 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 2758 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 2759 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 2760 #define PORTB_HOTPLUG_ENABLE (1 << 4) 2761 #define BXT_DDIB_HPD_INVERT (1 << 3) 2762 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ 2763 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ 2764 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ 2765 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ 2766 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ 2767 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) 2768 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 2769 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 2770 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 2771 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ 2772 BXT_DDIB_HPD_INVERT | \ 2773 BXT_DDIC_HPD_INVERT) 2774 2775 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ 2776 #define PORTE_HOTPLUG_ENABLE (1 << 4) 2777 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) 2778 #define PORTE_HOTPLUG_NO_DETECT (0 << 0) 2779 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) 2780 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) 2781 2782 /* This register is a reuse of PCH_PORT_HOTPLUG register. The 2783 * functionality covered in PCH_PORT_HOTPLUG is split into 2784 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. 2785 */ 2786 2787 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030) 2788 #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4)) 2789 #define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4 << (_HPD_PIN_DDI(hpd_pin) * 4)) 2790 #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 2791 #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4)) 2792 #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4)) 2793 #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4)) 2794 #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 2795 2796 #define SHOTPLUG_CTL_TC _MMIO(0xc4034) 2797 #define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 2798 #define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 2799 #define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 2800 2801 #define SHPD_FILTER_CNT _MMIO(0xc4038) 2802 #define SHPD_FILTER_CNT_500_ADJ 0x001D9 2803 #define SHPD_FILTER_CNT_250 0x000F8 2804 2805 #define _PCH_DPLL_A 0xc6014 2806 #define _PCH_DPLL_B 0xc6018 2807 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 2808 2809 #define _PCH_FPA0 0xc6040 2810 #define _PCH_FPB0 0xc6048 2811 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0) 2812 #define FP_CB_TUNE (0x3 << 22) 2813 2814 #define _PCH_FPA1 0xc6044 2815 #define _PCH_FPB1 0xc604c 2816 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1) 2817 2818 #define PCH_DPLL_TEST _MMIO(0xc606c) 2819 2820 #define PCH_DREF_CONTROL _MMIO(0xC6200) 2821 #define DREF_CONTROL_MASK 0x7fc3 2822 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 2823 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 2824 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 2825 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 2826 #define DREF_SSC_SOURCE_DISABLE (0 << 11) 2827 #define DREF_SSC_SOURCE_ENABLE (2 << 11) 2828 #define DREF_SSC_SOURCE_MASK (3 << 11) 2829 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 2830 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 2831 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 2832 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 2833 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 2834 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 2835 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 2836 #define DREF_SSC4_DOWNSPREAD (0 << 6) 2837 #define DREF_SSC4_CENTERSPREAD (1 << 6) 2838 #define DREF_SSC1_DISABLE (0 << 1) 2839 #define DREF_SSC1_ENABLE (1 << 1) 2840 #define DREF_SSC4_DISABLE (0) 2841 #define DREF_SSC4_ENABLE (1) 2842 2843 #define PCH_RAWCLK_FREQ _MMIO(0xc6204) 2844 #define FDL_TP1_TIMER_SHIFT 12 2845 #define FDL_TP1_TIMER_MASK (3 << 12) 2846 #define FDL_TP2_TIMER_SHIFT 10 2847 #define FDL_TP2_TIMER_MASK (3 << 10) 2848 #define RAWCLK_FREQ_MASK 0x3ff 2849 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16) 2850 #define CNP_RAWCLK_DIV(div) ((div) << 16) 2851 #define CNP_RAWCLK_FRAC_MASK (0xf << 26) 2852 #define CNP_RAWCLK_DEN(den) ((den) << 26) 2853 #define ICP_RAWCLK_NUM(num) ((num) << 11) 2854 2855 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) 2856 2857 #define PCH_SSC4_PARMS _MMIO(0xc6210) 2858 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) 2859 2860 #define PCH_DPLL_SEL _MMIO(0xc7000) 2861 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) 2862 #define TRANS_DPLLA_SEL(pipe) 0 2863 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) 2864 2865 /* transcoder */ 2866 2867 #define _PCH_TRANS_HTOTAL_A 0xe0000 2868 #define _PCH_TRANS_HTOTAL_B 0xe1000 2869 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 2870 #define TRANS_HTOTAL_SHIFT 16 2871 #define TRANS_HACTIVE_SHIFT 0 2872 2873 #define _PCH_TRANS_HBLANK_A 0xe0004 2874 #define _PCH_TRANS_HBLANK_B 0xe1004 2875 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 2876 #define TRANS_HBLANK_END_SHIFT 16 2877 #define TRANS_HBLANK_START_SHIFT 0 2878 2879 #define _PCH_TRANS_HSYNC_A 0xe0008 2880 #define _PCH_TRANS_HSYNC_B 0xe1008 2881 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 2882 #define TRANS_HSYNC_END_SHIFT 16 2883 #define TRANS_HSYNC_START_SHIFT 0 2884 2885 #define _PCH_TRANS_VTOTAL_A 0xe000c 2886 #define _PCH_TRANS_VTOTAL_B 0xe100c 2887 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 2888 #define TRANS_VTOTAL_SHIFT 16 2889 #define TRANS_VACTIVE_SHIFT 0 2890 2891 #define _PCH_TRANS_VBLANK_A 0xe0010 2892 #define _PCH_TRANS_VBLANK_B 0xe1010 2893 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 2894 #define TRANS_VBLANK_END_SHIFT 16 2895 #define TRANS_VBLANK_START_SHIFT 0 2896 2897 #define _PCH_TRANS_VSYNC_A 0xe0014 2898 #define _PCH_TRANS_VSYNC_B 0xe1014 2899 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 2900 #define TRANS_VSYNC_END_SHIFT 16 2901 #define TRANS_VSYNC_START_SHIFT 0 2902 2903 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 2904 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 2905 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) 2906 2907 #define _PCH_TRANSA_DATA_M1 0xe0030 2908 #define _PCH_TRANSB_DATA_M1 0xe1030 2909 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 2910 2911 #define _PCH_TRANSA_DATA_N1 0xe0034 2912 #define _PCH_TRANSB_DATA_N1 0xe1034 2913 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 2914 2915 #define _PCH_TRANSA_DATA_M2 0xe0038 2916 #define _PCH_TRANSB_DATA_M2 0xe1038 2917 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 2918 2919 #define _PCH_TRANSA_DATA_N2 0xe003c 2920 #define _PCH_TRANSB_DATA_N2 0xe103c 2921 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 2922 2923 #define _PCH_TRANSA_LINK_M1 0xe0040 2924 #define _PCH_TRANSB_LINK_M1 0xe1040 2925 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 2926 2927 #define _PCH_TRANSA_LINK_N1 0xe0044 2928 #define _PCH_TRANSB_LINK_N1 0xe1044 2929 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 2930 2931 #define _PCH_TRANSA_LINK_M2 0xe0048 2932 #define _PCH_TRANSB_LINK_M2 0xe1048 2933 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 2934 2935 #define _PCH_TRANSA_LINK_N2 0xe004c 2936 #define _PCH_TRANSB_LINK_N2 0xe104c 2937 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 2938 2939 /* Per-transcoder DIP controls (PCH) */ 2940 #define _VIDEO_DIP_CTL_A 0xe0200 2941 #define _VIDEO_DIP_CTL_B 0xe1200 2942 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 2943 2944 #define _VIDEO_DIP_DATA_A 0xe0208 2945 #define _VIDEO_DIP_DATA_B 0xe1208 2946 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 2947 2948 #define _VIDEO_DIP_GCP_A 0xe0210 2949 #define _VIDEO_DIP_GCP_B 0xe1210 2950 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 2951 #define GCP_COLOR_INDICATION (1 << 2) 2952 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) 2953 #define GCP_AV_MUTE (1 << 0) 2954 2955 /* Per-transcoder DIP controls (VLV) */ 2956 #define _VLV_VIDEO_DIP_CTL_A 0x60200 2957 #define _VLV_VIDEO_DIP_CTL_B 0x61170 2958 #define _CHV_VIDEO_DIP_CTL_C 0x611f0 2959 #define VLV_TVIDEO_DIP_CTL(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \ 2960 _VLV_VIDEO_DIP_CTL_A, \ 2961 _VLV_VIDEO_DIP_CTL_B, \ 2962 _CHV_VIDEO_DIP_CTL_C) 2963 2964 #define _VLV_VIDEO_DIP_DATA_A 0x60208 2965 #define _VLV_VIDEO_DIP_DATA_B 0x61174 2966 #define _CHV_VIDEO_DIP_DATA_C 0x611f4 2967 #define VLV_TVIDEO_DIP_DATA(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \ 2968 _VLV_VIDEO_DIP_DATA_A, \ 2969 _VLV_VIDEO_DIP_DATA_B, \ 2970 _CHV_VIDEO_DIP_DATA_C) 2971 2972 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210 2973 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178 2974 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C 0x611f8 2975 #define VLV_TVIDEO_DIP_GCP(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \ 2976 _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 2977 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, \ 2978 _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 2979 2980 /* Haswell DIP controls */ 2981 #define _HSW_VIDEO_DIP_CTL_A 0x60200 2982 #define _HSW_VIDEO_DIP_CTL_B 0x61200 2983 #define HSW_TVIDEO_DIP_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A) 2984 2985 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 2986 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 2987 #define HSW_TVIDEO_DIP_AVI_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) 2988 2989 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 2990 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 2991 #define HSW_TVIDEO_DIP_VS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) 2992 2993 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 2994 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 2995 #define HSW_TVIDEO_DIP_SPD_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) 2996 2997 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 2998 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 2999 #define HSW_TVIDEO_DIP_GMP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) 3000 3001 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 3002 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 3003 #define HSW_TVIDEO_DIP_VSC_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) 3004 3005 /*ADLP and later: */ 3006 #define _ADL_VIDEO_DIP_AS_DATA_A 0x60484 3007 #define _ADL_VIDEO_DIP_AS_DATA_B 0x61484 3008 #define ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans,\ 3009 _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4) 3010 3011 #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440 3012 #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440 3013 #define GLK_TVIDEO_DIP_DRM_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) 3014 3015 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 3016 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 3017 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 3018 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 3019 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 3020 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 3021 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 3022 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 3023 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 3024 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 3025 3026 #define _HSW_VIDEO_DIP_GCP_A 0x60210 3027 #define _HSW_VIDEO_DIP_GCP_B 0x61210 3028 #define HSW_TVIDEO_DIP_GCP(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A) 3029 3030 /* Icelake PPS_DATA and _ECC DIP Registers. 3031 * These are available for transcoders B,C and eDP. 3032 * Adding the _A so as to reuse the _MMIO_TRANS2 3033 * definition, with which it offsets to the right location. 3034 */ 3035 3036 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350 3037 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350 3038 #define ICL_VIDEO_DIP_PPS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) 3039 3040 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4 3041 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4 3042 #define ICL_VIDEO_DIP_PPS_ECC(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) 3043 3044 #define _HSW_STEREO_3D_CTL_A 0x70020 3045 #define _HSW_STEREO_3D_CTL_B 0x71020 3046 #define HSW_STEREO_3D_CTL(dev_priv, trans) _MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A) 3047 #define S3D_ENABLE (1 << 31) 3048 3049 #define _PCH_TRANSACONF 0xf0008 3050 #define _PCH_TRANSBCONF 0xf1008 3051 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 3052 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ 3053 #define TRANS_ENABLE REG_BIT(31) 3054 #define TRANS_STATE_ENABLE REG_BIT(30) 3055 #define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */ 3056 #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */ 3057 #define TRANS_INTERLACE_MASK REG_GENMASK(23, 21) 3058 #define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0) 3059 #define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */ 3060 #define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3) 3061 #define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */ 3062 #define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0) 3063 #define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1) 3064 #define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2) 3065 #define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3) 3066 3067 #define _TRANSA_CHICKEN1 0xf0060 3068 #define _TRANSB_CHICKEN1 0xf1060 3069 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 3070 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10) 3071 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4) 3072 3073 #define _TRANSA_CHICKEN2 0xf0064 3074 #define _TRANSB_CHICKEN2 0xf1064 3075 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 3076 #define TRANS_CHICKEN2_TIMING_OVERRIDE REG_BIT(31) 3077 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED REG_BIT(29) 3078 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) 3079 #define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */ 3080 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER REG_BIT(26) 3081 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25) 3082 3083 #define SOUTH_CHICKEN1 _MMIO(0xc2000) 3084 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 3085 #define FDIA_PHASE_SYNC_SHIFT_EN 18 3086 #define INVERT_DDIE_HPD REG_BIT(28) 3087 #define INVERT_DDID_HPD_MTP REG_BIT(27) 3088 #define INVERT_TC4_HPD REG_BIT(26) 3089 #define INVERT_TC3_HPD REG_BIT(25) 3090 #define INVERT_TC2_HPD REG_BIT(24) 3091 #define INVERT_TC1_HPD REG_BIT(23) 3092 #define INVERT_DDID_HPD (1 << 18) 3093 #define INVERT_DDIC_HPD (1 << 17) 3094 #define INVERT_DDIB_HPD (1 << 16) 3095 #define INVERT_DDIA_HPD (1 << 15) 3096 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 3097 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 3098 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 3099 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8) 3100 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8) 3101 #define SBCLK_RUN_REFCLK_DIS (1 << 7) 3102 #define ICP_SECOND_PPS_IO_SELECT REG_BIT(2) 3103 #define SPT_PWM_GRANULARITY (1 << 0) 3104 #define SOUTH_CHICKEN2 _MMIO(0xc2004) 3105 #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13) 3106 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12) 3107 #define LPT_PWM_GRANULARITY (1 << 5) 3108 #define DPLS_EDP_PPS_FIX_DIS (1 << 0) 3109 3110 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) 3111 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) 3112 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) 3113 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) 3114 #define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15) 3115 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) 3116 #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) 3117 #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) 3118 3119 #define PCH_DP_B _MMIO(0xe4100) 3120 #define PCH_DP_C _MMIO(0xe4200) 3121 #define PCH_DP_D _MMIO(0xe4300) 3122 3123 /* CPT */ 3124 #define _TRANS_DP_CTL_A 0xe0300 3125 #define _TRANS_DP_CTL_B 0xe1300 3126 #define _TRANS_DP_CTL_C 0xe2300 3127 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) 3128 #define TRANS_DP_OUTPUT_ENABLE REG_BIT(31) 3129 #define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29) 3130 #define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3) 3131 #define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B) 3132 #define TRANS_DP_AUDIO_ONLY REG_BIT(26) 3133 #define TRANS_DP_ENH_FRAMING REG_BIT(18) 3134 #define TRANS_DP_BPC_MASK REG_GENMASK(10, 9) 3135 #define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0) 3136 #define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1) 3137 #define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2) 3138 #define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3) 3139 #define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4) 3140 #define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3) 3141 3142 #define _TRANS_DP2_CTL_A 0x600a0 3143 #define _TRANS_DP2_CTL_B 0x610a0 3144 #define _TRANS_DP2_CTL_C 0x620a0 3145 #define _TRANS_DP2_CTL_D 0x630a0 3146 #define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B) 3147 #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31) 3148 #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30) 3149 #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23) 3150 3151 #define _TRANS_DP2_VFREQHIGH_A 0x600a4 3152 #define _TRANS_DP2_VFREQHIGH_B 0x610a4 3153 #define _TRANS_DP2_VFREQHIGH_C 0x620a4 3154 #define _TRANS_DP2_VFREQHIGH_D 0x630a4 3155 #define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B) 3156 #define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8) 3157 #define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz)) 3158 3159 #define _TRANS_DP2_VFREQLOW_A 0x600a8 3160 #define _TRANS_DP2_VFREQLOW_B 0x610a8 3161 #define _TRANS_DP2_VFREQLOW_C 0x620a8 3162 #define _TRANS_DP2_VFREQLOW_D 0x630a8 3163 #define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B) 3164 3165 #define _DP_MIN_HBLANK_CTL_A 0x600ac 3166 #define _DP_MIN_HBLANK_CTL_B 0x610ac 3167 #define DP_MIN_HBLANK_CTL(trans) _MMIO_TRANS(trans, _DP_MIN_HBLANK_CTL_A, _DP_MIN_HBLANK_CTL_B) 3168 3169 /* SNB eDP training params */ 3170 /* SNB A-stepping */ 3171 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 3172 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 3173 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 3174 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 3175 /* SNB B-stepping */ 3176 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22) 3177 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22) 3178 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22) 3179 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22) 3180 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22) 3181 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22) 3182 3183 /* IVB */ 3184 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22) 3185 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22) 3186 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22) 3187 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22) 3188 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22) 3189 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22) 3190 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22) 3191 3192 /* legacy values */ 3193 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22) 3194 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22) 3195 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22) 3196 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22) 3197 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22) 3198 3199 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22) 3200 3201 #define VLV_PMWGICZ _MMIO(0x1300a4) 3202 3203 #define HSW_EDRAM_CAP _MMIO(0x120010) 3204 #define EDRAM_ENABLED 0x1 3205 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) 3206 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) 3207 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) 3208 3209 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) 3210 #define PIXEL_OVERLAP_CNT_MASK (3 << 30) 3211 #define PIXEL_OVERLAP_CNT_SHIFT 30 3212 3213 #define GEN6_PCODE_MAILBOX _MMIO(0x138124) 3214 #define GEN6_PCODE_READY (1 << 31) 3215 #define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16) 3216 #define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8) 3217 #define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0) 3218 #define GEN6_PCODE_ERROR_MASK 0xFF 3219 #define GEN6_PCODE_SUCCESS 0x0 3220 #define GEN6_PCODE_ILLEGAL_CMD 0x1 3221 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2 3222 #define GEN6_PCODE_TIMEOUT 0x3 3223 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF 3224 #define GEN7_PCODE_TIMEOUT 0x2 3225 #define GEN7_PCODE_ILLEGAL_DATA 0x3 3226 #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4 3227 #define GEN11_PCODE_LOCKED 0x6 3228 #define GEN11_PCODE_REJECTED 0x11 3229 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 3230 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 3231 #define GEN6_PCODE_READ_RC6VIDS 0x5 3232 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 3233 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 3234 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 3235 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 3236 #define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24) 3237 #define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16) 3238 #define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8) 3239 #define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0) 3240 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5 3241 #define SKL_PCODE_CDCLK_CONTROL 0x7 3242 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 3243 #define SKL_CDCLK_READY_FOR_CHANGE 0x1 3244 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 3245 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 3246 #define GEN6_READ_OC_PARAMS 0xc 3247 #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd 3248 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8) 3249 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8)) 3250 #define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8)) 3251 #define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D 3252 #define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0) 3253 #define DISPLAY_TO_PCODE_VOLTAGE_MAX DISPLAY_TO_PCODE_VOLTAGE_MASK 3254 #define DISPLAY_TO_PCODE_CDCLK_VALID REG_BIT(27) 3255 #define DISPLAY_TO_PCODE_PIPE_COUNT_VALID REG_BIT(31) 3256 #define DISPLAY_TO_PCODE_CDCLK_MASK REG_GENMASK(25, 16) 3257 #define DISPLAY_TO_PCODE_PIPE_COUNT_MASK REG_GENMASK(30, 28) 3258 #define DISPLAY_TO_PCODE_CDCLK(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x)) 3259 #define DISPLAY_TO_PCODE_PIPE_COUNT(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x)) 3260 #define DISPLAY_TO_PCODE_VOLTAGE(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x)) 3261 #define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \ 3262 ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \ 3263 (DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \ 3264 (DISPLAY_TO_PCODE_VOLTAGE(voltage_level))) 3265 #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe 3266 #define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0) 3267 #define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0) 3268 #define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1) 3269 #define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2) 3270 #define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2) 3271 #define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0) 3272 #define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1) 3273 #define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2) 3274 #define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0) 3275 #define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x)) 3276 #define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8) 3277 #define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x)) 3278 #define GEN6_PCODE_READ_D_COMP 0x10 3279 #define GEN6_PCODE_WRITE_D_COMP 0x11 3280 #define ICL_PCODE_EXIT_TCCOLD 0x12 3281 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 3282 #define DISPLAY_IPS_CONTROL 0x19 3283 #define TGL_PCODE_TCCOLD 0x26 3284 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0) 3285 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0 3286 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0) 3287 /* See also IPS_CTL */ 3288 #define IPS_PCODE_CONTROL (1 << 30) 3289 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A 3290 #define GEN9_PCODE_SAGV_CONTROL 0x21 3291 #define GEN9_SAGV_DISABLE 0x0 3292 #define GEN9_SAGV_IS_DISABLED 0x1 3293 #define GEN9_SAGV_ENABLE 0x3 3294 #define DG1_PCODE_STATUS 0x7E 3295 #define DG1_UNCORE_GET_INIT_STATUS 0x0 3296 #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1 3297 #define PCODE_POWER_SETUP 0x7C 3298 #define POWER_SETUP_SUBCOMMAND_READ_I1 0x4 3299 #define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5 3300 #define POWER_SETUP_I1_WATTS REG_BIT(31) 3301 #define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */ 3302 #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0) 3303 #define POWER_SETUP_SUBCOMMAND_G8_ENABLE 0x6 3304 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 3305 #define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */ 3306 /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */ 3307 #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0 3308 #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1 3309 /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */ 3310 /* XEHP_PCODE_FREQUENCY_CONFIG param2 */ 3311 #define PCODE_MBOX_DOMAIN_NONE 0x0 3312 #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3 3313 #define GEN6_PCODE_DATA _MMIO(0x138128) 3314 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 3315 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 3316 #define GEN6_PCODE_DATA1 _MMIO(0x13812C) 3317 3318 #define MTL_PCODE_STOLEN_ACCESS _MMIO(0x138914) 3319 #define STOLEN_ACCESS_ALLOWED 0x1 3320 3321 /* IVYBRIDGE DPF */ 3322 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ 3323 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14) 3324 #define GEN7_PARITY_ERROR_VALID (1 << 13) 3325 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11) 3326 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8) 3327 #define GEN7_PARITY_ERROR_ROW(reg) \ 3328 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14) 3329 #define GEN7_PARITY_ERROR_BANK(reg) \ 3330 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11) 3331 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 3332 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 3333 #define GEN7_L3CDERRST1_ENABLE (1 << 7) 3334 3335 /* These are the 4 32-bit write offset registers for each stream 3336 * output buffer. It determines the offset from the 3337 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 3338 */ 3339 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) 3340 3341 /* 3342 * HSW - ICL power wells 3343 * 3344 * Platforms have up to 3 power well control register sets, each set 3345 * controlling up to 16 power wells via a request/status HW flag tuple: 3346 * - main (HSW_PWR_WELL_CTL[1-4]) 3347 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4]) 3348 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4]) 3349 * Each control register set consists of up to 4 registers used by different 3350 * sources that can request a power well to be enabled: 3351 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1) 3352 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2) 3353 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set) 3354 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4) 3355 */ 3356 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400) 3357 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404) 3358 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408) 3359 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C) 3360 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2)) 3361 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2)) 3362 3363 /* HSW/BDW power well */ 3364 #define HSW_PW_CTL_IDX_GLOBAL 15 3365 3366 /* SKL/BXT/GLK power wells */ 3367 #define SKL_PW_CTL_IDX_PW_2 15 3368 #define SKL_PW_CTL_IDX_PW_1 14 3369 #define GLK_PW_CTL_IDX_AUX_C 10 3370 #define GLK_PW_CTL_IDX_AUX_B 9 3371 #define GLK_PW_CTL_IDX_AUX_A 8 3372 #define SKL_PW_CTL_IDX_DDI_D 4 3373 #define SKL_PW_CTL_IDX_DDI_C 3 3374 #define SKL_PW_CTL_IDX_DDI_B 2 3375 #define SKL_PW_CTL_IDX_DDI_A_E 1 3376 #define GLK_PW_CTL_IDX_DDI_A 1 3377 #define SKL_PW_CTL_IDX_MISC_IO 0 3378 3379 /* ICL/TGL - power wells */ 3380 #define TGL_PW_CTL_IDX_PW_5 4 3381 #define ICL_PW_CTL_IDX_PW_4 3 3382 #define ICL_PW_CTL_IDX_PW_3 2 3383 #define ICL_PW_CTL_IDX_PW_2 1 3384 #define ICL_PW_CTL_IDX_PW_1 0 3385 3386 /* XE_LPD - power wells */ 3387 #define XELPD_PW_CTL_IDX_PW_D 8 3388 #define XELPD_PW_CTL_IDX_PW_C 7 3389 #define XELPD_PW_CTL_IDX_PW_B 6 3390 #define XELPD_PW_CTL_IDX_PW_A 5 3391 3392 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440) 3393 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444) 3394 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C) 3395 #define TGL_PW_CTL_IDX_AUX_TBT6 14 3396 #define TGL_PW_CTL_IDX_AUX_TBT5 13 3397 #define TGL_PW_CTL_IDX_AUX_TBT4 12 3398 #define ICL_PW_CTL_IDX_AUX_TBT4 11 3399 #define TGL_PW_CTL_IDX_AUX_TBT3 11 3400 #define ICL_PW_CTL_IDX_AUX_TBT3 10 3401 #define TGL_PW_CTL_IDX_AUX_TBT2 10 3402 #define ICL_PW_CTL_IDX_AUX_TBT2 9 3403 #define TGL_PW_CTL_IDX_AUX_TBT1 9 3404 #define ICL_PW_CTL_IDX_AUX_TBT1 8 3405 #define TGL_PW_CTL_IDX_AUX_TC6 8 3406 #define XELPD_PW_CTL_IDX_AUX_E 8 3407 #define TGL_PW_CTL_IDX_AUX_TC5 7 3408 #define XELPD_PW_CTL_IDX_AUX_D 7 3409 #define TGL_PW_CTL_IDX_AUX_TC4 6 3410 #define ICL_PW_CTL_IDX_AUX_F 5 3411 #define TGL_PW_CTL_IDX_AUX_TC3 5 3412 #define ICL_PW_CTL_IDX_AUX_E 4 3413 #define TGL_PW_CTL_IDX_AUX_TC2 4 3414 #define ICL_PW_CTL_IDX_AUX_D 3 3415 #define TGL_PW_CTL_IDX_AUX_TC1 3 3416 #define ICL_PW_CTL_IDX_AUX_C 2 3417 #define ICL_PW_CTL_IDX_AUX_B 1 3418 #define ICL_PW_CTL_IDX_AUX_A 0 3419 3420 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450) 3421 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454) 3422 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C) 3423 #define XELPD_PW_CTL_IDX_DDI_E 8 3424 #define TGL_PW_CTL_IDX_DDI_TC6 8 3425 #define XELPD_PW_CTL_IDX_DDI_D 7 3426 #define TGL_PW_CTL_IDX_DDI_TC5 7 3427 #define TGL_PW_CTL_IDX_DDI_TC4 6 3428 #define ICL_PW_CTL_IDX_DDI_F 5 3429 #define TGL_PW_CTL_IDX_DDI_TC3 5 3430 #define ICL_PW_CTL_IDX_DDI_E 4 3431 #define TGL_PW_CTL_IDX_DDI_TC2 4 3432 #define ICL_PW_CTL_IDX_DDI_D 3 3433 #define TGL_PW_CTL_IDX_DDI_TC1 3 3434 #define ICL_PW_CTL_IDX_DDI_C 2 3435 #define ICL_PW_CTL_IDX_DDI_B 1 3436 #define ICL_PW_CTL_IDX_DDI_A 0 3437 3438 /* HSW - power well misc debug registers */ 3439 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) 3440 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31) 3441 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20) 3442 #define HSW_PWR_WELL_FORCE_ON (1 << 19) 3443 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) 3444 3445 /* SKL Fuse Status */ 3446 enum skl_power_gate { 3447 SKL_PG0, 3448 SKL_PG1, 3449 SKL_PG2, 3450 ICL_PG3, 3451 ICL_PG4, 3452 }; 3453 3454 #define SKL_FUSE_STATUS _MMIO(0x42000) 3455 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31) 3456 /* 3457 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 3458 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2 3459 */ 3460 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ 3461 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1) 3462 /* 3463 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 3464 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4 3465 */ 3466 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ 3467 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1) 3468 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) 3469 3470 /* Per-pipe DDI Function Control */ 3471 #define _TRANS_DDI_FUNC_CTL_A 0x60400 3472 #define _TRANS_DDI_FUNC_CTL_B 0x61400 3473 #define _TRANS_DDI_FUNC_CTL_C 0x62400 3474 #define _TRANS_DDI_FUNC_CTL_D 0x63400 3475 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 3476 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 3477 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 3478 #define TRANS_DDI_FUNC_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL_A) 3479 3480 #define TRANS_DDI_FUNC_ENABLE (1 << 31) 3481 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 3482 #define TRANS_DDI_PORT_SHIFT 28 3483 #define TGL_TRANS_DDI_PORT_SHIFT 27 3484 #define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT) 3485 #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT) 3486 #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT) 3487 #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT) 3488 #define TRANS_DDI_MODE_SELECT_MASK (7 << 24) 3489 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) 3490 #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) 3491 #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) 3492 #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) 3493 #define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24) 3494 #define TRANS_DDI_BPC_MASK (7 << 20) 3495 #define TRANS_DDI_BPC_8 (0 << 20) 3496 #define TRANS_DDI_BPC_10 (1 << 20) 3497 #define TRANS_DDI_BPC_6 (2 << 20) 3498 #define TRANS_DDI_BPC_12 (3 << 20) 3499 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) 3500 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x)) 3501 #define TRANS_DDI_PVSYNC (1 << 17) 3502 #define TRANS_DDI_PHSYNC (1 << 16) 3503 #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) 3504 #define XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(15) 3505 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12) 3506 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) 3507 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) 3508 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) 3509 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) 3510 #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) 3511 #define TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12) 3512 #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) 3513 #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ 3514 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans) 3515 #define TRANS_DDI_HDCP_SIGNALLING (1 << 9) 3516 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8) 3517 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) 3518 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6) 3519 #define TRANS_DDI_HDCP_SELECT REG_BIT(5) 3520 #define TRANS_DDI_BFI_ENABLE (1 << 4) 3521 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4) 3522 #define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1) 3523 #define TRANS_DDI_PORT_WIDTH(width) REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1) 3524 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0) 3525 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ 3526 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ 3527 | TRANS_DDI_HDMI_SCRAMBLING) 3528 3529 #define _TRANS_DDI_FUNC_CTL2_A 0x60404 3530 #define _TRANS_DDI_FUNC_CTL2_B 0x61404 3531 #define _TRANS_DDI_FUNC_CTL2_C 0x62404 3532 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 3533 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 3534 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 3535 #define TRANS_DDI_FUNC_CTL2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A) 3536 #define PORT_SYNC_MODE_ENABLE REG_BIT(4) 3537 #define CMTG_SECONDARY_MODE REG_BIT(3) 3538 #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0) 3539 #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x)) 3540 3541 #define TRANS_CMTG_CHICKEN _MMIO(0x6fa90) 3542 #define DISABLE_DPT_CLK_GATING REG_BIT(1) 3543 3544 /* DisplayPort Transport Control */ 3545 #define _DP_TP_CTL_A 0x64040 3546 #define _DP_TP_CTL_B 0x64140 3547 #define _TGL_DP_TP_CTL_A 0x60540 3548 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) 3549 #define TGL_DP_TP_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A) 3550 #define DP_TP_CTL_ENABLE REG_BIT(31) 3551 #define DP_TP_CTL_FEC_ENABLE REG_BIT(30) 3552 #define DP_TP_CTL_MODE_MASK REG_BIT(27) 3553 #define DP_TP_CTL_MODE_SST REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 0) 3554 #define DP_TP_CTL_MODE_MST REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 1) 3555 #define DP_TP_CTL_FORCE_ACT REG_BIT(25) 3556 #define DP_TP_CTL_TRAIN_PAT4_SEL_MASK REG_GENMASK(20, 19) 3557 #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 0) 3558 #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 1) 3559 #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 2) 3560 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE REG_BIT(18) 3561 #define DP_TP_CTL_FDI_AUTOTRAIN REG_BIT(15) 3562 #define DP_TP_CTL_LINK_TRAIN_MASK REG_GENMASK(10, 8) 3563 #define DP_TP_CTL_LINK_TRAIN_PAT1 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 0) 3564 #define DP_TP_CTL_LINK_TRAIN_PAT2 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 1) 3565 #define DP_TP_CTL_LINK_TRAIN_PAT3 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 4) 3566 #define DP_TP_CTL_LINK_TRAIN_PAT4 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 5) 3567 #define DP_TP_CTL_LINK_TRAIN_IDLE REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 2) 3568 #define DP_TP_CTL_LINK_TRAIN_NORMAL REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 3) 3569 #define DP_TP_CTL_SCRAMBLE_DISABLE REG_BIT(7) 3570 3571 /* DisplayPort Transport Status */ 3572 #define _DP_TP_STATUS_A 0x64044 3573 #define _DP_TP_STATUS_B 0x64144 3574 #define _TGL_DP_TP_STATUS_A 0x60544 3575 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) 3576 #define TGL_DP_TP_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A) 3577 #define DP_TP_STATUS_FEC_ENABLE_LIVE REG_BIT(28) 3578 #define DP_TP_STATUS_IDLE_DONE REG_BIT(25) 3579 #define DP_TP_STATUS_ACT_SENT REG_BIT(24) 3580 #define DP_TP_STATUS_MODE_STATUS_MST REG_BIT(23) 3581 #define DP_TP_STATUS_STREAMS_ENABLED_MASK REG_GENMASK(18, 16) /* 17:16 on hsw but bit 18 mbz */ 3582 #define DP_TP_STATUS_AUTOTRAIN_DONE REG_BIT(12) 3583 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2_MASK REG_GENMASK(9, 8) 3584 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1_MASK REG_GENMASK(5, 4) 3585 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0_MASK REG_GENMASK(1, 0) 3586 3587 /* DDI Buffer Control */ 3588 #define _DDI_BUF_CTL_A 0x64000 3589 #define _DDI_BUF_CTL_B 0x64100 3590 /* Known as DDI_CTL_DE in MTL+ */ 3591 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) 3592 #define DDI_BUF_CTL_ENABLE REG_BIT(31) 3593 #define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29) 3594 #define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28) 3595 #define DDI_BUF_EMP_MASK REG_GENMASK(27, 24) 3596 #define DDI_BUF_TRANS_SELECT(n) REG_FIELD_PREP(DDI_BUF_EMP_MASK, (n)) 3597 #define DDI_BUF_PHY_LINK_RATE_MASK REG_GENMASK(23, 20) 3598 #define DDI_BUF_PHY_LINK_RATE(r) REG_FIELD_PREP(DDI_BUF_PHY_LINK_RATE_MASK, (r)) 3599 #define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19, 18) 3600 #define DDI_BUF_PORT_DATA_10BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0) 3601 #define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1) 3602 #define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2) 3603 #define DDI_BUF_PORT_REVERSAL REG_BIT(16) 3604 #define DDI_BUF_LANE_STAGGER_DELAY_MASK REG_GENMASK(15, 8) 3605 #define DDI_BUF_LANE_STAGGER_DELAY(symbols) REG_FIELD_PREP(DDI_BUF_LANE_STAGGER_DELAY_MASK, \ 3606 (symbols)) 3607 #define DDI_BUF_IS_IDLE REG_BIT(7) 3608 #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) 3609 #define DDI_A_4_LANES REG_BIT(4) 3610 #define DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1) 3611 #define DDI_PORT_WIDTH(width) REG_FIELD_PREP(DDI_PORT_WIDTH_MASK, \ 3612 ((width) == 3 ? 4 : (width) - 1)) 3613 #define DDI_PORT_WIDTH_SHIFT 1 3614 #define DDI_INIT_DISPLAY_DETECTED REG_BIT(0) 3615 3616 /* DDI Buffer Translations */ 3617 #define _DDI_BUF_TRANS_A 0x64E00 3618 #define _DDI_BUF_TRANS_B 0x64E60 3619 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) 3620 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) 3621 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) 3622 3623 /* DDI DP Compliance Control */ 3624 #define _DDI_DP_COMP_CTL_A 0x605F0 3625 #define _DDI_DP_COMP_CTL_B 0x615F0 3626 #define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) 3627 #define DDI_DP_COMP_CTL_ENABLE (1 << 31) 3628 #define DDI_DP_COMP_CTL_D10_2 (0 << 28) 3629 #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) 3630 #define DDI_DP_COMP_CTL_PRBS7 (2 << 28) 3631 #define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28) 3632 #define DDI_DP_COMP_CTL_HBR2 (4 << 28) 3633 #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) 3634 #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) 3635 3636 /* DDI DP Compliance Pattern */ 3637 #define _DDI_DP_COMP_PAT_A 0x605F4 3638 #define _DDI_DP_COMP_PAT_B 0x615F4 3639 #define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4) 3640 3641 /* Sideband Interface (SBI) is programmed indirectly, via 3642 * SBI_ADDR, which contains the register offset; and SBI_DATA, 3643 * which contains the payload */ 3644 #define SBI_ADDR _MMIO(0xC6000) 3645 #define SBI_DATA _MMIO(0xC6004) 3646 #define SBI_CTL_STAT _MMIO(0xC6008) 3647 #define SBI_CTL_DEST_ICLK (0x0 << 16) 3648 #define SBI_CTL_DEST_MPHY (0x1 << 16) 3649 #define SBI_CTL_OP_IORD (0x2 << 8) 3650 #define SBI_CTL_OP_IOWR (0x3 << 8) 3651 #define SBI_CTL_OP_CRRD (0x6 << 8) 3652 #define SBI_CTL_OP_CRWR (0x7 << 8) 3653 #define SBI_RESPONSE_FAIL (0x1 << 1) 3654 #define SBI_RESPONSE_SUCCESS (0x0 << 1) 3655 #define SBI_BUSY (0x1 << 0) 3656 #define SBI_READY (0x0 << 0) 3657 3658 /* SBI offsets */ 3659 #define SBI_SSCDIVINTPHASE 0x0200 3660 #define SBI_SSCDIVINTPHASE6 0x0600 3661 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 3662 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) 3663 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) 3664 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 3665 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) 3666 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) 3667 #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) 3668 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) 3669 #define SBI_SSCDITHPHASE 0x0204 3670 #define SBI_SSCCTL 0x020c 3671 #define SBI_SSCCTL6 0x060C 3672 #define SBI_SSCCTL_PATHALT (1 << 3) 3673 #define SBI_SSCCTL_DISABLE (1 << 0) 3674 #define SBI_SSCAUXDIV6 0x0610 3675 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 3676 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) 3677 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) 3678 #define SBI_DBUFF0 0x2a00 3679 #define SBI_GEN0 0x1f00 3680 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) 3681 3682 /* LPT PIXCLK_GATE */ 3683 #define PIXCLK_GATE _MMIO(0xC6020) 3684 #define PIXCLK_GATE_UNGATE (1 << 0) 3685 #define PIXCLK_GATE_GATE (0 << 0) 3686 3687 /* SPLL */ 3688 #define SPLL_CTL _MMIO(0x46020) 3689 #define SPLL_PLL_ENABLE (1 << 31) 3690 #define SPLL_REF_BCLK (0 << 28) 3691 #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 3692 #define SPLL_REF_NON_SSC_HSW (2 << 28) 3693 #define SPLL_REF_PCH_SSC_BDW (2 << 28) 3694 #define SPLL_REF_LCPLL (3 << 28) 3695 #define SPLL_REF_MASK (3 << 28) 3696 #define SPLL_FREQ_810MHz (0 << 26) 3697 #define SPLL_FREQ_1350MHz (1 << 26) 3698 #define SPLL_FREQ_2700MHz (2 << 26) 3699 #define SPLL_FREQ_MASK (3 << 26) 3700 3701 /* WRPLL */ 3702 #define _WRPLL_CTL1 0x46040 3703 #define _WRPLL_CTL2 0x46060 3704 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) 3705 #define WRPLL_PLL_ENABLE (1 << 31) 3706 #define WRPLL_REF_BCLK (0 << 28) 3707 #define WRPLL_REF_PCH_SSC (1 << 28) 3708 #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 3709 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */ 3710 #define WRPLL_REF_LCPLL (3 << 28) 3711 #define WRPLL_REF_MASK (3 << 28) 3712 /* WRPLL divider programming */ 3713 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0) 3714 #define WRPLL_DIVIDER_REF_MASK (0xff) 3715 #define WRPLL_DIVIDER_POST(x) ((x) << 8) 3716 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8) 3717 #define WRPLL_DIVIDER_POST_SHIFT 8 3718 #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16) 3719 #define WRPLL_DIVIDER_FB_SHIFT 16 3720 #define WRPLL_DIVIDER_FB_MASK (0xff << 16) 3721 3722 /* Port clock selection */ 3723 #define _PORT_CLK_SEL_A 0x46100 3724 #define _PORT_CLK_SEL_B 0x46104 3725 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) 3726 #define PORT_CLK_SEL_MASK REG_GENMASK(31, 29) 3727 #define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0) 3728 #define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1) 3729 #define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2) 3730 #define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3) 3731 #define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll)) 3732 #define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4) 3733 #define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5) 3734 #define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7) 3735 3736 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ 3737 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port) 3738 #define DDI_CLK_SEL_MASK REG_GENMASK(31, 28) 3739 #define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0) 3740 #define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8) 3741 #define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC) 3742 #define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD) 3743 #define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE) 3744 #define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF) 3745 3746 /* Transcoder clock selection */ 3747 #define _TRANS_CLK_SEL_A 0x46140 3748 #define _TRANS_CLK_SEL_B 0x46144 3749 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) 3750 /* For each transcoder, we need to select the corresponding port clock */ 3751 #define TRANS_CLK_SEL_DISABLED (0x0 << 29) 3752 #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29) 3753 #define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28) 3754 #define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28) 3755 3756 3757 #define CDCLK_FREQ _MMIO(0x46200) 3758 3759 #define _TRANSA_MSA_MISC 0x60410 3760 #define _TRANSB_MSA_MISC 0x61410 3761 #define _TRANSC_MSA_MISC 0x62410 3762 #define _TRANS_EDP_MSA_MISC 0x6f410 3763 #define TRANS_MSA_MISC(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANSA_MSA_MISC) 3764 /* See DP_MSA_MISC_* for the bit definitions */ 3765 3766 #define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C 3767 #define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C 3768 #define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C 3769 #define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C 3770 #define TRANS_SET_CONTEXT_LATENCY(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY) 3771 #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0) 3772 #define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x)) 3773 3774 /* LCPLL Control */ 3775 #define LCPLL_CTL _MMIO(0x130040) 3776 #define LCPLL_PLL_DISABLE (1 << 31) 3777 #define LCPLL_PLL_LOCK (1 << 30) 3778 #define LCPLL_REF_NON_SSC (0 << 28) 3779 #define LCPLL_REF_BCLK (2 << 28) 3780 #define LCPLL_REF_PCH_SSC (3 << 28) 3781 #define LCPLL_REF_MASK (3 << 28) 3782 #define LCPLL_CLK_FREQ_MASK (3 << 26) 3783 #define LCPLL_CLK_FREQ_450 (0 << 26) 3784 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26) 3785 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) 3786 #define LCPLL_CLK_FREQ_675_BDW (3 << 26) 3787 #define LCPLL_CD_CLOCK_DISABLE (1 << 25) 3788 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24) 3789 #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23) 3790 #define LCPLL_POWER_DOWN_ALLOW (1 << 22) 3791 #define LCPLL_CD_SOURCE_FCLK (1 << 21) 3792 #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19) 3793 3794 /* 3795 * SKL Clocks 3796 */ 3797 3798 /* CDCLK_CTL */ 3799 #define CDCLK_CTL _MMIO(0x46000) 3800 #define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26) 3801 #define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0) 3802 #define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1) 3803 #define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2) 3804 #define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3) 3805 #define MDCLK_SOURCE_SEL_MASK REG_GENMASK(25, 25) 3806 #define MDCLK_SOURCE_SEL_CD2XCLK REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 0) 3807 #define MDCLK_SOURCE_SEL_CDCLK_PLL REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 1) 3808 #define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22) 3809 #define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0) 3810 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1) 3811 #define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2) 3812 #define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3) 3813 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) 3814 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) 3815 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) 3816 #define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19) 3817 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) 3818 #define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe) 3819 #define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE 3820 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) 3821 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) 3822 3823 /* CDCLK_SQUASH_CTL */ 3824 #define CDCLK_SQUASH_CTL _MMIO(0x46008) 3825 #define CDCLK_SQUASH_ENABLE REG_BIT(31) 3826 #define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24) 3827 #define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x)) 3828 #define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0) 3829 #define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x)) 3830 3831 /* LCPLL_CTL */ 3832 #define LCPLL1_CTL _MMIO(0x46010) 3833 #define LCPLL2_CTL _MMIO(0x46014) 3834 #define LCPLL_PLL_ENABLE (1 << 31) 3835 3836 /* DPLL control1 */ 3837 #define DPLL_CTRL1 _MMIO(0x6C058) 3838 #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5)) 3839 #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4)) 3840 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1)) 3841 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1) 3842 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1)) 3843 #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6)) 3844 #define DPLL_CTRL1_LINK_RATE_2700 0 3845 #define DPLL_CTRL1_LINK_RATE_1350 1 3846 #define DPLL_CTRL1_LINK_RATE_810 2 3847 #define DPLL_CTRL1_LINK_RATE_1620 3 3848 #define DPLL_CTRL1_LINK_RATE_1080 4 3849 #define DPLL_CTRL1_LINK_RATE_2160 5 3850 3851 /* DPLL control2 */ 3852 #define DPLL_CTRL2 _MMIO(0x6C05C) 3853 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15)) 3854 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1)) 3855 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1) 3856 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1)) 3857 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3)) 3858 3859 /* DPLL Status */ 3860 #define DPLL_STATUS _MMIO(0x6C060) 3861 #define DPLL_LOCK(id) (1 << ((id) * 8)) 3862 3863 /* DPLL cfg */ 3864 #define _DPLL1_CFGCR1 0x6C040 3865 #define _DPLL2_CFGCR1 0x6C048 3866 #define _DPLL3_CFGCR1 0x6C050 3867 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) 3868 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) 3869 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) 3870 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) 3871 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) 3872 3873 #define _DPLL1_CFGCR2 0x6C044 3874 #define _DPLL2_CFGCR2 0x6C04C 3875 #define _DPLL3_CFGCR2 0x6C054 3876 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) 3877 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) 3878 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) 3879 #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) 3880 #define DPLL_CFGCR2_KDIV_MASK (3 << 5) 3881 #define DPLL_CFGCR2_KDIV(x) ((x) << 5) 3882 #define DPLL_CFGCR2_KDIV_5 (0 << 5) 3883 #define DPLL_CFGCR2_KDIV_2 (1 << 5) 3884 #define DPLL_CFGCR2_KDIV_3 (2 << 5) 3885 #define DPLL_CFGCR2_KDIV_1 (3 << 5) 3886 #define DPLL_CFGCR2_PDIV_MASK (7 << 2) 3887 #define DPLL_CFGCR2_PDIV(x) ((x) << 2) 3888 #define DPLL_CFGCR2_PDIV_1 (0 << 2) 3889 #define DPLL_CFGCR2_PDIV_2 (1 << 2) 3890 #define DPLL_CFGCR2_PDIV_3 (2 << 2) 3891 #define DPLL_CFGCR2_PDIV_7 (4 << 2) 3892 #define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2) 3893 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) 3894 3895 /* ICL Clocks */ 3896 #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) 3897 #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5)) 3898 #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) 3899 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ 3900 (tc_port) + 12 : \ 3901 (tc_port) - TC_PORT_4 + 21)) 3902 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) 3903 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 3904 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 3905 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) 3906 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ 3907 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 3908 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ 3909 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 3910 3911 /* 3912 * DG1 Clocks 3913 * First registers controls the first A and B, while the second register 3914 * controls the phy C and D. The bits on these registers are the 3915 * same, but refer to different phys 3916 */ 3917 #define _DG1_DPCLKA_CFGCR0 0x164280 3918 #define _DG1_DPCLKA1_CFGCR0 0x16C280 3919 #define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2) 3920 #define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2) 3921 #define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \ 3922 _DG1_DPCLKA_CFGCR0, \ 3923 _DG1_DPCLKA1_CFGCR0) 3924 #define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10) 3925 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2) 3926 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 3927 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 3928 3929 /* ADLS Clocks */ 3930 #define _ADLS_DPCLKA_CFGCR0 0x164280 3931 #define _ADLS_DPCLKA_CFGCR1 0x1642BC 3932 #define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \ 3933 _ADLS_DPCLKA_CFGCR0, \ 3934 _ADLS_DPCLKA_CFGCR1) 3935 #define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2) 3936 /* ADLS DPCLKA_CFGCR0 DDI mask */ 3937 #define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4) 3938 #define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2) 3939 #define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0) 3940 /* ADLS DPCLKA_CFGCR1 DDI mask */ 3941 #define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2) 3942 #define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0) 3943 #define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \ 3944 ADLS_DPCLKA_DDIA_SEL_MASK, \ 3945 ADLS_DPCLKA_DDIB_SEL_MASK, \ 3946 ADLS_DPCLKA_DDII_SEL_MASK, \ 3947 ADLS_DPCLKA_DDIJ_SEL_MASK, \ 3948 ADLS_DPCLKA_DDIK_SEL_MASK) 3949 3950 /* ICL PLL */ 3951 #define _DPLL0_ENABLE 0x46010 3952 #define _DPLL1_ENABLE 0x46014 3953 #define _ADLS_DPLL2_ENABLE 0x46018 3954 #define _ADLS_DPLL3_ENABLE 0x46030 3955 #define PLL_ENABLE REG_BIT(31) 3956 #define PLL_LOCK REG_BIT(30) 3957 #define PLL_POWER_ENABLE REG_BIT(27) 3958 #define PLL_POWER_STATE REG_BIT(26) 3959 #define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \ 3960 _DPLL0_ENABLE, _DPLL1_ENABLE, \ 3961 _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE)) 3962 3963 #define _DG2_PLL3_ENABLE 0x4601C 3964 3965 #define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \ 3966 _DPLL0_ENABLE, _DPLL1_ENABLE, \ 3967 _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE)) 3968 3969 #define TBT_PLL_ENABLE _MMIO(0x46020) 3970 3971 #define _MG_PLL1_ENABLE 0x46030 3972 #define _MG_PLL2_ENABLE 0x46034 3973 #define _MG_PLL3_ENABLE 0x46038 3974 #define _MG_PLL4_ENABLE 0x4603C 3975 /* Bits are the same as _DPLL0_ENABLE */ 3976 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ 3977 _MG_PLL2_ENABLE) 3978 3979 /* DG1 PLL */ 3980 #define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 3981 _DPLL0_ENABLE, _DPLL1_ENABLE, \ 3982 _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)) 3983 3984 /* ADL-P Type C PLL */ 3985 #define PORTTC1_PLL_ENABLE 0x46038 3986 #define PORTTC2_PLL_ENABLE 0x46040 3987 #define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \ 3988 PORTTC1_PLL_ENABLE, \ 3989 PORTTC2_PLL_ENABLE) 3990 3991 #define _ICL_DPLL0_CFGCR0 0x164000 3992 #define _ICL_DPLL1_CFGCR0 0x164080 3993 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \ 3994 _ICL_DPLL1_CFGCR0) 3995 #define DPLL_CFGCR0_HDMI_MODE (1 << 30) 3996 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29) 3997 #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25) 3998 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) 3999 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) 4000 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) 4001 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) 4002 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) 4003 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) 4004 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) 4005 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) 4006 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) 4007 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) 4008 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) 4009 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) 4010 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) 4011 4012 #define _ICL_DPLL0_CFGCR1 0x164004 4013 #define _ICL_DPLL1_CFGCR1 0x164084 4014 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \ 4015 _ICL_DPLL1_CFGCR1) 4016 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) 4017 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) 4018 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) 4019 #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9) 4020 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) 4021 #define DPLL_CFGCR1_KDIV_MASK (7 << 6) 4022 #define DPLL_CFGCR1_KDIV_SHIFT (6) 4023 #define DPLL_CFGCR1_KDIV(x) ((x) << 6) 4024 #define DPLL_CFGCR1_KDIV_1 (1 << 6) 4025 #define DPLL_CFGCR1_KDIV_2 (2 << 6) 4026 #define DPLL_CFGCR1_KDIV_3 (4 << 6) 4027 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2) 4028 #define DPLL_CFGCR1_PDIV_SHIFT (2) 4029 #define DPLL_CFGCR1_PDIV(x) ((x) << 2) 4030 #define DPLL_CFGCR1_PDIV_2 (1 << 2) 4031 #define DPLL_CFGCR1_PDIV_3 (2 << 2) 4032 #define DPLL_CFGCR1_PDIV_5 (4 << 2) 4033 #define DPLL_CFGCR1_PDIV_7 (8 << 2) 4034 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) 4035 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0) 4036 #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0) 4037 4038 #define _TGL_DPLL0_CFGCR0 0x164284 4039 #define _TGL_DPLL1_CFGCR0 0x16428C 4040 #define _TGL_TBTPLL_CFGCR0 0x16429C 4041 #define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 4042 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ 4043 _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0)) 4044 #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ 4045 _TGL_DPLL1_CFGCR0) 4046 4047 #define _TGL_DPLL0_DIV0 0x164B00 4048 #define _TGL_DPLL1_DIV0 0x164C00 4049 #define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0) 4050 #define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) 4051 #define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val)) 4052 4053 #define _TGL_DPLL0_CFGCR1 0x164288 4054 #define _TGL_DPLL1_CFGCR1 0x164290 4055 #define _TGL_TBTPLL_CFGCR1 0x1642A0 4056 #define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 4057 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ 4058 _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1)) 4059 #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ 4060 _TGL_DPLL1_CFGCR1) 4061 4062 #define _DG1_DPLL2_CFGCR0 0x16C284 4063 #define _DG1_DPLL3_CFGCR0 0x16C28C 4064 #define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 4065 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ 4066 _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0)) 4067 4068 #define _DG1_DPLL2_CFGCR1 0x16C288 4069 #define _DG1_DPLL3_CFGCR1 0x16C290 4070 #define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 4071 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ 4072 _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1)) 4073 4074 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */ 4075 #define _ADLS_DPLL4_CFGCR0 0x164294 4076 #define _ADLS_DPLL3_CFGCR0 0x1642C0 4077 #define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 4078 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ 4079 _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0)) 4080 4081 #define _ADLS_DPLL4_CFGCR1 0x164298 4082 #define _ADLS_DPLL3_CFGCR1 0x1642C4 4083 #define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 4084 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ 4085 _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1)) 4086 4087 /* BXT display engine PLL */ 4088 #define BXT_DE_PLL_CTL _MMIO(0x6d000) 4089 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ 4090 #define BXT_DE_PLL_RATIO_MASK 0xff 4091 4092 #define BXT_DE_PLL_ENABLE _MMIO(0x46070) 4093 #define BXT_DE_PLL_PLL_ENABLE (1 << 31) 4094 #define BXT_DE_PLL_LOCK (1 << 30) 4095 #define BXT_DE_PLL_FREQ_REQ (1 << 23) 4096 #define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22) 4097 #define ICL_CDCLK_PLL_RATIO(x) (x) 4098 #define ICL_CDCLK_PLL_RATIO_MASK 0xff 4099 4100 /* GEN9 DC */ 4101 #define DC_STATE_EN _MMIO(0x45504) 4102 #define DC_STATE_DISABLE 0 4103 #define DC_STATE_EN_DC3CO REG_BIT(30) 4104 #define DC_STATE_DC3CO_STATUS REG_BIT(29) 4105 #define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21) 4106 #define HOLD_PHY_PG1_LATCH REG_BIT(20) 4107 #define DC_STATE_EN_UPTO_DC5 (1 << 0) 4108 #define DC_STATE_EN_DC9 (1 << 3) 4109 #define DC_STATE_EN_UPTO_DC6 (2 << 0) 4110 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 4111 4112 #define DC_STATE_DEBUG _MMIO(0x45520) 4113 #define DC_STATE_DEBUG_MASK_CORES (1 << 0) 4114 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) 4115 4116 #define D_COMP_BDW _MMIO(0x138144) 4117 4118 /* Pipe WM_LINETIME - watermark line time */ 4119 #define _WM_LINETIME_A 0x45270 4120 #define _WM_LINETIME_B 0x45274 4121 #define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B) 4122 #define HSW_LINETIME_MASK REG_GENMASK(8, 0) 4123 #define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x)) 4124 #define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16) 4125 #define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x)) 4126 4127 /* SFUSE_STRAP */ 4128 #define SFUSE_STRAP _MMIO(0xc2014) 4129 #define SFUSE_STRAP_FUSE_LOCK (1 << 13) 4130 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) 4131 #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7) 4132 #define SFUSE_STRAP_CRT_DISABLED (1 << 6) 4133 #define SFUSE_STRAP_DDIF_DETECTED (1 << 3) 4134 #define SFUSE_STRAP_DDIB_DETECTED (1 << 2) 4135 #define SFUSE_STRAP_DDIC_DETECTED (1 << 1) 4136 #define SFUSE_STRAP_DDID_DETECTED (1 << 0) 4137 4138 /* Gen4+ Timestamp and Pipe Frame time stamp registers */ 4139 #define GEN4_TIMESTAMP _MMIO(0x2358) 4140 #define ILK_TIMESTAMP_HI _MMIO(0x70070) 4141 #define IVB_TIMESTAMP_CTR _MMIO(0x44070) 4142 4143 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) 4144 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 4145 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff 4146 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 4147 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) 4148 4149 /* g4x+, except vlv/chv! */ 4150 #define _PIPE_FRMTMSTMP_A 0x70048 4151 #define _PIPE_FRMTMSTMP_B 0x71048 4152 #define PIPE_FRMTMSTMP(pipe) \ 4153 _MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B) 4154 4155 /* g4x+, except vlv/chv! */ 4156 #define _PIPE_FLIPTMSTMP_A 0x7004C 4157 #define _PIPE_FLIPTMSTMP_B 0x7104C 4158 #define PIPE_FLIPTMSTMP(pipe) \ 4159 _MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B) 4160 4161 /* tgl+ */ 4162 #define _PIPE_FLIPDONETMSTMP_A 0x70054 4163 #define _PIPE_FLIPDONETMSTMP_B 0x71054 4164 #define PIPE_FLIPDONETIMSTMP(pipe) \ 4165 _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B) 4166 4167 #define _VLV_PIPE_MSA_MISC_A 0x70048 4168 #define VLV_PIPE_MSA_MISC(__display, pipe) \ 4169 _MMIO_PIPE2(__display, pipe, _VLV_PIPE_MSA_MISC_A) 4170 #define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31) 4171 #define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */ 4172 4173 #define GGC _MMIO(0x108040) 4174 #define GMS_MASK REG_GENMASK(15, 8) 4175 #define GGMS_MASK REG_GENMASK(7, 6) 4176 4177 #define GEN6_GSMBASE _MMIO(0x108100) 4178 #define GEN6_DSMBASE _MMIO(0x1080C0) 4179 #define GEN6_BDSM_MASK REG_GENMASK64(31, 20) 4180 #define GEN11_BDSM_MASK REG_GENMASK64(63, 20) 4181 4182 #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014) 4183 #define SGSI_SIDECLK_DIS REG_BIT(17) 4184 #define SGGI_DIS REG_BIT(15) 4185 #define SGR_DIS REG_BIT(13) 4186 4187 #define _ICL_PHY_MISC_A 0x64C00 4188 #define _ICL_PHY_MISC_B 0x64C04 4189 #define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */ 4190 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B) 4191 #define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \ 4192 ICL_PHY_MISC(port)) 4193 #define ICL_PHY_MISC_MUX_DDID (1 << 28) 4194 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23) 4195 #define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20) 4196 4197 #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0) 4198 #define MODULAR_FIA_MASK (1 << 4) 4199 #define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6)) 4200 #define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5)) 4201 #define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8) 4202 #define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8)) 4203 #define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8)) 4204 4205 #define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890) 4206 #define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx)) 4207 4208 #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894) 4209 #define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx)) 4210 4211 #define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880) 4212 #define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4) 4213 #define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4)) 4214 #define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4)) 4215 4216 #define _TCSS_DDI_STATUS_1 0x161500 4217 #define _TCSS_DDI_STATUS_2 0x161504 4218 #define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \ 4219 _TCSS_DDI_STATUS_1, \ 4220 _TCSS_DDI_STATUS_2)) 4221 #define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25) 4222 #define TCSS_DDI_STATUS_READY REG_BIT(2) 4223 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1) 4224 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0) 4225 4226 #define PRIMARY_SPI_TRIGGER _MMIO(0x102040) 4227 #define PRIMARY_SPI_ADDRESS _MMIO(0x102080) 4228 #define PRIMARY_SPI_REGIONID _MMIO(0x102084) 4229 #define SPI_STATIC_REGIONS _MMIO(0x102090) 4230 #define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0) 4231 #define OROM_OFFSET _MMIO(0x1020c0) 4232 #define OROM_OFFSET_MASK REG_GENMASK(20, 16) 4233 4234 #define CLKREQ_POLICY _MMIO(0x101038) 4235 #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1) 4236 4237 #define CLKGATE_DIS_MISC _MMIO(0x46534) 4238 #define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21) 4239 4240 #define _MTL_CLKGATE_DIS_TRANS_A 0x604E8 4241 #define _MTL_CLKGATE_DIS_TRANS_B 0x614E8 4242 #define MTL_CLKGATE_DIS_TRANS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A) 4243 #define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7) 4244 4245 #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) 4246 #define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8) 4247 #define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4) 4248 #define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0) 4249 4250 #define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710 4251 #define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8) 4252 #define MTL_TRCD_MASK REG_GENMASK(31, 24) 4253 #define MTL_TRP_MASK REG_GENMASK(23, 16) 4254 #define MTL_DCLK_MASK REG_GENMASK(15, 0) 4255 4256 #define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 + 4) 4257 #define MTL_TRAS_MASK REG_GENMASK(16, 8) 4258 #define MTL_TRDPRE_MASK REG_GENMASK(7, 0) 4259 4260 #define MTL_MEDIA_GSI_BASE 0x380000 4261 4262 #endif /* _I915_REG_H_ */ 4263