xref: /linux/drivers/gpu/drm/xe/xe_guc_fwif.h (revision 2c1ed907520c50326b8f604907a8478b27881a2e)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #ifndef _XE_GUC_FWIF_H
7 #define _XE_GUC_FWIF_H
8 
9 #include <linux/bits.h>
10 
11 #include "abi/guc_capture_abi.h"
12 #include "abi/guc_klvs_abi.h"
13 #include "xe_hw_engine_types.h"
14 
15 #define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET	4
16 #define G2H_LEN_DW_DEREGISTER_CONTEXT		3
17 #define G2H_LEN_DW_TLB_INVALIDATE		3
18 
19 #define GUC_ID_MAX			65535
20 #define GUC_ID_UNKNOWN			0xffffffff
21 
22 #define GUC_CONTEXT_DISABLE		0
23 #define GUC_CONTEXT_ENABLE		1
24 
25 #define GUC_CLIENT_PRIORITY_KMD_HIGH	0
26 #define GUC_CLIENT_PRIORITY_HIGH	1
27 #define GUC_CLIENT_PRIORITY_KMD_NORMAL	2
28 #define GUC_CLIENT_PRIORITY_NORMAL	3
29 #define GUC_CLIENT_PRIORITY_NUM		4
30 
31 #define GUC_RENDER_ENGINE		0
32 #define GUC_VIDEO_ENGINE		1
33 #define GUC_BLITTER_ENGINE		2
34 #define GUC_VIDEOENHANCE_ENGINE		3
35 #define GUC_VIDEO_ENGINE2		4
36 #define GUC_MAX_ENGINES_NUM		(GUC_VIDEO_ENGINE2 + 1)
37 
38 #define GUC_RENDER_CLASS		0
39 #define GUC_VIDEO_CLASS			1
40 #define GUC_VIDEOENHANCE_CLASS		2
41 #define GUC_BLITTER_CLASS		3
42 #define GUC_COMPUTE_CLASS		4
43 #define GUC_GSC_OTHER_CLASS		5
44 #define GUC_LAST_ENGINE_CLASS		GUC_GSC_OTHER_CLASS
45 #define GUC_MAX_ENGINE_CLASSES		16
46 #define GUC_MAX_INSTANCES_PER_CLASS	32
47 
48 /* Helper for context registration H2G */
49 struct guc_ctxt_registration_info {
50 	u32 flags;
51 	u32 context_idx;
52 	u32 engine_class;
53 	u32 engine_submit_mask;
54 	u32 wq_desc_lo;
55 	u32 wq_desc_hi;
56 	u32 wq_base_lo;
57 	u32 wq_base_hi;
58 	u32 wq_size;
59 	u32 hwlrca_lo;
60 	u32 hwlrca_hi;
61 };
62 #define CONTEXT_REGISTRATION_FLAG_KMD	BIT(0)
63 
64 /* 32-bit KLV structure as used by policy updates and others */
65 struct guc_klv_generic_dw_t {
66 	u32 kl;
67 	u32 value;
68 } __packed;
69 
70 /* Format of the UPDATE_CONTEXT_POLICIES H2G data packet */
71 struct guc_update_exec_queue_policy_header {
72 	u32 action;
73 	u32 guc_id;
74 } __packed;
75 
76 struct guc_update_exec_queue_policy {
77 	struct guc_update_exec_queue_policy_header header;
78 	struct guc_klv_generic_dw_t klv[GUC_CONTEXT_POLICIES_KLV_NUM_IDS];
79 } __packed;
80 
81 /* GUC_CTL_* - Parameters for loading the GuC */
82 #define GUC_CTL_LOG_PARAMS		0
83 #define   GUC_LOG_VALID			BIT(0)
84 #define   GUC_LOG_NOTIFY_ON_HALF_FULL	BIT(1)
85 #define   GUC_LOG_CAPTURE_ALLOC_UNITS	BIT(2)
86 #define   GUC_LOG_LOG_ALLOC_UNITS	BIT(3)
87 #define   GUC_LOG_CRASH_SHIFT		4
88 #define   GUC_LOG_CRASH_MASK		(0x3 << GUC_LOG_CRASH_SHIFT)
89 #define   GUC_LOG_DEBUG_SHIFT		6
90 #define   GUC_LOG_DEBUG_MASK	        (0xF << GUC_LOG_DEBUG_SHIFT)
91 #define   GUC_LOG_CAPTURE_SHIFT		10
92 #define   GUC_LOG_CAPTURE_MASK	        (0x3 << GUC_LOG_CAPTURE_SHIFT)
93 #define   GUC_LOG_BUF_ADDR_SHIFT	12
94 
95 #define GUC_CTL_WA			1
96 #define   GUC_WA_GAM_CREDITS		BIT(10)
97 #define   GUC_WA_DUAL_QUEUE		BIT(11)
98 #define   GUC_WA_RCS_RESET_BEFORE_RC6	BIT(13)
99 #define   GUC_WA_CONTEXT_ISOLATION	BIT(15)
100 #define   GUC_WA_PRE_PARSER		BIT(14)
101 #define   GUC_WA_HOLD_CCS_SWITCHOUT	BIT(17)
102 #define   GUC_WA_POLLCS			BIT(18)
103 #define   GUC_WA_RENDER_RST_RC6_EXIT	BIT(19)
104 #define   GUC_WA_RCS_REGS_IN_CCS_REGS_LIST	BIT(21)
105 #define   GUC_WA_ENABLE_TSC_CHECK_ON_RC6	BIT(22)
106 
107 #define GUC_CTL_FEATURE			2
108 #define   GUC_CTL_ENABLE_SLPC		BIT(2)
109 #define   GUC_CTL_ENABLE_LITE_RESTORE	BIT(4)
110 #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
111 
112 #define GUC_CTL_DEBUG			3
113 #define   GUC_LOG_VERBOSITY_SHIFT	0
114 #define   GUC_LOG_VERBOSITY_LOW		(0 << GUC_LOG_VERBOSITY_SHIFT)
115 #define   GUC_LOG_VERBOSITY_MED		(1 << GUC_LOG_VERBOSITY_SHIFT)
116 #define   GUC_LOG_VERBOSITY_HIGH	(2 << GUC_LOG_VERBOSITY_SHIFT)
117 #define   GUC_LOG_VERBOSITY_ULTRA	(3 << GUC_LOG_VERBOSITY_SHIFT)
118 #define	  GUC_LOG_VERBOSITY_MIN		0
119 #define	  GUC_LOG_VERBOSITY_MAX		3
120 #define	  GUC_LOG_VERBOSITY_MASK	0x0000000f
121 #define	  GUC_LOG_DESTINATION_MASK	(3 << 4)
122 #define   GUC_LOG_DISABLED		(1 << 6)
123 #define   GUC_PROFILE_ENABLED		(1 << 7)
124 
125 #define GUC_CTL_ADS			4
126 #define   GUC_ADS_ADDR_SHIFT		1
127 #define   GUC_ADS_ADDR_MASK		(0xFFFFF << GUC_ADS_ADDR_SHIFT)
128 
129 #define GUC_CTL_DEVID			5
130 
131 #define GUC_CTL_MAX_DWORDS		14
132 
133 /* Scheduling policy settings */
134 
135 #define GLOBAL_POLICY_MAX_NUM_WI 15
136 
137 /* Don't reset an engine upon preemption failure */
138 #define GLOBAL_POLICY_DISABLE_ENGINE_RESET				BIT(0)
139 
140 #define GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000
141 
142 struct guc_policies {
143 	u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];
144 	/*
145 	 * In micro seconds. How much time to allow before DPC processing is
146 	 * called back via interrupt (to prevent DPC queue drain starving).
147 	 * Typically 1000s of micro seconds (example only, not granularity).
148 	 */
149 	u32 dpc_promote_time;
150 
151 	/* Must be set to take these new values. */
152 	u32 is_valid;
153 
154 	/*
155 	 * Max number of WIs to process per call. A large value may keep CS
156 	 * idle.
157 	 */
158 	u32 max_num_work_items;
159 
160 	u32 global_flags;
161 	u32 reserved[4];
162 } __packed;
163 
164 /* Generic GT SysInfo data types */
165 #define GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED		0
166 #define GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK	1
167 #define GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI	2
168 #define GUC_GENERIC_GT_SYSINFO_MAX			16
169 
170 /* HW info */
171 struct guc_gt_system_info {
172 	u8 mapping_table[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
173 	u32 engine_enabled_masks[GUC_MAX_ENGINE_CLASSES];
174 	u32 generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_MAX];
175 } __packed;
176 
177 /* GuC Additional Data Struct */
178 struct guc_ads {
179 	struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
180 	u32 reserved0;
181 	u32 scheduler_policies;
182 	u32 gt_system_info;
183 	u32 reserved1;
184 	u32 control_data;
185 	u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];
186 	u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];
187 	u32 private_data;
188 	u32 um_init_data;
189 	u32 capture_instance[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
190 	u32 capture_class[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
191 	u32 capture_global[GUC_CAPTURE_LIST_INDEX_MAX];
192 	u32 wa_klv_addr_lo;
193 	u32 wa_klv_addr_hi;
194 	u32 wa_klv_size;
195 	u32 reserved[11];
196 } __packed;
197 
198 /* Engine usage stats */
199 struct guc_engine_usage_record {
200 	u32 current_context_index;
201 	u32 last_switch_in_stamp;
202 	u32 reserved0;
203 	u32 total_runtime;
204 	u32 reserved1[4];
205 } __packed;
206 
207 struct guc_engine_usage {
208 	struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
209 } __packed;
210 
211 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
212 enum xe_guc_recv_message {
213 	XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
214 	XE_GUC_RECV_MSG_EXCEPTION = BIT(30),
215 };
216 
217 /* Page fault structures */
218 struct access_counter_desc {
219 	u32 dw0;
220 #define ACCESS_COUNTER_TYPE	BIT(0)
221 #define ACCESS_COUNTER_SUBG_LO	GENMASK(31, 1)
222 
223 	u32 dw1;
224 #define ACCESS_COUNTER_SUBG_HI	BIT(0)
225 #define ACCESS_COUNTER_RSVD0	GENMASK(2, 1)
226 #define ACCESS_COUNTER_ENG_INSTANCE	GENMASK(8, 3)
227 #define ACCESS_COUNTER_ENG_CLASS	GENMASK(11, 9)
228 #define ACCESS_COUNTER_ASID	GENMASK(31, 12)
229 
230 	u32 dw2;
231 #define ACCESS_COUNTER_VFID	GENMASK(5, 0)
232 #define ACCESS_COUNTER_RSVD1	GENMASK(7, 6)
233 #define ACCESS_COUNTER_GRANULARITY	GENMASK(10, 8)
234 #define ACCESS_COUNTER_RSVD2	GENMASK(16, 11)
235 #define ACCESS_COUNTER_VIRTUAL_ADDR_RANGE_LO	GENMASK(31, 17)
236 
237 	u32 dw3;
238 #define ACCESS_COUNTER_VIRTUAL_ADDR_RANGE_HI	GENMASK(31, 0)
239 } __packed;
240 
241 enum guc_um_queue_type {
242 	GUC_UM_HW_QUEUE_PAGE_FAULT = 0,
243 	GUC_UM_HW_QUEUE_PAGE_FAULT_RESPONSE,
244 	GUC_UM_HW_QUEUE_ACCESS_COUNTER,
245 	GUC_UM_HW_QUEUE_MAX
246 };
247 
248 struct guc_um_queue_params {
249 	u64 base_dpa;
250 	u32 base_ggtt_address;
251 	u32 size_in_bytes;
252 	u32 rsvd[4];
253 } __packed;
254 
255 struct guc_um_init_params {
256 	u64 page_response_timeout_in_us;
257 	u32 rsvd[6];
258 	struct guc_um_queue_params queue_params[GUC_UM_HW_QUEUE_MAX];
259 } __packed;
260 
261 enum xe_guc_fault_reply_type {
262 	PFR_ACCESS = 0,
263 	PFR_ENGINE,
264 	PFR_VFID,
265 	PFR_ALL,
266 	PFR_INVALID
267 };
268 
269 enum xe_guc_response_desc_type {
270 	TLB_INVALIDATION_DESC = 0,
271 	FAULT_RESPONSE_DESC
272 };
273 
274 struct xe_guc_pagefault_desc {
275 	u32 dw0;
276 #define PFD_FAULT_LEVEL		GENMASK(2, 0)
277 #define PFD_SRC_ID		GENMASK(10, 3)
278 #define PFD_RSVD_0		GENMASK(17, 11)
279 #define XE2_PFD_TRVA_FAULT	BIT(18)
280 #define PFD_ENG_INSTANCE	GENMASK(24, 19)
281 #define PFD_ENG_CLASS		GENMASK(27, 25)
282 #define PFD_PDATA_LO		GENMASK(31, 28)
283 
284 	u32 dw1;
285 #define PFD_PDATA_HI		GENMASK(11, 0)
286 #define PFD_PDATA_HI_SHIFT	4
287 #define PFD_ASID		GENMASK(31, 12)
288 
289 	u32 dw2;
290 #define PFD_ACCESS_TYPE		GENMASK(1, 0)
291 #define PFD_FAULT_TYPE		GENMASK(3, 2)
292 #define PFD_VFID		GENMASK(9, 4)
293 #define PFD_RSVD_1		GENMASK(11, 10)
294 #define PFD_VIRTUAL_ADDR_LO	GENMASK(31, 12)
295 #define PFD_VIRTUAL_ADDR_LO_SHIFT 12
296 
297 	u32 dw3;
298 #define PFD_VIRTUAL_ADDR_HI	GENMASK(31, 0)
299 #define PFD_VIRTUAL_ADDR_HI_SHIFT 32
300 } __packed;
301 
302 struct xe_guc_pagefault_reply {
303 	u32 dw0;
304 #define PFR_VALID		BIT(0)
305 #define PFR_SUCCESS		BIT(1)
306 #define PFR_REPLY		GENMASK(4, 2)
307 #define PFR_RSVD_0		GENMASK(9, 5)
308 #define PFR_DESC_TYPE		GENMASK(11, 10)
309 #define PFR_ASID		GENMASK(31, 12)
310 
311 	u32 dw1;
312 #define PFR_VFID		GENMASK(5, 0)
313 #define PFR_RSVD_1		BIT(6)
314 #define PFR_ENG_INSTANCE	GENMASK(12, 7)
315 #define PFR_ENG_CLASS		GENMASK(15, 13)
316 #define PFR_PDATA		GENMASK(31, 16)
317 
318 	u32 dw2;
319 #define PFR_RSVD_2		GENMASK(31, 0)
320 } __packed;
321 
322 struct xe_guc_acc_desc {
323 	u32 dw0;
324 #define ACC_TYPE	BIT(0)
325 #define ACC_TRIGGER	0
326 #define ACC_NOTIFY	1
327 #define ACC_SUBG_LO	GENMASK(31, 1)
328 
329 	u32 dw1;
330 #define ACC_SUBG_HI	BIT(0)
331 #define ACC_RSVD0	GENMASK(2, 1)
332 #define ACC_ENG_INSTANCE	GENMASK(8, 3)
333 #define ACC_ENG_CLASS	GENMASK(11, 9)
334 #define ACC_ASID	GENMASK(31, 12)
335 
336 	u32 dw2;
337 #define ACC_VFID	GENMASK(5, 0)
338 #define ACC_RSVD1	GENMASK(7, 6)
339 #define ACC_GRANULARITY	GENMASK(10, 8)
340 #define ACC_RSVD2	GENMASK(16, 11)
341 #define ACC_VIRTUAL_ADDR_RANGE_LO	GENMASK(31, 17)
342 
343 	u32 dw3;
344 #define ACC_VIRTUAL_ADDR_RANGE_HI	GENMASK(31, 0)
345 } __packed;
346 
347 #endif
348