1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2024, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* Machine generated file. Do not edit. */ 33 34 #ifndef _ICE_HW_AUTOGEN_H_ 35 #define _ICE_HW_AUTOGEN_H_ 36 37 #define PRTMAC_CTL_TX_PAUSE_ENABLE_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_TX_PAUSE_ENABLE : E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE) 38 #define PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_S_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_S : E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_S) 39 #define PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_M : E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_M) 40 #define PRTMAC_CTL_RX_PAUSE_ENABLE_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_RX_PAUSE_ENABLE : E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE) 41 #define PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_S_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_S : E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_S) 42 #define PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_M : E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_M) 43 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE(_i) (0x000FD000 + ((_i) * 64)) /* _i=0...7 */ /* Reset Source: CORER */ 44 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_MAX_INDEX 7 45 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_START_S 0 46 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_START_M MAKEMASK(0x3F, 0) 47 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_END_S 6 48 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_END_M MAKEMASK(0x3F, 6) 49 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_VM_VF_TYPE_S 12 50 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_VM_VF_TYPE_M MAKEMASK(0x3, 12) 51 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_VM_VF_NUM_S 14 52 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_VM_VF_NUM_M MAKEMASK(0x3FF, 14) 53 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_PF_NUM_S 24 54 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_PF_NUM_M MAKEMASK(0x7, 24) 55 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_ENABLE_S 31 56 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_ENABLE_M BIT(31) 57 #define GL_HIDA(_i) (0x00082000 + ((_i) * 4)) 58 #define GL_HIBA(_i) (0x00081000 + ((_i) * 4)) 59 #define GL_HICR 0x00082040 60 #define GL_HICR_EN 0x00082044 61 #define GLGEN_CSR_DEBUG_C 0x00075750 62 #define GLNVM_GENS 0x000B6100 63 #define GLNVM_FLA 0x000B6108 64 #define GL_HIDA_MAX_INDEX 15 65 #define GL_HIBA_MAX_INDEX 1023 66 #define GL_MNG_FWSM_FW_LOADING_M BIT(30) 67 #define GL_RDPU_CNTRL 0x00052054 /* Reset Source: CORER */ 68 #define GL_RDPU_CNTRL_RX_PAD_EN_S 0 69 #define GL_RDPU_CNTRL_RX_PAD_EN_M BIT(0) 70 #define GL_RDPU_CNTRL_UDP_ZERO_EN_S 1 71 #define GL_RDPU_CNTRL_UDP_ZERO_EN_M BIT(1) 72 #define GL_RDPU_CNTRL_BLNC_EN_S 2 73 #define GL_RDPU_CNTRL_BLNC_EN_M BIT(2) 74 #define GL_RDPU_CNTRL_RECIPE_BYPASS_S 3 75 #define GL_RDPU_CNTRL_RECIPE_BYPASS_M BIT(3) 76 #define GL_RDPU_CNTRL_RLAN_ACK_REQ_PM_TH_S 4 77 #define GL_RDPU_CNTRL_RLAN_ACK_REQ_PM_TH_M MAKEMASK(0x3F, 4) 78 #define GL_RDPU_CNTRL_PE_ACK_REQ_PM_TH_S 10 79 #define GL_RDPU_CNTRL_PE_ACK_REQ_PM_TH_M MAKEMASK(0x3F, 10) 80 #define GL_RDPU_CNTRL_REQ_WB_PM_TH_S 16 81 #define GL_RDPU_CNTRL_REQ_WB_PM_TH_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_RDPU_CNTRL_REQ_WB_PM_TH_M : E800_GL_RDPU_CNTRL_REQ_WB_PM_TH_M) 82 #define E800_GL_RDPU_CNTRL_REQ_WB_PM_TH_M MAKEMASK(0x1F, 16) 83 #define E830_GL_RDPU_CNTRL_REQ_WB_PM_TH_M MAKEMASK(0x3F, 16) 84 #define GL_RDPU_CNTRL_ECO_S_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_RDPU_CNTRL_ECO_S : E800_GL_RDPU_CNTRL_ECO_S) 85 #define E800_GL_RDPU_CNTRL_ECO_S 21 86 #define E830_GL_RDPU_CNTRL_ECO_S 23 87 #define GL_RDPU_CNTRL_ECO_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_RDPU_CNTRL_ECO_M : E800_GL_RDPU_CNTRL_ECO_M) 88 #define E800_GL_RDPU_CNTRL_ECO_M MAKEMASK(0x7FF, 21) 89 #define E830_GL_RDPU_CNTRL_ECO_M MAKEMASK(0x1FF, 23) 90 #define MSIX_PBA(_i) (0x00008000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: FLR */ 91 #define MSIX_PBA_MAX_INDEX 2 92 #define MSIX_PBA_PENBIT_S 0 93 #define MSIX_PBA_PENBIT_M MAKEMASK(0xFFFFFFFF, 0) 94 #define MSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */ 95 #define MSIX_TADD_MAX_INDEX 64 96 #define MSIX_TADD_MSIXTADD10_S 0 97 #define MSIX_TADD_MSIXTADD10_M MAKEMASK(0x3, 0) 98 #define MSIX_TADD_MSIXTADD_S 2 99 #define MSIX_TADD_MSIXTADD_M MAKEMASK(0x3FFFFFFF, 2) 100 #define MSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */ 101 #define MSIX_TUADD_MAX_INDEX 64 102 #define MSIX_TUADD_MSIXTUADD_S 0 103 #define MSIX_TUADD_MSIXTUADD_M MAKEMASK(0xFFFFFFFF, 0) 104 #define MSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */ 105 #define MSIX_TVCTRL_MAX_INDEX 64 106 #define MSIX_TVCTRL_MASK_S 0 107 #define MSIX_TVCTRL_MASK_M BIT(0) 108 #define PF0_FW_HLP_ARQBAH_PAGE 0x02D00180 /* Reset Source: EMPR */ 109 #define PF0_FW_HLP_ARQBAH_PAGE_ARQBAH_S 0 110 #define PF0_FW_HLP_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 111 #define PF0_FW_HLP_ARQBAL_PAGE 0x02D00080 /* Reset Source: EMPR */ 112 #define PF0_FW_HLP_ARQBAL_PAGE_ARQBAL_LSB_S 0 113 #define PF0_FW_HLP_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 114 #define PF0_FW_HLP_ARQBAL_PAGE_ARQBAL_S 6 115 #define PF0_FW_HLP_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 116 #define PF0_FW_HLP_ARQH_PAGE 0x02D00380 /* Reset Source: EMPR */ 117 #define PF0_FW_HLP_ARQH_PAGE_ARQH_S 0 118 #define PF0_FW_HLP_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0) 119 #define PF0_FW_HLP_ARQLEN_PAGE 0x02D00280 /* Reset Source: EMPR */ 120 #define PF0_FW_HLP_ARQLEN_PAGE_ARQLEN_S 0 121 #define PF0_FW_HLP_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0) 122 #define PF0_FW_HLP_ARQLEN_PAGE_ARQVFE_S 28 123 #define PF0_FW_HLP_ARQLEN_PAGE_ARQVFE_M BIT(28) 124 #define PF0_FW_HLP_ARQLEN_PAGE_ARQOVFL_S 29 125 #define PF0_FW_HLP_ARQLEN_PAGE_ARQOVFL_M BIT(29) 126 #define PF0_FW_HLP_ARQLEN_PAGE_ARQCRIT_S 30 127 #define PF0_FW_HLP_ARQLEN_PAGE_ARQCRIT_M BIT(30) 128 #define PF0_FW_HLP_ARQLEN_PAGE_ARQENABLE_S 31 129 #define PF0_FW_HLP_ARQLEN_PAGE_ARQENABLE_M BIT(31) 130 #define PF0_FW_HLP_ARQT_PAGE 0x02D00480 /* Reset Source: EMPR */ 131 #define PF0_FW_HLP_ARQT_PAGE_ARQT_S 0 132 #define PF0_FW_HLP_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0) 133 #define PF0_FW_HLP_ATQBAH_PAGE 0x02D00100 /* Reset Source: EMPR */ 134 #define PF0_FW_HLP_ATQBAH_PAGE_ATQBAH_S 0 135 #define PF0_FW_HLP_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 136 #define PF0_FW_HLP_ATQBAL_PAGE 0x02D00000 /* Reset Source: EMPR */ 137 #define PF0_FW_HLP_ATQBAL_PAGE_ATQBAL_LSB_S 0 138 #define PF0_FW_HLP_ATQBAL_PAGE_ATQBAL_LSB_M MAKEMASK(0x3F, 0) 139 #define PF0_FW_HLP_ATQBAL_PAGE_ATQBAL_S 6 140 #define PF0_FW_HLP_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 141 #define PF0_FW_HLP_ATQH_PAGE 0x02D00300 /* Reset Source: EMPR */ 142 #define PF0_FW_HLP_ATQH_PAGE_ATQH_S 0 143 #define PF0_FW_HLP_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0) 144 #define PF0_FW_HLP_ATQLEN_PAGE 0x02D00200 /* Reset Source: EMPR */ 145 #define PF0_FW_HLP_ATQLEN_PAGE_ATQLEN_S 0 146 #define PF0_FW_HLP_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0) 147 #define PF0_FW_HLP_ATQLEN_PAGE_ATQVFE_S 28 148 #define PF0_FW_HLP_ATQLEN_PAGE_ATQVFE_M BIT(28) 149 #define PF0_FW_HLP_ATQLEN_PAGE_ATQOVFL_S 29 150 #define PF0_FW_HLP_ATQLEN_PAGE_ATQOVFL_M BIT(29) 151 #define PF0_FW_HLP_ATQLEN_PAGE_ATQCRIT_S 30 152 #define PF0_FW_HLP_ATQLEN_PAGE_ATQCRIT_M BIT(30) 153 #define PF0_FW_HLP_ATQLEN_PAGE_ATQENABLE_S 31 154 #define PF0_FW_HLP_ATQLEN_PAGE_ATQENABLE_M BIT(31) 155 #define PF0_FW_HLP_ATQT_PAGE 0x02D00400 /* Reset Source: EMPR */ 156 #define PF0_FW_HLP_ATQT_PAGE_ATQT_S 0 157 #define PF0_FW_HLP_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0) 158 #define PF0_FW_PSM_ARQBAH_PAGE 0x02D40180 /* Reset Source: EMPR */ 159 #define PF0_FW_PSM_ARQBAH_PAGE_ARQBAH_S 0 160 #define PF0_FW_PSM_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 161 #define PF0_FW_PSM_ARQBAL_PAGE 0x02D40080 /* Reset Source: EMPR */ 162 #define PF0_FW_PSM_ARQBAL_PAGE_ARQBAL_LSB_S 0 163 #define PF0_FW_PSM_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 164 #define PF0_FW_PSM_ARQBAL_PAGE_ARQBAL_S 6 165 #define PF0_FW_PSM_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 166 #define PF0_FW_PSM_ARQH_PAGE 0x02D40380 /* Reset Source: EMPR */ 167 #define PF0_FW_PSM_ARQH_PAGE_ARQH_S 0 168 #define PF0_FW_PSM_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0) 169 #define PF0_FW_PSM_ARQLEN_PAGE 0x02D40280 /* Reset Source: EMPR */ 170 #define PF0_FW_PSM_ARQLEN_PAGE_ARQLEN_S 0 171 #define PF0_FW_PSM_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0) 172 #define PF0_FW_PSM_ARQLEN_PAGE_ARQVFE_S 28 173 #define PF0_FW_PSM_ARQLEN_PAGE_ARQVFE_M BIT(28) 174 #define PF0_FW_PSM_ARQLEN_PAGE_ARQOVFL_S 29 175 #define PF0_FW_PSM_ARQLEN_PAGE_ARQOVFL_M BIT(29) 176 #define PF0_FW_PSM_ARQLEN_PAGE_ARQCRIT_S 30 177 #define PF0_FW_PSM_ARQLEN_PAGE_ARQCRIT_M BIT(30) 178 #define PF0_FW_PSM_ARQLEN_PAGE_ARQENABLE_S 31 179 #define PF0_FW_PSM_ARQLEN_PAGE_ARQENABLE_M BIT(31) 180 #define PF0_FW_PSM_ARQT_PAGE 0x02D40480 /* Reset Source: EMPR */ 181 #define PF0_FW_PSM_ARQT_PAGE_ARQT_S 0 182 #define PF0_FW_PSM_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0) 183 #define PF0_FW_PSM_ATQBAH_PAGE 0x02D40100 /* Reset Source: EMPR */ 184 #define PF0_FW_PSM_ATQBAH_PAGE_ATQBAH_S 0 185 #define PF0_FW_PSM_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 186 #define PF0_FW_PSM_ATQBAL_PAGE 0x02D40000 /* Reset Source: EMPR */ 187 #define PF0_FW_PSM_ATQBAL_PAGE_ATQBAL_LSB_S 0 188 #define PF0_FW_PSM_ATQBAL_PAGE_ATQBAL_LSB_M MAKEMASK(0x3F, 0) 189 #define PF0_FW_PSM_ATQBAL_PAGE_ATQBAL_S 6 190 #define PF0_FW_PSM_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 191 #define PF0_FW_PSM_ATQH_PAGE 0x02D40300 /* Reset Source: EMPR */ 192 #define PF0_FW_PSM_ATQH_PAGE_ATQH_S 0 193 #define PF0_FW_PSM_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0) 194 #define PF0_FW_PSM_ATQLEN_PAGE 0x02D40200 /* Reset Source: EMPR */ 195 #define PF0_FW_PSM_ATQLEN_PAGE_ATQLEN_S 0 196 #define PF0_FW_PSM_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0) 197 #define PF0_FW_PSM_ATQLEN_PAGE_ATQVFE_S 28 198 #define PF0_FW_PSM_ATQLEN_PAGE_ATQVFE_M BIT(28) 199 #define PF0_FW_PSM_ATQLEN_PAGE_ATQOVFL_S 29 200 #define PF0_FW_PSM_ATQLEN_PAGE_ATQOVFL_M BIT(29) 201 #define PF0_FW_PSM_ATQLEN_PAGE_ATQCRIT_S 30 202 #define PF0_FW_PSM_ATQLEN_PAGE_ATQCRIT_M BIT(30) 203 #define PF0_FW_PSM_ATQLEN_PAGE_ATQENABLE_S 31 204 #define PF0_FW_PSM_ATQLEN_PAGE_ATQENABLE_M BIT(31) 205 #define PF0_FW_PSM_ATQT_PAGE 0x02D40400 /* Reset Source: EMPR */ 206 #define PF0_FW_PSM_ATQT_PAGE_ATQT_S 0 207 #define PF0_FW_PSM_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0) 208 #define PF0_MBX_CPM_ARQBAH_PAGE 0x02D80190 /* Reset Source: CORER */ 209 #define PF0_MBX_CPM_ARQBAH_PAGE_ARQBAH_S 0 210 #define PF0_MBX_CPM_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 211 #define PF0_MBX_CPM_ARQBAL_PAGE 0x02D80090 /* Reset Source: CORER */ 212 #define PF0_MBX_CPM_ARQBAL_PAGE_ARQBAL_LSB_S 0 213 #define PF0_MBX_CPM_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 214 #define PF0_MBX_CPM_ARQBAL_PAGE_ARQBAL_S 6 215 #define PF0_MBX_CPM_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 216 #define PF0_MBX_CPM_ARQH_PAGE 0x02D80390 /* Reset Source: CORER */ 217 #define PF0_MBX_CPM_ARQH_PAGE_ARQH_S 0 218 #define PF0_MBX_CPM_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0) 219 #define PF0_MBX_CPM_ARQLEN_PAGE 0x02D80290 /* Reset Source: PFR */ 220 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQLEN_S 0 221 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0) 222 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQVFE_S 28 223 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQVFE_M BIT(28) 224 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQOVFL_S 29 225 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQOVFL_M BIT(29) 226 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQCRIT_S 30 227 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQCRIT_M BIT(30) 228 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQENABLE_S 31 229 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQENABLE_M BIT(31) 230 #define PF0_MBX_CPM_ARQT_PAGE 0x02D80490 /* Reset Source: CORER */ 231 #define PF0_MBX_CPM_ARQT_PAGE_ARQT_S 0 232 #define PF0_MBX_CPM_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0) 233 #define PF0_MBX_CPM_ATQBAH_PAGE 0x02D80110 /* Reset Source: CORER */ 234 #define PF0_MBX_CPM_ATQBAH_PAGE_ATQBAH_S 0 235 #define PF0_MBX_CPM_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 236 #define PF0_MBX_CPM_ATQBAL_PAGE 0x02D80010 /* Reset Source: CORER */ 237 #define PF0_MBX_CPM_ATQBAL_PAGE_ATQBAL_S 6 238 #define PF0_MBX_CPM_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 239 #define PF0_MBX_CPM_ATQH_PAGE 0x02D80310 /* Reset Source: CORER */ 240 #define PF0_MBX_CPM_ATQH_PAGE_ATQH_S 0 241 #define PF0_MBX_CPM_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0) 242 #define PF0_MBX_CPM_ATQLEN_PAGE 0x02D80210 /* Reset Source: PFR */ 243 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQLEN_S 0 244 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0) 245 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQVFE_S 28 246 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQVFE_M BIT(28) 247 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQOVFL_S 29 248 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQOVFL_M BIT(29) 249 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQCRIT_S 30 250 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQCRIT_M BIT(30) 251 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQENABLE_S 31 252 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQENABLE_M BIT(31) 253 #define PF0_MBX_CPM_ATQT_PAGE 0x02D80410 /* Reset Source: CORER */ 254 #define PF0_MBX_CPM_ATQT_PAGE_ATQT_S 0 255 #define PF0_MBX_CPM_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0) 256 #define PF0_MBX_HLP_ARQBAH_PAGE 0x02D00190 /* Reset Source: CORER */ 257 #define PF0_MBX_HLP_ARQBAH_PAGE_ARQBAH_S 0 258 #define PF0_MBX_HLP_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 259 #define PF0_MBX_HLP_ARQBAL_PAGE 0x02D00090 /* Reset Source: CORER */ 260 #define PF0_MBX_HLP_ARQBAL_PAGE_ARQBAL_LSB_S 0 261 #define PF0_MBX_HLP_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 262 #define PF0_MBX_HLP_ARQBAL_PAGE_ARQBAL_S 6 263 #define PF0_MBX_HLP_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 264 #define PF0_MBX_HLP_ARQH_PAGE 0x02D00390 /* Reset Source: CORER */ 265 #define PF0_MBX_HLP_ARQH_PAGE_ARQH_S 0 266 #define PF0_MBX_HLP_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0) 267 #define PF0_MBX_HLP_ARQLEN_PAGE 0x02D00290 /* Reset Source: PFR */ 268 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQLEN_S 0 269 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0) 270 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQVFE_S 28 271 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQVFE_M BIT(28) 272 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQOVFL_S 29 273 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQOVFL_M BIT(29) 274 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQCRIT_S 30 275 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQCRIT_M BIT(30) 276 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQENABLE_S 31 277 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQENABLE_M BIT(31) 278 #define PF0_MBX_HLP_ARQT_PAGE 0x02D00490 /* Reset Source: CORER */ 279 #define PF0_MBX_HLP_ARQT_PAGE_ARQT_S 0 280 #define PF0_MBX_HLP_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0) 281 #define PF0_MBX_HLP_ATQBAH_PAGE 0x02D00110 /* Reset Source: CORER */ 282 #define PF0_MBX_HLP_ATQBAH_PAGE_ATQBAH_S 0 283 #define PF0_MBX_HLP_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 284 #define PF0_MBX_HLP_ATQBAL_PAGE 0x02D00010 /* Reset Source: CORER */ 285 #define PF0_MBX_HLP_ATQBAL_PAGE_ATQBAL_S 6 286 #define PF0_MBX_HLP_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 287 #define PF0_MBX_HLP_ATQH_PAGE 0x02D00310 /* Reset Source: CORER */ 288 #define PF0_MBX_HLP_ATQH_PAGE_ATQH_S 0 289 #define PF0_MBX_HLP_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0) 290 #define PF0_MBX_HLP_ATQLEN_PAGE 0x02D00210 /* Reset Source: PFR */ 291 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQLEN_S 0 292 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0) 293 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQVFE_S 28 294 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQVFE_M BIT(28) 295 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQOVFL_S 29 296 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQOVFL_M BIT(29) 297 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQCRIT_S 30 298 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQCRIT_M BIT(30) 299 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQENABLE_S 31 300 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQENABLE_M BIT(31) 301 #define PF0_MBX_HLP_ATQT_PAGE 0x02D00410 /* Reset Source: CORER */ 302 #define PF0_MBX_HLP_ATQT_PAGE_ATQT_S 0 303 #define PF0_MBX_HLP_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0) 304 #define PF0_MBX_PSM_ARQBAH_PAGE 0x02D40190 /* Reset Source: CORER */ 305 #define PF0_MBX_PSM_ARQBAH_PAGE_ARQBAH_S 0 306 #define PF0_MBX_PSM_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 307 #define PF0_MBX_PSM_ARQBAL_PAGE 0x02D40090 /* Reset Source: CORER */ 308 #define PF0_MBX_PSM_ARQBAL_PAGE_ARQBAL_LSB_S 0 309 #define PF0_MBX_PSM_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 310 #define PF0_MBX_PSM_ARQBAL_PAGE_ARQBAL_S 6 311 #define PF0_MBX_PSM_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 312 #define PF0_MBX_PSM_ARQH_PAGE 0x02D40390 /* Reset Source: CORER */ 313 #define PF0_MBX_PSM_ARQH_PAGE_ARQH_S 0 314 #define PF0_MBX_PSM_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0) 315 #define PF0_MBX_PSM_ARQLEN_PAGE 0x02D40290 /* Reset Source: PFR */ 316 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQLEN_S 0 317 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0) 318 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQVFE_S 28 319 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQVFE_M BIT(28) 320 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQOVFL_S 29 321 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQOVFL_M BIT(29) 322 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQCRIT_S 30 323 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQCRIT_M BIT(30) 324 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQENABLE_S 31 325 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQENABLE_M BIT(31) 326 #define PF0_MBX_PSM_ARQT_PAGE 0x02D40490 /* Reset Source: CORER */ 327 #define PF0_MBX_PSM_ARQT_PAGE_ARQT_S 0 328 #define PF0_MBX_PSM_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0) 329 #define PF0_MBX_PSM_ATQBAH_PAGE 0x02D40110 /* Reset Source: CORER */ 330 #define PF0_MBX_PSM_ATQBAH_PAGE_ATQBAH_S 0 331 #define PF0_MBX_PSM_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 332 #define PF0_MBX_PSM_ATQBAL_PAGE 0x02D40010 /* Reset Source: CORER */ 333 #define PF0_MBX_PSM_ATQBAL_PAGE_ATQBAL_S 6 334 #define PF0_MBX_PSM_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 335 #define PF0_MBX_PSM_ATQH_PAGE 0x02D40310 /* Reset Source: CORER */ 336 #define PF0_MBX_PSM_ATQH_PAGE_ATQH_S 0 337 #define PF0_MBX_PSM_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0) 338 #define PF0_MBX_PSM_ATQLEN_PAGE 0x02D40210 /* Reset Source: PFR */ 339 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQLEN_S 0 340 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0) 341 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQVFE_S 28 342 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQVFE_M BIT(28) 343 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQOVFL_S 29 344 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQOVFL_M BIT(29) 345 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQCRIT_S 30 346 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQCRIT_M BIT(30) 347 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQENABLE_S 31 348 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQENABLE_M BIT(31) 349 #define PF0_MBX_PSM_ATQT_PAGE 0x02D40410 /* Reset Source: CORER */ 350 #define PF0_MBX_PSM_ATQT_PAGE_ATQT_S 0 351 #define PF0_MBX_PSM_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0) 352 #define PF0_SB_CPM_ARQBAH_PAGE 0x02D801A0 /* Reset Source: CORER */ 353 #define PF0_SB_CPM_ARQBAH_PAGE_ARQBAH_S 0 354 #define PF0_SB_CPM_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 355 #define PF0_SB_CPM_ARQBAL_PAGE 0x02D800A0 /* Reset Source: CORER */ 356 #define PF0_SB_CPM_ARQBAL_PAGE_ARQBAL_LSB_S 0 357 #define PF0_SB_CPM_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 358 #define PF0_SB_CPM_ARQBAL_PAGE_ARQBAL_S 6 359 #define PF0_SB_CPM_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 360 #define PF0_SB_CPM_ARQH_PAGE 0x02D803A0 /* Reset Source: CORER */ 361 #define PF0_SB_CPM_ARQH_PAGE_ARQH_S 0 362 #define PF0_SB_CPM_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0) 363 #define PF0_SB_CPM_ARQLEN_PAGE 0x02D802A0 /* Reset Source: PFR */ 364 #define PF0_SB_CPM_ARQLEN_PAGE_ARQLEN_S 0 365 #define PF0_SB_CPM_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0) 366 #define PF0_SB_CPM_ARQLEN_PAGE_ARQVFE_S 28 367 #define PF0_SB_CPM_ARQLEN_PAGE_ARQVFE_M BIT(28) 368 #define PF0_SB_CPM_ARQLEN_PAGE_ARQOVFL_S 29 369 #define PF0_SB_CPM_ARQLEN_PAGE_ARQOVFL_M BIT(29) 370 #define PF0_SB_CPM_ARQLEN_PAGE_ARQCRIT_S 30 371 #define PF0_SB_CPM_ARQLEN_PAGE_ARQCRIT_M BIT(30) 372 #define PF0_SB_CPM_ARQLEN_PAGE_ARQENABLE_S 31 373 #define PF0_SB_CPM_ARQLEN_PAGE_ARQENABLE_M BIT(31) 374 #define PF0_SB_CPM_ARQT_PAGE 0x02D804A0 /* Reset Source: CORER */ 375 #define PF0_SB_CPM_ARQT_PAGE_ARQT_S 0 376 #define PF0_SB_CPM_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0) 377 #define PF0_SB_CPM_ATQBAH_PAGE 0x02D80120 /* Reset Source: CORER */ 378 #define PF0_SB_CPM_ATQBAH_PAGE_ATQBAH_S 0 379 #define PF0_SB_CPM_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 380 #define PF0_SB_CPM_ATQBAL_PAGE 0x02D80020 /* Reset Source: CORER */ 381 #define PF0_SB_CPM_ATQBAL_PAGE_ATQBAL_S 6 382 #define PF0_SB_CPM_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 383 #define PF0_SB_CPM_ATQH_PAGE 0x02D80320 /* Reset Source: CORER */ 384 #define PF0_SB_CPM_ATQH_PAGE_ATQH_S 0 385 #define PF0_SB_CPM_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0) 386 #define PF0_SB_CPM_ATQLEN_PAGE 0x02D80220 /* Reset Source: PFR */ 387 #define PF0_SB_CPM_ATQLEN_PAGE_ATQLEN_S 0 388 #define PF0_SB_CPM_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0) 389 #define PF0_SB_CPM_ATQLEN_PAGE_ATQVFE_S 28 390 #define PF0_SB_CPM_ATQLEN_PAGE_ATQVFE_M BIT(28) 391 #define PF0_SB_CPM_ATQLEN_PAGE_ATQOVFL_S 29 392 #define PF0_SB_CPM_ATQLEN_PAGE_ATQOVFL_M BIT(29) 393 #define PF0_SB_CPM_ATQLEN_PAGE_ATQCRIT_S 30 394 #define PF0_SB_CPM_ATQLEN_PAGE_ATQCRIT_M BIT(30) 395 #define PF0_SB_CPM_ATQLEN_PAGE_ATQENABLE_S 31 396 #define PF0_SB_CPM_ATQLEN_PAGE_ATQENABLE_M BIT(31) 397 #define PF0_SB_CPM_ATQT_PAGE 0x02D80420 /* Reset Source: CORER */ 398 #define PF0_SB_CPM_ATQT_PAGE_ATQT_S 0 399 #define PF0_SB_CPM_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0) 400 #define PF0_SB_HLP_ARQBAH_PAGE 0x02D001A0 /* Reset Source: CORER */ 401 #define PF0_SB_HLP_ARQBAH_PAGE_ARQBAH_S 0 402 #define PF0_SB_HLP_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 403 #define PF0_SB_HLP_ARQBAL_PAGE 0x02D000A0 /* Reset Source: CORER */ 404 #define PF0_SB_HLP_ARQBAL_PAGE_ARQBAL_LSB_S 0 405 #define PF0_SB_HLP_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 406 #define PF0_SB_HLP_ARQBAL_PAGE_ARQBAL_S 6 407 #define PF0_SB_HLP_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 408 #define PF0_SB_HLP_ARQH_PAGE 0x02D003A0 /* Reset Source: CORER */ 409 #define PF0_SB_HLP_ARQH_PAGE_ARQH_S 0 410 #define PF0_SB_HLP_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0) 411 #define PF0_SB_HLP_ARQLEN_PAGE 0x02D002A0 /* Reset Source: PFR */ 412 #define PF0_SB_HLP_ARQLEN_PAGE_ARQLEN_S 0 413 #define PF0_SB_HLP_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0) 414 #define PF0_SB_HLP_ARQLEN_PAGE_ARQVFE_S 28 415 #define PF0_SB_HLP_ARQLEN_PAGE_ARQVFE_M BIT(28) 416 #define PF0_SB_HLP_ARQLEN_PAGE_ARQOVFL_S 29 417 #define PF0_SB_HLP_ARQLEN_PAGE_ARQOVFL_M BIT(29) 418 #define PF0_SB_HLP_ARQLEN_PAGE_ARQCRIT_S 30 419 #define PF0_SB_HLP_ARQLEN_PAGE_ARQCRIT_M BIT(30) 420 #define PF0_SB_HLP_ARQLEN_PAGE_ARQENABLE_S 31 421 #define PF0_SB_HLP_ARQLEN_PAGE_ARQENABLE_M BIT(31) 422 #define PF0_SB_HLP_ARQT_PAGE 0x02D004A0 /* Reset Source: CORER */ 423 #define PF0_SB_HLP_ARQT_PAGE_ARQT_S 0 424 #define PF0_SB_HLP_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0) 425 #define PF0_SB_HLP_ATQBAH_PAGE 0x02D00120 /* Reset Source: CORER */ 426 #define PF0_SB_HLP_ATQBAH_PAGE_ATQBAH_S 0 427 #define PF0_SB_HLP_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 428 #define PF0_SB_HLP_ATQBAL_PAGE 0x02D00020 /* Reset Source: CORER */ 429 #define PF0_SB_HLP_ATQBAL_PAGE_ATQBAL_S 6 430 #define PF0_SB_HLP_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 431 #define PF0_SB_HLP_ATQH_PAGE 0x02D00320 /* Reset Source: CORER */ 432 #define PF0_SB_HLP_ATQH_PAGE_ATQH_S 0 433 #define PF0_SB_HLP_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0) 434 #define PF0_SB_HLP_ATQLEN_PAGE 0x02D00220 /* Reset Source: PFR */ 435 #define PF0_SB_HLP_ATQLEN_PAGE_ATQLEN_S 0 436 #define PF0_SB_HLP_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0) 437 #define PF0_SB_HLP_ATQLEN_PAGE_ATQVFE_S 28 438 #define PF0_SB_HLP_ATQLEN_PAGE_ATQVFE_M BIT(28) 439 #define PF0_SB_HLP_ATQLEN_PAGE_ATQOVFL_S 29 440 #define PF0_SB_HLP_ATQLEN_PAGE_ATQOVFL_M BIT(29) 441 #define PF0_SB_HLP_ATQLEN_PAGE_ATQCRIT_S 30 442 #define PF0_SB_HLP_ATQLEN_PAGE_ATQCRIT_M BIT(30) 443 #define PF0_SB_HLP_ATQLEN_PAGE_ATQENABLE_S 31 444 #define PF0_SB_HLP_ATQLEN_PAGE_ATQENABLE_M BIT(31) 445 #define PF0_SB_HLP_ATQT_PAGE 0x02D00420 /* Reset Source: CORER */ 446 #define PF0_SB_HLP_ATQT_PAGE_ATQT_S 0 447 #define PF0_SB_HLP_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0) 448 #define PF0INT_DYN_CTL(_i) (0x03000000 + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */ 449 #define PF0INT_DYN_CTL_MAX_INDEX 2047 450 #define PF0INT_DYN_CTL_INTENA_S 0 451 #define PF0INT_DYN_CTL_INTENA_M BIT(0) 452 #define PF0INT_DYN_CTL_CLEARPBA_S 1 453 #define PF0INT_DYN_CTL_CLEARPBA_M BIT(1) 454 #define PF0INT_DYN_CTL_SWINT_TRIG_S 2 455 #define PF0INT_DYN_CTL_SWINT_TRIG_M BIT(2) 456 #define PF0INT_DYN_CTL_ITR_INDX_S 3 457 #define PF0INT_DYN_CTL_ITR_INDX_M MAKEMASK(0x3, 3) 458 #define PF0INT_DYN_CTL_INTERVAL_S 5 459 #define PF0INT_DYN_CTL_INTERVAL_M MAKEMASK(0xFFF, 5) 460 #define PF0INT_DYN_CTL_SW_ITR_INDX_ENA_S 24 461 #define PF0INT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(24) 462 #define PF0INT_DYN_CTL_SW_ITR_INDX_S 25 463 #define PF0INT_DYN_CTL_SW_ITR_INDX_M MAKEMASK(0x3, 25) 464 #define PF0INT_DYN_CTL_WB_ON_ITR_S 30 465 #define PF0INT_DYN_CTL_WB_ON_ITR_M BIT(30) 466 #define PF0INT_DYN_CTL_INTENA_MSK_S 31 467 #define PF0INT_DYN_CTL_INTENA_MSK_M BIT(31) 468 #define PF0INT_ITR_0(_i) (0x03000004 + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */ 469 #define PF0INT_ITR_0_MAX_INDEX 2047 470 #define PF0INT_ITR_0_INTERVAL_S 0 471 #define PF0INT_ITR_0_INTERVAL_M MAKEMASK(0xFFF, 0) 472 #define PF0INT_ITR_1(_i) (0x03000008 + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */ 473 #define PF0INT_ITR_1_MAX_INDEX 2047 474 #define PF0INT_ITR_1_INTERVAL_S 0 475 #define PF0INT_ITR_1_INTERVAL_M MAKEMASK(0xFFF, 0) 476 #define PF0INT_ITR_2(_i) (0x0300000C + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */ 477 #define PF0INT_ITR_2_MAX_INDEX 2047 478 #define PF0INT_ITR_2_INTERVAL_S 0 479 #define PF0INT_ITR_2_INTERVAL_M MAKEMASK(0xFFF, 0) 480 #define PF0INT_OICR_CPM_PAGE 0x02D03000 /* Reset Source: CORER */ 481 #define PF0INT_OICR_CPM_PAGE_INTEVENT_S 0 482 #define PF0INT_OICR_CPM_PAGE_INTEVENT_M BIT(0) 483 #define PF0INT_OICR_CPM_PAGE_QUEUE_S 1 484 #define PF0INT_OICR_CPM_PAGE_QUEUE_M BIT(1) 485 #define PF0INT_OICR_CPM_PAGE_RSV1_S 2 486 #define PF0INT_OICR_CPM_PAGE_RSV1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PF0INT_OICR_CPM_PAGE_RSV1_M : E800_PF0INT_OICR_CPM_PAGE_RSV1_M) 487 #define E800_PF0INT_OICR_CPM_PAGE_RSV1_M MAKEMASK(0xFF, 2) 488 #define E830_PF0INT_OICR_CPM_PAGE_RSV1_M MAKEMASK(0x3F, 2) 489 #define E800_PF0INT_OICR_CPM_PAGE_HH_COMP_S 10 490 #define E800_PF0INT_OICR_CPM_PAGE_HH_COMP_M BIT(10) 491 #define PF0INT_OICR_CPM_PAGE_TSYN_TX_S 11 492 #define PF0INT_OICR_CPM_PAGE_TSYN_TX_M BIT(11) 493 #define PF0INT_OICR_CPM_PAGE_TSYN_EVNT_S 12 494 #define PF0INT_OICR_CPM_PAGE_TSYN_EVNT_M BIT(12) 495 #define PF0INT_OICR_CPM_PAGE_TSYN_TGT_S 13 496 #define PF0INT_OICR_CPM_PAGE_TSYN_TGT_M BIT(13) 497 #define PF0INT_OICR_CPM_PAGE_HLP_RDY_S 14 498 #define PF0INT_OICR_CPM_PAGE_HLP_RDY_M BIT(14) 499 #define PF0INT_OICR_CPM_PAGE_CPM_RDY_S 15 500 #define PF0INT_OICR_CPM_PAGE_CPM_RDY_M BIT(15) 501 #define PF0INT_OICR_CPM_PAGE_ECC_ERR_S 16 502 #define PF0INT_OICR_CPM_PAGE_ECC_ERR_M BIT(16) 503 #define PF0INT_OICR_CPM_PAGE_RSV2_S 17 504 #define PF0INT_OICR_CPM_PAGE_RSV2_M MAKEMASK(0x3, 17) 505 #define PF0INT_OICR_CPM_PAGE_MAL_DETECT_S 19 506 #define PF0INT_OICR_CPM_PAGE_MAL_DETECT_M BIT(19) 507 #define PF0INT_OICR_CPM_PAGE_GRST_S 20 508 #define PF0INT_OICR_CPM_PAGE_GRST_M BIT(20) 509 #define PF0INT_OICR_CPM_PAGE_PCI_EXCEPTION_S 21 510 #define PF0INT_OICR_CPM_PAGE_PCI_EXCEPTION_M BIT(21) 511 #define PF0INT_OICR_CPM_PAGE_GPIO_S 22 512 #define PF0INT_OICR_CPM_PAGE_GPIO_M BIT(22) 513 #define PF0INT_OICR_CPM_PAGE_RSV3_S 23 514 #define PF0INT_OICR_CPM_PAGE_RSV3_M BIT(23) 515 #define PF0INT_OICR_CPM_PAGE_STORM_DETECT_S 24 516 #define PF0INT_OICR_CPM_PAGE_STORM_DETECT_M BIT(24) 517 #define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_S 25 518 #define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_M BIT(25) 519 #define PF0INT_OICR_CPM_PAGE_HMC_ERR_S 26 520 #define PF0INT_OICR_CPM_PAGE_HMC_ERR_M BIT(26) 521 #define PF0INT_OICR_CPM_PAGE_PE_PUSH_S 27 522 #define PF0INT_OICR_CPM_PAGE_PE_PUSH_M BIT(27) 523 #define PF0INT_OICR_CPM_PAGE_PE_CRITERR_S 28 524 #define PF0INT_OICR_CPM_PAGE_PE_CRITERR_M BIT(28) 525 #define PF0INT_OICR_CPM_PAGE_VFLR_S 29 526 #define PF0INT_OICR_CPM_PAGE_VFLR_M BIT(29) 527 #define PF0INT_OICR_CPM_PAGE_XLR_HW_DONE_S 30 528 #define PF0INT_OICR_CPM_PAGE_XLR_HW_DONE_M BIT(30) 529 #define PF0INT_OICR_CPM_PAGE_SWINT_S 31 530 #define PF0INT_OICR_CPM_PAGE_SWINT_M BIT(31) 531 #define PF0INT_OICR_ENA_CPM_PAGE 0x02D03100 /* Reset Source: CORER */ 532 #define PF0INT_OICR_ENA_CPM_PAGE_RSV0_S 0 533 #define PF0INT_OICR_ENA_CPM_PAGE_RSV0_M BIT(0) 534 #define PF0INT_OICR_ENA_CPM_PAGE_INT_ENA_S 1 535 #define PF0INT_OICR_ENA_CPM_PAGE_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1) 536 #define PF0INT_OICR_ENA_HLP_PAGE 0x02D01100 /* Reset Source: CORER */ 537 #define PF0INT_OICR_ENA_HLP_PAGE_RSV0_S 0 538 #define PF0INT_OICR_ENA_HLP_PAGE_RSV0_M BIT(0) 539 #define PF0INT_OICR_ENA_HLP_PAGE_INT_ENA_S 1 540 #define PF0INT_OICR_ENA_HLP_PAGE_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1) 541 #define PF0INT_OICR_ENA_PSM_PAGE 0x02D02100 /* Reset Source: CORER */ 542 #define PF0INT_OICR_ENA_PSM_PAGE_RSV0_S 0 543 #define PF0INT_OICR_ENA_PSM_PAGE_RSV0_M BIT(0) 544 #define PF0INT_OICR_ENA_PSM_PAGE_INT_ENA_S 1 545 #define PF0INT_OICR_ENA_PSM_PAGE_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1) 546 #define PF0INT_OICR_HLP_PAGE 0x02D01000 /* Reset Source: CORER */ 547 #define PF0INT_OICR_HLP_PAGE_INTEVENT_S 0 548 #define PF0INT_OICR_HLP_PAGE_INTEVENT_M BIT(0) 549 #define PF0INT_OICR_HLP_PAGE_QUEUE_S 1 550 #define PF0INT_OICR_HLP_PAGE_QUEUE_M BIT(1) 551 #define PF0INT_OICR_HLP_PAGE_RSV1_S 2 552 #define PF0INT_OICR_HLP_PAGE_RSV1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PF0INT_OICR_HLP_PAGE_RSV1_M : E800_PF0INT_OICR_HLP_PAGE_RSV1_M) 553 #define E800_PF0INT_OICR_HLP_PAGE_RSV1_M MAKEMASK(0xFF, 2) 554 #define E830_PF0INT_OICR_HLP_PAGE_RSV1_M MAKEMASK(0x3F, 2) 555 #define E800_PF0INT_OICR_HLP_PAGE_HH_COMP_S 10 556 #define E800_PF0INT_OICR_HLP_PAGE_HH_COMP_M BIT(10) 557 #define PF0INT_OICR_HLP_PAGE_TSYN_TX_S 11 558 #define PF0INT_OICR_HLP_PAGE_TSYN_TX_M BIT(11) 559 #define PF0INT_OICR_HLP_PAGE_TSYN_EVNT_S 12 560 #define PF0INT_OICR_HLP_PAGE_TSYN_EVNT_M BIT(12) 561 #define PF0INT_OICR_HLP_PAGE_TSYN_TGT_S 13 562 #define PF0INT_OICR_HLP_PAGE_TSYN_TGT_M BIT(13) 563 #define PF0INT_OICR_HLP_PAGE_HLP_RDY_S 14 564 #define PF0INT_OICR_HLP_PAGE_HLP_RDY_M BIT(14) 565 #define PF0INT_OICR_HLP_PAGE_CPM_RDY_S 15 566 #define PF0INT_OICR_HLP_PAGE_CPM_RDY_M BIT(15) 567 #define PF0INT_OICR_HLP_PAGE_ECC_ERR_S 16 568 #define PF0INT_OICR_HLP_PAGE_ECC_ERR_M BIT(16) 569 #define PF0INT_OICR_HLP_PAGE_RSV2_S 17 570 #define PF0INT_OICR_HLP_PAGE_RSV2_M MAKEMASK(0x3, 17) 571 #define PF0INT_OICR_HLP_PAGE_MAL_DETECT_S 19 572 #define PF0INT_OICR_HLP_PAGE_MAL_DETECT_M BIT(19) 573 #define PF0INT_OICR_HLP_PAGE_GRST_S 20 574 #define PF0INT_OICR_HLP_PAGE_GRST_M BIT(20) 575 #define PF0INT_OICR_HLP_PAGE_PCI_EXCEPTION_S 21 576 #define PF0INT_OICR_HLP_PAGE_PCI_EXCEPTION_M BIT(21) 577 #define PF0INT_OICR_HLP_PAGE_GPIO_S 22 578 #define PF0INT_OICR_HLP_PAGE_GPIO_M BIT(22) 579 #define PF0INT_OICR_HLP_PAGE_RSV3_S 23 580 #define PF0INT_OICR_HLP_PAGE_RSV3_M BIT(23) 581 #define PF0INT_OICR_HLP_PAGE_STORM_DETECT_S 24 582 #define PF0INT_OICR_HLP_PAGE_STORM_DETECT_M BIT(24) 583 #define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_S 25 584 #define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_M BIT(25) 585 #define PF0INT_OICR_HLP_PAGE_HMC_ERR_S 26 586 #define PF0INT_OICR_HLP_PAGE_HMC_ERR_M BIT(26) 587 #define PF0INT_OICR_HLP_PAGE_PE_PUSH_S 27 588 #define PF0INT_OICR_HLP_PAGE_PE_PUSH_M BIT(27) 589 #define PF0INT_OICR_HLP_PAGE_PE_CRITERR_S 28 590 #define PF0INT_OICR_HLP_PAGE_PE_CRITERR_M BIT(28) 591 #define PF0INT_OICR_HLP_PAGE_VFLR_S 29 592 #define PF0INT_OICR_HLP_PAGE_VFLR_M BIT(29) 593 #define PF0INT_OICR_HLP_PAGE_XLR_HW_DONE_S 30 594 #define PF0INT_OICR_HLP_PAGE_XLR_HW_DONE_M BIT(30) 595 #define PF0INT_OICR_HLP_PAGE_SWINT_S 31 596 #define PF0INT_OICR_HLP_PAGE_SWINT_M BIT(31) 597 #define PF0INT_OICR_PSM_PAGE 0x02D02000 /* Reset Source: CORER */ 598 #define PF0INT_OICR_PSM_PAGE_INTEVENT_S 0 599 #define PF0INT_OICR_PSM_PAGE_INTEVENT_M BIT(0) 600 #define PF0INT_OICR_PSM_PAGE_QUEUE_S 1 601 #define PF0INT_OICR_PSM_PAGE_QUEUE_M BIT(1) 602 #define PF0INT_OICR_PSM_PAGE_RSV1_S 2 603 #define PF0INT_OICR_PSM_PAGE_RSV1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PF0INT_OICR_PSM_PAGE_RSV1_M : E800_PF0INT_OICR_PSM_PAGE_RSV1_M) 604 #define E800_PF0INT_OICR_PSM_PAGE_RSV1_M MAKEMASK(0xFF, 2) 605 #define E830_PF0INT_OICR_PSM_PAGE_RSV1_M MAKEMASK(0x3F, 2) 606 #define E800_PF0INT_OICR_PSM_PAGE_HH_COMP_S 10 607 #define E800_PF0INT_OICR_PSM_PAGE_HH_COMP_M BIT(10) 608 #define PF0INT_OICR_PSM_PAGE_TSYN_TX_S 11 609 #define PF0INT_OICR_PSM_PAGE_TSYN_TX_M BIT(11) 610 #define PF0INT_OICR_PSM_PAGE_TSYN_EVNT_S 12 611 #define PF0INT_OICR_PSM_PAGE_TSYN_EVNT_M BIT(12) 612 #define PF0INT_OICR_PSM_PAGE_TSYN_TGT_S 13 613 #define PF0INT_OICR_PSM_PAGE_TSYN_TGT_M BIT(13) 614 #define PF0INT_OICR_PSM_PAGE_HLP_RDY_S 14 615 #define PF0INT_OICR_PSM_PAGE_HLP_RDY_M BIT(14) 616 #define PF0INT_OICR_PSM_PAGE_CPM_RDY_S 15 617 #define PF0INT_OICR_PSM_PAGE_CPM_RDY_M BIT(15) 618 #define PF0INT_OICR_PSM_PAGE_ECC_ERR_S 16 619 #define PF0INT_OICR_PSM_PAGE_ECC_ERR_M BIT(16) 620 #define PF0INT_OICR_PSM_PAGE_RSV2_S 17 621 #define PF0INT_OICR_PSM_PAGE_RSV2_M MAKEMASK(0x3, 17) 622 #define PF0INT_OICR_PSM_PAGE_MAL_DETECT_S 19 623 #define PF0INT_OICR_PSM_PAGE_MAL_DETECT_M BIT(19) 624 #define PF0INT_OICR_PSM_PAGE_GRST_S 20 625 #define PF0INT_OICR_PSM_PAGE_GRST_M BIT(20) 626 #define PF0INT_OICR_PSM_PAGE_PCI_EXCEPTION_S 21 627 #define PF0INT_OICR_PSM_PAGE_PCI_EXCEPTION_M BIT(21) 628 #define PF0INT_OICR_PSM_PAGE_GPIO_S 22 629 #define PF0INT_OICR_PSM_PAGE_GPIO_M BIT(22) 630 #define PF0INT_OICR_PSM_PAGE_RSV3_S 23 631 #define PF0INT_OICR_PSM_PAGE_RSV3_M BIT(23) 632 #define PF0INT_OICR_PSM_PAGE_STORM_DETECT_S 24 633 #define PF0INT_OICR_PSM_PAGE_STORM_DETECT_M BIT(24) 634 #define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_S 25 635 #define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_M BIT(25) 636 #define PF0INT_OICR_PSM_PAGE_HMC_ERR_S 26 637 #define PF0INT_OICR_PSM_PAGE_HMC_ERR_M BIT(26) 638 #define PF0INT_OICR_PSM_PAGE_PE_PUSH_S 27 639 #define PF0INT_OICR_PSM_PAGE_PE_PUSH_M BIT(27) 640 #define PF0INT_OICR_PSM_PAGE_PE_CRITERR_S 28 641 #define PF0INT_OICR_PSM_PAGE_PE_CRITERR_M BIT(28) 642 #define PF0INT_OICR_PSM_PAGE_VFLR_S 29 643 #define PF0INT_OICR_PSM_PAGE_VFLR_M BIT(29) 644 #define PF0INT_OICR_PSM_PAGE_XLR_HW_DONE_S 30 645 #define PF0INT_OICR_PSM_PAGE_XLR_HW_DONE_M BIT(30) 646 #define PF0INT_OICR_PSM_PAGE_SWINT_S 31 647 #define PF0INT_OICR_PSM_PAGE_SWINT_M BIT(31) 648 #define QRX_TAIL_PAGE(_QRX) (0x03800000 + ((_QRX) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */ 649 #define QRX_TAIL_PAGE_MAX_INDEX 2047 650 #define QRX_TAIL_PAGE_TAIL_S 0 651 #define QRX_TAIL_PAGE_TAIL_M MAKEMASK(0x1FFF, 0) 652 #define QTX_COMM_DBELL_PAGE(_DBQM) (0x04000000 + ((_DBQM) * 4096)) /* _i=0...16383 */ /* Reset Source: CORER */ 653 #define QTX_COMM_DBELL_PAGE_MAX_INDEX 16383 654 #define QTX_COMM_DBELL_PAGE_QTX_COMM_DBELL_S 0 655 #define QTX_COMM_DBELL_PAGE_QTX_COMM_DBELL_M MAKEMASK(0xFFFFFFFF, 0) 656 #define E800_QTX_COMM_DBLQ_DBELL_PAGE(_DBLQ) (0x02F00000 + ((_DBLQ) * 4096)) /* _i=0...255 */ /* Reset Source: CORER */ 657 #define E800_QTX_COMM_DBLQ_DBELL_PAGE_MAX_INDEX 255 658 #define E800_QTX_COMM_DBLQ_DBELL_PAGE_TAIL_S 0 659 #define E800_QTX_COMM_DBLQ_DBELL_PAGE_TAIL_M MAKEMASK(0x1FFF, 0) 660 #define VSI_MBX_ARQBAH(_VSI) (0x02000018 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */ 661 #define VSI_MBX_ARQBAH_MAX_INDEX 767 662 #define VSI_MBX_ARQBAH_ARQBAH_S 0 663 #define VSI_MBX_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 664 #define VSI_MBX_ARQBAL(_VSI) (0x02000014 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */ 665 #define VSI_MBX_ARQBAL_MAX_INDEX 767 666 #define VSI_MBX_ARQBAL_ARQBAL_LSB_S 0 667 #define VSI_MBX_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 668 #define VSI_MBX_ARQBAL_ARQBAL_S 6 669 #define VSI_MBX_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 670 #define VSI_MBX_ARQH(_VSI) (0x02000020 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */ 671 #define VSI_MBX_ARQH_MAX_INDEX 767 672 #define VSI_MBX_ARQH_ARQH_S 0 673 #define VSI_MBX_ARQH_ARQH_M MAKEMASK(0x3FF, 0) 674 #define VSI_MBX_ARQLEN(_VSI) (0x0200001C + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: PFR */ 675 #define VSI_MBX_ARQLEN_MAX_INDEX 767 676 #define VSI_MBX_ARQLEN_ARQLEN_S 0 677 #define VSI_MBX_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0) 678 #define VSI_MBX_ARQLEN_ARQVFE_S 28 679 #define VSI_MBX_ARQLEN_ARQVFE_M BIT(28) 680 #define VSI_MBX_ARQLEN_ARQOVFL_S 29 681 #define VSI_MBX_ARQLEN_ARQOVFL_M BIT(29) 682 #define VSI_MBX_ARQLEN_ARQCRIT_S 30 683 #define VSI_MBX_ARQLEN_ARQCRIT_M BIT(30) 684 #define VSI_MBX_ARQLEN_ARQENABLE_S 31 685 #define VSI_MBX_ARQLEN_ARQENABLE_M BIT(31) 686 #define VSI_MBX_ARQT(_VSI) (0x02000024 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */ 687 #define VSI_MBX_ARQT_MAX_INDEX 767 688 #define VSI_MBX_ARQT_ARQT_S 0 689 #define VSI_MBX_ARQT_ARQT_M MAKEMASK(0x3FF, 0) 690 #define VSI_MBX_ATQBAH(_VSI) (0x02000004 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */ 691 #define VSI_MBX_ATQBAH_MAX_INDEX 767 692 #define VSI_MBX_ATQBAH_ATQBAH_S 0 693 #define VSI_MBX_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 694 #define VSI_MBX_ATQBAL(_VSI) (0x02000000 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */ 695 #define VSI_MBX_ATQBAL_MAX_INDEX 767 696 #define VSI_MBX_ATQBAL_ATQBAL_S 6 697 #define VSI_MBX_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 698 #define VSI_MBX_ATQH(_VSI) (0x0200000C + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */ 699 #define VSI_MBX_ATQH_MAX_INDEX 767 700 #define VSI_MBX_ATQH_ATQH_S 0 701 #define VSI_MBX_ATQH_ATQH_M MAKEMASK(0x3FF, 0) 702 #define VSI_MBX_ATQLEN(_VSI) (0x02000008 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: PFR */ 703 #define VSI_MBX_ATQLEN_MAX_INDEX 767 704 #define VSI_MBX_ATQLEN_ATQLEN_S 0 705 #define VSI_MBX_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0) 706 #define VSI_MBX_ATQLEN_ATQVFE_S 28 707 #define VSI_MBX_ATQLEN_ATQVFE_M BIT(28) 708 #define VSI_MBX_ATQLEN_ATQOVFL_S 29 709 #define VSI_MBX_ATQLEN_ATQOVFL_M BIT(29) 710 #define VSI_MBX_ATQLEN_ATQCRIT_S 30 711 #define VSI_MBX_ATQLEN_ATQCRIT_M BIT(30) 712 #define VSI_MBX_ATQLEN_ATQENABLE_S 31 713 #define VSI_MBX_ATQLEN_ATQENABLE_M BIT(31) 714 #define VSI_MBX_ATQT(_VSI) (0x02000010 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */ 715 #define VSI_MBX_ATQT_MAX_INDEX 767 716 #define VSI_MBX_ATQT_ATQT_S 0 717 #define VSI_MBX_ATQT_ATQT_M MAKEMASK(0x3FF, 0) 718 #define GL_ACL_ACCESS_CMD 0x00391000 /* Reset Source: CORER */ 719 #define GL_ACL_ACCESS_CMD_TABLE_ID_S 0 720 #define GL_ACL_ACCESS_CMD_TABLE_ID_M MAKEMASK(0xFF, 0) 721 #define GL_ACL_ACCESS_CMD_ENTRY_INDEX_S 8 722 #define GL_ACL_ACCESS_CMD_ENTRY_INDEX_M MAKEMASK(0xFFF, 8) 723 #define GL_ACL_ACCESS_CMD_OPERATION_S 20 724 #define GL_ACL_ACCESS_CMD_OPERATION_M BIT(20) 725 #define GL_ACL_ACCESS_CMD_OBJ_TYPE_S 24 726 #define GL_ACL_ACCESS_CMD_OBJ_TYPE_M MAKEMASK(0xF, 24) 727 #define GL_ACL_ACCESS_CMD_EXECUTE_S 31 728 #define GL_ACL_ACCESS_CMD_EXECUTE_M BIT(31) 729 #define GL_ACL_ACCESS_STATUS 0x00391004 /* Reset Source: CORER */ 730 #define GL_ACL_ACCESS_STATUS_BUSY_S 0 731 #define GL_ACL_ACCESS_STATUS_BUSY_M BIT(0) 732 #define GL_ACL_ACCESS_STATUS_DONE_S 1 733 #define GL_ACL_ACCESS_STATUS_DONE_M BIT(1) 734 #define GL_ACL_ACCESS_STATUS_ERROR_S 2 735 #define GL_ACL_ACCESS_STATUS_ERROR_M BIT(2) 736 #define GL_ACL_ACCESS_STATUS_OPERATION_S 3 737 #define GL_ACL_ACCESS_STATUS_OPERATION_M BIT(3) 738 #define GL_ACL_ACCESS_STATUS_ERROR_CODE_S 4 739 #define GL_ACL_ACCESS_STATUS_ERROR_CODE_M MAKEMASK(0xF, 4) 740 #define GL_ACL_ACCESS_STATUS_TABLE_ID_S 8 741 #define GL_ACL_ACCESS_STATUS_TABLE_ID_M MAKEMASK(0xFF, 8) 742 #define GL_ACL_ACCESS_STATUS_ENTRY_INDEX_S 16 743 #define GL_ACL_ACCESS_STATUS_ENTRY_INDEX_M MAKEMASK(0xFFF, 16) 744 #define GL_ACL_ACCESS_STATUS_OBJ_TYPE_S 28 745 #define GL_ACL_ACCESS_STATUS_OBJ_TYPE_M MAKEMASK(0xF, 28) 746 #define GL_ACL_ACTMEM_ACT(_i) (0x00393824 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 747 #define GL_ACL_ACTMEM_ACT_MAX_INDEX 1 748 #define GL_ACL_ACTMEM_ACT_VALUE_S 0 749 #define GL_ACL_ACTMEM_ACT_VALUE_M MAKEMASK(0xFFFF, 0) 750 #define GL_ACL_ACTMEM_ACT_MDID_S 20 751 #define GL_ACL_ACTMEM_ACT_MDID_M MAKEMASK(0x3F, 20) 752 #define GL_ACL_ACTMEM_ACT_PRIORITY_S 28 753 #define GL_ACL_ACTMEM_ACT_PRIORITY_M MAKEMASK(0x7, 28) 754 #define GL_ACL_CHICKEN_REGISTER 0x00393810 /* Reset Source: CORER */ 755 #define GL_ACL_CHICKEN_REGISTER_TCAM_DATA_POL_CH_S 0 756 #define GL_ACL_CHICKEN_REGISTER_TCAM_DATA_POL_CH_M BIT(0) 757 #define GL_ACL_CHICKEN_REGISTER_TCAM_ADDR_POL_CH_S 1 758 #define GL_ACL_CHICKEN_REGISTER_TCAM_ADDR_POL_CH_M BIT(1) 759 #define GL_ACL_DEFAULT_ACT(_i) (0x00391168 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 760 #define GL_ACL_DEFAULT_ACT_MAX_INDEX 15 761 #define GL_ACL_DEFAULT_ACT_VALUE_S 0 762 #define GL_ACL_DEFAULT_ACT_VALUE_M MAKEMASK(0xFFFF, 0) 763 #define GL_ACL_DEFAULT_ACT_MDID_S 20 764 #define GL_ACL_DEFAULT_ACT_MDID_M MAKEMASK(0x3F, 20) 765 #define GL_ACL_DEFAULT_ACT_PRIORITY_S 28 766 #define GL_ACL_DEFAULT_ACT_PRIORITY_M MAKEMASK(0x7, 28) 767 #define GL_ACL_PROFILE_BWSB_SEL(_i) (0x00391008 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 768 #define GL_ACL_PROFILE_BWSB_SEL_MAX_INDEX 31 769 #define GL_ACL_PROFILE_BWSB_SEL_BSB_SRC_OFF_S 0 770 #define GL_ACL_PROFILE_BWSB_SEL_BSB_SRC_OFF_M MAKEMASK(0x3F, 0) 771 #define GL_ACL_PROFILE_BWSB_SEL_WSB_SRC_OFF_S 8 772 #define GL_ACL_PROFILE_BWSB_SEL_WSB_SRC_OFF_M MAKEMASK(0x1F, 8) 773 #define GL_ACL_PROFILE_DWSB_SEL(_i) (0x00391088 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 774 #define GL_ACL_PROFILE_DWSB_SEL_MAX_INDEX 15 775 #define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_S 0 776 #define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_M MAKEMASK(0xF, 0) 777 #define GL_ACL_PROFILE_PF_CFG(_i) (0x003910C8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 778 #define GL_ACL_PROFILE_PF_CFG_MAX_INDEX 7 779 #define GL_ACL_PROFILE_PF_CFG_SCEN_SEL_S 0 780 #define GL_ACL_PROFILE_PF_CFG_SCEN_SEL_M MAKEMASK(0x3F, 0) 781 #define GL_ACL_PROFILE_RC_CFG(_i) (0x003910E8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 782 #define GL_ACL_PROFILE_RC_CFG_MAX_INDEX 7 783 #define GL_ACL_PROFILE_RC_CFG_LOW_BOUND_S 0 784 #define GL_ACL_PROFILE_RC_CFG_LOW_BOUND_M MAKEMASK(0xFFFF, 0) 785 #define GL_ACL_PROFILE_RC_CFG_HIGH_BOUND_S 16 786 #define GL_ACL_PROFILE_RC_CFG_HIGH_BOUND_M MAKEMASK(0xFFFF, 16) 787 #define GL_ACL_PROFILE_RCF_MASK(_i) (0x00391108 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 788 #define GL_ACL_PROFILE_RCF_MASK_MAX_INDEX 7 789 #define GL_ACL_PROFILE_RCF_MASK_MASK_S 0 790 #define GL_ACL_PROFILE_RCF_MASK_MASK_M MAKEMASK(0xFFFF, 0) 791 #define GL_ACL_SCENARIO_ACT_CFG(_i) (0x003938AC + ((_i) * 4)) /* _i=0...19 */ /* Reset Source: CORER */ 792 #define GL_ACL_SCENARIO_ACT_CFG_MAX_INDEX 19 793 #define GL_ACL_SCENARIO_ACT_CFG_ACTMEM_SEL_S 0 794 #define GL_ACL_SCENARIO_ACT_CFG_ACTMEM_SEL_M MAKEMASK(0xF, 0) 795 #define GL_ACL_SCENARIO_ACT_CFG_ACTMEM_EN_S 8 796 #define GL_ACL_SCENARIO_ACT_CFG_ACTMEM_EN_M BIT(8) 797 #define GL_ACL_SCENARIO_CFG_H(_i) (0x0039386C + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 798 #define GL_ACL_SCENARIO_CFG_H_MAX_INDEX 15 799 #define GL_ACL_SCENARIO_CFG_H_SELECT4_S 0 800 #define GL_ACL_SCENARIO_CFG_H_SELECT4_M MAKEMASK(0x1F, 0) 801 #define GL_ACL_SCENARIO_CFG_H_CHUNKMASK_S 8 802 #define GL_ACL_SCENARIO_CFG_H_CHUNKMASK_M MAKEMASK(0xFF, 8) 803 #define GL_ACL_SCENARIO_CFG_H_START_COMPARE_S 24 804 #define GL_ACL_SCENARIO_CFG_H_START_COMPARE_M BIT(24) 805 #define GL_ACL_SCENARIO_CFG_H_START_SET_S 28 806 #define GL_ACL_SCENARIO_CFG_H_START_SET_M BIT(28) 807 #define GL_ACL_SCENARIO_CFG_L(_i) (0x0039382C + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 808 #define GL_ACL_SCENARIO_CFG_L_MAX_INDEX 15 809 #define GL_ACL_SCENARIO_CFG_L_SELECT0_S 0 810 #define GL_ACL_SCENARIO_CFG_L_SELECT0_M MAKEMASK(0x7F, 0) 811 #define GL_ACL_SCENARIO_CFG_L_SELECT1_S 8 812 #define GL_ACL_SCENARIO_CFG_L_SELECT1_M MAKEMASK(0x7F, 8) 813 #define GL_ACL_SCENARIO_CFG_L_SELECT2_S 16 814 #define GL_ACL_SCENARIO_CFG_L_SELECT2_M MAKEMASK(0x7F, 16) 815 #define GL_ACL_SCENARIO_CFG_L_SELECT3_S 24 816 #define GL_ACL_SCENARIO_CFG_L_SELECT3_M MAKEMASK(0x7F, 24) 817 #define GL_ACL_TCAM_KEY_H 0x00393818 /* Reset Source: CORER */ 818 #define GL_ACL_TCAM_KEY_H_GL_ACL_FFU_TCAM_KEY_H_S 0 819 #define GL_ACL_TCAM_KEY_H_GL_ACL_FFU_TCAM_KEY_H_M MAKEMASK(0xFF, 0) 820 #define GL_ACL_TCAM_KEY_INV_H 0x00393820 /* Reset Source: CORER */ 821 #define GL_ACL_TCAM_KEY_INV_H_GL_ACL_FFU_TCAM_KEY_INV_H_S 0 822 #define GL_ACL_TCAM_KEY_INV_H_GL_ACL_FFU_TCAM_KEY_INV_H_M MAKEMASK(0xFF, 0) 823 #define GL_ACL_TCAM_KEY_INV_L 0x0039381C /* Reset Source: CORER */ 824 #define GL_ACL_TCAM_KEY_INV_L_GL_ACL_FFU_TCAM_KEY_INV_L_S 0 825 #define GL_ACL_TCAM_KEY_INV_L_GL_ACL_FFU_TCAM_KEY_INV_L_M MAKEMASK(0xFFFFFFFF, 0) 826 #define GL_ACL_TCAM_KEY_L 0x00393814 /* Reset Source: CORER */ 827 #define GL_ACL_TCAM_KEY_L_GL_ACL_FFU_TCAM_KEY_L_S 0 828 #define GL_ACL_TCAM_KEY_L_GL_ACL_FFU_TCAM_KEY_L_M MAKEMASK(0xFFFFFFFF, 0) 829 #define VSI_ACL_DEF_SEL(_VSI) (0x00391800 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 830 #define VSI_ACL_DEF_SEL_MAX_INDEX 767 831 #define VSI_ACL_DEF_SEL_RX_PROFILE_MISS_SEL_S 0 832 #define VSI_ACL_DEF_SEL_RX_PROFILE_MISS_SEL_M MAKEMASK(0x3, 0) 833 #define VSI_ACL_DEF_SEL_RX_TABLES_MISS_SEL_S 4 834 #define VSI_ACL_DEF_SEL_RX_TABLES_MISS_SEL_M MAKEMASK(0x3, 4) 835 #define VSI_ACL_DEF_SEL_TX_PROFILE_MISS_SEL_S 8 836 #define VSI_ACL_DEF_SEL_TX_PROFILE_MISS_SEL_M MAKEMASK(0x3, 8) 837 #define VSI_ACL_DEF_SEL_TX_TABLES_MISS_SEL_S 12 838 #define VSI_ACL_DEF_SEL_TX_TABLES_MISS_SEL_M MAKEMASK(0x3, 12) 839 #define GL_SWT_L2TAG0(_i) (0x000492A8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 840 #define GL_SWT_L2TAG0_MAX_INDEX 7 841 #define GL_SWT_L2TAG0_DATA_S 0 842 #define GL_SWT_L2TAG0_DATA_M MAKEMASK(0xFFFFFFFF, 0) 843 #define GL_SWT_L2TAG1(_i) (0x000492C8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 844 #define GL_SWT_L2TAG1_MAX_INDEX 7 845 #define GL_SWT_L2TAG1_DATA_S 0 846 #define GL_SWT_L2TAG1_DATA_M MAKEMASK(0xFFFFFFFF, 0) 847 #define GL_SWT_L2TAGCTRL(_i) (0x001D2660 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 848 #define GL_SWT_L2TAGCTRL_MAX_INDEX 7 849 #define GL_SWT_L2TAGCTRL_LENGTH_S 0 850 #define GL_SWT_L2TAGCTRL_LENGTH_M MAKEMASK(0x7F, 0) 851 #define GL_SWT_L2TAGCTRL_HAS_UP_S 7 852 #define GL_SWT_L2TAGCTRL_HAS_UP_M BIT(7) 853 #define GL_SWT_L2TAGCTRL_ISVLAN_S 9 854 #define GL_SWT_L2TAGCTRL_ISVLAN_M BIT(9) 855 #define GL_SWT_L2TAGCTRL_INNERUP_S 10 856 #define GL_SWT_L2TAGCTRL_INNERUP_M BIT(10) 857 #define GL_SWT_L2TAGCTRL_OUTERUP_S 11 858 #define GL_SWT_L2TAGCTRL_OUTERUP_M BIT(11) 859 #define GL_SWT_L2TAGCTRL_LONG_S 12 860 #define GL_SWT_L2TAGCTRL_LONG_M BIT(12) 861 #define GL_SWT_L2TAGCTRL_ISMPLS_S 13 862 #define GL_SWT_L2TAGCTRL_ISMPLS_M BIT(13) 863 #define GL_SWT_L2TAGCTRL_ISNSH_S 14 864 #define GL_SWT_L2TAGCTRL_ISNSH_M BIT(14) 865 #define GL_SWT_L2TAGCTRL_ETHERTYPE_S 16 866 #define GL_SWT_L2TAGCTRL_ETHERTYPE_M MAKEMASK(0xFFFF, 16) 867 #define GL_SWT_L2TAGRXEB(_i) (0x00052000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 868 #define GL_SWT_L2TAGRXEB_MAX_INDEX 7 869 #define GL_SWT_L2TAGRXEB_OFFSET_S 0 870 #define GL_SWT_L2TAGRXEB_OFFSET_M MAKEMASK(0xFF, 0) 871 #define GL_SWT_L2TAGRXEB_LENGTH_S 8 872 #define GL_SWT_L2TAGRXEB_LENGTH_M MAKEMASK(0x3, 8) 873 #define GL_SWT_L2TAGTXIB(_i) (0x000492E8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 874 #define GL_SWT_L2TAGTXIB_MAX_INDEX 7 875 #define GL_SWT_L2TAGTXIB_OFFSET_S 0 876 #define GL_SWT_L2TAGTXIB_OFFSET_M MAKEMASK(0xFF, 0) 877 #define GL_SWT_L2TAGTXIB_LENGTH_S 8 878 #define GL_SWT_L2TAGTXIB_LENGTH_M MAKEMASK(0x3, 8) 879 #define GLCM_PE_CACHESIZE 0x005046B4 /* Reset Source: CORER */ 880 #define GLCM_PE_CACHESIZE_WORD_SIZE_S 0 881 #define GLCM_PE_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFFF, 0) 882 #define GLCM_PE_CACHESIZE_SETS_S 12 883 #define GLCM_PE_CACHESIZE_SETS_M MAKEMASK(0xF, 12) 884 #define GLCM_PE_CACHESIZE_WAYS_S 16 885 #define GLCM_PE_CACHESIZE_WAYS_M MAKEMASK(0x1FF, 16) 886 #define GLCOMM_CQ_CTL(_CQ) (0x000F0000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 887 #define GLCOMM_CQ_CTL_MAX_INDEX 511 888 #define GLCOMM_CQ_CTL_COMP_TYPE_S 0 889 #define GLCOMM_CQ_CTL_COMP_TYPE_M MAKEMASK(0x7, 0) 890 #define GLCOMM_CQ_CTL_CMD_S 4 891 #define GLCOMM_CQ_CTL_CMD_M MAKEMASK(0x7, 4) 892 #define GLCOMM_CQ_CTL_ID_S 16 893 #define GLCOMM_CQ_CTL_ID_M MAKEMASK(0x3FFF, 16) 894 #define GLCOMM_MIN_MAX_PKT 0x000FC064 /* Reset Source: CORER */ 895 #define GLCOMM_MIN_MAX_PKT_MAHDL_S 0 896 #define GLCOMM_MIN_MAX_PKT_MAHDL_M MAKEMASK(0x3FFF, 0) 897 #define GLCOMM_MIN_MAX_PKT_MIHDL_S 16 898 #define GLCOMM_MIN_MAX_PKT_MIHDL_M MAKEMASK(0x3F, 16) 899 #define GLCOMM_MIN_MAX_PKT_LSO_COMS_MIHDL_S 22 900 #define GLCOMM_MIN_MAX_PKT_LSO_COMS_MIHDL_M MAKEMASK(0x3FF, 22) 901 #define GLCOMM_PKT_SHAPER_PROF(_i) (0x002D2DA8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 902 #define GLCOMM_PKT_SHAPER_PROF_MAX_INDEX 7 903 #define GLCOMM_PKT_SHAPER_PROF_PKTCNT_S 0 904 #define GLCOMM_PKT_SHAPER_PROF_PKTCNT_M MAKEMASK(0x3F, 0) 905 #define GLCOMM_QTX_CNTX_CTL 0x002D2DC8 /* Reset Source: CORER */ 906 #define GLCOMM_QTX_CNTX_CTL_QUEUE_ID_S 0 907 #define GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M MAKEMASK(0x3FFF, 0) 908 #define GLCOMM_QTX_CNTX_CTL_CMD_S 16 909 #define GLCOMM_QTX_CNTX_CTL_CMD_M MAKEMASK(0x7, 16) 910 #define GLCOMM_QTX_CNTX_CTL_CMD_EXEC_S 19 911 #define GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M BIT(19) 912 #define GLCOMM_QTX_CNTX_DATA(_i) (0x002D2D40 + ((_i) * 4)) /* _i=0...9 */ /* Reset Source: CORER */ 913 #define GLCOMM_QTX_CNTX_DATA_MAX_INDEX 9 914 #define GLCOMM_QTX_CNTX_DATA_DATA_S 0 915 #define GLCOMM_QTX_CNTX_DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0) 916 #define GLCOMM_QTX_CNTX_STAT 0x002D2DCC /* Reset Source: CORER */ 917 #define GLCOMM_QTX_CNTX_STAT_CMD_IN_PROG_S 0 918 #define GLCOMM_QTX_CNTX_STAT_CMD_IN_PROG_M BIT(0) 919 #define GLCOMM_QUANTA_PROF(_i) (0x002D2D68 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 920 #define GLCOMM_QUANTA_PROF_MAX_INDEX 15 921 #define GLCOMM_QUANTA_PROF_QUANTA_SIZE_S 0 922 #define GLCOMM_QUANTA_PROF_QUANTA_SIZE_M MAKEMASK(0x3FFF, 0) 923 #define GLCOMM_QUANTA_PROF_MAX_CMD_S 16 924 #define GLCOMM_QUANTA_PROF_MAX_CMD_M MAKEMASK(0xFF, 16) 925 #define GLCOMM_QUANTA_PROF_MAX_DESC_S 24 926 #define GLCOMM_QUANTA_PROF_MAX_DESC_M MAKEMASK(0x3F, 24) 927 #define GLLAN_TCLAN_CACHE_CTL 0x000FC0B8 /* Reset Source: CORER */ 928 #define GLLAN_TCLAN_CACHE_CTL_MIN_FETCH_THRESH_S 0 929 #define GLLAN_TCLAN_CACHE_CTL_MIN_FETCH_THRESH_M MAKEMASK(0x3F, 0) 930 #define GLLAN_TCLAN_CACHE_CTL_FETCH_CL_ALIGN_S 6 931 #define GLLAN_TCLAN_CACHE_CTL_FETCH_CL_ALIGN_M BIT(6) 932 #define GLLAN_TCLAN_CACHE_CTL_MIN_ALLOC_THRESH_S 7 933 #define GLLAN_TCLAN_CACHE_CTL_MIN_ALLOC_THRESH_M MAKEMASK(0x7F, 7) 934 #define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_S 14 935 #define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_M MAKEMASK(0xFF, 14) 936 #define GLLAN_TCLAN_CACHE_CTL_CACHE_DESC_LIM_S 22 937 #define GLLAN_TCLAN_CACHE_CTL_CACHE_DESC_LIM_M MAKEMASK(0x3FF, 22) 938 #define GLTCLAN_CQ_CNTX0(_CQ) (0x000F0800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 939 #define GLTCLAN_CQ_CNTX0_MAX_INDEX 511 940 #define GLTCLAN_CQ_CNTX0_RING_ADDR_LSB_S 0 941 #define GLTCLAN_CQ_CNTX0_RING_ADDR_LSB_M MAKEMASK(0xFFFFFFFF, 0) 942 #define GLTCLAN_CQ_CNTX1(_CQ) (0x000F1000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 943 #define GLTCLAN_CQ_CNTX1_MAX_INDEX 511 944 #define GLTCLAN_CQ_CNTX1_RING_ADDR_MSB_S 0 945 #define GLTCLAN_CQ_CNTX1_RING_ADDR_MSB_M MAKEMASK(0x1FFFFFF, 0) 946 #define GLTCLAN_CQ_CNTX10(_CQ) (0x000F5800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 947 #define GLTCLAN_CQ_CNTX10_MAX_INDEX 511 948 #define GLTCLAN_CQ_CNTX10_CQ_CACHLINE_S 0 949 #define GLTCLAN_CQ_CNTX10_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0) 950 #define GLTCLAN_CQ_CNTX11(_CQ) (0x000F6000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 951 #define GLTCLAN_CQ_CNTX11_MAX_INDEX 511 952 #define GLTCLAN_CQ_CNTX11_CQ_CACHLINE_S 0 953 #define GLTCLAN_CQ_CNTX11_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0) 954 #define GLTCLAN_CQ_CNTX12(_CQ) (0x000F6800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 955 #define GLTCLAN_CQ_CNTX12_MAX_INDEX 511 956 #define GLTCLAN_CQ_CNTX12_CQ_CACHLINE_S 0 957 #define GLTCLAN_CQ_CNTX12_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0) 958 #define GLTCLAN_CQ_CNTX13(_CQ) (0x000F7000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 959 #define GLTCLAN_CQ_CNTX13_MAX_INDEX 511 960 #define GLTCLAN_CQ_CNTX13_CQ_CACHLINE_S 0 961 #define GLTCLAN_CQ_CNTX13_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0) 962 #define GLTCLAN_CQ_CNTX14(_CQ) (0x000F7800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 963 #define GLTCLAN_CQ_CNTX14_MAX_INDEX 511 964 #define GLTCLAN_CQ_CNTX14_CQ_CACHLINE_S 0 965 #define GLTCLAN_CQ_CNTX14_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0) 966 #define GLTCLAN_CQ_CNTX15(_CQ) (0x000F8000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 967 #define GLTCLAN_CQ_CNTX15_MAX_INDEX 511 968 #define GLTCLAN_CQ_CNTX15_CQ_CACHLINE_S 0 969 #define GLTCLAN_CQ_CNTX15_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0) 970 #define GLTCLAN_CQ_CNTX16(_CQ) (0x000F8800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 971 #define GLTCLAN_CQ_CNTX16_MAX_INDEX 511 972 #define GLTCLAN_CQ_CNTX16_CQ_CACHLINE_S 0 973 #define GLTCLAN_CQ_CNTX16_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0) 974 #define GLTCLAN_CQ_CNTX17(_CQ) (0x000F9000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 975 #define GLTCLAN_CQ_CNTX17_MAX_INDEX 511 976 #define GLTCLAN_CQ_CNTX17_CQ_CACHLINE_S 0 977 #define GLTCLAN_CQ_CNTX17_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0) 978 #define GLTCLAN_CQ_CNTX18(_CQ) (0x000F9800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 979 #define GLTCLAN_CQ_CNTX18_MAX_INDEX 511 980 #define GLTCLAN_CQ_CNTX18_CQ_CACHLINE_S 0 981 #define GLTCLAN_CQ_CNTX18_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0) 982 #define GLTCLAN_CQ_CNTX19(_CQ) (0x000FA000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 983 #define GLTCLAN_CQ_CNTX19_MAX_INDEX 511 984 #define GLTCLAN_CQ_CNTX19_CQ_CACHLINE_S 0 985 #define GLTCLAN_CQ_CNTX19_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0) 986 #define GLTCLAN_CQ_CNTX2(_CQ) (0x000F1800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 987 #define GLTCLAN_CQ_CNTX2_MAX_INDEX 511 988 #define GLTCLAN_CQ_CNTX2_RING_LEN_S 0 989 #define GLTCLAN_CQ_CNTX2_RING_LEN_M MAKEMASK(0x3FFFF, 0) 990 #define GLTCLAN_CQ_CNTX20(_CQ) (0x000FA800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 991 #define GLTCLAN_CQ_CNTX20_MAX_INDEX 511 992 #define GLTCLAN_CQ_CNTX20_CQ_CACHLINE_S 0 993 #define GLTCLAN_CQ_CNTX20_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0) 994 #define GLTCLAN_CQ_CNTX21(_CQ) (0x000FB000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 995 #define GLTCLAN_CQ_CNTX21_MAX_INDEX 511 996 #define GLTCLAN_CQ_CNTX21_CQ_CACHLINE_S 0 997 #define GLTCLAN_CQ_CNTX21_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0) 998 #define GLTCLAN_CQ_CNTX3(_CQ) (0x000F2000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 999 #define GLTCLAN_CQ_CNTX3_MAX_INDEX 511 1000 #define GLTCLAN_CQ_CNTX3_GENERATION_S 0 1001 #define GLTCLAN_CQ_CNTX3_GENERATION_M BIT(0) 1002 #define GLTCLAN_CQ_CNTX3_CQ_WR_PTR_S 1 1003 #define GLTCLAN_CQ_CNTX3_CQ_WR_PTR_M MAKEMASK(0x3FFFFF, 1) 1004 #define GLTCLAN_CQ_CNTX4(_CQ) (0x000F2800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 1005 #define GLTCLAN_CQ_CNTX4_MAX_INDEX 511 1006 #define GLTCLAN_CQ_CNTX4_PF_NUM_S 0 1007 #define GLTCLAN_CQ_CNTX4_PF_NUM_M MAKEMASK(0x7, 0) 1008 #define GLTCLAN_CQ_CNTX4_VMVF_NUM_S 3 1009 #define GLTCLAN_CQ_CNTX4_VMVF_NUM_M MAKEMASK(0x3FF, 3) 1010 #define GLTCLAN_CQ_CNTX4_VMVF_TYPE_S 13 1011 #define GLTCLAN_CQ_CNTX4_VMVF_TYPE_M MAKEMASK(0x3, 13) 1012 #define GLTCLAN_CQ_CNTX5(_CQ) (0x000F3000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 1013 #define GLTCLAN_CQ_CNTX5_MAX_INDEX 511 1014 #define GLTCLAN_CQ_CNTX5_TPH_EN_S 0 1015 #define GLTCLAN_CQ_CNTX5_TPH_EN_M BIT(0) 1016 #define GLTCLAN_CQ_CNTX5_CPU_ID_S 1 1017 #define GLTCLAN_CQ_CNTX5_CPU_ID_M MAKEMASK(0xFF, 1) 1018 #define GLTCLAN_CQ_CNTX5_FLUSH_ON_ITR_DIS_S 9 1019 #define GLTCLAN_CQ_CNTX5_FLUSH_ON_ITR_DIS_M BIT(9) 1020 #define GLTCLAN_CQ_CNTX6(_CQ) (0x000F3800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 1021 #define GLTCLAN_CQ_CNTX6_MAX_INDEX 511 1022 #define GLTCLAN_CQ_CNTX6_CQ_CACHLINE_S 0 1023 #define GLTCLAN_CQ_CNTX6_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0) 1024 #define GLTCLAN_CQ_CNTX7(_CQ) (0x000F4000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 1025 #define GLTCLAN_CQ_CNTX7_MAX_INDEX 511 1026 #define GLTCLAN_CQ_CNTX7_CQ_CACHLINE_S 0 1027 #define GLTCLAN_CQ_CNTX7_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0) 1028 #define GLTCLAN_CQ_CNTX8(_CQ) (0x000F4800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 1029 #define GLTCLAN_CQ_CNTX8_MAX_INDEX 511 1030 #define GLTCLAN_CQ_CNTX8_CQ_CACHLINE_S 0 1031 #define GLTCLAN_CQ_CNTX8_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0) 1032 #define GLTCLAN_CQ_CNTX9(_CQ) (0x000F5000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 1033 #define GLTCLAN_CQ_CNTX9_MAX_INDEX 511 1034 #define GLTCLAN_CQ_CNTX9_CQ_CACHLINE_S 0 1035 #define GLTCLAN_CQ_CNTX9_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0) 1036 #define QTX_COMM_DBELL(_DBQM) (0x002C0000 + ((_DBQM) * 4)) /* _i=0...16383 */ /* Reset Source: CORER */ 1037 #define QTX_COMM_DBELL_MAX_INDEX 16383 1038 #define QTX_COMM_DBELL_QTX_COMM_DBELL_S 0 1039 #define QTX_COMM_DBELL_QTX_COMM_DBELL_M MAKEMASK(0xFFFFFFFF, 0) 1040 #define QTX_COMM_DBLQ_CNTX(_i, _DBLQ) (0x002D0000 + ((_i) * 1024 + (_DBLQ) * 4)) /* _i=0...4, _DBLQ=0...255 */ /* Reset Source: CORER */ 1041 #define QTX_COMM_DBLQ_CNTX_MAX_INDEX 4 1042 #define QTX_COMM_DBLQ_CNTX_DATA_S 0 1043 #define QTX_COMM_DBLQ_CNTX_DATA_M MAKEMASK(0xFFFFFFFF, 0) 1044 #define QTX_COMM_DBLQ_DBELL(_DBLQ) (0x002D1400 + ((_DBLQ) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 1045 #define QTX_COMM_DBLQ_DBELL_MAX_INDEX 255 1046 #define QTX_COMM_DBLQ_DBELL_TAIL_S 0 1047 #define QTX_COMM_DBLQ_DBELL_TAIL_M MAKEMASK(0x1FFF, 0) 1048 #define QTX_COMM_HEAD(_DBQM) (0x000E0000 + ((_DBQM) * 4)) /* _i=0...16383 */ /* Reset Source: CORER */ 1049 #define QTX_COMM_HEAD_MAX_INDEX 16383 1050 #define QTX_COMM_HEAD_HEAD_S 0 1051 #define QTX_COMM_HEAD_HEAD_M MAKEMASK(0x1FFF, 0) 1052 #define QTX_COMM_HEAD_RS_PENDING_S 16 1053 #define QTX_COMM_HEAD_RS_PENDING_M BIT(16) 1054 #define GL_FW_TOOL_ARQBAH 0x000801C0 /* Reset Source: EMPR */ 1055 #define GL_FW_TOOL_ARQBAH_ARQBAH_S 0 1056 #define GL_FW_TOOL_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1057 #define GL_FW_TOOL_ARQBAL 0x000800C0 /* Reset Source: EMPR */ 1058 #define GL_FW_TOOL_ARQBAL_ARQBAL_LSB_S 0 1059 #define GL_FW_TOOL_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 1060 #define GL_FW_TOOL_ARQBAL_ARQBAL_S 6 1061 #define GL_FW_TOOL_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 1062 #define GL_FW_TOOL_ARQH 0x000803C0 /* Reset Source: EMPR */ 1063 #define GL_FW_TOOL_ARQH_ARQH_S 0 1064 #define GL_FW_TOOL_ARQH_ARQH_M MAKEMASK(0x3FF, 0) 1065 #define GL_FW_TOOL_ARQLEN 0x000802C0 /* Reset Source: EMPR */ 1066 #define GL_FW_TOOL_ARQLEN_ARQLEN_S 0 1067 #define GL_FW_TOOL_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0) 1068 #define GL_FW_TOOL_ARQLEN_ARQVFE_S 28 1069 #define GL_FW_TOOL_ARQLEN_ARQVFE_M BIT(28) 1070 #define GL_FW_TOOL_ARQLEN_ARQOVFL_S 29 1071 #define GL_FW_TOOL_ARQLEN_ARQOVFL_M BIT(29) 1072 #define GL_FW_TOOL_ARQLEN_ARQCRIT_S 30 1073 #define GL_FW_TOOL_ARQLEN_ARQCRIT_M BIT(30) 1074 #define GL_FW_TOOL_ARQLEN_ARQENABLE_S 31 1075 #define GL_FW_TOOL_ARQLEN_ARQENABLE_M BIT(31) 1076 #define GL_FW_TOOL_ARQT 0x000804C0 /* Reset Source: EMPR */ 1077 #define GL_FW_TOOL_ARQT_ARQT_S 0 1078 #define GL_FW_TOOL_ARQT_ARQT_M MAKEMASK(0x3FF, 0) 1079 #define GL_FW_TOOL_ATQBAH 0x00080140 /* Reset Source: EMPR */ 1080 #define GL_FW_TOOL_ATQBAH_ATQBAH_S 0 1081 #define GL_FW_TOOL_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1082 #define GL_FW_TOOL_ATQBAL 0x00080040 /* Reset Source: EMPR */ 1083 #define GL_FW_TOOL_ATQBAL_ATQBAL_LSB_S 0 1084 #define GL_FW_TOOL_ATQBAL_ATQBAL_LSB_M MAKEMASK(0x3F, 0) 1085 #define GL_FW_TOOL_ATQBAL_ATQBAL_S 6 1086 #define GL_FW_TOOL_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 1087 #define GL_FW_TOOL_ATQH 0x00080340 /* Reset Source: EMPR */ 1088 #define GL_FW_TOOL_ATQH_ATQH_S 0 1089 #define GL_FW_TOOL_ATQH_ATQH_M MAKEMASK(0x3FF, 0) 1090 #define GL_FW_TOOL_ATQLEN 0x00080240 /* Reset Source: EMPR */ 1091 #define GL_FW_TOOL_ATQLEN_ATQLEN_S 0 1092 #define GL_FW_TOOL_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0) 1093 #define GL_FW_TOOL_ATQLEN_ATQVFE_S 28 1094 #define GL_FW_TOOL_ATQLEN_ATQVFE_M BIT(28) 1095 #define GL_FW_TOOL_ATQLEN_ATQOVFL_S 29 1096 #define GL_FW_TOOL_ATQLEN_ATQOVFL_M BIT(29) 1097 #define GL_FW_TOOL_ATQLEN_ATQCRIT_S 30 1098 #define GL_FW_TOOL_ATQLEN_ATQCRIT_M BIT(30) 1099 #define GL_FW_TOOL_ATQLEN_ATQENABLE_S 31 1100 #define GL_FW_TOOL_ATQLEN_ATQENABLE_M BIT(31) 1101 #define GL_FW_TOOL_ATQT 0x00080440 /* Reset Source: EMPR */ 1102 #define GL_FW_TOOL_ATQT_ATQT_S 0 1103 #define GL_FW_TOOL_ATQT_ATQT_M MAKEMASK(0x3FF, 0) 1104 #define GL_MBX_PASID 0x00231EC0 /* Reset Source: CORER */ 1105 #define GL_MBX_PASID_PASID_MODE_S 0 1106 #define GL_MBX_PASID_PASID_MODE_M BIT(0) 1107 #define GL_MBX_PASID_PASID_MODE_VALID_S 1 1108 #define GL_MBX_PASID_PASID_MODE_VALID_M BIT(1) 1109 #define PF_FW_ARQBAH 0x00080180 /* Reset Source: EMPR */ 1110 #define PF_FW_ARQBAH_ARQBAH_S 0 1111 #define PF_FW_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1112 #define PF_FW_ARQBAL 0x00080080 /* Reset Source: EMPR */ 1113 #define PF_FW_ARQBAL_ARQBAL_LSB_S 0 1114 #define PF_FW_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 1115 #define PF_FW_ARQBAL_ARQBAL_S 6 1116 #define PF_FW_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 1117 #define PF_FW_ARQH 0x00080380 /* Reset Source: EMPR */ 1118 #define PF_FW_ARQH_ARQH_S 0 1119 #define PF_FW_ARQH_ARQH_M MAKEMASK(0x3FF, 0) 1120 #define PF_FW_ARQLEN 0x00080280 /* Reset Source: EMPR */ 1121 #define PF_FW_ARQLEN_ARQLEN_S 0 1122 #define PF_FW_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0) 1123 #define PF_FW_ARQLEN_ARQVFE_S 28 1124 #define PF_FW_ARQLEN_ARQVFE_M BIT(28) 1125 #define PF_FW_ARQLEN_ARQOVFL_S 29 1126 #define PF_FW_ARQLEN_ARQOVFL_M BIT(29) 1127 #define PF_FW_ARQLEN_ARQCRIT_S 30 1128 #define PF_FW_ARQLEN_ARQCRIT_M BIT(30) 1129 #define PF_FW_ARQLEN_ARQENABLE_S 31 1130 #define PF_FW_ARQLEN_ARQENABLE_M BIT(31) 1131 #define PF_FW_ARQT 0x00080480 /* Reset Source: EMPR */ 1132 #define PF_FW_ARQT_ARQT_S 0 1133 #define PF_FW_ARQT_ARQT_M MAKEMASK(0x3FF, 0) 1134 #define PF_FW_ATQBAH 0x00080100 /* Reset Source: EMPR */ 1135 #define PF_FW_ATQBAH_ATQBAH_S 0 1136 #define PF_FW_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1137 #define PF_FW_ATQBAL 0x00080000 /* Reset Source: EMPR */ 1138 #define PF_FW_ATQBAL_ATQBAL_LSB_S 0 1139 #define PF_FW_ATQBAL_ATQBAL_LSB_M MAKEMASK(0x3F, 0) 1140 #define PF_FW_ATQBAL_ATQBAL_S 6 1141 #define PF_FW_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 1142 #define PF_FW_ATQH 0x00080300 /* Reset Source: EMPR */ 1143 #define PF_FW_ATQH_ATQH_S 0 1144 #define PF_FW_ATQH_ATQH_M MAKEMASK(0x3FF, 0) 1145 #define PF_FW_ATQLEN 0x00080200 /* Reset Source: EMPR */ 1146 #define PF_FW_ATQLEN_ATQLEN_S 0 1147 #define PF_FW_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0) 1148 #define PF_FW_ATQLEN_ATQVFE_S 28 1149 #define PF_FW_ATQLEN_ATQVFE_M BIT(28) 1150 #define PF_FW_ATQLEN_ATQOVFL_S 29 1151 #define PF_FW_ATQLEN_ATQOVFL_M BIT(29) 1152 #define PF_FW_ATQLEN_ATQCRIT_S 30 1153 #define PF_FW_ATQLEN_ATQCRIT_M BIT(30) 1154 #define PF_FW_ATQLEN_ATQENABLE_S 31 1155 #define PF_FW_ATQLEN_ATQENABLE_M BIT(31) 1156 #define PF_FW_ATQT 0x00080400 /* Reset Source: EMPR */ 1157 #define PF_FW_ATQT_ATQT_S 0 1158 #define PF_FW_ATQT_ATQT_M MAKEMASK(0x3FF, 0) 1159 #define PF_MBX_ARQBAH 0x0022E400 /* Reset Source: CORER */ 1160 #define PF_MBX_ARQBAH_ARQBAH_S 0 1161 #define PF_MBX_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1162 #define PF_MBX_ARQBAL 0x0022E380 /* Reset Source: CORER */ 1163 #define PF_MBX_ARQBAL_ARQBAL_LSB_S 0 1164 #define PF_MBX_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 1165 #define PF_MBX_ARQBAL_ARQBAL_S 6 1166 #define PF_MBX_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 1167 #define PF_MBX_ARQH 0x0022E500 /* Reset Source: CORER */ 1168 #define PF_MBX_ARQH_ARQH_S 0 1169 #define PF_MBX_ARQH_ARQH_M MAKEMASK(0x3FF, 0) 1170 #define PF_MBX_ARQLEN 0x0022E480 /* Reset Source: PFR */ 1171 #define PF_MBX_ARQLEN_ARQLEN_S 0 1172 #define PF_MBX_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0) 1173 #define PF_MBX_ARQLEN_ARQVFE_S 28 1174 #define PF_MBX_ARQLEN_ARQVFE_M BIT(28) 1175 #define PF_MBX_ARQLEN_ARQOVFL_S 29 1176 #define PF_MBX_ARQLEN_ARQOVFL_M BIT(29) 1177 #define PF_MBX_ARQLEN_ARQCRIT_S 30 1178 #define PF_MBX_ARQLEN_ARQCRIT_M BIT(30) 1179 #define PF_MBX_ARQLEN_ARQENABLE_S 31 1180 #define PF_MBX_ARQLEN_ARQENABLE_M BIT(31) 1181 #define PF_MBX_ARQT 0x0022E580 /* Reset Source: CORER */ 1182 #define PF_MBX_ARQT_ARQT_S 0 1183 #define PF_MBX_ARQT_ARQT_M MAKEMASK(0x3FF, 0) 1184 #define PF_MBX_ATQBAH 0x0022E180 /* Reset Source: CORER */ 1185 #define PF_MBX_ATQBAH_ATQBAH_S 0 1186 #define PF_MBX_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1187 #define PF_MBX_ATQBAL 0x0022E100 /* Reset Source: CORER */ 1188 #define PF_MBX_ATQBAL_ATQBAL_S 6 1189 #define PF_MBX_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 1190 #define PF_MBX_ATQH 0x0022E280 /* Reset Source: CORER */ 1191 #define PF_MBX_ATQH_ATQH_S 0 1192 #define PF_MBX_ATQH_ATQH_M MAKEMASK(0x3FF, 0) 1193 #define PF_MBX_ATQLEN 0x0022E200 /* Reset Source: PFR */ 1194 #define PF_MBX_ATQLEN_ATQLEN_S 0 1195 #define PF_MBX_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0) 1196 #define PF_MBX_ATQLEN_ATQVFE_S 28 1197 #define PF_MBX_ATQLEN_ATQVFE_M BIT(28) 1198 #define PF_MBX_ATQLEN_ATQOVFL_S 29 1199 #define PF_MBX_ATQLEN_ATQOVFL_M BIT(29) 1200 #define PF_MBX_ATQLEN_ATQCRIT_S 30 1201 #define PF_MBX_ATQLEN_ATQCRIT_M BIT(30) 1202 #define PF_MBX_ATQLEN_ATQENABLE_S 31 1203 #define PF_MBX_ATQLEN_ATQENABLE_M BIT(31) 1204 #define PF_MBX_ATQT 0x0022E300 /* Reset Source: CORER */ 1205 #define PF_MBX_ATQT_ATQT_S 0 1206 #define PF_MBX_ATQT_ATQT_M MAKEMASK(0x3FF, 0) 1207 #define PF_SB_ARQBAH 0x0022FF00 /* Reset Source: CORER */ 1208 #define PF_SB_ARQBAH_ARQBAH_S 0 1209 #define PF_SB_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1210 #define PF_SB_ARQBAL 0x0022FE80 /* Reset Source: CORER */ 1211 #define PF_SB_ARQBAL_ARQBAL_LSB_S 0 1212 #define PF_SB_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 1213 #define PF_SB_ARQBAL_ARQBAL_S 6 1214 #define PF_SB_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 1215 #define PF_SB_ARQH 0x00230000 /* Reset Source: CORER */ 1216 #define PF_SB_ARQH_ARQH_S 0 1217 #define PF_SB_ARQH_ARQH_M MAKEMASK(0x3FF, 0) 1218 #define PF_SB_ARQLEN 0x0022FF80 /* Reset Source: PFR */ 1219 #define PF_SB_ARQLEN_ARQLEN_S 0 1220 #define PF_SB_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0) 1221 #define PF_SB_ARQLEN_ARQVFE_S 28 1222 #define PF_SB_ARQLEN_ARQVFE_M BIT(28) 1223 #define PF_SB_ARQLEN_ARQOVFL_S 29 1224 #define PF_SB_ARQLEN_ARQOVFL_M BIT(29) 1225 #define PF_SB_ARQLEN_ARQCRIT_S 30 1226 #define PF_SB_ARQLEN_ARQCRIT_M BIT(30) 1227 #define PF_SB_ARQLEN_ARQENABLE_S 31 1228 #define PF_SB_ARQLEN_ARQENABLE_M BIT(31) 1229 #define PF_SB_ARQT 0x00230080 /* Reset Source: CORER */ 1230 #define PF_SB_ARQT_ARQT_S 0 1231 #define PF_SB_ARQT_ARQT_M MAKEMASK(0x3FF, 0) 1232 #define PF_SB_ATQBAH 0x0022FC80 /* Reset Source: CORER */ 1233 #define PF_SB_ATQBAH_ATQBAH_S 0 1234 #define PF_SB_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1235 #define PF_SB_ATQBAL 0x0022FC00 /* Reset Source: CORER */ 1236 #define PF_SB_ATQBAL_ATQBAL_S 6 1237 #define PF_SB_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 1238 #define PF_SB_ATQH 0x0022FD80 /* Reset Source: CORER */ 1239 #define PF_SB_ATQH_ATQH_S 0 1240 #define PF_SB_ATQH_ATQH_M MAKEMASK(0x3FF, 0) 1241 #define PF_SB_ATQLEN 0x0022FD00 /* Reset Source: PFR */ 1242 #define PF_SB_ATQLEN_ATQLEN_S 0 1243 #define PF_SB_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0) 1244 #define PF_SB_ATQLEN_ATQVFE_S 28 1245 #define PF_SB_ATQLEN_ATQVFE_M BIT(28) 1246 #define PF_SB_ATQLEN_ATQOVFL_S 29 1247 #define PF_SB_ATQLEN_ATQOVFL_M BIT(29) 1248 #define PF_SB_ATQLEN_ATQCRIT_S 30 1249 #define PF_SB_ATQLEN_ATQCRIT_M BIT(30) 1250 #define PF_SB_ATQLEN_ATQENABLE_S 31 1251 #define PF_SB_ATQLEN_ATQENABLE_M BIT(31) 1252 #define PF_SB_ATQT 0x0022FE00 /* Reset Source: CORER */ 1253 #define PF_SB_ATQT_ATQT_S 0 1254 #define PF_SB_ATQT_ATQT_M MAKEMASK(0x3FF, 0) 1255 #define PF_SB_REM_DEV_CTL 0x002300F0 /* Reset Source: CORER */ 1256 #define PF_SB_REM_DEV_CTL_DEST_EN_S 0 1257 #define PF_SB_REM_DEV_CTL_DEST_EN_M MAKEMASK(0xFFFF, 0) 1258 #define PF0_FW_HLP_ARQBAH 0x000801C8 /* Reset Source: EMPR */ 1259 #define PF0_FW_HLP_ARQBAH_ARQBAH_S 0 1260 #define PF0_FW_HLP_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1261 #define PF0_FW_HLP_ARQBAL 0x000800C8 /* Reset Source: EMPR */ 1262 #define PF0_FW_HLP_ARQBAL_ARQBAL_LSB_S 0 1263 #define PF0_FW_HLP_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 1264 #define PF0_FW_HLP_ARQBAL_ARQBAL_S 6 1265 #define PF0_FW_HLP_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 1266 #define PF0_FW_HLP_ARQH 0x000803C8 /* Reset Source: EMPR */ 1267 #define PF0_FW_HLP_ARQH_ARQH_S 0 1268 #define PF0_FW_HLP_ARQH_ARQH_M MAKEMASK(0x3FF, 0) 1269 #define PF0_FW_HLP_ARQLEN 0x000802C8 /* Reset Source: EMPR */ 1270 #define PF0_FW_HLP_ARQLEN_ARQLEN_S 0 1271 #define PF0_FW_HLP_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0) 1272 #define PF0_FW_HLP_ARQLEN_ARQVFE_S 28 1273 #define PF0_FW_HLP_ARQLEN_ARQVFE_M BIT(28) 1274 #define PF0_FW_HLP_ARQLEN_ARQOVFL_S 29 1275 #define PF0_FW_HLP_ARQLEN_ARQOVFL_M BIT(29) 1276 #define PF0_FW_HLP_ARQLEN_ARQCRIT_S 30 1277 #define PF0_FW_HLP_ARQLEN_ARQCRIT_M BIT(30) 1278 #define PF0_FW_HLP_ARQLEN_ARQENABLE_S 31 1279 #define PF0_FW_HLP_ARQLEN_ARQENABLE_M BIT(31) 1280 #define PF0_FW_HLP_ARQT 0x000804C8 /* Reset Source: EMPR */ 1281 #define PF0_FW_HLP_ARQT_ARQT_S 0 1282 #define PF0_FW_HLP_ARQT_ARQT_M MAKEMASK(0x3FF, 0) 1283 #define PF0_FW_HLP_ATQBAH 0x00080148 /* Reset Source: EMPR */ 1284 #define PF0_FW_HLP_ATQBAH_ATQBAH_S 0 1285 #define PF0_FW_HLP_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1286 #define PF0_FW_HLP_ATQBAL 0x00080048 /* Reset Source: EMPR */ 1287 #define PF0_FW_HLP_ATQBAL_ATQBAL_LSB_S 0 1288 #define PF0_FW_HLP_ATQBAL_ATQBAL_LSB_M MAKEMASK(0x3F, 0) 1289 #define PF0_FW_HLP_ATQBAL_ATQBAL_S 6 1290 #define PF0_FW_HLP_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 1291 #define PF0_FW_HLP_ATQH 0x00080348 /* Reset Source: EMPR */ 1292 #define PF0_FW_HLP_ATQH_ATQH_S 0 1293 #define PF0_FW_HLP_ATQH_ATQH_M MAKEMASK(0x3FF, 0) 1294 #define PF0_FW_HLP_ATQLEN 0x00080248 /* Reset Source: EMPR */ 1295 #define PF0_FW_HLP_ATQLEN_ATQLEN_S 0 1296 #define PF0_FW_HLP_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0) 1297 #define PF0_FW_HLP_ATQLEN_ATQVFE_S 28 1298 #define PF0_FW_HLP_ATQLEN_ATQVFE_M BIT(28) 1299 #define PF0_FW_HLP_ATQLEN_ATQOVFL_S 29 1300 #define PF0_FW_HLP_ATQLEN_ATQOVFL_M BIT(29) 1301 #define PF0_FW_HLP_ATQLEN_ATQCRIT_S 30 1302 #define PF0_FW_HLP_ATQLEN_ATQCRIT_M BIT(30) 1303 #define PF0_FW_HLP_ATQLEN_ATQENABLE_S 31 1304 #define PF0_FW_HLP_ATQLEN_ATQENABLE_M BIT(31) 1305 #define PF0_FW_HLP_ATQT 0x00080448 /* Reset Source: EMPR */ 1306 #define PF0_FW_HLP_ATQT_ATQT_S 0 1307 #define PF0_FW_HLP_ATQT_ATQT_M MAKEMASK(0x3FF, 0) 1308 #define PF0_FW_PSM_ARQBAH 0x000801C4 /* Reset Source: EMPR */ 1309 #define PF0_FW_PSM_ARQBAH_ARQBAH_S 0 1310 #define PF0_FW_PSM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1311 #define PF0_FW_PSM_ARQBAL 0x000800C4 /* Reset Source: EMPR */ 1312 #define PF0_FW_PSM_ARQBAL_ARQBAL_LSB_S 0 1313 #define PF0_FW_PSM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 1314 #define PF0_FW_PSM_ARQBAL_ARQBAL_S 6 1315 #define PF0_FW_PSM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 1316 #define PF0_FW_PSM_ARQH 0x000803C4 /* Reset Source: EMPR */ 1317 #define PF0_FW_PSM_ARQH_ARQH_S 0 1318 #define PF0_FW_PSM_ARQH_ARQH_M MAKEMASK(0x3FF, 0) 1319 #define PF0_FW_PSM_ARQLEN 0x000802C4 /* Reset Source: EMPR */ 1320 #define PF0_FW_PSM_ARQLEN_ARQLEN_S 0 1321 #define PF0_FW_PSM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0) 1322 #define PF0_FW_PSM_ARQLEN_ARQVFE_S 28 1323 #define PF0_FW_PSM_ARQLEN_ARQVFE_M BIT(28) 1324 #define PF0_FW_PSM_ARQLEN_ARQOVFL_S 29 1325 #define PF0_FW_PSM_ARQLEN_ARQOVFL_M BIT(29) 1326 #define PF0_FW_PSM_ARQLEN_ARQCRIT_S 30 1327 #define PF0_FW_PSM_ARQLEN_ARQCRIT_M BIT(30) 1328 #define PF0_FW_PSM_ARQLEN_ARQENABLE_S 31 1329 #define PF0_FW_PSM_ARQLEN_ARQENABLE_M BIT(31) 1330 #define PF0_FW_PSM_ARQT 0x000804C4 /* Reset Source: EMPR */ 1331 #define PF0_FW_PSM_ARQT_ARQT_S 0 1332 #define PF0_FW_PSM_ARQT_ARQT_M MAKEMASK(0x3FF, 0) 1333 #define PF0_FW_PSM_ATQBAH 0x00080144 /* Reset Source: EMPR */ 1334 #define PF0_FW_PSM_ATQBAH_ATQBAH_S 0 1335 #define PF0_FW_PSM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1336 #define PF0_FW_PSM_ATQBAL 0x00080044 /* Reset Source: EMPR */ 1337 #define PF0_FW_PSM_ATQBAL_ATQBAL_LSB_S 0 1338 #define PF0_FW_PSM_ATQBAL_ATQBAL_LSB_M MAKEMASK(0x3F, 0) 1339 #define PF0_FW_PSM_ATQBAL_ATQBAL_S 6 1340 #define PF0_FW_PSM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 1341 #define PF0_FW_PSM_ATQH 0x00080344 /* Reset Source: EMPR */ 1342 #define PF0_FW_PSM_ATQH_ATQH_S 0 1343 #define PF0_FW_PSM_ATQH_ATQH_M MAKEMASK(0x3FF, 0) 1344 #define PF0_FW_PSM_ATQLEN 0x00080244 /* Reset Source: EMPR */ 1345 #define PF0_FW_PSM_ATQLEN_ATQLEN_S 0 1346 #define PF0_FW_PSM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0) 1347 #define PF0_FW_PSM_ATQLEN_ATQVFE_S 28 1348 #define PF0_FW_PSM_ATQLEN_ATQVFE_M BIT(28) 1349 #define PF0_FW_PSM_ATQLEN_ATQOVFL_S 29 1350 #define PF0_FW_PSM_ATQLEN_ATQOVFL_M BIT(29) 1351 #define PF0_FW_PSM_ATQLEN_ATQCRIT_S 30 1352 #define PF0_FW_PSM_ATQLEN_ATQCRIT_M BIT(30) 1353 #define PF0_FW_PSM_ATQLEN_ATQENABLE_S 31 1354 #define PF0_FW_PSM_ATQLEN_ATQENABLE_M BIT(31) 1355 #define PF0_FW_PSM_ATQT 0x00080444 /* Reset Source: EMPR */ 1356 #define PF0_FW_PSM_ATQT_ATQT_S 0 1357 #define PF0_FW_PSM_ATQT_ATQT_M MAKEMASK(0x3FF, 0) 1358 #define PF0_MBX_CPM_ARQBAH 0x0022E5D8 /* Reset Source: CORER */ 1359 #define PF0_MBX_CPM_ARQBAH_ARQBAH_S 0 1360 #define PF0_MBX_CPM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1361 #define PF0_MBX_CPM_ARQBAL 0x0022E5D4 /* Reset Source: CORER */ 1362 #define PF0_MBX_CPM_ARQBAL_ARQBAL_LSB_S 0 1363 #define PF0_MBX_CPM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 1364 #define PF0_MBX_CPM_ARQBAL_ARQBAL_S 6 1365 #define PF0_MBX_CPM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 1366 #define PF0_MBX_CPM_ARQH 0x0022E5E0 /* Reset Source: CORER */ 1367 #define PF0_MBX_CPM_ARQH_ARQH_S 0 1368 #define PF0_MBX_CPM_ARQH_ARQH_M MAKEMASK(0x3FF, 0) 1369 #define PF0_MBX_CPM_ARQLEN 0x0022E5DC /* Reset Source: PFR */ 1370 #define PF0_MBX_CPM_ARQLEN_ARQLEN_S 0 1371 #define PF0_MBX_CPM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0) 1372 #define PF0_MBX_CPM_ARQLEN_ARQVFE_S 28 1373 #define PF0_MBX_CPM_ARQLEN_ARQVFE_M BIT(28) 1374 #define PF0_MBX_CPM_ARQLEN_ARQOVFL_S 29 1375 #define PF0_MBX_CPM_ARQLEN_ARQOVFL_M BIT(29) 1376 #define PF0_MBX_CPM_ARQLEN_ARQCRIT_S 30 1377 #define PF0_MBX_CPM_ARQLEN_ARQCRIT_M BIT(30) 1378 #define PF0_MBX_CPM_ARQLEN_ARQENABLE_S 31 1379 #define PF0_MBX_CPM_ARQLEN_ARQENABLE_M BIT(31) 1380 #define PF0_MBX_CPM_ARQT 0x0022E5E4 /* Reset Source: CORER */ 1381 #define PF0_MBX_CPM_ARQT_ARQT_S 0 1382 #define PF0_MBX_CPM_ARQT_ARQT_M MAKEMASK(0x3FF, 0) 1383 #define PF0_MBX_CPM_ATQBAH 0x0022E5C4 /* Reset Source: CORER */ 1384 #define PF0_MBX_CPM_ATQBAH_ATQBAH_S 0 1385 #define PF0_MBX_CPM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1386 #define PF0_MBX_CPM_ATQBAL 0x0022E5C0 /* Reset Source: CORER */ 1387 #define PF0_MBX_CPM_ATQBAL_ATQBAL_S 6 1388 #define PF0_MBX_CPM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 1389 #define PF0_MBX_CPM_ATQH 0x0022E5CC /* Reset Source: CORER */ 1390 #define PF0_MBX_CPM_ATQH_ATQH_S 0 1391 #define PF0_MBX_CPM_ATQH_ATQH_M MAKEMASK(0x3FF, 0) 1392 #define PF0_MBX_CPM_ATQLEN 0x0022E5C8 /* Reset Source: PFR */ 1393 #define PF0_MBX_CPM_ATQLEN_ATQLEN_S 0 1394 #define PF0_MBX_CPM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0) 1395 #define PF0_MBX_CPM_ATQLEN_ATQVFE_S 28 1396 #define PF0_MBX_CPM_ATQLEN_ATQVFE_M BIT(28) 1397 #define PF0_MBX_CPM_ATQLEN_ATQOVFL_S 29 1398 #define PF0_MBX_CPM_ATQLEN_ATQOVFL_M BIT(29) 1399 #define PF0_MBX_CPM_ATQLEN_ATQCRIT_S 30 1400 #define PF0_MBX_CPM_ATQLEN_ATQCRIT_M BIT(30) 1401 #define PF0_MBX_CPM_ATQLEN_ATQENABLE_S 31 1402 #define PF0_MBX_CPM_ATQLEN_ATQENABLE_M BIT(31) 1403 #define PF0_MBX_CPM_ATQT 0x0022E5D0 /* Reset Source: CORER */ 1404 #define PF0_MBX_CPM_ATQT_ATQT_S 0 1405 #define PF0_MBX_CPM_ATQT_ATQT_M MAKEMASK(0x3FF, 0) 1406 #define PF0_MBX_HLP_ARQBAH 0x0022E600 /* Reset Source: CORER */ 1407 #define PF0_MBX_HLP_ARQBAH_ARQBAH_S 0 1408 #define PF0_MBX_HLP_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1409 #define PF0_MBX_HLP_ARQBAL 0x0022E5FC /* Reset Source: CORER */ 1410 #define PF0_MBX_HLP_ARQBAL_ARQBAL_LSB_S 0 1411 #define PF0_MBX_HLP_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 1412 #define PF0_MBX_HLP_ARQBAL_ARQBAL_S 6 1413 #define PF0_MBX_HLP_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 1414 #define PF0_MBX_HLP_ARQH 0x0022E608 /* Reset Source: CORER */ 1415 #define PF0_MBX_HLP_ARQH_ARQH_S 0 1416 #define PF0_MBX_HLP_ARQH_ARQH_M MAKEMASK(0x3FF, 0) 1417 #define PF0_MBX_HLP_ARQLEN 0x0022E604 /* Reset Source: PFR */ 1418 #define PF0_MBX_HLP_ARQLEN_ARQLEN_S 0 1419 #define PF0_MBX_HLP_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0) 1420 #define PF0_MBX_HLP_ARQLEN_ARQVFE_S 28 1421 #define PF0_MBX_HLP_ARQLEN_ARQVFE_M BIT(28) 1422 #define PF0_MBX_HLP_ARQLEN_ARQOVFL_S 29 1423 #define PF0_MBX_HLP_ARQLEN_ARQOVFL_M BIT(29) 1424 #define PF0_MBX_HLP_ARQLEN_ARQCRIT_S 30 1425 #define PF0_MBX_HLP_ARQLEN_ARQCRIT_M BIT(30) 1426 #define PF0_MBX_HLP_ARQLEN_ARQENABLE_S 31 1427 #define PF0_MBX_HLP_ARQLEN_ARQENABLE_M BIT(31) 1428 #define PF0_MBX_HLP_ARQT 0x0022E60C /* Reset Source: CORER */ 1429 #define PF0_MBX_HLP_ARQT_ARQT_S 0 1430 #define PF0_MBX_HLP_ARQT_ARQT_M MAKEMASK(0x3FF, 0) 1431 #define PF0_MBX_HLP_ATQBAH 0x0022E5EC /* Reset Source: CORER */ 1432 #define PF0_MBX_HLP_ATQBAH_ATQBAH_S 0 1433 #define PF0_MBX_HLP_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1434 #define PF0_MBX_HLP_ATQBAL 0x0022E5E8 /* Reset Source: CORER */ 1435 #define PF0_MBX_HLP_ATQBAL_ATQBAL_S 6 1436 #define PF0_MBX_HLP_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 1437 #define PF0_MBX_HLP_ATQH 0x0022E5F4 /* Reset Source: CORER */ 1438 #define PF0_MBX_HLP_ATQH_ATQH_S 0 1439 #define PF0_MBX_HLP_ATQH_ATQH_M MAKEMASK(0x3FF, 0) 1440 #define PF0_MBX_HLP_ATQLEN 0x0022E5F0 /* Reset Source: PFR */ 1441 #define PF0_MBX_HLP_ATQLEN_ATQLEN_S 0 1442 #define PF0_MBX_HLP_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0) 1443 #define PF0_MBX_HLP_ATQLEN_ATQVFE_S 28 1444 #define PF0_MBX_HLP_ATQLEN_ATQVFE_M BIT(28) 1445 #define PF0_MBX_HLP_ATQLEN_ATQOVFL_S 29 1446 #define PF0_MBX_HLP_ATQLEN_ATQOVFL_M BIT(29) 1447 #define PF0_MBX_HLP_ATQLEN_ATQCRIT_S 30 1448 #define PF0_MBX_HLP_ATQLEN_ATQCRIT_M BIT(30) 1449 #define PF0_MBX_HLP_ATQLEN_ATQENABLE_S 31 1450 #define PF0_MBX_HLP_ATQLEN_ATQENABLE_M BIT(31) 1451 #define PF0_MBX_HLP_ATQT 0x0022E5F8 /* Reset Source: CORER */ 1452 #define PF0_MBX_HLP_ATQT_ATQT_S 0 1453 #define PF0_MBX_HLP_ATQT_ATQT_M MAKEMASK(0x3FF, 0) 1454 #define PF0_MBX_PSM_ARQBAH 0x0022E628 /* Reset Source: CORER */ 1455 #define PF0_MBX_PSM_ARQBAH_ARQBAH_S 0 1456 #define PF0_MBX_PSM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1457 #define PF0_MBX_PSM_ARQBAL 0x0022E624 /* Reset Source: CORER */ 1458 #define PF0_MBX_PSM_ARQBAL_ARQBAL_LSB_S 0 1459 #define PF0_MBX_PSM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 1460 #define PF0_MBX_PSM_ARQBAL_ARQBAL_S 6 1461 #define PF0_MBX_PSM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 1462 #define PF0_MBX_PSM_ARQH 0x0022E630 /* Reset Source: CORER */ 1463 #define PF0_MBX_PSM_ARQH_ARQH_S 0 1464 #define PF0_MBX_PSM_ARQH_ARQH_M MAKEMASK(0x3FF, 0) 1465 #define PF0_MBX_PSM_ARQLEN 0x0022E62C /* Reset Source: PFR */ 1466 #define PF0_MBX_PSM_ARQLEN_ARQLEN_S 0 1467 #define PF0_MBX_PSM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0) 1468 #define PF0_MBX_PSM_ARQLEN_ARQVFE_S 28 1469 #define PF0_MBX_PSM_ARQLEN_ARQVFE_M BIT(28) 1470 #define PF0_MBX_PSM_ARQLEN_ARQOVFL_S 29 1471 #define PF0_MBX_PSM_ARQLEN_ARQOVFL_M BIT(29) 1472 #define PF0_MBX_PSM_ARQLEN_ARQCRIT_S 30 1473 #define PF0_MBX_PSM_ARQLEN_ARQCRIT_M BIT(30) 1474 #define PF0_MBX_PSM_ARQLEN_ARQENABLE_S 31 1475 #define PF0_MBX_PSM_ARQLEN_ARQENABLE_M BIT(31) 1476 #define PF0_MBX_PSM_ARQT 0x0022E634 /* Reset Source: CORER */ 1477 #define PF0_MBX_PSM_ARQT_ARQT_S 0 1478 #define PF0_MBX_PSM_ARQT_ARQT_M MAKEMASK(0x3FF, 0) 1479 #define PF0_MBX_PSM_ATQBAH 0x0022E614 /* Reset Source: CORER */ 1480 #define PF0_MBX_PSM_ATQBAH_ATQBAH_S 0 1481 #define PF0_MBX_PSM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1482 #define PF0_MBX_PSM_ATQBAL 0x0022E610 /* Reset Source: CORER */ 1483 #define PF0_MBX_PSM_ATQBAL_ATQBAL_S 6 1484 #define PF0_MBX_PSM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 1485 #define PF0_MBX_PSM_ATQH 0x0022E61C /* Reset Source: CORER */ 1486 #define PF0_MBX_PSM_ATQH_ATQH_S 0 1487 #define PF0_MBX_PSM_ATQH_ATQH_M MAKEMASK(0x3FF, 0) 1488 #define PF0_MBX_PSM_ATQLEN 0x0022E618 /* Reset Source: PFR */ 1489 #define PF0_MBX_PSM_ATQLEN_ATQLEN_S 0 1490 #define PF0_MBX_PSM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0) 1491 #define PF0_MBX_PSM_ATQLEN_ATQVFE_S 28 1492 #define PF0_MBX_PSM_ATQLEN_ATQVFE_M BIT(28) 1493 #define PF0_MBX_PSM_ATQLEN_ATQOVFL_S 29 1494 #define PF0_MBX_PSM_ATQLEN_ATQOVFL_M BIT(29) 1495 #define PF0_MBX_PSM_ATQLEN_ATQCRIT_S 30 1496 #define PF0_MBX_PSM_ATQLEN_ATQCRIT_M BIT(30) 1497 #define PF0_MBX_PSM_ATQLEN_ATQENABLE_S 31 1498 #define PF0_MBX_PSM_ATQLEN_ATQENABLE_M BIT(31) 1499 #define PF0_MBX_PSM_ATQT 0x0022E620 /* Reset Source: CORER */ 1500 #define PF0_MBX_PSM_ATQT_ATQT_S 0 1501 #define PF0_MBX_PSM_ATQT_ATQT_M MAKEMASK(0x3FF, 0) 1502 #define PF0_SB_CPM_ARQBAH 0x0022E650 /* Reset Source: CORER */ 1503 #define PF0_SB_CPM_ARQBAH_ARQBAH_S 0 1504 #define PF0_SB_CPM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1505 #define PF0_SB_CPM_ARQBAL 0x0022E64C /* Reset Source: CORER */ 1506 #define PF0_SB_CPM_ARQBAL_ARQBAL_LSB_S 0 1507 #define PF0_SB_CPM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 1508 #define PF0_SB_CPM_ARQBAL_ARQBAL_S 6 1509 #define PF0_SB_CPM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 1510 #define PF0_SB_CPM_ARQH 0x0022E658 /* Reset Source: CORER */ 1511 #define PF0_SB_CPM_ARQH_ARQH_S 0 1512 #define PF0_SB_CPM_ARQH_ARQH_M MAKEMASK(0x3FF, 0) 1513 #define PF0_SB_CPM_ARQLEN 0x0022E654 /* Reset Source: PFR */ 1514 #define PF0_SB_CPM_ARQLEN_ARQLEN_S 0 1515 #define PF0_SB_CPM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0) 1516 #define PF0_SB_CPM_ARQLEN_ARQVFE_S 28 1517 #define PF0_SB_CPM_ARQLEN_ARQVFE_M BIT(28) 1518 #define PF0_SB_CPM_ARQLEN_ARQOVFL_S 29 1519 #define PF0_SB_CPM_ARQLEN_ARQOVFL_M BIT(29) 1520 #define PF0_SB_CPM_ARQLEN_ARQCRIT_S 30 1521 #define PF0_SB_CPM_ARQLEN_ARQCRIT_M BIT(30) 1522 #define PF0_SB_CPM_ARQLEN_ARQENABLE_S 31 1523 #define PF0_SB_CPM_ARQLEN_ARQENABLE_M BIT(31) 1524 #define PF0_SB_CPM_ARQT 0x0022E65C /* Reset Source: CORER */ 1525 #define PF0_SB_CPM_ARQT_ARQT_S 0 1526 #define PF0_SB_CPM_ARQT_ARQT_M MAKEMASK(0x3FF, 0) 1527 #define PF0_SB_CPM_ATQBAH 0x0022E63C /* Reset Source: CORER */ 1528 #define PF0_SB_CPM_ATQBAH_ATQBAH_S 0 1529 #define PF0_SB_CPM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1530 #define PF0_SB_CPM_ATQBAL 0x0022E638 /* Reset Source: CORER */ 1531 #define PF0_SB_CPM_ATQBAL_ATQBAL_S 6 1532 #define PF0_SB_CPM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 1533 #define PF0_SB_CPM_ATQH 0x0022E644 /* Reset Source: CORER */ 1534 #define PF0_SB_CPM_ATQH_ATQH_S 0 1535 #define PF0_SB_CPM_ATQH_ATQH_M MAKEMASK(0x3FF, 0) 1536 #define PF0_SB_CPM_ATQLEN 0x0022E640 /* Reset Source: PFR */ 1537 #define PF0_SB_CPM_ATQLEN_ATQLEN_S 0 1538 #define PF0_SB_CPM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0) 1539 #define PF0_SB_CPM_ATQLEN_ATQVFE_S 28 1540 #define PF0_SB_CPM_ATQLEN_ATQVFE_M BIT(28) 1541 #define PF0_SB_CPM_ATQLEN_ATQOVFL_S 29 1542 #define PF0_SB_CPM_ATQLEN_ATQOVFL_M BIT(29) 1543 #define PF0_SB_CPM_ATQLEN_ATQCRIT_S 30 1544 #define PF0_SB_CPM_ATQLEN_ATQCRIT_M BIT(30) 1545 #define PF0_SB_CPM_ATQLEN_ATQENABLE_S 31 1546 #define PF0_SB_CPM_ATQLEN_ATQENABLE_M BIT(31) 1547 #define PF0_SB_CPM_ATQT 0x0022E648 /* Reset Source: CORER */ 1548 #define PF0_SB_CPM_ATQT_ATQT_S 0 1549 #define PF0_SB_CPM_ATQT_ATQT_M MAKEMASK(0x3FF, 0) 1550 #define PF0_SB_CPM_REM_DEV_CTL 0x002300F4 /* Reset Source: CORER */ 1551 #define PF0_SB_CPM_REM_DEV_CTL_DEST_EN_S 0 1552 #define PF0_SB_CPM_REM_DEV_CTL_DEST_EN_M MAKEMASK(0xFFFF, 0) 1553 #define PF0_SB_HLP_ARQBAH 0x002300D8 /* Reset Source: CORER */ 1554 #define PF0_SB_HLP_ARQBAH_ARQBAH_S 0 1555 #define PF0_SB_HLP_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1556 #define PF0_SB_HLP_ARQBAL 0x002300D4 /* Reset Source: CORER */ 1557 #define PF0_SB_HLP_ARQBAL_ARQBAL_LSB_S 0 1558 #define PF0_SB_HLP_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 1559 #define PF0_SB_HLP_ARQBAL_ARQBAL_S 6 1560 #define PF0_SB_HLP_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 1561 #define PF0_SB_HLP_ARQH 0x002300E0 /* Reset Source: CORER */ 1562 #define PF0_SB_HLP_ARQH_ARQH_S 0 1563 #define PF0_SB_HLP_ARQH_ARQH_M MAKEMASK(0x3FF, 0) 1564 #define PF0_SB_HLP_ARQLEN 0x002300DC /* Reset Source: PFR */ 1565 #define PF0_SB_HLP_ARQLEN_ARQLEN_S 0 1566 #define PF0_SB_HLP_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0) 1567 #define PF0_SB_HLP_ARQLEN_ARQVFE_S 28 1568 #define PF0_SB_HLP_ARQLEN_ARQVFE_M BIT(28) 1569 #define PF0_SB_HLP_ARQLEN_ARQOVFL_S 29 1570 #define PF0_SB_HLP_ARQLEN_ARQOVFL_M BIT(29) 1571 #define PF0_SB_HLP_ARQLEN_ARQCRIT_S 30 1572 #define PF0_SB_HLP_ARQLEN_ARQCRIT_M BIT(30) 1573 #define PF0_SB_HLP_ARQLEN_ARQENABLE_S 31 1574 #define PF0_SB_HLP_ARQLEN_ARQENABLE_M BIT(31) 1575 #define PF0_SB_HLP_ARQT 0x002300E4 /* Reset Source: CORER */ 1576 #define PF0_SB_HLP_ARQT_ARQT_S 0 1577 #define PF0_SB_HLP_ARQT_ARQT_M MAKEMASK(0x3FF, 0) 1578 #define PF0_SB_HLP_ATQBAH 0x002300C4 /* Reset Source: CORER */ 1579 #define PF0_SB_HLP_ATQBAH_ATQBAH_S 0 1580 #define PF0_SB_HLP_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1581 #define PF0_SB_HLP_ATQBAL 0x002300C0 /* Reset Source: CORER */ 1582 #define PF0_SB_HLP_ATQBAL_ATQBAL_S 6 1583 #define PF0_SB_HLP_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 1584 #define PF0_SB_HLP_ATQH 0x002300CC /* Reset Source: CORER */ 1585 #define PF0_SB_HLP_ATQH_ATQH_S 0 1586 #define PF0_SB_HLP_ATQH_ATQH_M MAKEMASK(0x3FF, 0) 1587 #define PF0_SB_HLP_ATQLEN 0x002300C8 /* Reset Source: PFR */ 1588 #define PF0_SB_HLP_ATQLEN_ATQLEN_S 0 1589 #define PF0_SB_HLP_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0) 1590 #define PF0_SB_HLP_ATQLEN_ATQVFE_S 28 1591 #define PF0_SB_HLP_ATQLEN_ATQVFE_M BIT(28) 1592 #define PF0_SB_HLP_ATQLEN_ATQOVFL_S 29 1593 #define PF0_SB_HLP_ATQLEN_ATQOVFL_M BIT(29) 1594 #define PF0_SB_HLP_ATQLEN_ATQCRIT_S 30 1595 #define PF0_SB_HLP_ATQLEN_ATQCRIT_M BIT(30) 1596 #define PF0_SB_HLP_ATQLEN_ATQENABLE_S 31 1597 #define PF0_SB_HLP_ATQLEN_ATQENABLE_M BIT(31) 1598 #define PF0_SB_HLP_ATQT 0x002300D0 /* Reset Source: CORER */ 1599 #define PF0_SB_HLP_ATQT_ATQT_S 0 1600 #define PF0_SB_HLP_ATQT_ATQT_M MAKEMASK(0x3FF, 0) 1601 #define PF0_SB_HLP_REM_DEV_CTL 0x002300E8 /* Reset Source: CORER */ 1602 #define PF0_SB_HLP_REM_DEV_CTL_DEST_EN_S 0 1603 #define PF0_SB_HLP_REM_DEV_CTL_DEST_EN_M MAKEMASK(0xFFFF, 0) 1604 #define SB_REM_DEV_DEST(_i) (0x002300F8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 1605 #define SB_REM_DEV_DEST_MAX_INDEX 7 1606 #define SB_REM_DEV_DEST_DEST_S 0 1607 #define SB_REM_DEV_DEST_DEST_M MAKEMASK(0xF, 0) 1608 #define SB_REM_DEV_DEST_DEST_VALID_S 31 1609 #define SB_REM_DEV_DEST_DEST_VALID_M BIT(31) 1610 #define VF_MBX_ARQBAH(_VF) (0x0022B800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 1611 #define VF_MBX_ARQBAH_MAX_INDEX 255 1612 #define VF_MBX_ARQBAH_ARQBAH_S 0 1613 #define VF_MBX_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1614 #define VF_MBX_ARQBAL(_VF) (0x0022B400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 1615 #define VF_MBX_ARQBAL_MAX_INDEX 255 1616 #define VF_MBX_ARQBAL_ARQBAL_LSB_S 0 1617 #define VF_MBX_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 1618 #define VF_MBX_ARQBAL_ARQBAL_S 6 1619 #define VF_MBX_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 1620 #define VF_MBX_ARQH(_VF) (0x0022C000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 1621 #define VF_MBX_ARQH_MAX_INDEX 255 1622 #define VF_MBX_ARQH_ARQH_S 0 1623 #define VF_MBX_ARQH_ARQH_M MAKEMASK(0x3FF, 0) 1624 #define VF_MBX_ARQLEN(_VF) (0x0022BC00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */ 1625 #define VF_MBX_ARQLEN_MAX_INDEX 255 1626 #define VF_MBX_ARQLEN_ARQLEN_S 0 1627 #define VF_MBX_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0) 1628 #define VF_MBX_ARQLEN_ARQVFE_S 28 1629 #define VF_MBX_ARQLEN_ARQVFE_M BIT(28) 1630 #define VF_MBX_ARQLEN_ARQOVFL_S 29 1631 #define VF_MBX_ARQLEN_ARQOVFL_M BIT(29) 1632 #define VF_MBX_ARQLEN_ARQCRIT_S 30 1633 #define VF_MBX_ARQLEN_ARQCRIT_M BIT(30) 1634 #define VF_MBX_ARQLEN_ARQENABLE_S 31 1635 #define VF_MBX_ARQLEN_ARQENABLE_M BIT(31) 1636 #define VF_MBX_ARQT(_VF) (0x0022C400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 1637 #define VF_MBX_ARQT_MAX_INDEX 255 1638 #define VF_MBX_ARQT_ARQT_S 0 1639 #define VF_MBX_ARQT_ARQT_M MAKEMASK(0x3FF, 0) 1640 #define VF_MBX_ATQBAH(_VF) (0x0022A400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 1641 #define VF_MBX_ATQBAH_MAX_INDEX 255 1642 #define VF_MBX_ATQBAH_ATQBAH_S 0 1643 #define VF_MBX_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1644 #define VF_MBX_ATQBAL(_VF) (0x0022A000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 1645 #define VF_MBX_ATQBAL_MAX_INDEX 255 1646 #define VF_MBX_ATQBAL_ATQBAL_S 6 1647 #define VF_MBX_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 1648 #define VF_MBX_ATQH(_VF) (0x0022AC00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 1649 #define VF_MBX_ATQH_MAX_INDEX 255 1650 #define VF_MBX_ATQH_ATQH_S 0 1651 #define VF_MBX_ATQH_ATQH_M MAKEMASK(0x3FF, 0) 1652 #define VF_MBX_ATQLEN(_VF) (0x0022A800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */ 1653 #define VF_MBX_ATQLEN_MAX_INDEX 255 1654 #define VF_MBX_ATQLEN_ATQLEN_S 0 1655 #define VF_MBX_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0) 1656 #define VF_MBX_ATQLEN_ATQVFE_S 28 1657 #define VF_MBX_ATQLEN_ATQVFE_M BIT(28) 1658 #define VF_MBX_ATQLEN_ATQOVFL_S 29 1659 #define VF_MBX_ATQLEN_ATQOVFL_M BIT(29) 1660 #define VF_MBX_ATQLEN_ATQCRIT_S 30 1661 #define VF_MBX_ATQLEN_ATQCRIT_M BIT(30) 1662 #define VF_MBX_ATQLEN_ATQENABLE_S 31 1663 #define VF_MBX_ATQLEN_ATQENABLE_M BIT(31) 1664 #define VF_MBX_ATQT(_VF) (0x0022B000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 1665 #define VF_MBX_ATQT_MAX_INDEX 255 1666 #define VF_MBX_ATQT_ATQT_S 0 1667 #define VF_MBX_ATQT_ATQT_M MAKEMASK(0x3FF, 0) 1668 #define VF_MBX_CPM_ARQBAH(_VF128) (0x0022D400 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 1669 #define VF_MBX_CPM_ARQBAH_MAX_INDEX 127 1670 #define VF_MBX_CPM_ARQBAH_ARQBAH_S 0 1671 #define VF_MBX_CPM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1672 #define VF_MBX_CPM_ARQBAL(_VF128) (0x0022D200 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 1673 #define VF_MBX_CPM_ARQBAL_MAX_INDEX 127 1674 #define VF_MBX_CPM_ARQBAL_ARQBAL_LSB_S 0 1675 #define VF_MBX_CPM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 1676 #define VF_MBX_CPM_ARQBAL_ARQBAL_S 6 1677 #define VF_MBX_CPM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 1678 #define VF_MBX_CPM_ARQH(_VF128) (0x0022D800 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 1679 #define VF_MBX_CPM_ARQH_MAX_INDEX 127 1680 #define VF_MBX_CPM_ARQH_ARQH_S 0 1681 #define VF_MBX_CPM_ARQH_ARQH_M MAKEMASK(0x3FF, 0) 1682 #define VF_MBX_CPM_ARQLEN(_VF128) (0x0022D600 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: PFR */ 1683 #define VF_MBX_CPM_ARQLEN_MAX_INDEX 127 1684 #define VF_MBX_CPM_ARQLEN_ARQLEN_S 0 1685 #define VF_MBX_CPM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0) 1686 #define VF_MBX_CPM_ARQLEN_ARQVFE_S 28 1687 #define VF_MBX_CPM_ARQLEN_ARQVFE_M BIT(28) 1688 #define VF_MBX_CPM_ARQLEN_ARQOVFL_S 29 1689 #define VF_MBX_CPM_ARQLEN_ARQOVFL_M BIT(29) 1690 #define VF_MBX_CPM_ARQLEN_ARQCRIT_S 30 1691 #define VF_MBX_CPM_ARQLEN_ARQCRIT_M BIT(30) 1692 #define VF_MBX_CPM_ARQLEN_ARQENABLE_S 31 1693 #define VF_MBX_CPM_ARQLEN_ARQENABLE_M BIT(31) 1694 #define VF_MBX_CPM_ARQT(_VF128) (0x0022DA00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 1695 #define VF_MBX_CPM_ARQT_MAX_INDEX 127 1696 #define VF_MBX_CPM_ARQT_ARQT_S 0 1697 #define VF_MBX_CPM_ARQT_ARQT_M MAKEMASK(0x3FF, 0) 1698 #define VF_MBX_CPM_ATQBAH(_VF128) (0x0022CA00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 1699 #define VF_MBX_CPM_ATQBAH_MAX_INDEX 127 1700 #define VF_MBX_CPM_ATQBAH_ATQBAH_S 0 1701 #define VF_MBX_CPM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1702 #define VF_MBX_CPM_ATQBAL(_VF128) (0x0022C800 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 1703 #define VF_MBX_CPM_ATQBAL_MAX_INDEX 127 1704 #define VF_MBX_CPM_ATQBAL_ATQBAL_S 6 1705 #define VF_MBX_CPM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 1706 #define VF_MBX_CPM_ATQH(_VF128) (0x0022CE00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 1707 #define VF_MBX_CPM_ATQH_MAX_INDEX 127 1708 #define VF_MBX_CPM_ATQH_ATQH_S 0 1709 #define VF_MBX_CPM_ATQH_ATQH_M MAKEMASK(0x3FF, 0) 1710 #define VF_MBX_CPM_ATQLEN(_VF128) (0x0022CC00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: PFR */ 1711 #define VF_MBX_CPM_ATQLEN_MAX_INDEX 127 1712 #define VF_MBX_CPM_ATQLEN_ATQLEN_S 0 1713 #define VF_MBX_CPM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0) 1714 #define VF_MBX_CPM_ATQLEN_ATQVFE_S 28 1715 #define VF_MBX_CPM_ATQLEN_ATQVFE_M BIT(28) 1716 #define VF_MBX_CPM_ATQLEN_ATQOVFL_S 29 1717 #define VF_MBX_CPM_ATQLEN_ATQOVFL_M BIT(29) 1718 #define VF_MBX_CPM_ATQLEN_ATQCRIT_S 30 1719 #define VF_MBX_CPM_ATQLEN_ATQCRIT_M BIT(30) 1720 #define VF_MBX_CPM_ATQLEN_ATQENABLE_S 31 1721 #define VF_MBX_CPM_ATQLEN_ATQENABLE_M BIT(31) 1722 #define VF_MBX_CPM_ATQT(_VF128) (0x0022D000 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 1723 #define VF_MBX_CPM_ATQT_MAX_INDEX 127 1724 #define VF_MBX_CPM_ATQT_ATQT_S 0 1725 #define VF_MBX_CPM_ATQT_ATQT_M MAKEMASK(0x3FF, 0) 1726 #define VF_MBX_HLP_ARQBAH(_VF16) (0x0022DD80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 1727 #define VF_MBX_HLP_ARQBAH_MAX_INDEX 15 1728 #define VF_MBX_HLP_ARQBAH_ARQBAH_S 0 1729 #define VF_MBX_HLP_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1730 #define VF_MBX_HLP_ARQBAL(_VF16) (0x0022DD40 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 1731 #define VF_MBX_HLP_ARQBAL_MAX_INDEX 15 1732 #define VF_MBX_HLP_ARQBAL_ARQBAL_LSB_S 0 1733 #define VF_MBX_HLP_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 1734 #define VF_MBX_HLP_ARQBAL_ARQBAL_S 6 1735 #define VF_MBX_HLP_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 1736 #define VF_MBX_HLP_ARQH(_VF16) (0x0022DE00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 1737 #define VF_MBX_HLP_ARQH_MAX_INDEX 15 1738 #define VF_MBX_HLP_ARQH_ARQH_S 0 1739 #define VF_MBX_HLP_ARQH_ARQH_M MAKEMASK(0x3FF, 0) 1740 #define VF_MBX_HLP_ARQLEN(_VF16) (0x0022DDC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: PFR */ 1741 #define VF_MBX_HLP_ARQLEN_MAX_INDEX 15 1742 #define VF_MBX_HLP_ARQLEN_ARQLEN_S 0 1743 #define VF_MBX_HLP_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0) 1744 #define VF_MBX_HLP_ARQLEN_ARQVFE_S 28 1745 #define VF_MBX_HLP_ARQLEN_ARQVFE_M BIT(28) 1746 #define VF_MBX_HLP_ARQLEN_ARQOVFL_S 29 1747 #define VF_MBX_HLP_ARQLEN_ARQOVFL_M BIT(29) 1748 #define VF_MBX_HLP_ARQLEN_ARQCRIT_S 30 1749 #define VF_MBX_HLP_ARQLEN_ARQCRIT_M BIT(30) 1750 #define VF_MBX_HLP_ARQLEN_ARQENABLE_S 31 1751 #define VF_MBX_HLP_ARQLEN_ARQENABLE_M BIT(31) 1752 #define VF_MBX_HLP_ARQT(_VF16) (0x0022DE40 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 1753 #define VF_MBX_HLP_ARQT_MAX_INDEX 15 1754 #define VF_MBX_HLP_ARQT_ARQT_S 0 1755 #define VF_MBX_HLP_ARQT_ARQT_M MAKEMASK(0x3FF, 0) 1756 #define VF_MBX_HLP_ATQBAH(_VF16) (0x0022DC40 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 1757 #define VF_MBX_HLP_ATQBAH_MAX_INDEX 15 1758 #define VF_MBX_HLP_ATQBAH_ATQBAH_S 0 1759 #define VF_MBX_HLP_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1760 #define VF_MBX_HLP_ATQBAL(_VF16) (0x0022DC00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 1761 #define VF_MBX_HLP_ATQBAL_MAX_INDEX 15 1762 #define VF_MBX_HLP_ATQBAL_ATQBAL_S 6 1763 #define VF_MBX_HLP_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 1764 #define VF_MBX_HLP_ATQH(_VF16) (0x0022DCC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 1765 #define VF_MBX_HLP_ATQH_MAX_INDEX 15 1766 #define VF_MBX_HLP_ATQH_ATQH_S 0 1767 #define VF_MBX_HLP_ATQH_ATQH_M MAKEMASK(0x3FF, 0) 1768 #define VF_MBX_HLP_ATQLEN(_VF16) (0x0022DC80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: PFR */ 1769 #define VF_MBX_HLP_ATQLEN_MAX_INDEX 15 1770 #define VF_MBX_HLP_ATQLEN_ATQLEN_S 0 1771 #define VF_MBX_HLP_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0) 1772 #define VF_MBX_HLP_ATQLEN_ATQVFE_S 28 1773 #define VF_MBX_HLP_ATQLEN_ATQVFE_M BIT(28) 1774 #define VF_MBX_HLP_ATQLEN_ATQOVFL_S 29 1775 #define VF_MBX_HLP_ATQLEN_ATQOVFL_M BIT(29) 1776 #define VF_MBX_HLP_ATQLEN_ATQCRIT_S 30 1777 #define VF_MBX_HLP_ATQLEN_ATQCRIT_M BIT(30) 1778 #define VF_MBX_HLP_ATQLEN_ATQENABLE_S 31 1779 #define VF_MBX_HLP_ATQLEN_ATQENABLE_M BIT(31) 1780 #define VF_MBX_HLP_ATQT(_VF16) (0x0022DD00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 1781 #define VF_MBX_HLP_ATQT_MAX_INDEX 15 1782 #define VF_MBX_HLP_ATQT_ATQT_S 0 1783 #define VF_MBX_HLP_ATQT_ATQT_M MAKEMASK(0x3FF, 0) 1784 #define VF_MBX_PSM_ARQBAH(_VF16) (0x0022E000 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 1785 #define VF_MBX_PSM_ARQBAH_MAX_INDEX 15 1786 #define VF_MBX_PSM_ARQBAH_ARQBAH_S 0 1787 #define VF_MBX_PSM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1788 #define VF_MBX_PSM_ARQBAL(_VF16) (0x0022DFC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 1789 #define VF_MBX_PSM_ARQBAL_MAX_INDEX 15 1790 #define VF_MBX_PSM_ARQBAL_ARQBAL_LSB_S 0 1791 #define VF_MBX_PSM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 1792 #define VF_MBX_PSM_ARQBAL_ARQBAL_S 6 1793 #define VF_MBX_PSM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 1794 #define VF_MBX_PSM_ARQH(_VF16) (0x0022E080 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 1795 #define VF_MBX_PSM_ARQH_MAX_INDEX 15 1796 #define VF_MBX_PSM_ARQH_ARQH_S 0 1797 #define VF_MBX_PSM_ARQH_ARQH_M MAKEMASK(0x3FF, 0) 1798 #define VF_MBX_PSM_ARQLEN(_VF16) (0x0022E040 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: PFR */ 1799 #define VF_MBX_PSM_ARQLEN_MAX_INDEX 15 1800 #define VF_MBX_PSM_ARQLEN_ARQLEN_S 0 1801 #define VF_MBX_PSM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0) 1802 #define VF_MBX_PSM_ARQLEN_ARQVFE_S 28 1803 #define VF_MBX_PSM_ARQLEN_ARQVFE_M BIT(28) 1804 #define VF_MBX_PSM_ARQLEN_ARQOVFL_S 29 1805 #define VF_MBX_PSM_ARQLEN_ARQOVFL_M BIT(29) 1806 #define VF_MBX_PSM_ARQLEN_ARQCRIT_S 30 1807 #define VF_MBX_PSM_ARQLEN_ARQCRIT_M BIT(30) 1808 #define VF_MBX_PSM_ARQLEN_ARQENABLE_S 31 1809 #define VF_MBX_PSM_ARQLEN_ARQENABLE_M BIT(31) 1810 #define VF_MBX_PSM_ARQT(_VF16) (0x0022E0C0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 1811 #define VF_MBX_PSM_ARQT_MAX_INDEX 15 1812 #define VF_MBX_PSM_ARQT_ARQT_S 0 1813 #define VF_MBX_PSM_ARQT_ARQT_M MAKEMASK(0x3FF, 0) 1814 #define VF_MBX_PSM_ATQBAH(_VF16) (0x0022DEC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 1815 #define VF_MBX_PSM_ATQBAH_MAX_INDEX 15 1816 #define VF_MBX_PSM_ATQBAH_ATQBAH_S 0 1817 #define VF_MBX_PSM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1818 #define VF_MBX_PSM_ATQBAL(_VF16) (0x0022DE80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 1819 #define VF_MBX_PSM_ATQBAL_MAX_INDEX 15 1820 #define VF_MBX_PSM_ATQBAL_ATQBAL_S 6 1821 #define VF_MBX_PSM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 1822 #define VF_MBX_PSM_ATQH(_VF16) (0x0022DF40 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 1823 #define VF_MBX_PSM_ATQH_MAX_INDEX 15 1824 #define VF_MBX_PSM_ATQH_ATQH_S 0 1825 #define VF_MBX_PSM_ATQH_ATQH_M MAKEMASK(0x3FF, 0) 1826 #define VF_MBX_PSM_ATQLEN(_VF16) (0x0022DF00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: PFR */ 1827 #define VF_MBX_PSM_ATQLEN_MAX_INDEX 15 1828 #define VF_MBX_PSM_ATQLEN_ATQLEN_S 0 1829 #define VF_MBX_PSM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0) 1830 #define VF_MBX_PSM_ATQLEN_ATQVFE_S 28 1831 #define VF_MBX_PSM_ATQLEN_ATQVFE_M BIT(28) 1832 #define VF_MBX_PSM_ATQLEN_ATQOVFL_S 29 1833 #define VF_MBX_PSM_ATQLEN_ATQOVFL_M BIT(29) 1834 #define VF_MBX_PSM_ATQLEN_ATQCRIT_S 30 1835 #define VF_MBX_PSM_ATQLEN_ATQCRIT_M BIT(30) 1836 #define VF_MBX_PSM_ATQLEN_ATQENABLE_S 31 1837 #define VF_MBX_PSM_ATQLEN_ATQENABLE_M BIT(31) 1838 #define VF_MBX_PSM_ATQT(_VF16) (0x0022DF80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 1839 #define VF_MBX_PSM_ATQT_MAX_INDEX 15 1840 #define VF_MBX_PSM_ATQT_ATQT_S 0 1841 #define VF_MBX_PSM_ATQT_ATQT_M MAKEMASK(0x3FF, 0) 1842 #define VF_SB_CPM_ARQBAH(_VF128) (0x0022F400 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 1843 #define VF_SB_CPM_ARQBAH_MAX_INDEX 127 1844 #define VF_SB_CPM_ARQBAH_ARQBAH_S 0 1845 #define VF_SB_CPM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1846 #define VF_SB_CPM_ARQBAL(_VF128) (0x0022F200 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 1847 #define VF_SB_CPM_ARQBAL_MAX_INDEX 127 1848 #define VF_SB_CPM_ARQBAL_ARQBAL_LSB_S 0 1849 #define VF_SB_CPM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 1850 #define VF_SB_CPM_ARQBAL_ARQBAL_S 6 1851 #define VF_SB_CPM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 1852 #define VF_SB_CPM_ARQH(_VF128) (0x0022F800 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 1853 #define VF_SB_CPM_ARQH_MAX_INDEX 127 1854 #define VF_SB_CPM_ARQH_ARQH_S 0 1855 #define VF_SB_CPM_ARQH_ARQH_M MAKEMASK(0x3FF, 0) 1856 #define VF_SB_CPM_ARQLEN(_VF128) (0x0022F600 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: PFR */ 1857 #define VF_SB_CPM_ARQLEN_MAX_INDEX 127 1858 #define VF_SB_CPM_ARQLEN_ARQLEN_S 0 1859 #define VF_SB_CPM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0) 1860 #define VF_SB_CPM_ARQLEN_ARQVFE_S 28 1861 #define VF_SB_CPM_ARQLEN_ARQVFE_M BIT(28) 1862 #define VF_SB_CPM_ARQLEN_ARQOVFL_S 29 1863 #define VF_SB_CPM_ARQLEN_ARQOVFL_M BIT(29) 1864 #define VF_SB_CPM_ARQLEN_ARQCRIT_S 30 1865 #define VF_SB_CPM_ARQLEN_ARQCRIT_M BIT(30) 1866 #define VF_SB_CPM_ARQLEN_ARQENABLE_S 31 1867 #define VF_SB_CPM_ARQLEN_ARQENABLE_M BIT(31) 1868 #define VF_SB_CPM_ARQT(_VF128) (0x0022FA00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 1869 #define VF_SB_CPM_ARQT_MAX_INDEX 127 1870 #define VF_SB_CPM_ARQT_ARQT_S 0 1871 #define VF_SB_CPM_ARQT_ARQT_M MAKEMASK(0x3FF, 0) 1872 #define VF_SB_CPM_ATQBAH(_VF128) (0x0022EA00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 1873 #define VF_SB_CPM_ATQBAH_MAX_INDEX 127 1874 #define VF_SB_CPM_ATQBAH_ATQBAH_S 0 1875 #define VF_SB_CPM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 1876 #define VF_SB_CPM_ATQBAL(_VF128) (0x0022E800 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 1877 #define VF_SB_CPM_ATQBAL_MAX_INDEX 127 1878 #define VF_SB_CPM_ATQBAL_ATQBAL_S 6 1879 #define VF_SB_CPM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 1880 #define VF_SB_CPM_ATQH(_VF128) (0x0022EE00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 1881 #define VF_SB_CPM_ATQH_MAX_INDEX 127 1882 #define VF_SB_CPM_ATQH_ATQH_S 0 1883 #define VF_SB_CPM_ATQH_ATQH_M MAKEMASK(0x3FF, 0) 1884 #define VF_SB_CPM_ATQLEN(_VF128) (0x0022EC00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: PFR */ 1885 #define VF_SB_CPM_ATQLEN_MAX_INDEX 127 1886 #define VF_SB_CPM_ATQLEN_ATQLEN_S 0 1887 #define VF_SB_CPM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0) 1888 #define VF_SB_CPM_ATQLEN_ATQVFE_S 28 1889 #define VF_SB_CPM_ATQLEN_ATQVFE_M BIT(28) 1890 #define VF_SB_CPM_ATQLEN_ATQOVFL_S 29 1891 #define VF_SB_CPM_ATQLEN_ATQOVFL_M BIT(29) 1892 #define VF_SB_CPM_ATQLEN_ATQCRIT_S 30 1893 #define VF_SB_CPM_ATQLEN_ATQCRIT_M BIT(30) 1894 #define VF_SB_CPM_ATQLEN_ATQENABLE_S 31 1895 #define VF_SB_CPM_ATQLEN_ATQENABLE_M BIT(31) 1896 #define VF_SB_CPM_ATQT(_VF128) (0x0022F000 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 1897 #define VF_SB_CPM_ATQT_MAX_INDEX 127 1898 #define VF_SB_CPM_ATQT_ATQT_S 0 1899 #define VF_SB_CPM_ATQT_ATQT_M MAKEMASK(0x3FF, 0) 1900 #define VF_SB_CPM_REM_DEV_CTL 0x002300EC /* Reset Source: CORER */ 1901 #define VF_SB_CPM_REM_DEV_CTL_DEST_EN_S 0 1902 #define VF_SB_CPM_REM_DEV_CTL_DEST_EN_M MAKEMASK(0xFFFF, 0) 1903 #define VP_MBX_CPM_PF_VF_CTRL(_VP128) (0x00231800 + ((_VP128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 1904 #define VP_MBX_CPM_PF_VF_CTRL_MAX_INDEX 127 1905 #define VP_MBX_CPM_PF_VF_CTRL_QUEUE_EN_S 0 1906 #define VP_MBX_CPM_PF_VF_CTRL_QUEUE_EN_M BIT(0) 1907 #define VP_MBX_HLP_PF_VF_CTRL(_VP16) (0x00231A00 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 1908 #define VP_MBX_HLP_PF_VF_CTRL_MAX_INDEX 15 1909 #define VP_MBX_HLP_PF_VF_CTRL_QUEUE_EN_S 0 1910 #define VP_MBX_HLP_PF_VF_CTRL_QUEUE_EN_M BIT(0) 1911 #define VP_MBX_PF_VF_CTRL(_VSI) (0x00230800 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 1912 #define VP_MBX_PF_VF_CTRL_MAX_INDEX 767 1913 #define VP_MBX_PF_VF_CTRL_QUEUE_EN_S 0 1914 #define VP_MBX_PF_VF_CTRL_QUEUE_EN_M BIT(0) 1915 #define VP_MBX_PSM_PF_VF_CTRL(_VP16) (0x00231A40 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 1916 #define VP_MBX_PSM_PF_VF_CTRL_MAX_INDEX 15 1917 #define VP_MBX_PSM_PF_VF_CTRL_QUEUE_EN_S 0 1918 #define VP_MBX_PSM_PF_VF_CTRL_QUEUE_EN_M BIT(0) 1919 #define VP_SB_CPM_PF_VF_CTRL(_VP128) (0x00231C00 + ((_VP128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 1920 #define VP_SB_CPM_PF_VF_CTRL_MAX_INDEX 127 1921 #define VP_SB_CPM_PF_VF_CTRL_QUEUE_EN_S 0 1922 #define VP_SB_CPM_PF_VF_CTRL_QUEUE_EN_M BIT(0) 1923 #define GL_DCB_TDSCP2TC_BLOCK_DIS 0x00049218 /* Reset Source: CORER */ 1924 #define GL_DCB_TDSCP2TC_BLOCK_DIS_DSCP2TC_BLOCK_DIS_S 0 1925 #define GL_DCB_TDSCP2TC_BLOCK_DIS_DSCP2TC_BLOCK_DIS_M BIT(0) 1926 #define GL_DCB_TDSCP2TC_BLOCK_IPV4(_i) (0x00049018 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 1927 #define GL_DCB_TDSCP2TC_BLOCK_IPV4_MAX_INDEX 63 1928 #define GL_DCB_TDSCP2TC_BLOCK_IPV4_TC_BLOCK_LUT_S 0 1929 #define GL_DCB_TDSCP2TC_BLOCK_IPV4_TC_BLOCK_LUT_M MAKEMASK(0xFFFFFFFF, 0) 1930 #define GL_DCB_TDSCP2TC_BLOCK_IPV6(_i) (0x00049118 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 1931 #define GL_DCB_TDSCP2TC_BLOCK_IPV6_MAX_INDEX 63 1932 #define GL_DCB_TDSCP2TC_BLOCK_IPV6_TC_BLOCK_LUT_S 0 1933 #define GL_DCB_TDSCP2TC_BLOCK_IPV6_TC_BLOCK_LUT_M MAKEMASK(0xFFFFFFFF, 0) 1934 #define GLDCB_GENC 0x00083044 /* Reset Source: CORER */ 1935 #define GLDCB_GENC_PCIRTT_S 0 1936 #define GLDCB_GENC_PCIRTT_M MAKEMASK(0xFFFF, 0) 1937 #define GLDCB_PRS_RETSTCC(_i) (0x002000B0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 1938 #define GLDCB_PRS_RETSTCC_MAX_INDEX 31 1939 #define GLDCB_PRS_RETSTCC_BWSHARE_S 0 1940 #define GLDCB_PRS_RETSTCC_BWSHARE_M MAKEMASK(0x7F, 0) 1941 #define GLDCB_PRS_RETSTCC_ETSTC_S 31 1942 #define GLDCB_PRS_RETSTCC_ETSTC_M BIT(31) 1943 #define GLDCB_PRS_RSPMC 0x00200160 /* Reset Source: CORER */ 1944 #define GLDCB_PRS_RSPMC_RSPM_S 0 1945 #define GLDCB_PRS_RSPMC_RSPM_M MAKEMASK(0xFF, 0) 1946 #define GLDCB_PRS_RSPMC_RPM_MODE_S 8 1947 #define GLDCB_PRS_RSPMC_RPM_MODE_M MAKEMASK(0x3, 8) 1948 #define GLDCB_PRS_RSPMC_PRR_MAX_EXP_S 10 1949 #define GLDCB_PRS_RSPMC_PRR_MAX_EXP_M MAKEMASK(0xF, 10) 1950 #define GLDCB_PRS_RSPMC_PFCTIMER_S 14 1951 #define GLDCB_PRS_RSPMC_PFCTIMER_M MAKEMASK(0x3FFF, 14) 1952 #define GLDCB_PRS_RSPMC_RPM_DIS_S 31 1953 #define GLDCB_PRS_RSPMC_RPM_DIS_M BIT(31) 1954 #define GLDCB_RETSTCC(_i) (0x00122140 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 1955 #define GLDCB_RETSTCC_MAX_INDEX 31 1956 #define GLDCB_RETSTCC_BWSHARE_S 0 1957 #define GLDCB_RETSTCC_BWSHARE_M MAKEMASK(0x7F, 0) 1958 #define GLDCB_RETSTCC_ETSTC_S 31 1959 #define GLDCB_RETSTCC_ETSTC_M BIT(31) 1960 #define GLDCB_RETSTCS(_i) (0x001221C0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 1961 #define GLDCB_RETSTCS_MAX_INDEX 31 1962 #define GLDCB_RETSTCS_CREDITS_S 0 1963 #define GLDCB_RETSTCS_CREDITS_M MAKEMASK(0xFFFFFFFF, 0) 1964 #define GLDCB_RTC2PFC_RCB 0x00122100 /* Reset Source: CORER */ 1965 #define GLDCB_RTC2PFC_RCB_TC2PFC_S 0 1966 #define GLDCB_RTC2PFC_RCB_TC2PFC_M MAKEMASK(0xFFFFFFFF, 0) 1967 #define GLDCB_SWT_RETSTCC(_i) (0x0020A040 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 1968 #define GLDCB_SWT_RETSTCC_MAX_INDEX 31 1969 #define GLDCB_SWT_RETSTCC_BWSHARE_S 0 1970 #define GLDCB_SWT_RETSTCC_BWSHARE_M MAKEMASK(0x7F, 0) 1971 #define GLDCB_SWT_RETSTCC_ETSTC_S 31 1972 #define GLDCB_SWT_RETSTCC_ETSTC_M BIT(31) 1973 #define GLDCB_TC2PFC 0x001D2694 /* Reset Source: CORER */ 1974 #define GLDCB_TC2PFC_TC2PFC_S 0 1975 #define GLDCB_TC2PFC_TC2PFC_M MAKEMASK(0xFFFFFFFF, 0) 1976 #define GLDCB_TCB_MNG_SP 0x000AE12C /* Reset Source: CORER */ 1977 #define GLDCB_TCB_MNG_SP_MNG_SP_S 0 1978 #define GLDCB_TCB_MNG_SP_MNG_SP_M BIT(0) 1979 #define GLDCB_TCB_TCLL_CFG 0x000AE134 /* Reset Source: CORER */ 1980 #define GLDCB_TCB_TCLL_CFG_LLTC_S 0 1981 #define GLDCB_TCB_TCLL_CFG_LLTC_M MAKEMASK(0xFFFFFFFF, 0) 1982 #define GLDCB_TCB_WB_SP 0x000AE310 /* Reset Source: CORER */ 1983 #define GLDCB_TCB_WB_SP_WB_SP_S 0 1984 #define GLDCB_TCB_WB_SP_WB_SP_M BIT(0) 1985 #define GLDCB_TCUPM_IMM_EN 0x000BC824 /* Reset Source: CORER */ 1986 #define GLDCB_TCUPM_IMM_EN_IMM_EN_S 0 1987 #define GLDCB_TCUPM_IMM_EN_IMM_EN_M MAKEMASK(0xFFFFFFFF, 0) 1988 #define GLDCB_TCUPM_LEGACY_TC 0x000BC828 /* Reset Source: CORER */ 1989 #define GLDCB_TCUPM_LEGACY_TC_LEGTC_S 0 1990 #define GLDCB_TCUPM_LEGACY_TC_LEGTC_M MAKEMASK(0xFFFFFFFF, 0) 1991 #define GLDCB_TCUPM_NO_EXCEED_DIS 0x000BC830 /* Reset Source: CORER */ 1992 #define GLDCB_TCUPM_NO_EXCEED_DIS_NON_EXCEED_DIS_S 0 1993 #define GLDCB_TCUPM_NO_EXCEED_DIS_NON_EXCEED_DIS_M BIT(0) 1994 #define GLDCB_TCUPM_WB_DIS 0x000BC834 /* Reset Source: CORER */ 1995 #define GLDCB_TCUPM_WB_DIS_PORT_DISABLE_S 0 1996 #define GLDCB_TCUPM_WB_DIS_PORT_DISABLE_M BIT(0) 1997 #define GLDCB_TCUPM_WB_DIS_TC_DISABLE_S 1 1998 #define GLDCB_TCUPM_WB_DIS_TC_DISABLE_M BIT(1) 1999 #define GLDCB_TFPFCI 0x0009949C /* Reset Source: CORER */ 2000 #define GLDCB_TFPFCI_GLDCB_TFPFCI_S 0 2001 #define GLDCB_TFPFCI_GLDCB_TFPFCI_M MAKEMASK(0xFFFFFFFF, 0) 2002 #define GLDCB_TLPM_IMM_TCB 0x000A0190 /* Reset Source: CORER */ 2003 #define GLDCB_TLPM_IMM_TCB_IMM_EN_S 0 2004 #define GLDCB_TLPM_IMM_TCB_IMM_EN_M MAKEMASK(0xFFFFFFFF, 0) 2005 #define GLDCB_TLPM_IMM_TCUPM 0x000A018C /* Reset Source: CORER */ 2006 #define GLDCB_TLPM_IMM_TCUPM_IMM_EN_S 0 2007 #define GLDCB_TLPM_IMM_TCUPM_IMM_EN_M MAKEMASK(0xFFFFFFFF, 0) 2008 #define GLDCB_TLPM_PCI_DM 0x000A0180 /* Reset Source: CORER */ 2009 #define GLDCB_TLPM_PCI_DM_MONITOR_S 0 2010 #define GLDCB_TLPM_PCI_DM_MONITOR_M MAKEMASK(0x7FFFF, 0) 2011 #define GLDCB_TLPM_PCI_DTHR 0x000A0184 /* Reset Source: CORER */ 2012 #define GLDCB_TLPM_PCI_DTHR_PCI_TDATA_S 0 2013 #define GLDCB_TLPM_PCI_DTHR_PCI_TDATA_M MAKEMASK(0xFFF, 0) 2014 #define GLDCB_TPB_IMM_TLPM 0x00099468 /* Reset Source: CORER */ 2015 #define GLDCB_TPB_IMM_TLPM_IMM_EN_S 0 2016 #define GLDCB_TPB_IMM_TLPM_IMM_EN_M MAKEMASK(0xFFFFFFFF, 0) 2017 #define GLDCB_TPB_IMM_TPB 0x0009946C /* Reset Source: CORER */ 2018 #define GLDCB_TPB_IMM_TPB_IMM_EN_S 0 2019 #define GLDCB_TPB_IMM_TPB_IMM_EN_M MAKEMASK(0xFFFFFFFF, 0) 2020 #define GLDCB_TPB_TCLL_CFG 0x00099464 /* Reset Source: CORER */ 2021 #define GLDCB_TPB_TCLL_CFG_LLTC_S 0 2022 #define GLDCB_TPB_TCLL_CFG_LLTC_M MAKEMASK(0xFFFFFFFF, 0) 2023 #define GLTCB_BULK_DWRR_REG_QUANTA 0x000AE0E0 /* Reset Source: CORER */ 2024 #define GLTCB_BULK_DWRR_REG_QUANTA_QUANTA_S 0 2025 #define GLTCB_BULK_DWRR_REG_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0) 2026 #define GLTCB_BULK_DWRR_REG_SAT 0x000AE0F0 /* Reset Source: CORER */ 2027 #define GLTCB_BULK_DWRR_REG_SAT_SATURATION_S 0 2028 #define GLTCB_BULK_DWRR_REG_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0) 2029 #define GLTCB_BULK_DWRR_WB_QUANTA 0x000AE0E4 /* Reset Source: CORER */ 2030 #define GLTCB_BULK_DWRR_WB_QUANTA_QUANTA_S 0 2031 #define GLTCB_BULK_DWRR_WB_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0) 2032 #define GLTCB_BULK_DWRR_WB_SAT 0x000AE0F4 /* Reset Source: CORER */ 2033 #define GLTCB_BULK_DWRR_WB_SAT_SATURATION_S 0 2034 #define GLTCB_BULK_DWRR_WB_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0) 2035 #define GLTCB_CREDIT_EXP_CTL 0x000AE120 /* Reset Source: CORER */ 2036 #define GLTCB_CREDIT_EXP_CTL_EN_S 0 2037 #define GLTCB_CREDIT_EXP_CTL_EN_M BIT(0) 2038 #define GLTCB_CREDIT_EXP_CTL_MIN_PKT_S 1 2039 #define GLTCB_CREDIT_EXP_CTL_MIN_PKT_M MAKEMASK(0x1FF, 1) 2040 #define GLTCB_LL_DWRR_REG_QUANTA 0x000AE0E8 /* Reset Source: CORER */ 2041 #define GLTCB_LL_DWRR_REG_QUANTA_QUANTA_S 0 2042 #define GLTCB_LL_DWRR_REG_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0) 2043 #define GLTCB_LL_DWRR_REG_SAT 0x000AE0F8 /* Reset Source: CORER */ 2044 #define GLTCB_LL_DWRR_REG_SAT_SATURATION_S 0 2045 #define GLTCB_LL_DWRR_REG_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0) 2046 #define GLTCB_LL_DWRR_WB_QUANTA 0x000AE0EC /* Reset Source: CORER */ 2047 #define GLTCB_LL_DWRR_WB_QUANTA_QUANTA_S 0 2048 #define GLTCB_LL_DWRR_WB_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0) 2049 #define GLTCB_LL_DWRR_WB_SAT 0x000AE0FC /* Reset Source: CORER */ 2050 #define GLTCB_LL_DWRR_WB_SAT_SATURATION_S 0 2051 #define GLTCB_LL_DWRR_WB_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0) 2052 #define GLTCB_WB_RL 0x000AE238 /* Reset Source: CORER */ 2053 #define GLTCB_WB_RL_PERIOD_S 0 2054 #define GLTCB_WB_RL_PERIOD_M MAKEMASK(0xFFFF, 0) 2055 #define GLTCB_WB_RL_EN_S 16 2056 #define GLTCB_WB_RL_EN_M BIT(16) 2057 #define GLTPB_WB_RL 0x00099460 /* Reset Source: CORER */ 2058 #define GLTPB_WB_RL_PERIOD_S 0 2059 #define GLTPB_WB_RL_PERIOD_M MAKEMASK(0xFFFF, 0) 2060 #define GLTPB_WB_RL_EN_S 16 2061 #define GLTPB_WB_RL_EN_M BIT(16) 2062 #define E800_PRTDCB_FCCFG 0x001E4640 /* Reset Source: GLOBR */ 2063 #define E800_PRTDCB_FCCFG_TFCE_S 3 2064 #define E800_PRTDCB_FCCFG_TFCE_M MAKEMASK(0x3, 3) 2065 #define E800_PRTDCB_FCRTV 0x001E4600 /* Reset Source: GLOBR */ 2066 #define E800_PRTDCB_FCRTV_FC_REFRESH_TH_S 0 2067 #define E800_PRTDCB_FCRTV_FC_REFRESH_TH_M MAKEMASK(0xFFFF, 0) 2068 #define E800_PRTDCB_FCTTVN(_i) (0x001E4580 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: GLOBR */ 2069 #define E800_PRTDCB_FCTTVN_MAX_INDEX 3 2070 #define E800_PRTDCB_FCTTVN_TTV_2N_S 0 2071 #define E800_PRTDCB_FCTTVN_TTV_2N_M MAKEMASK(0xFFFF, 0) 2072 #define E800_PRTDCB_FCTTVN_TTV_2N_P1_S 16 2073 #define E800_PRTDCB_FCTTVN_TTV_2N_P1_M MAKEMASK(0xFFFF, 16) 2074 #define PRTDCB_GENC 0x00083000 /* Reset Source: CORER */ 2075 #define PRTDCB_GENC_NUMTC_S 2 2076 #define PRTDCB_GENC_NUMTC_M MAKEMASK(0xF, 2) 2077 #define PRTDCB_GENC_FCOEUP_S 6 2078 #define PRTDCB_GENC_FCOEUP_M MAKEMASK(0x7, 6) 2079 #define PRTDCB_GENC_FCOEUP_VALID_S 9 2080 #define PRTDCB_GENC_FCOEUP_VALID_M BIT(9) 2081 #define PRTDCB_GENC_PFCLDA_S 16 2082 #define PRTDCB_GENC_PFCLDA_M MAKEMASK(0xFFFF, 16) 2083 #define PRTDCB_GENS 0x00083020 /* Reset Source: CORER */ 2084 #define PRTDCB_GENS_DCBX_STATUS_S 0 2085 #define PRTDCB_GENS_DCBX_STATUS_M MAKEMASK(0x7, 0) 2086 #define PRTDCB_PRS_RETSC 0x002001A0 /* Reset Source: CORER */ 2087 #define PRTDCB_PRS_RETSC_ETS_MODE_S 0 2088 #define PRTDCB_PRS_RETSC_ETS_MODE_M BIT(0) 2089 #define PRTDCB_PRS_RETSC_NON_ETS_MODE_S 1 2090 #define PRTDCB_PRS_RETSC_NON_ETS_MODE_M BIT(1) 2091 #define PRTDCB_PRS_RETSC_ETS_MAX_EXP_S 2 2092 #define PRTDCB_PRS_RETSC_ETS_MAX_EXP_M MAKEMASK(0xF, 2) 2093 #define PRTDCB_PRS_RPRRC 0x00200180 /* Reset Source: CORER */ 2094 #define PRTDCB_PRS_RPRRC_BWSHARE_S 0 2095 #define PRTDCB_PRS_RPRRC_BWSHARE_M MAKEMASK(0x3FF, 0) 2096 #define PRTDCB_PRS_RPRRC_BWSHARE_DIS_S 31 2097 #define PRTDCB_PRS_RPRRC_BWSHARE_DIS_M BIT(31) 2098 #define PRTDCB_RETSC 0x001222A0 /* Reset Source: CORER */ 2099 #define PRTDCB_RETSC_ETS_MODE_S 0 2100 #define PRTDCB_RETSC_ETS_MODE_M BIT(0) 2101 #define PRTDCB_RETSC_NON_ETS_MODE_S 1 2102 #define PRTDCB_RETSC_NON_ETS_MODE_M BIT(1) 2103 #define PRTDCB_RETSC_ETS_MAX_EXP_S 2 2104 #define PRTDCB_RETSC_ETS_MAX_EXP_M MAKEMASK(0xF, 2) 2105 #define PRTDCB_RPRRC 0x001220C0 /* Reset Source: CORER */ 2106 #define PRTDCB_RPRRC_BWSHARE_S 0 2107 #define PRTDCB_RPRRC_BWSHARE_M MAKEMASK(0x3FF, 0) 2108 #define PRTDCB_RPRRC_BWSHARE_DIS_S 31 2109 #define PRTDCB_RPRRC_BWSHARE_DIS_M BIT(31) 2110 #define PRTDCB_RPRRS 0x001220E0 /* Reset Source: CORER */ 2111 #define PRTDCB_RPRRS_CREDITS_S 0 2112 #define PRTDCB_RPRRS_CREDITS_M MAKEMASK(0xFFFFFFFF, 0) 2113 #define PRTDCB_RUP_TDPU 0x00040960 /* Reset Source: CORER */ 2114 #define PRTDCB_RUP_TDPU_NOVLANUP_S 0 2115 #define PRTDCB_RUP_TDPU_NOVLANUP_M MAKEMASK(0x7, 0) 2116 #define PRTDCB_RUP2TC 0x001D2640 /* Reset Source: CORER */ 2117 #define PRTDCB_RUP2TC_UP0TC_S 0 2118 #define PRTDCB_RUP2TC_UP0TC_M MAKEMASK(0x7, 0) 2119 #define PRTDCB_RUP2TC_UP1TC_S 3 2120 #define PRTDCB_RUP2TC_UP1TC_M MAKEMASK(0x7, 3) 2121 #define PRTDCB_RUP2TC_UP2TC_S 6 2122 #define PRTDCB_RUP2TC_UP2TC_M MAKEMASK(0x7, 6) 2123 #define PRTDCB_RUP2TC_UP3TC_S 9 2124 #define PRTDCB_RUP2TC_UP3TC_M MAKEMASK(0x7, 9) 2125 #define PRTDCB_RUP2TC_UP4TC_S 12 2126 #define PRTDCB_RUP2TC_UP4TC_M MAKEMASK(0x7, 12) 2127 #define PRTDCB_RUP2TC_UP5TC_S 15 2128 #define PRTDCB_RUP2TC_UP5TC_M MAKEMASK(0x7, 15) 2129 #define PRTDCB_RUP2TC_UP6TC_S 18 2130 #define PRTDCB_RUP2TC_UP6TC_M MAKEMASK(0x7, 18) 2131 #define PRTDCB_RUP2TC_UP7TC_S 21 2132 #define PRTDCB_RUP2TC_UP7TC_M MAKEMASK(0x7, 21) 2133 #define PRTDCB_SWT_RETSC 0x0020A140 /* Reset Source: CORER */ 2134 #define PRTDCB_SWT_RETSC_ETS_MODE_S 0 2135 #define PRTDCB_SWT_RETSC_ETS_MODE_M BIT(0) 2136 #define PRTDCB_SWT_RETSC_NON_ETS_MODE_S 1 2137 #define PRTDCB_SWT_RETSC_NON_ETS_MODE_M BIT(1) 2138 #define PRTDCB_SWT_RETSC_ETS_MAX_EXP_S 2 2139 #define PRTDCB_SWT_RETSC_ETS_MAX_EXP_M MAKEMASK(0xF, 2) 2140 #define PRTDCB_TCB_DWRR_CREDITS 0x000AE000 /* Reset Source: CORER */ 2141 #define PRTDCB_TCB_DWRR_CREDITS_CREDITS_S 0 2142 #define PRTDCB_TCB_DWRR_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0) 2143 #define PRTDCB_TCB_DWRR_QUANTA 0x000AE020 /* Reset Source: CORER */ 2144 #define PRTDCB_TCB_DWRR_QUANTA_QUANTA_S 0 2145 #define PRTDCB_TCB_DWRR_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0) 2146 #define PRTDCB_TCB_DWRR_SAT 0x000AE040 /* Reset Source: CORER */ 2147 #define PRTDCB_TCB_DWRR_SAT_SATURATION_S 0 2148 #define PRTDCB_TCB_DWRR_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0) 2149 #define PRTDCB_TCUPM_NO_EXCEED_DM 0x000BC3C0 /* Reset Source: CORER */ 2150 #define PRTDCB_TCUPM_NO_EXCEED_DM_MONITOR_S 0 2151 #define PRTDCB_TCUPM_NO_EXCEED_DM_MONITOR_M MAKEMASK(0x7FFFF, 0) 2152 #define PRTDCB_TCUPM_REG_CM 0x000BC360 /* Reset Source: CORER */ 2153 #define PRTDCB_TCUPM_REG_CM_MONITOR_S 0 2154 #define PRTDCB_TCUPM_REG_CM_MONITOR_M MAKEMASK(0x7FFF, 0) 2155 #define PRTDCB_TCUPM_REG_CTHR 0x000BC380 /* Reset Source: CORER */ 2156 #define PRTDCB_TCUPM_REG_CTHR_PORTOFFTH_H_S 0 2157 #define PRTDCB_TCUPM_REG_CTHR_PORTOFFTH_H_M MAKEMASK(0x7FFF, 0) 2158 #define PRTDCB_TCUPM_REG_CTHR_PORTOFFTH_L_S 15 2159 #define PRTDCB_TCUPM_REG_CTHR_PORTOFFTH_L_M MAKEMASK(0x7FFF, 15) 2160 #define PRTDCB_TCUPM_REG_DM 0x000BC3A0 /* Reset Source: CORER */ 2161 #define PRTDCB_TCUPM_REG_DM_MONITOR_S 0 2162 #define PRTDCB_TCUPM_REG_DM_MONITOR_M MAKEMASK(0x7FFFF, 0) 2163 #define PRTDCB_TCUPM_REG_DTHR 0x000BC3E0 /* Reset Source: CORER */ 2164 #define PRTDCB_TCUPM_REG_DTHR_PORTOFFTH_H_S 0 2165 #define PRTDCB_TCUPM_REG_DTHR_PORTOFFTH_H_M MAKEMASK(0xFFF, 0) 2166 #define PRTDCB_TCUPM_REG_DTHR_PORTOFFTH_L_S 12 2167 #define PRTDCB_TCUPM_REG_DTHR_PORTOFFTH_L_M MAKEMASK(0xFFF, 12) 2168 #define PRTDCB_TCUPM_REG_PE_HB_DM 0x000BC400 /* Reset Source: CORER */ 2169 #define PRTDCB_TCUPM_REG_PE_HB_DM_MONITOR_S 0 2170 #define PRTDCB_TCUPM_REG_PE_HB_DM_MONITOR_M MAKEMASK(0xFFF, 0) 2171 #define PRTDCB_TCUPM_REG_PE_HB_DTHR 0x000BC420 /* Reset Source: CORER */ 2172 #define PRTDCB_TCUPM_REG_PE_HB_DTHR_PORTOFFTH_H_S 0 2173 #define PRTDCB_TCUPM_REG_PE_HB_DTHR_PORTOFFTH_H_M MAKEMASK(0xFFF, 0) 2174 #define PRTDCB_TCUPM_REG_PE_HB_DTHR_PORTOFFTH_L_S 12 2175 #define PRTDCB_TCUPM_REG_PE_HB_DTHR_PORTOFFTH_L_M MAKEMASK(0xFFF, 12) 2176 #define PRTDCB_TCUPM_WAIT_PFC_CM 0x000BC440 /* Reset Source: CORER */ 2177 #define PRTDCB_TCUPM_WAIT_PFC_CM_MONITOR_S 0 2178 #define PRTDCB_TCUPM_WAIT_PFC_CM_MONITOR_M MAKEMASK(0x7FFF, 0) 2179 #define PRTDCB_TCUPM_WAIT_PFC_CTHR 0x000BC460 /* Reset Source: CORER */ 2180 #define PRTDCB_TCUPM_WAIT_PFC_CTHR_PORTOFFTH_S 0 2181 #define PRTDCB_TCUPM_WAIT_PFC_CTHR_PORTOFFTH_M MAKEMASK(0x7FFF, 0) 2182 #define PRTDCB_TCUPM_WAIT_PFC_DM 0x000BC480 /* Reset Source: CORER */ 2183 #define PRTDCB_TCUPM_WAIT_PFC_DM_MONITOR_S 0 2184 #define PRTDCB_TCUPM_WAIT_PFC_DM_MONITOR_M MAKEMASK(0x7FFFF, 0) 2185 #define PRTDCB_TCUPM_WAIT_PFC_DTHR 0x000BC4A0 /* Reset Source: CORER */ 2186 #define PRTDCB_TCUPM_WAIT_PFC_DTHR_PORTOFFTH_S 0 2187 #define PRTDCB_TCUPM_WAIT_PFC_DTHR_PORTOFFTH_M MAKEMASK(0xFFF, 0) 2188 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DM 0x000BC4C0 /* Reset Source: CORER */ 2189 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DM_MONITOR_S 0 2190 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DM_MONITOR_M MAKEMASK(0xFFF, 0) 2191 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DTHR 0x000BC4E0 /* Reset Source: CORER */ 2192 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DTHR_PORTOFFTH_S 0 2193 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DTHR_PORTOFFTH_M MAKEMASK(0xFFF, 0) 2194 #define PRTDCB_TDPUC 0x00040940 /* Reset Source: CORER */ 2195 #define PRTDCB_TDPUC_MAX_TXFRAME_S 0 2196 #define PRTDCB_TDPUC_MAX_TXFRAME_M MAKEMASK(0xFFFF, 0) 2197 #define PRTDCB_TDPUC_MAL_LENGTH_S 16 2198 #define PRTDCB_TDPUC_MAL_LENGTH_M BIT(16) 2199 #define PRTDCB_TDPUC_MAL_CMD_S 17 2200 #define PRTDCB_TDPUC_MAL_CMD_M BIT(17) 2201 #define PRTDCB_TDPUC_TTL_DROP_S 18 2202 #define PRTDCB_TDPUC_TTL_DROP_M BIT(18) 2203 #define PRTDCB_TDPUC_UR_DROP_S 19 2204 #define PRTDCB_TDPUC_UR_DROP_M BIT(19) 2205 #define PRTDCB_TDPUC_DUMMY_S 20 2206 #define PRTDCB_TDPUC_DUMMY_M BIT(20) 2207 #define PRTDCB_TDPUC_BIG_PKT_SIZE_S 21 2208 #define PRTDCB_TDPUC_BIG_PKT_SIZE_M BIT(21) 2209 #define PRTDCB_TDPUC_L2_ACCEPT_FAIL_S 22 2210 #define PRTDCB_TDPUC_L2_ACCEPT_FAIL_M BIT(22) 2211 #define PRTDCB_TDPUC_DSCP_CHECK_FAIL_S 23 2212 #define PRTDCB_TDPUC_DSCP_CHECK_FAIL_M BIT(23) 2213 #define PRTDCB_TDPUC_RCU_ANTISPOOF_S 24 2214 #define PRTDCB_TDPUC_RCU_ANTISPOOF_M BIT(24) 2215 #define PRTDCB_TDPUC_NIC_DSI_S 25 2216 #define PRTDCB_TDPUC_NIC_DSI_M BIT(25) 2217 #define PRTDCB_TDPUC_NIC_IPSEC_S 26 2218 #define PRTDCB_TDPUC_NIC_IPSEC_M BIT(26) 2219 #define PRTDCB_TDPUC_CLEAR_DROP_S 31 2220 #define PRTDCB_TDPUC_CLEAR_DROP_M BIT(31) 2221 #define PRTDCB_TFCS 0x001E4560 /* Reset Source: GLOBR */ 2222 #define PRTDCB_TFCS_TXOFF_S 0 2223 #define PRTDCB_TFCS_TXOFF_M BIT(0) 2224 #define PRTDCB_TFCS_TXOFF0_S 8 2225 #define PRTDCB_TFCS_TXOFF0_M BIT(8) 2226 #define PRTDCB_TFCS_TXOFF1_S 9 2227 #define PRTDCB_TFCS_TXOFF1_M BIT(9) 2228 #define PRTDCB_TFCS_TXOFF2_S 10 2229 #define PRTDCB_TFCS_TXOFF2_M BIT(10) 2230 #define PRTDCB_TFCS_TXOFF3_S 11 2231 #define PRTDCB_TFCS_TXOFF3_M BIT(11) 2232 #define PRTDCB_TFCS_TXOFF4_S 12 2233 #define PRTDCB_TFCS_TXOFF4_M BIT(12) 2234 #define PRTDCB_TFCS_TXOFF5_S 13 2235 #define PRTDCB_TFCS_TXOFF5_M BIT(13) 2236 #define PRTDCB_TFCS_TXOFF6_S 14 2237 #define PRTDCB_TFCS_TXOFF6_M BIT(14) 2238 #define PRTDCB_TFCS_TXOFF7_S 15 2239 #define PRTDCB_TFCS_TXOFF7_M BIT(15) 2240 #define PRTDCB_TLPM_REG_DM 0x000A0000 /* Reset Source: CORER */ 2241 #define PRTDCB_TLPM_REG_DM_MONITOR_S 0 2242 #define PRTDCB_TLPM_REG_DM_MONITOR_M MAKEMASK(0x7FFFF, 0) 2243 #define PRTDCB_TLPM_REG_DTHR 0x000A0020 /* Reset Source: CORER */ 2244 #define PRTDCB_TLPM_REG_DTHR_PORTOFFTH_H_S 0 2245 #define PRTDCB_TLPM_REG_DTHR_PORTOFFTH_H_M MAKEMASK(0xFFF, 0) 2246 #define PRTDCB_TLPM_REG_DTHR_PORTOFFTH_L_S 12 2247 #define PRTDCB_TLPM_REG_DTHR_PORTOFFTH_L_M MAKEMASK(0xFFF, 12) 2248 #define PRTDCB_TLPM_WAIT_PFC_DM 0x000A0040 /* Reset Source: CORER */ 2249 #define PRTDCB_TLPM_WAIT_PFC_DM_MONITOR_S 0 2250 #define PRTDCB_TLPM_WAIT_PFC_DM_MONITOR_M MAKEMASK(0x7FFFF, 0) 2251 #define PRTDCB_TLPM_WAIT_PFC_DTHR 0x000A0060 /* Reset Source: CORER */ 2252 #define PRTDCB_TLPM_WAIT_PFC_DTHR_PORTOFFTH_S 0 2253 #define PRTDCB_TLPM_WAIT_PFC_DTHR_PORTOFFTH_M MAKEMASK(0xFFF, 0) 2254 #define PRTDCB_TPFCTS(_i) (0x001E4660 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: GLOBR */ 2255 #define PRTDCB_TPFCTS_MAX_INDEX 7 2256 #define PRTDCB_TPFCTS_PFCTIMER_S 0 2257 #define PRTDCB_TPFCTS_PFCTIMER_M MAKEMASK(0x3FFF, 0) 2258 #define PRTDCB_TUP2TC 0x001D26C0 /* Reset Source: CORER */ 2259 #define PRTDCB_TUP2TC_UP0TC_S 0 2260 #define PRTDCB_TUP2TC_UP0TC_M MAKEMASK(0x7, 0) 2261 #define PRTDCB_TUP2TC_UP1TC_S 3 2262 #define PRTDCB_TUP2TC_UP1TC_M MAKEMASK(0x7, 3) 2263 #define PRTDCB_TUP2TC_UP2TC_S 6 2264 #define PRTDCB_TUP2TC_UP2TC_M MAKEMASK(0x7, 6) 2265 #define PRTDCB_TUP2TC_UP3TC_S 9 2266 #define PRTDCB_TUP2TC_UP3TC_M MAKEMASK(0x7, 9) 2267 #define PRTDCB_TUP2TC_UP4TC_S 12 2268 #define PRTDCB_TUP2TC_UP4TC_M MAKEMASK(0x7, 12) 2269 #define PRTDCB_TUP2TC_UP5TC_S 15 2270 #define PRTDCB_TUP2TC_UP5TC_M MAKEMASK(0x7, 15) 2271 #define PRTDCB_TUP2TC_UP6TC_S 18 2272 #define PRTDCB_TUP2TC_UP6TC_M MAKEMASK(0x7, 18) 2273 #define PRTDCB_TUP2TC_UP7TC_S 21 2274 #define PRTDCB_TUP2TC_UP7TC_M MAKEMASK(0x7, 21) 2275 #define PRTDCB_TX_DSCP2UP_CTL 0x00040980 /* Reset Source: CORER */ 2276 #define PRTDCB_TX_DSCP2UP_CTL_DSCP2UP_ENA_S 0 2277 #define PRTDCB_TX_DSCP2UP_CTL_DSCP2UP_ENA_M BIT(0) 2278 #define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_S 1 2279 #define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_M MAKEMASK(0x7, 1) 2280 #define PRTDCB_TX_DSCP2UP_IPV4_LUT(_i) (0x000409A0 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: CORER */ 2281 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_MAX_INDEX 7 2282 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_0_S 0 2283 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_0_M MAKEMASK(0x7, 0) 2284 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_1_S 4 2285 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_1_M MAKEMASK(0x7, 4) 2286 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_2_S 8 2287 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_2_M MAKEMASK(0x7, 8) 2288 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_3_S 12 2289 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_3_M MAKEMASK(0x7, 12) 2290 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_4_S 16 2291 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_4_M MAKEMASK(0x7, 16) 2292 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_5_S 20 2293 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_5_M MAKEMASK(0x7, 20) 2294 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_6_S 24 2295 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_6_M MAKEMASK(0x7, 24) 2296 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_7_S 28 2297 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_7_M MAKEMASK(0x7, 28) 2298 #define PRTDCB_TX_DSCP2UP_IPV6_LUT(_i) (0x00040AA0 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: CORER */ 2299 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_MAX_INDEX 7 2300 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_0_S 0 2301 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_0_M MAKEMASK(0x7, 0) 2302 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_1_S 4 2303 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_1_M MAKEMASK(0x7, 4) 2304 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_2_S 8 2305 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_2_M MAKEMASK(0x7, 8) 2306 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_3_S 12 2307 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_3_M MAKEMASK(0x7, 12) 2308 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_4_S 16 2309 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_4_M MAKEMASK(0x7, 16) 2310 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_5_S 20 2311 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_5_M MAKEMASK(0x7, 20) 2312 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_6_S 24 2313 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_6_M MAKEMASK(0x7, 24) 2314 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_7_S 28 2315 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_7_M MAKEMASK(0x7, 28) 2316 #define PRTTCB_BULK_DWRR_REG_CREDITS 0x000AE060 /* Reset Source: CORER */ 2317 #define PRTTCB_BULK_DWRR_REG_CREDITS_CREDITS_S 0 2318 #define PRTTCB_BULK_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0) 2319 #define PRTTCB_BULK_DWRR_WB_CREDITS 0x000AE080 /* Reset Source: CORER */ 2320 #define PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_S 0 2321 #define PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0) 2322 #define PRTTCB_CREDIT_EXP 0x000AE100 /* Reset Source: CORER */ 2323 #define PRTTCB_CREDIT_EXP_EXPANSION_S 0 2324 #define PRTTCB_CREDIT_EXP_EXPANSION_M MAKEMASK(0xFF, 0) 2325 #define PRTTCB_LL_DWRR_REG_CREDITS 0x000AE0A0 /* Reset Source: CORER */ 2326 #define PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_S 0 2327 #define PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0) 2328 #define PRTTCB_LL_DWRR_WB_CREDITS 0x000AE0C0 /* Reset Source: CORER */ 2329 #define PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_S 0 2330 #define PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0) 2331 #define TCDCB_TCUPM_WAIT_CM(_i) (0x000BC520 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 2332 #define TCDCB_TCUPM_WAIT_CM_MAX_INDEX 31 2333 #define TCDCB_TCUPM_WAIT_CM_MONITOR_S 0 2334 #define TCDCB_TCUPM_WAIT_CM_MONITOR_M MAKEMASK(0x7FFF, 0) 2335 #define TCDCB_TCUPM_WAIT_CTHR(_i) (0x000BC5A0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 2336 #define TCDCB_TCUPM_WAIT_CTHR_MAX_INDEX 31 2337 #define TCDCB_TCUPM_WAIT_CTHR_TCOFFTH_S 0 2338 #define TCDCB_TCUPM_WAIT_CTHR_TCOFFTH_M MAKEMASK(0x7FFF, 0) 2339 #define TCDCB_TCUPM_WAIT_DM(_i) (0x000BC620 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 2340 #define TCDCB_TCUPM_WAIT_DM_MAX_INDEX 31 2341 #define TCDCB_TCUPM_WAIT_DM_MONITOR_S 0 2342 #define TCDCB_TCUPM_WAIT_DM_MONITOR_M MAKEMASK(0x7FFFF, 0) 2343 #define TCDCB_TCUPM_WAIT_DTHR(_i) (0x000BC6A0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 2344 #define TCDCB_TCUPM_WAIT_DTHR_MAX_INDEX 31 2345 #define TCDCB_TCUPM_WAIT_DTHR_TCOFFTH_S 0 2346 #define TCDCB_TCUPM_WAIT_DTHR_TCOFFTH_M MAKEMASK(0xFFF, 0) 2347 #define TCDCB_TCUPM_WAIT_PE_HB_DM(_i) (0x000BC720 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 2348 #define TCDCB_TCUPM_WAIT_PE_HB_DM_MAX_INDEX 31 2349 #define TCDCB_TCUPM_WAIT_PE_HB_DM_MONITOR_S 0 2350 #define TCDCB_TCUPM_WAIT_PE_HB_DM_MONITOR_M MAKEMASK(0xFFF, 0) 2351 #define TCDCB_TCUPM_WAIT_PE_HB_DTHR(_i) (0x000BC7A0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 2352 #define TCDCB_TCUPM_WAIT_PE_HB_DTHR_MAX_INDEX 31 2353 #define TCDCB_TCUPM_WAIT_PE_HB_DTHR_TCOFFTH_S 0 2354 #define TCDCB_TCUPM_WAIT_PE_HB_DTHR_TCOFFTH_M MAKEMASK(0xFFF, 0) 2355 #define TCDCB_TLPM_WAIT_DM(_i) (0x000A0080 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 2356 #define TCDCB_TLPM_WAIT_DM_MAX_INDEX 31 2357 #define TCDCB_TLPM_WAIT_DM_MONITOR_S 0 2358 #define TCDCB_TLPM_WAIT_DM_MONITOR_M MAKEMASK(0x7FFFF, 0) 2359 #define TCDCB_TLPM_WAIT_DTHR(_i) (0x000A0100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 2360 #define TCDCB_TLPM_WAIT_DTHR_MAX_INDEX 31 2361 #define TCDCB_TLPM_WAIT_DTHR_TCOFFTH_S 0 2362 #define TCDCB_TLPM_WAIT_DTHR_TCOFFTH_M MAKEMASK(0xFFF, 0) 2363 #define TCTCB_WB_RL_TC_CFG(_i) (0x000AE138 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 2364 #define TCTCB_WB_RL_TC_CFG_MAX_INDEX 31 2365 #define TCTCB_WB_RL_TC_CFG_TOKENS_S 0 2366 #define TCTCB_WB_RL_TC_CFG_TOKENS_M MAKEMASK(0xFFF, 0) 2367 #define TCTCB_WB_RL_TC_CFG_BURST_SIZE_S 12 2368 #define TCTCB_WB_RL_TC_CFG_BURST_SIZE_M MAKEMASK(0x3FF, 12) 2369 #define TCTCB_WB_RL_TC_STAT(_i) (0x000AE1B8 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 2370 #define TCTCB_WB_RL_TC_STAT_MAX_INDEX 31 2371 #define TCTCB_WB_RL_TC_STAT_BUCKET_S 0 2372 #define TCTCB_WB_RL_TC_STAT_BUCKET_M MAKEMASK(0x1FFFF, 0) 2373 #define TPB_BULK_DWRR_REG_QUANTA 0x00099340 /* Reset Source: CORER */ 2374 #define TPB_BULK_DWRR_REG_QUANTA_QUANTA_S 0 2375 #define TPB_BULK_DWRR_REG_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0) 2376 #define TPB_BULK_DWRR_REG_SAT 0x00099350 /* Reset Source: CORER */ 2377 #define TPB_BULK_DWRR_REG_SAT_SATURATION_S 0 2378 #define TPB_BULK_DWRR_REG_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0) 2379 #define TPB_BULK_DWRR_WB_QUANTA 0x00099344 /* Reset Source: CORER */ 2380 #define TPB_BULK_DWRR_WB_QUANTA_QUANTA_S 0 2381 #define TPB_BULK_DWRR_WB_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0) 2382 #define TPB_BULK_DWRR_WB_SAT 0x00099354 /* Reset Source: CORER */ 2383 #define TPB_BULK_DWRR_WB_SAT_SATURATION_S 0 2384 #define TPB_BULK_DWRR_WB_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0) 2385 #define TPB_GLDCB_TCB_WB_SP 0x0009966C /* Reset Source: CORER */ 2386 #define TPB_GLDCB_TCB_WB_SP_WB_SP_S 0 2387 #define TPB_GLDCB_TCB_WB_SP_WB_SP_M BIT(0) 2388 #define TPB_GLTCB_CREDIT_EXP_CTL 0x00099664 /* Reset Source: CORER */ 2389 #define TPB_GLTCB_CREDIT_EXP_CTL_EN_S 0 2390 #define TPB_GLTCB_CREDIT_EXP_CTL_EN_M BIT(0) 2391 #define TPB_GLTCB_CREDIT_EXP_CTL_MIN_PKT_S 1 2392 #define TPB_GLTCB_CREDIT_EXP_CTL_MIN_PKT_M MAKEMASK(0x1FF, 1) 2393 #define TPB_LL_DWRR_REG_QUANTA 0x00099348 /* Reset Source: CORER */ 2394 #define TPB_LL_DWRR_REG_QUANTA_QUANTA_S 0 2395 #define TPB_LL_DWRR_REG_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0) 2396 #define TPB_LL_DWRR_REG_SAT 0x00099358 /* Reset Source: CORER */ 2397 #define TPB_LL_DWRR_REG_SAT_SATURATION_S 0 2398 #define TPB_LL_DWRR_REG_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0) 2399 #define TPB_LL_DWRR_WB_QUANTA 0x0009934C /* Reset Source: CORER */ 2400 #define TPB_LL_DWRR_WB_QUANTA_QUANTA_S 0 2401 #define TPB_LL_DWRR_WB_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0) 2402 #define TPB_LL_DWRR_WB_SAT 0x0009935C /* Reset Source: CORER */ 2403 #define TPB_LL_DWRR_WB_SAT_SATURATION_S 0 2404 #define TPB_LL_DWRR_WB_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0) 2405 #define TPB_PRTDCB_TCB_DWRR_CREDITS 0x000991C0 /* Reset Source: CORER */ 2406 #define TPB_PRTDCB_TCB_DWRR_CREDITS_CREDITS_S 0 2407 #define TPB_PRTDCB_TCB_DWRR_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0) 2408 #define TPB_PRTDCB_TCB_DWRR_QUANTA 0x00099220 /* Reset Source: CORER */ 2409 #define TPB_PRTDCB_TCB_DWRR_QUANTA_QUANTA_S 0 2410 #define TPB_PRTDCB_TCB_DWRR_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0) 2411 #define TPB_PRTDCB_TCB_DWRR_SAT 0x00099260 /* Reset Source: CORER */ 2412 #define TPB_PRTDCB_TCB_DWRR_SAT_SATURATION_S 0 2413 #define TPB_PRTDCB_TCB_DWRR_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0) 2414 #define TPB_PRTTCB_BULK_DWRR_REG_CREDITS 0x000992A0 /* Reset Source: CORER */ 2415 #define TPB_PRTTCB_BULK_DWRR_REG_CREDITS_CREDITS_S 0 2416 #define TPB_PRTTCB_BULK_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0) 2417 #define TPB_PRTTCB_BULK_DWRR_WB_CREDITS 0x000992C0 /* Reset Source: CORER */ 2418 #define TPB_PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_S 0 2419 #define TPB_PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0) 2420 #define TPB_PRTTCB_CREDIT_EXP 0x00099644 /* Reset Source: CORER */ 2421 #define TPB_PRTTCB_CREDIT_EXP_EXPANSION_S 0 2422 #define TPB_PRTTCB_CREDIT_EXP_EXPANSION_M MAKEMASK(0xFF, 0) 2423 #define TPB_PRTTCB_LL_DWRR_REG_CREDITS 0x00099300 /* Reset Source: CORER */ 2424 #define TPB_PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_S 0 2425 #define TPB_PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0) 2426 #define TPB_PRTTCB_LL_DWRR_WB_CREDITS 0x00099320 /* Reset Source: CORER */ 2427 #define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_S 0 2428 #define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0) 2429 #define TPB_WB_RL_TC_CFG(_i) (0x00099360 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 2430 #define TPB_WB_RL_TC_CFG_MAX_INDEX 31 2431 #define TPB_WB_RL_TC_CFG_TOKENS_S 0 2432 #define TPB_WB_RL_TC_CFG_TOKENS_M MAKEMASK(0xFFF, 0) 2433 #define TPB_WB_RL_TC_CFG_BURST_SIZE_S 12 2434 #define TPB_WB_RL_TC_CFG_BURST_SIZE_M MAKEMASK(0x3FF, 12) 2435 #define TPB_WB_RL_TC_STAT(_i) (0x000993E0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 2436 #define TPB_WB_RL_TC_STAT_MAX_INDEX 31 2437 #define TPB_WB_RL_TC_STAT_BUCKET_S 0 2438 #define TPB_WB_RL_TC_STAT_BUCKET_M MAKEMASK(0x1FFFF, 0) 2439 #define E800_GL_ACLEXT_CDMD_L1SEL(_i) (0x00210054 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2440 #define E800_GL_ACLEXT_CDMD_L1SEL_MAX_INDEX 2 2441 #define E800_GL_ACLEXT_CDMD_L1SEL_RX_SEL_S 0 2442 #define E800_GL_ACLEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x1F, 0) 2443 #define E800_GL_ACLEXT_CDMD_L1SEL_TX_SEL_S 8 2444 #define E800_GL_ACLEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x1F, 8) 2445 #define E800_GL_ACLEXT_CDMD_L1SEL_AUX0_SEL_S 16 2446 #define E800_GL_ACLEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x1F, 16) 2447 #define E800_GL_ACLEXT_CDMD_L1SEL_AUX1_SEL_S 24 2448 #define E800_GL_ACLEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x1F, 24) 2449 #define E800_GL_ACLEXT_CDMD_L1SEL_BIDIR_ENA_S 30 2450 #define E800_GL_ACLEXT_CDMD_L1SEL_BIDIR_ENA_M MAKEMASK(0x3, 30) 2451 #define E800_GL_ACLEXT_CTLTBL_L2ADDR(_i) (0x00210084 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2452 #define E800_GL_ACLEXT_CTLTBL_L2ADDR_MAX_INDEX 2 2453 #define E800_GL_ACLEXT_CTLTBL_L2ADDR_LINE_OFF_S 0 2454 #define E800_GL_ACLEXT_CTLTBL_L2ADDR_LINE_OFF_M MAKEMASK(0x7, 0) 2455 #define E800_GL_ACLEXT_CTLTBL_L2ADDR_LINE_IDX_S 8 2456 #define E800_GL_ACLEXT_CTLTBL_L2ADDR_LINE_IDX_M MAKEMASK(0x7, 8) 2457 #define E800_GL_ACLEXT_CTLTBL_L2ADDR_AUTO_INC_S 31 2458 #define E800_GL_ACLEXT_CTLTBL_L2ADDR_AUTO_INC_M BIT(31) 2459 #define E800_GL_ACLEXT_CTLTBL_L2DATA(_i) (0x00210090 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2460 #define E800_GL_ACLEXT_CTLTBL_L2DATA_MAX_INDEX 2 2461 #define E800_GL_ACLEXT_CTLTBL_L2DATA_DATA_S 0 2462 #define E800_GL_ACLEXT_CTLTBL_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0) 2463 #define E800_GL_ACLEXT_DFLT_L2PRFL(_i) (0x00210138 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2464 #define E800_GL_ACLEXT_DFLT_L2PRFL_MAX_INDEX 2 2465 #define E800_GL_ACLEXT_DFLT_L2PRFL_DFLT_PRFL_S 0 2466 #define E800_GL_ACLEXT_DFLT_L2PRFL_DFLT_PRFL_M MAKEMASK(0xFFFF, 0) 2467 #define GL_ACLEXT_DFLT_L2PRFL_ACL(_i) (0x00393800 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2468 #define GL_ACLEXT_DFLT_L2PRFL_ACL_MAX_INDEX 2 2469 #define GL_ACLEXT_DFLT_L2PRFL_ACL_DFLT_PRFL_S 0 2470 #define GL_ACLEXT_DFLT_L2PRFL_ACL_DFLT_PRFL_M MAKEMASK(0xFFFF, 0) 2471 #define E800_GL_ACLEXT_FLGS_L1SEL0_1(_i) (0x0021006C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2472 #define E800_GL_ACLEXT_FLGS_L1SEL0_1_MAX_INDEX 2 2473 #define E800_GL_ACLEXT_FLGS_L1SEL0_1_FLS0_S 0 2474 #define E800_GL_ACLEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x1FF, 0) 2475 #define E800_GL_ACLEXT_FLGS_L1SEL0_1_FLS1_S 16 2476 #define E800_GL_ACLEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x1FF, 16) 2477 #define E800_GL_ACLEXT_FLGS_L1SEL2_3(_i) (0x00210078 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2478 #define E800_GL_ACLEXT_FLGS_L1SEL2_3_MAX_INDEX 2 2479 #define E800_GL_ACLEXT_FLGS_L1SEL2_3_FLS2_S 0 2480 #define E800_GL_ACLEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x1FF, 0) 2481 #define E800_GL_ACLEXT_FLGS_L1SEL2_3_FLS3_S 16 2482 #define E800_GL_ACLEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x1FF, 16) 2483 #define E800_GL_ACLEXT_FLGS_L1TBL(_i) (0x00210060 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2484 #define E800_GL_ACLEXT_FLGS_L1TBL_MAX_INDEX 2 2485 #define E800_GL_ACLEXT_FLGS_L1TBL_LSB_S 0 2486 #define E800_GL_ACLEXT_FLGS_L1TBL_LSB_M MAKEMASK(0xFFFF, 0) 2487 #define E800_GL_ACLEXT_FLGS_L1TBL_MSB_S 16 2488 #define E800_GL_ACLEXT_FLGS_L1TBL_MSB_M MAKEMASK(0xFFFF, 16) 2489 #define E800_GL_ACLEXT_FORCE_L1CDID(_i) (0x00210018 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2490 #define E800_GL_ACLEXT_FORCE_L1CDID_MAX_INDEX 2 2491 #define E800_GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_S 0 2492 #define E800_GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0) 2493 #define E800_GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31 2494 #define E800_GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31) 2495 #define E800_GL_ACLEXT_FORCE_PID(_i) (0x00210000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2496 #define E800_GL_ACLEXT_FORCE_PID_MAX_INDEX 2 2497 #define E800_GL_ACLEXT_FORCE_PID_STATIC_PID_S 0 2498 #define E800_GL_ACLEXT_FORCE_PID_STATIC_PID_M MAKEMASK(0xFFFF, 0) 2499 #define E800_GL_ACLEXT_FORCE_PID_STATIC_PID_EN_S 31 2500 #define E800_GL_ACLEXT_FORCE_PID_STATIC_PID_EN_M BIT(31) 2501 #define E800_GL_ACLEXT_K2N_L2ADDR(_i) (0x00210144 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2502 #define E800_GL_ACLEXT_K2N_L2ADDR_MAX_INDEX 2 2503 #define E800_GL_ACLEXT_K2N_L2ADDR_LINE_IDX_S 0 2504 #define E800_GL_ACLEXT_K2N_L2ADDR_LINE_IDX_M MAKEMASK(0x7F, 0) 2505 #define E800_GL_ACLEXT_K2N_L2ADDR_AUTO_INC_S 31 2506 #define E800_GL_ACLEXT_K2N_L2ADDR_AUTO_INC_M BIT(31) 2507 #define E800_GL_ACLEXT_K2N_L2DATA(_i) (0x00210150 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2508 #define E800_GL_ACLEXT_K2N_L2DATA_MAX_INDEX 2 2509 #define E800_GL_ACLEXT_K2N_L2DATA_DATA0_S 0 2510 #define E800_GL_ACLEXT_K2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0) 2511 #define E800_GL_ACLEXT_K2N_L2DATA_DATA1_S 8 2512 #define E800_GL_ACLEXT_K2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8) 2513 #define E800_GL_ACLEXT_K2N_L2DATA_DATA2_S 16 2514 #define E800_GL_ACLEXT_K2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16) 2515 #define E800_GL_ACLEXT_K2N_L2DATA_DATA3_S 24 2516 #define E800_GL_ACLEXT_K2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24) 2517 #define E800_GL_ACLEXT_L2_PMASK0(_i) (0x002100FC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2518 #define E800_GL_ACLEXT_L2_PMASK0_MAX_INDEX 2 2519 #define E800_GL_ACLEXT_L2_PMASK0_BITMASK_S 0 2520 #define E800_GL_ACLEXT_L2_PMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0) 2521 #define E800_GL_ACLEXT_L2_PMASK1(_i) (0x00210108 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2522 #define E800_GL_ACLEXT_L2_PMASK1_MAX_INDEX 2 2523 #define E800_GL_ACLEXT_L2_PMASK1_BITMASK_S 0 2524 #define E800_GL_ACLEXT_L2_PMASK1_BITMASK_M MAKEMASK(0xFFFF, 0) 2525 #define E800_GL_ACLEXT_L2_TMASK0(_i) (0x00210498 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2526 #define E800_GL_ACLEXT_L2_TMASK0_MAX_INDEX 2 2527 #define E800_GL_ACLEXT_L2_TMASK0_BITMASK_S 0 2528 #define E800_GL_ACLEXT_L2_TMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0) 2529 #define E800_GL_ACLEXT_L2_TMASK1(_i) (0x002104A4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2530 #define E800_GL_ACLEXT_L2_TMASK1_MAX_INDEX 2 2531 #define E800_GL_ACLEXT_L2_TMASK1_BITMASK_S 0 2532 #define E800_GL_ACLEXT_L2_TMASK1_BITMASK_M MAKEMASK(0xFF, 0) 2533 #define E800_GL_ACLEXT_L2BMP0_3(_i) (0x002100A8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2534 #define E800_GL_ACLEXT_L2BMP0_3_MAX_INDEX 2 2535 #define E800_GL_ACLEXT_L2BMP0_3_BMP0_S 0 2536 #define E800_GL_ACLEXT_L2BMP0_3_BMP0_M MAKEMASK(0xFF, 0) 2537 #define E800_GL_ACLEXT_L2BMP0_3_BMP1_S 8 2538 #define E800_GL_ACLEXT_L2BMP0_3_BMP1_M MAKEMASK(0xFF, 8) 2539 #define E800_GL_ACLEXT_L2BMP0_3_BMP2_S 16 2540 #define E800_GL_ACLEXT_L2BMP0_3_BMP2_M MAKEMASK(0xFF, 16) 2541 #define E800_GL_ACLEXT_L2BMP0_3_BMP3_S 24 2542 #define E800_GL_ACLEXT_L2BMP0_3_BMP3_M MAKEMASK(0xFF, 24) 2543 #define E800_GL_ACLEXT_L2BMP4_7(_i) (0x002100B4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2544 #define E800_GL_ACLEXT_L2BMP4_7_MAX_INDEX 2 2545 #define E800_GL_ACLEXT_L2BMP4_7_BMP4_S 0 2546 #define E800_GL_ACLEXT_L2BMP4_7_BMP4_M MAKEMASK(0xFF, 0) 2547 #define E800_GL_ACLEXT_L2BMP4_7_BMP5_S 8 2548 #define E800_GL_ACLEXT_L2BMP4_7_BMP5_M MAKEMASK(0xFF, 8) 2549 #define E800_GL_ACLEXT_L2BMP4_7_BMP6_S 16 2550 #define E800_GL_ACLEXT_L2BMP4_7_BMP6_M MAKEMASK(0xFF, 16) 2551 #define E800_GL_ACLEXT_L2BMP4_7_BMP7_S 24 2552 #define E800_GL_ACLEXT_L2BMP4_7_BMP7_M MAKEMASK(0xFF, 24) 2553 #define E800_GL_ACLEXT_L2PRTMOD(_i) (0x0021009C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2554 #define E800_GL_ACLEXT_L2PRTMOD_MAX_INDEX 2 2555 #define E800_GL_ACLEXT_L2PRTMOD_XLT1_S 0 2556 #define E800_GL_ACLEXT_L2PRTMOD_XLT1_M MAKEMASK(0x3, 0) 2557 #define E800_GL_ACLEXT_L2PRTMOD_XLT2_S 8 2558 #define E800_GL_ACLEXT_L2PRTMOD_XLT2_M MAKEMASK(0x3, 8) 2559 #define E800_GL_ACLEXT_N2N_L2ADDR(_i) (0x0021015C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2560 #define E800_GL_ACLEXT_N2N_L2ADDR_MAX_INDEX 2 2561 #define E800_GL_ACLEXT_N2N_L2ADDR_LINE_IDX_S 0 2562 #define E800_GL_ACLEXT_N2N_L2ADDR_LINE_IDX_M MAKEMASK(0x3F, 0) 2563 #define E800_GL_ACLEXT_N2N_L2ADDR_AUTO_INC_S 31 2564 #define E800_GL_ACLEXT_N2N_L2ADDR_AUTO_INC_M BIT(31) 2565 #define E800_GL_ACLEXT_N2N_L2DATA(_i) (0x00210168 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2566 #define E800_GL_ACLEXT_N2N_L2DATA_MAX_INDEX 2 2567 #define E800_GL_ACLEXT_N2N_L2DATA_DATA0_S 0 2568 #define E800_GL_ACLEXT_N2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0) 2569 #define E800_GL_ACLEXT_N2N_L2DATA_DATA1_S 8 2570 #define E800_GL_ACLEXT_N2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8) 2571 #define E800_GL_ACLEXT_N2N_L2DATA_DATA2_S 16 2572 #define E800_GL_ACLEXT_N2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16) 2573 #define E800_GL_ACLEXT_N2N_L2DATA_DATA3_S 24 2574 #define E800_GL_ACLEXT_N2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24) 2575 #define E800_GL_ACLEXT_P2P_L1ADDR(_i) (0x00210024 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2576 #define E800_GL_ACLEXT_P2P_L1ADDR_MAX_INDEX 2 2577 #define E800_GL_ACLEXT_P2P_L1ADDR_LINE_IDX_S 0 2578 #define E800_GL_ACLEXT_P2P_L1ADDR_LINE_IDX_M BIT(0) 2579 #define E800_GL_ACLEXT_P2P_L1ADDR_AUTO_INC_S 31 2580 #define E800_GL_ACLEXT_P2P_L1ADDR_AUTO_INC_M BIT(31) 2581 #define E800_GL_ACLEXT_P2P_L1DATA(_i) (0x00210030 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2582 #define E800_GL_ACLEXT_P2P_L1DATA_MAX_INDEX 2 2583 #define E800_GL_ACLEXT_P2P_L1DATA_DATA_S 0 2584 #define E800_GL_ACLEXT_P2P_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0) 2585 #define E800_GL_ACLEXT_PID_L2GKTYPE(_i) (0x002100F0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2586 #define E800_GL_ACLEXT_PID_L2GKTYPE_MAX_INDEX 2 2587 #define E800_GL_ACLEXT_PID_L2GKTYPE_PID_GKTYPE_S 0 2588 #define E800_GL_ACLEXT_PID_L2GKTYPE_PID_GKTYPE_M MAKEMASK(0x3, 0) 2589 #define E800_GL_ACLEXT_PLVL_SEL(_i) (0x0021000C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2590 #define E800_GL_ACLEXT_PLVL_SEL_MAX_INDEX 2 2591 #define E800_GL_ACLEXT_PLVL_SEL_PLVL_SEL_S 0 2592 #define E800_GL_ACLEXT_PLVL_SEL_PLVL_SEL_M BIT(0) 2593 #define E800_GL_ACLEXT_TCAM_L2ADDR(_i) (0x00210114 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2594 #define E800_GL_ACLEXT_TCAM_L2ADDR_MAX_INDEX 2 2595 #define E800_GL_ACLEXT_TCAM_L2ADDR_LINE_IDX_S 0 2596 #define E800_GL_ACLEXT_TCAM_L2ADDR_LINE_IDX_M MAKEMASK(0x3FF, 0) 2597 #define E800_GL_ACLEXT_TCAM_L2ADDR_AUTO_INC_S 31 2598 #define E800_GL_ACLEXT_TCAM_L2ADDR_AUTO_INC_M BIT(31) 2599 #define E800_GL_ACLEXT_TCAM_L2DATALSB(_i) (0x00210120 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2600 #define E800_GL_ACLEXT_TCAM_L2DATALSB_MAX_INDEX 2 2601 #define E800_GL_ACLEXT_TCAM_L2DATALSB_DATALSB_S 0 2602 #define E800_GL_ACLEXT_TCAM_L2DATALSB_DATALSB_M MAKEMASK(0xFFFFFFFF, 0) 2603 #define E800_GL_ACLEXT_TCAM_L2DATAMSB(_i) (0x0021012C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2604 #define E800_GL_ACLEXT_TCAM_L2DATAMSB_MAX_INDEX 2 2605 #define E800_GL_ACLEXT_TCAM_L2DATAMSB_DATAMSB_S 0 2606 #define E800_GL_ACLEXT_TCAM_L2DATAMSB_DATAMSB_M MAKEMASK(0xFF, 0) 2607 #define E800_GL_ACLEXT_XLT0_L1ADDR(_i) (0x0021003C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2608 #define E800_GL_ACLEXT_XLT0_L1ADDR_MAX_INDEX 2 2609 #define E800_GL_ACLEXT_XLT0_L1ADDR_LINE_IDX_S 0 2610 #define E800_GL_ACLEXT_XLT0_L1ADDR_LINE_IDX_M MAKEMASK(0xFF, 0) 2611 #define E800_GL_ACLEXT_XLT0_L1ADDR_AUTO_INC_S 31 2612 #define E800_GL_ACLEXT_XLT0_L1ADDR_AUTO_INC_M BIT(31) 2613 #define E800_GL_ACLEXT_XLT0_L1DATA(_i) (0x00210048 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2614 #define E800_GL_ACLEXT_XLT0_L1DATA_MAX_INDEX 2 2615 #define E800_GL_ACLEXT_XLT0_L1DATA_DATA_S 0 2616 #define E800_GL_ACLEXT_XLT0_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0) 2617 #define E800_GL_ACLEXT_XLT1_L2ADDR(_i) (0x002100C0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2618 #define E800_GL_ACLEXT_XLT1_L2ADDR_MAX_INDEX 2 2619 #define E800_GL_ACLEXT_XLT1_L2ADDR_LINE_IDX_S 0 2620 #define E800_GL_ACLEXT_XLT1_L2ADDR_LINE_IDX_M MAKEMASK(0x7FF, 0) 2621 #define E800_GL_ACLEXT_XLT1_L2ADDR_AUTO_INC_S 31 2622 #define E800_GL_ACLEXT_XLT1_L2ADDR_AUTO_INC_M BIT(31) 2623 #define E800_GL_ACLEXT_XLT1_L2DATA(_i) (0x002100CC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2624 #define E800_GL_ACLEXT_XLT1_L2DATA_MAX_INDEX 2 2625 #define E800_GL_ACLEXT_XLT1_L2DATA_DATA_S 0 2626 #define E800_GL_ACLEXT_XLT1_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0) 2627 #define E800_GL_ACLEXT_XLT2_L2ADDR(_i) (0x002100D8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2628 #define E800_GL_ACLEXT_XLT2_L2ADDR_MAX_INDEX 2 2629 #define E800_GL_ACLEXT_XLT2_L2ADDR_LINE_IDX_S 0 2630 #define E800_GL_ACLEXT_XLT2_L2ADDR_LINE_IDX_M MAKEMASK(0x1FF, 0) 2631 #define E800_GL_ACLEXT_XLT2_L2ADDR_AUTO_INC_S 31 2632 #define E800_GL_ACLEXT_XLT2_L2ADDR_AUTO_INC_M BIT(31) 2633 #define E800_GL_ACLEXT_XLT2_L2DATA(_i) (0x002100E4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2634 #define E800_GL_ACLEXT_XLT2_L2DATA_MAX_INDEX 2 2635 #define E800_GL_ACLEXT_XLT2_L2DATA_DATA_S 0 2636 #define E800_GL_ACLEXT_XLT2_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0) 2637 #define GL_PREEXT_CDMD_L1SEL(_i) (0x0020F054 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2638 #define GL_PREEXT_CDMD_L1SEL_MAX_INDEX 2 2639 #define GL_PREEXT_CDMD_L1SEL_RX_SEL_S 0 2640 #define GL_PREEXT_CDMD_L1SEL_RX_SEL_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PREEXT_CDMD_L1SEL_RX_SEL_M : E800_GL_PREEXT_CDMD_L1SEL_RX_SEL_M) 2641 #define E800_GL_PREEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x1F, 0) 2642 #define E830_GL_PREEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x3F, 0) 2643 #define GL_PREEXT_CDMD_L1SEL_TX_SEL_S 8 2644 #define GL_PREEXT_CDMD_L1SEL_TX_SEL_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PREEXT_CDMD_L1SEL_TX_SEL_M : E800_GL_PREEXT_CDMD_L1SEL_TX_SEL_M) 2645 #define E800_GL_PREEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x1F, 8) 2646 #define E830_GL_PREEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x3F, 8) 2647 #define GL_PREEXT_CDMD_L1SEL_AUX0_SEL_S 16 2648 #define GL_PREEXT_CDMD_L1SEL_AUX0_SEL_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PREEXT_CDMD_L1SEL_AUX0_SEL_M : E800_GL_PREEXT_CDMD_L1SEL_AUX0_SEL_M) 2649 #define E800_GL_PREEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x1F, 16) 2650 #define E830_GL_PREEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x3F, 16) 2651 #define GL_PREEXT_CDMD_L1SEL_AUX1_SEL_S 24 2652 #define GL_PREEXT_CDMD_L1SEL_AUX1_SEL_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PREEXT_CDMD_L1SEL_AUX1_SEL_M : E800_GL_PREEXT_CDMD_L1SEL_AUX1_SEL_M) 2653 #define E800_GL_PREEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x1F, 24) 2654 #define E830_GL_PREEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x3F, 24) 2655 #define GL_PREEXT_CDMD_L1SEL_BIDIR_ENA_S 30 2656 #define GL_PREEXT_CDMD_L1SEL_BIDIR_ENA_M MAKEMASK(0x3, 30) 2657 #define GL_PREEXT_CTLTBL_L2ADDR(_i) (0x0020F084 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2658 #define GL_PREEXT_CTLTBL_L2ADDR_MAX_INDEX 2 2659 #define GL_PREEXT_CTLTBL_L2ADDR_LINE_OFF_S 0 2660 #define GL_PREEXT_CTLTBL_L2ADDR_LINE_OFF_M MAKEMASK(0x7, 0) 2661 #define GL_PREEXT_CTLTBL_L2ADDR_LINE_IDX_S 8 2662 #define GL_PREEXT_CTLTBL_L2ADDR_LINE_IDX_M MAKEMASK(0x7, 8) 2663 #define GL_PREEXT_CTLTBL_L2ADDR_AUTO_INC_S 31 2664 #define GL_PREEXT_CTLTBL_L2ADDR_AUTO_INC_M BIT(31) 2665 #define GL_PREEXT_CTLTBL_L2DATA(_i) (0x0020F090 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2666 #define GL_PREEXT_CTLTBL_L2DATA_MAX_INDEX 2 2667 #define GL_PREEXT_CTLTBL_L2DATA_DATA_S 0 2668 #define GL_PREEXT_CTLTBL_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0) 2669 #define GL_PREEXT_DFLT_L2PRFL(_i) (0x0020F138 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2670 #define GL_PREEXT_DFLT_L2PRFL_MAX_INDEX 2 2671 #define GL_PREEXT_DFLT_L2PRFL_DFLT_PRFL_S 0 2672 #define GL_PREEXT_DFLT_L2PRFL_DFLT_PRFL_M MAKEMASK(0xFFFF, 0) 2673 #define GL_PREEXT_FLGS_L1SEL0_1(_i) (0x0020F06C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2674 #define GL_PREEXT_FLGS_L1SEL0_1_MAX_INDEX 2 2675 #define GL_PREEXT_FLGS_L1SEL0_1_FLS0_S 0 2676 #define GL_PREEXT_FLGS_L1SEL0_1_FLS0_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PREEXT_FLGS_L1SEL0_1_FLS0_M : E800_GL_PREEXT_FLGS_L1SEL0_1_FLS0_M) 2677 #define E800_GL_PREEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x1FF, 0) 2678 #define E830_GL_PREEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x3FF, 0) 2679 #define GL_PREEXT_FLGS_L1SEL0_1_FLS1_S 16 2680 #define GL_PREEXT_FLGS_L1SEL0_1_FLS1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PREEXT_FLGS_L1SEL0_1_FLS1_M : E800_GL_PREEXT_FLGS_L1SEL0_1_FLS1_M) 2681 #define E800_GL_PREEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x1FF, 16) 2682 #define E830_GL_PREEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x3FF, 16) 2683 #define GL_PREEXT_FLGS_L1SEL2_3(_i) (0x0020F078 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2684 #define GL_PREEXT_FLGS_L1SEL2_3_MAX_INDEX 2 2685 #define GL_PREEXT_FLGS_L1SEL2_3_FLS2_S 0 2686 #define GL_PREEXT_FLGS_L1SEL2_3_FLS2_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PREEXT_FLGS_L1SEL2_3_FLS2_M : E800_GL_PREEXT_FLGS_L1SEL2_3_FLS2_M) 2687 #define E800_GL_PREEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x1FF, 0) 2688 #define E830_GL_PREEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x3FF, 0) 2689 #define GL_PREEXT_FLGS_L1SEL2_3_FLS3_S 16 2690 #define GL_PREEXT_FLGS_L1SEL2_3_FLS3_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PREEXT_FLGS_L1SEL2_3_FLS3_M : E800_GL_PREEXT_FLGS_L1SEL2_3_FLS3_M) 2691 #define E800_GL_PREEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x1FF, 16) 2692 #define E830_GL_PREEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x3FF, 16) 2693 #define GL_PREEXT_FLGS_L1TBL(_i) (0x0020F060 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2694 #define GL_PREEXT_FLGS_L1TBL_MAX_INDEX 2 2695 #define GL_PREEXT_FLGS_L1TBL_LSB_S 0 2696 #define GL_PREEXT_FLGS_L1TBL_LSB_M MAKEMASK(0xFFFF, 0) 2697 #define GL_PREEXT_FLGS_L1TBL_MSB_S 16 2698 #define GL_PREEXT_FLGS_L1TBL_MSB_M MAKEMASK(0xFFFF, 16) 2699 #define GL_PREEXT_FORCE_L1CDID(_i) (0x0020F018 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2700 #define GL_PREEXT_FORCE_L1CDID_MAX_INDEX 2 2701 #define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_S 0 2702 #define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0) 2703 #define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31 2704 #define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31) 2705 #define GL_PREEXT_FORCE_PID(_i) (0x0020F000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2706 #define GL_PREEXT_FORCE_PID_MAX_INDEX 2 2707 #define GL_PREEXT_FORCE_PID_STATIC_PID_S 0 2708 #define GL_PREEXT_FORCE_PID_STATIC_PID_M MAKEMASK(0xFFFF, 0) 2709 #define GL_PREEXT_FORCE_PID_STATIC_PID_EN_S 31 2710 #define GL_PREEXT_FORCE_PID_STATIC_PID_EN_M BIT(31) 2711 #define GL_PREEXT_K2N_L2ADDR(_i) (0x0020F144 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2712 #define GL_PREEXT_K2N_L2ADDR_MAX_INDEX 2 2713 #define GL_PREEXT_K2N_L2ADDR_LINE_IDX_S 0 2714 #define GL_PREEXT_K2N_L2ADDR_LINE_IDX_M MAKEMASK(0x7F, 0) 2715 #define GL_PREEXT_K2N_L2ADDR_AUTO_INC_S 31 2716 #define GL_PREEXT_K2N_L2ADDR_AUTO_INC_M BIT(31) 2717 #define GL_PREEXT_K2N_L2DATA(_i) (0x0020F150 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2718 #define GL_PREEXT_K2N_L2DATA_MAX_INDEX 2 2719 #define GL_PREEXT_K2N_L2DATA_DATA0_S 0 2720 #define GL_PREEXT_K2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0) 2721 #define GL_PREEXT_K2N_L2DATA_DATA1_S 8 2722 #define GL_PREEXT_K2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8) 2723 #define GL_PREEXT_K2N_L2DATA_DATA2_S 16 2724 #define GL_PREEXT_K2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16) 2725 #define GL_PREEXT_K2N_L2DATA_DATA3_S 24 2726 #define GL_PREEXT_K2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24) 2727 #define GL_PREEXT_L2_PMASK0(_i) (0x0020F0FC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2728 #define GL_PREEXT_L2_PMASK0_MAX_INDEX 2 2729 #define GL_PREEXT_L2_PMASK0_BITMASK_S 0 2730 #define GL_PREEXT_L2_PMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0) 2731 #define GL_PREEXT_L2_PMASK1(_i) (0x0020F108 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2732 #define GL_PREEXT_L2_PMASK1_MAX_INDEX 2 2733 #define GL_PREEXT_L2_PMASK1_BITMASK_S 0 2734 #define GL_PREEXT_L2_PMASK1_BITMASK_M MAKEMASK(0xFFFF, 0) 2735 #define GL_PREEXT_L2_TMASK0(_i) (0x0020F498 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2736 #define GL_PREEXT_L2_TMASK0_MAX_INDEX 2 2737 #define GL_PREEXT_L2_TMASK0_BITMASK_S 0 2738 #define GL_PREEXT_L2_TMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0) 2739 #define GL_PREEXT_L2_TMASK1(_i) (0x0020F4A4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2740 #define GL_PREEXT_L2_TMASK1_MAX_INDEX 2 2741 #define GL_PREEXT_L2_TMASK1_BITMASK_S 0 2742 #define GL_PREEXT_L2_TMASK1_BITMASK_M MAKEMASK(0xFF, 0) 2743 #define GL_PREEXT_L2BMP0_3(_i) (0x0020F0A8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2744 #define GL_PREEXT_L2BMP0_3_MAX_INDEX 2 2745 #define GL_PREEXT_L2BMP0_3_BMP0_S 0 2746 #define GL_PREEXT_L2BMP0_3_BMP0_M MAKEMASK(0xFF, 0) 2747 #define GL_PREEXT_L2BMP0_3_BMP1_S 8 2748 #define GL_PREEXT_L2BMP0_3_BMP1_M MAKEMASK(0xFF, 8) 2749 #define GL_PREEXT_L2BMP0_3_BMP2_S 16 2750 #define GL_PREEXT_L2BMP0_3_BMP2_M MAKEMASK(0xFF, 16) 2751 #define GL_PREEXT_L2BMP0_3_BMP3_S 24 2752 #define GL_PREEXT_L2BMP0_3_BMP3_M MAKEMASK(0xFF, 24) 2753 #define GL_PREEXT_L2BMP4_7(_i) (0x0020F0B4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2754 #define GL_PREEXT_L2BMP4_7_MAX_INDEX 2 2755 #define GL_PREEXT_L2BMP4_7_BMP4_S 0 2756 #define GL_PREEXT_L2BMP4_7_BMP4_M MAKEMASK(0xFF, 0) 2757 #define GL_PREEXT_L2BMP4_7_BMP5_S 8 2758 #define GL_PREEXT_L2BMP4_7_BMP5_M MAKEMASK(0xFF, 8) 2759 #define GL_PREEXT_L2BMP4_7_BMP6_S 16 2760 #define GL_PREEXT_L2BMP4_7_BMP6_M MAKEMASK(0xFF, 16) 2761 #define GL_PREEXT_L2BMP4_7_BMP7_S 24 2762 #define GL_PREEXT_L2BMP4_7_BMP7_M MAKEMASK(0xFF, 24) 2763 #define GL_PREEXT_L2PRTMOD(_i) (0x0020F09C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2764 #define GL_PREEXT_L2PRTMOD_MAX_INDEX 2 2765 #define GL_PREEXT_L2PRTMOD_XLT1_S 0 2766 #define GL_PREEXT_L2PRTMOD_XLT1_M MAKEMASK(0x3, 0) 2767 #define GL_PREEXT_L2PRTMOD_XLT2_S 8 2768 #define GL_PREEXT_L2PRTMOD_XLT2_M MAKEMASK(0x3, 8) 2769 #define GL_PREEXT_N2N_L2ADDR(_i) (0x0020F15C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2770 #define GL_PREEXT_N2N_L2ADDR_MAX_INDEX 2 2771 #define GL_PREEXT_N2N_L2ADDR_LINE_IDX_S 0 2772 #define GL_PREEXT_N2N_L2ADDR_LINE_IDX_M MAKEMASK(0x3F, 0) 2773 #define GL_PREEXT_N2N_L2ADDR_AUTO_INC_S 31 2774 #define GL_PREEXT_N2N_L2ADDR_AUTO_INC_M BIT(31) 2775 #define GL_PREEXT_N2N_L2DATA(_i) (0x0020F168 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2776 #define GL_PREEXT_N2N_L2DATA_MAX_INDEX 2 2777 #define GL_PREEXT_N2N_L2DATA_DATA0_S 0 2778 #define GL_PREEXT_N2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0) 2779 #define GL_PREEXT_N2N_L2DATA_DATA1_S 8 2780 #define GL_PREEXT_N2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8) 2781 #define GL_PREEXT_N2N_L2DATA_DATA2_S 16 2782 #define GL_PREEXT_N2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16) 2783 #define GL_PREEXT_N2N_L2DATA_DATA3_S 24 2784 #define GL_PREEXT_N2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24) 2785 #define GL_PREEXT_P2P_L1ADDR(_i) (0x0020F024 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2786 #define GL_PREEXT_P2P_L1ADDR_MAX_INDEX 2 2787 #define GL_PREEXT_P2P_L1ADDR_LINE_IDX_S 0 2788 #define GL_PREEXT_P2P_L1ADDR_LINE_IDX_M BIT(0) 2789 #define GL_PREEXT_P2P_L1ADDR_AUTO_INC_S 31 2790 #define GL_PREEXT_P2P_L1ADDR_AUTO_INC_M BIT(31) 2791 #define GL_PREEXT_P2P_L1DATA(_i) (0x0020F030 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2792 #define GL_PREEXT_P2P_L1DATA_MAX_INDEX 2 2793 #define GL_PREEXT_P2P_L1DATA_DATA_S 0 2794 #define GL_PREEXT_P2P_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0) 2795 #define GL_PREEXT_PID_L2GKTYPE(_i) (0x0020F0F0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2796 #define GL_PREEXT_PID_L2GKTYPE_MAX_INDEX 2 2797 #define GL_PREEXT_PID_L2GKTYPE_PID_GKTYPE_S 0 2798 #define GL_PREEXT_PID_L2GKTYPE_PID_GKTYPE_M MAKEMASK(0x3, 0) 2799 #define GL_PREEXT_PLVL_SEL(_i) (0x0020F00C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2800 #define GL_PREEXT_PLVL_SEL_MAX_INDEX 2 2801 #define GL_PREEXT_PLVL_SEL_PLVL_SEL_S 0 2802 #define GL_PREEXT_PLVL_SEL_PLVL_SEL_M BIT(0) 2803 #define GL_PREEXT_TCAM_L2ADDR(_i) (0x0020F114 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2804 #define GL_PREEXT_TCAM_L2ADDR_MAX_INDEX 2 2805 #define GL_PREEXT_TCAM_L2ADDR_LINE_IDX_S 0 2806 #define GL_PREEXT_TCAM_L2ADDR_LINE_IDX_M MAKEMASK(0x3FF, 0) 2807 #define GL_PREEXT_TCAM_L2ADDR_AUTO_INC_S 31 2808 #define GL_PREEXT_TCAM_L2ADDR_AUTO_INC_M BIT(31) 2809 #define GL_PREEXT_TCAM_L2DATALSB(_i) (0x0020F120 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2810 #define GL_PREEXT_TCAM_L2DATALSB_MAX_INDEX 2 2811 #define GL_PREEXT_TCAM_L2DATALSB_DATALSB_S 0 2812 #define GL_PREEXT_TCAM_L2DATALSB_DATALSB_M MAKEMASK(0xFFFFFFFF, 0) 2813 #define GL_PREEXT_TCAM_L2DATAMSB(_i) (0x0020F12C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2814 #define GL_PREEXT_TCAM_L2DATAMSB_MAX_INDEX 2 2815 #define GL_PREEXT_TCAM_L2DATAMSB_DATAMSB_S 0 2816 #define GL_PREEXT_TCAM_L2DATAMSB_DATAMSB_M MAKEMASK(0xFF, 0) 2817 #define GL_PREEXT_XLT0_L1ADDR(_i) (0x0020F03C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2818 #define GL_PREEXT_XLT0_L1ADDR_MAX_INDEX 2 2819 #define GL_PREEXT_XLT0_L1ADDR_LINE_IDX_S 0 2820 #define GL_PREEXT_XLT0_L1ADDR_LINE_IDX_M MAKEMASK(0xFF, 0) 2821 #define GL_PREEXT_XLT0_L1ADDR_AUTO_INC_S 31 2822 #define GL_PREEXT_XLT0_L1ADDR_AUTO_INC_M BIT(31) 2823 #define GL_PREEXT_XLT0_L1DATA(_i) (0x0020F048 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2824 #define GL_PREEXT_XLT0_L1DATA_MAX_INDEX 2 2825 #define GL_PREEXT_XLT0_L1DATA_DATA_S 0 2826 #define GL_PREEXT_XLT0_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0) 2827 #define GL_PREEXT_XLT1_L2ADDR(_i) (0x0020F0C0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2828 #define GL_PREEXT_XLT1_L2ADDR_MAX_INDEX 2 2829 #define GL_PREEXT_XLT1_L2ADDR_LINE_IDX_S 0 2830 #define GL_PREEXT_XLT1_L2ADDR_LINE_IDX_M MAKEMASK(0x7FF, 0) 2831 #define GL_PREEXT_XLT1_L2ADDR_AUTO_INC_S 31 2832 #define GL_PREEXT_XLT1_L2ADDR_AUTO_INC_M BIT(31) 2833 #define GL_PREEXT_XLT1_L2DATA(_i) (0x0020F0CC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2834 #define GL_PREEXT_XLT1_L2DATA_MAX_INDEX 2 2835 #define GL_PREEXT_XLT1_L2DATA_DATA_S 0 2836 #define GL_PREEXT_XLT1_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0) 2837 #define GL_PREEXT_XLT2_L2ADDR(_i) (0x0020F0D8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2838 #define GL_PREEXT_XLT2_L2ADDR_MAX_INDEX 2 2839 #define GL_PREEXT_XLT2_L2ADDR_LINE_IDX_S 0 2840 #define GL_PREEXT_XLT2_L2ADDR_LINE_IDX_M MAKEMASK(0x1FF, 0) 2841 #define GL_PREEXT_XLT2_L2ADDR_AUTO_INC_S 31 2842 #define GL_PREEXT_XLT2_L2ADDR_AUTO_INC_M BIT(31) 2843 #define GL_PREEXT_XLT2_L2DATA(_i) (0x0020F0E4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2844 #define GL_PREEXT_XLT2_L2DATA_MAX_INDEX 2 2845 #define GL_PREEXT_XLT2_L2DATA_DATA_S 0 2846 #define GL_PREEXT_XLT2_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0) 2847 #define GL_PSTEXT_CDMD_L1SEL(_i) (0x0020E054 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2848 #define GL_PSTEXT_CDMD_L1SEL_MAX_INDEX 2 2849 #define GL_PSTEXT_CDMD_L1SEL_RX_SEL_S 0 2850 #define GL_PSTEXT_CDMD_L1SEL_RX_SEL_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PSTEXT_CDMD_L1SEL_RX_SEL_M : E800_GL_PSTEXT_CDMD_L1SEL_RX_SEL_M) 2851 #define E800_GL_PSTEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x1F, 0) 2852 #define E830_GL_PSTEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x3F, 0) 2853 #define GL_PSTEXT_CDMD_L1SEL_TX_SEL_S 8 2854 #define GL_PSTEXT_CDMD_L1SEL_TX_SEL_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PSTEXT_CDMD_L1SEL_TX_SEL_M : E800_GL_PSTEXT_CDMD_L1SEL_TX_SEL_M) 2855 #define E800_GL_PSTEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x1F, 8) 2856 #define E830_GL_PSTEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x3F, 8) 2857 #define GL_PSTEXT_CDMD_L1SEL_AUX0_SEL_S 16 2858 #define GL_PSTEXT_CDMD_L1SEL_AUX0_SEL_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PSTEXT_CDMD_L1SEL_AUX0_SEL_M : E800_GL_PSTEXT_CDMD_L1SEL_AUX0_SEL_M) 2859 #define E800_GL_PSTEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x1F, 16) 2860 #define E830_GL_PSTEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x3F, 16) 2861 #define GL_PSTEXT_CDMD_L1SEL_AUX1_SEL_S 24 2862 #define GL_PSTEXT_CDMD_L1SEL_AUX1_SEL_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PSTEXT_CDMD_L1SEL_AUX1_SEL_M : E800_GL_PSTEXT_CDMD_L1SEL_AUX1_SEL_M) 2863 #define E800_GL_PSTEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x1F, 24) 2864 #define E830_GL_PSTEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x3F, 24) 2865 #define GL_PSTEXT_CDMD_L1SEL_BIDIR_ENA_S 30 2866 #define GL_PSTEXT_CDMD_L1SEL_BIDIR_ENA_M MAKEMASK(0x3, 30) 2867 #define GL_PSTEXT_CTLTBL_L2ADDR(_i) (0x0020E084 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2868 #define GL_PSTEXT_CTLTBL_L2ADDR_MAX_INDEX 2 2869 #define GL_PSTEXT_CTLTBL_L2ADDR_LINE_OFF_S 0 2870 #define GL_PSTEXT_CTLTBL_L2ADDR_LINE_OFF_M MAKEMASK(0x7, 0) 2871 #define GL_PSTEXT_CTLTBL_L2ADDR_LINE_IDX_S 8 2872 #define GL_PSTEXT_CTLTBL_L2ADDR_LINE_IDX_M MAKEMASK(0x7, 8) 2873 #define GL_PSTEXT_CTLTBL_L2ADDR_AUTO_INC_S 31 2874 #define GL_PSTEXT_CTLTBL_L2ADDR_AUTO_INC_M BIT(31) 2875 #define GL_PSTEXT_CTLTBL_L2DATA(_i) (0x0020E090 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2876 #define GL_PSTEXT_CTLTBL_L2DATA_MAX_INDEX 2 2877 #define GL_PSTEXT_CTLTBL_L2DATA_DATA_S 0 2878 #define GL_PSTEXT_CTLTBL_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0) 2879 #define GL_PSTEXT_DFLT_L2PRFL(_i) (0x0020E138 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2880 #define GL_PSTEXT_DFLT_L2PRFL_MAX_INDEX 2 2881 #define GL_PSTEXT_DFLT_L2PRFL_DFLT_PRFL_S 0 2882 #define GL_PSTEXT_DFLT_L2PRFL_DFLT_PRFL_M MAKEMASK(0xFFFF, 0) 2883 #define GL_PSTEXT_FL15_BMPLSB(_i) (0x0020E480 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2884 #define GL_PSTEXT_FL15_BMPLSB_MAX_INDEX 2 2885 #define GL_PSTEXT_FL15_BMPLSB_BMPLSB_S 0 2886 #define GL_PSTEXT_FL15_BMPLSB_BMPLSB_M MAKEMASK(0xFFFFFFFF, 0) 2887 #define GL_PSTEXT_FL15_BMPMSB(_i) (0x0020E48C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2888 #define GL_PSTEXT_FL15_BMPMSB_MAX_INDEX 2 2889 #define GL_PSTEXT_FL15_BMPMSB_BMPMSB_S 0 2890 #define GL_PSTEXT_FL15_BMPMSB_BMPMSB_M MAKEMASK(0xFFFFFFFF, 0) 2891 #define GL_PSTEXT_FLGS_L1SEL0_1(_i) (0x0020E06C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2892 #define GL_PSTEXT_FLGS_L1SEL0_1_MAX_INDEX 2 2893 #define GL_PSTEXT_FLGS_L1SEL0_1_FLS0_S 0 2894 #define GL_PSTEXT_FLGS_L1SEL0_1_FLS0_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PSTEXT_FLGS_L1SEL0_1_FLS0_M : E800_GL_PSTEXT_FLGS_L1SEL0_1_FLS0_M) 2895 #define E800_GL_PSTEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x1FF, 0) 2896 #define E830_GL_PSTEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x3FF, 0) 2897 #define GL_PSTEXT_FLGS_L1SEL0_1_FLS1_S 16 2898 #define GL_PSTEXT_FLGS_L1SEL0_1_FLS1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PSTEXT_FLGS_L1SEL0_1_FLS1_M : E800_GL_PSTEXT_FLGS_L1SEL0_1_FLS1_M) 2899 #define E800_GL_PSTEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x1FF, 16) 2900 #define E830_GL_PSTEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x3FF, 16) 2901 #define GL_PSTEXT_FLGS_L1SEL2_3(_i) (0x0020E078 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2902 #define GL_PSTEXT_FLGS_L1SEL2_3_MAX_INDEX 2 2903 #define GL_PSTEXT_FLGS_L1SEL2_3_FLS2_S 0 2904 #define GL_PSTEXT_FLGS_L1SEL2_3_FLS2_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PSTEXT_FLGS_L1SEL2_3_FLS2_M : E800_GL_PSTEXT_FLGS_L1SEL2_3_FLS2_M) 2905 #define E800_GL_PSTEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x1FF, 0) 2906 #define E830_GL_PSTEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x3FF, 0) 2907 #define GL_PSTEXT_FLGS_L1SEL2_3_FLS3_S 16 2908 #define GL_PSTEXT_FLGS_L1SEL2_3_FLS3_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PSTEXT_FLGS_L1SEL2_3_FLS3_M : E800_GL_PSTEXT_FLGS_L1SEL2_3_FLS3_M) 2909 #define E800_GL_PSTEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x1FF, 16) 2910 #define E830_GL_PSTEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x3FF, 16) 2911 #define GL_PSTEXT_FLGS_L1TBL(_i) (0x0020E060 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2912 #define GL_PSTEXT_FLGS_L1TBL_MAX_INDEX 2 2913 #define GL_PSTEXT_FLGS_L1TBL_LSB_S 0 2914 #define GL_PSTEXT_FLGS_L1TBL_LSB_M MAKEMASK(0xFFFF, 0) 2915 #define GL_PSTEXT_FLGS_L1TBL_MSB_S 16 2916 #define GL_PSTEXT_FLGS_L1TBL_MSB_M MAKEMASK(0xFFFF, 16) 2917 #define GL_PSTEXT_FORCE_L1CDID(_i) (0x0020E018 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2918 #define GL_PSTEXT_FORCE_L1CDID_MAX_INDEX 2 2919 #define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_S 0 2920 #define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0) 2921 #define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31 2922 #define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31) 2923 #define GL_PSTEXT_FORCE_PID(_i) (0x0020E000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2924 #define GL_PSTEXT_FORCE_PID_MAX_INDEX 2 2925 #define GL_PSTEXT_FORCE_PID_STATIC_PID_S 0 2926 #define GL_PSTEXT_FORCE_PID_STATIC_PID_M MAKEMASK(0xFFFF, 0) 2927 #define GL_PSTEXT_FORCE_PID_STATIC_PID_EN_S 31 2928 #define GL_PSTEXT_FORCE_PID_STATIC_PID_EN_M BIT(31) 2929 #define GL_PSTEXT_K2N_L2ADDR(_i) (0x0020E144 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2930 #define GL_PSTEXT_K2N_L2ADDR_MAX_INDEX 2 2931 #define GL_PSTEXT_K2N_L2ADDR_LINE_IDX_S 0 2932 #define GL_PSTEXT_K2N_L2ADDR_LINE_IDX_M MAKEMASK(0x7F, 0) 2933 #define GL_PSTEXT_K2N_L2ADDR_AUTO_INC_S 31 2934 #define GL_PSTEXT_K2N_L2ADDR_AUTO_INC_M BIT(31) 2935 #define GL_PSTEXT_K2N_L2DATA(_i) (0x0020E150 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2936 #define GL_PSTEXT_K2N_L2DATA_MAX_INDEX 2 2937 #define GL_PSTEXT_K2N_L2DATA_DATA0_S 0 2938 #define GL_PSTEXT_K2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0) 2939 #define GL_PSTEXT_K2N_L2DATA_DATA1_S 8 2940 #define GL_PSTEXT_K2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8) 2941 #define GL_PSTEXT_K2N_L2DATA_DATA2_S 16 2942 #define GL_PSTEXT_K2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16) 2943 #define GL_PSTEXT_K2N_L2DATA_DATA3_S 24 2944 #define GL_PSTEXT_K2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24) 2945 #define GL_PSTEXT_L2_PMASK0(_i) (0x0020E0FC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2946 #define GL_PSTEXT_L2_PMASK0_MAX_INDEX 2 2947 #define GL_PSTEXT_L2_PMASK0_BITMASK_S 0 2948 #define GL_PSTEXT_L2_PMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0) 2949 #define GL_PSTEXT_L2_PMASK1(_i) (0x0020E108 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2950 #define GL_PSTEXT_L2_PMASK1_MAX_INDEX 2 2951 #define GL_PSTEXT_L2_PMASK1_BITMASK_S 0 2952 #define GL_PSTEXT_L2_PMASK1_BITMASK_M MAKEMASK(0xFFFF, 0) 2953 #define GL_PSTEXT_L2_TMASK0(_i) (0x0020E498 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2954 #define GL_PSTEXT_L2_TMASK0_MAX_INDEX 2 2955 #define GL_PSTEXT_L2_TMASK0_BITMASK_S 0 2956 #define GL_PSTEXT_L2_TMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0) 2957 #define GL_PSTEXT_L2_TMASK1(_i) (0x0020E4A4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2958 #define GL_PSTEXT_L2_TMASK1_MAX_INDEX 2 2959 #define GL_PSTEXT_L2_TMASK1_BITMASK_S 0 2960 #define GL_PSTEXT_L2_TMASK1_BITMASK_M MAKEMASK(0xFF, 0) 2961 #define GL_PSTEXT_L2PRTMOD(_i) (0x0020E09C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2962 #define GL_PSTEXT_L2PRTMOD_MAX_INDEX 2 2963 #define GL_PSTEXT_L2PRTMOD_XLT1_S 0 2964 #define GL_PSTEXT_L2PRTMOD_XLT1_M MAKEMASK(0x3, 0) 2965 #define GL_PSTEXT_L2PRTMOD_XLT2_S 8 2966 #define GL_PSTEXT_L2PRTMOD_XLT2_M MAKEMASK(0x3, 8) 2967 #define GL_PSTEXT_N2N_L2ADDR(_i) (0x0020E15C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2968 #define GL_PSTEXT_N2N_L2ADDR_MAX_INDEX 2 2969 #define GL_PSTEXT_N2N_L2ADDR_LINE_IDX_S 0 2970 #define GL_PSTEXT_N2N_L2ADDR_LINE_IDX_M MAKEMASK(0x3F, 0) 2971 #define GL_PSTEXT_N2N_L2ADDR_AUTO_INC_S 31 2972 #define GL_PSTEXT_N2N_L2ADDR_AUTO_INC_M BIT(31) 2973 #define GL_PSTEXT_N2N_L2DATA(_i) (0x0020E168 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2974 #define GL_PSTEXT_N2N_L2DATA_MAX_INDEX 2 2975 #define GL_PSTEXT_N2N_L2DATA_DATA0_S 0 2976 #define GL_PSTEXT_N2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0) 2977 #define GL_PSTEXT_N2N_L2DATA_DATA1_S 8 2978 #define GL_PSTEXT_N2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8) 2979 #define GL_PSTEXT_N2N_L2DATA_DATA2_S 16 2980 #define GL_PSTEXT_N2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16) 2981 #define GL_PSTEXT_N2N_L2DATA_DATA3_S 24 2982 #define GL_PSTEXT_N2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24) 2983 #define GL_PSTEXT_P2P_L1ADDR(_i) (0x0020E024 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2984 #define GL_PSTEXT_P2P_L1ADDR_MAX_INDEX 2 2985 #define GL_PSTEXT_P2P_L1ADDR_LINE_IDX_S 0 2986 #define GL_PSTEXT_P2P_L1ADDR_LINE_IDX_M BIT(0) 2987 #define GL_PSTEXT_P2P_L1ADDR_AUTO_INC_S 31 2988 #define GL_PSTEXT_P2P_L1ADDR_AUTO_INC_M BIT(31) 2989 #define GL_PSTEXT_P2P_L1DATA(_i) (0x0020E030 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2990 #define GL_PSTEXT_P2P_L1DATA_MAX_INDEX 2 2991 #define GL_PSTEXT_P2P_L1DATA_DATA_S 0 2992 #define GL_PSTEXT_P2P_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0) 2993 #define GL_PSTEXT_PID_L2GKTYPE(_i) (0x0020E0F0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2994 #define GL_PSTEXT_PID_L2GKTYPE_MAX_INDEX 2 2995 #define GL_PSTEXT_PID_L2GKTYPE_PID_GKTYPE_S 0 2996 #define GL_PSTEXT_PID_L2GKTYPE_PID_GKTYPE_M MAKEMASK(0x3, 0) 2997 #define GL_PSTEXT_PLVL_SEL(_i) (0x0020E00C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 2998 #define GL_PSTEXT_PLVL_SEL_MAX_INDEX 2 2999 #define GL_PSTEXT_PLVL_SEL_PLVL_SEL_S 0 3000 #define GL_PSTEXT_PLVL_SEL_PLVL_SEL_M BIT(0) 3001 #define GL_PSTEXT_PRFLM_CTRL(_i) (0x0020E474 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 3002 #define GL_PSTEXT_PRFLM_CTRL_MAX_INDEX 2 3003 #define GL_PSTEXT_PRFLM_CTRL_PRFL_IDX_S 0 3004 #define GL_PSTEXT_PRFLM_CTRL_PRFL_IDX_M MAKEMASK(0xFF, 0) 3005 #define GL_PSTEXT_PRFLM_CTRL_RD_REQ_S 30 3006 #define GL_PSTEXT_PRFLM_CTRL_RD_REQ_M BIT(30) 3007 #define GL_PSTEXT_PRFLM_CTRL_WR_REQ_S 31 3008 #define GL_PSTEXT_PRFLM_CTRL_WR_REQ_M BIT(31) 3009 #define GL_PSTEXT_PRFLM_DATA_0(_i) (0x0020E174 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 3010 #define GL_PSTEXT_PRFLM_DATA_0_MAX_INDEX 63 3011 #define GL_PSTEXT_PRFLM_DATA_0_PROT_S 0 3012 #define GL_PSTEXT_PRFLM_DATA_0_PROT_M MAKEMASK(0xFF, 0) 3013 #define GL_PSTEXT_PRFLM_DATA_0_OFF_S 16 3014 #define GL_PSTEXT_PRFLM_DATA_0_OFF_M MAKEMASK(0x1FF, 16) 3015 #define GL_PSTEXT_PRFLM_DATA_1(_i) (0x0020E274 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 3016 #define GL_PSTEXT_PRFLM_DATA_1_MAX_INDEX 63 3017 #define GL_PSTEXT_PRFLM_DATA_1_PROT_S 0 3018 #define GL_PSTEXT_PRFLM_DATA_1_PROT_M MAKEMASK(0xFF, 0) 3019 #define GL_PSTEXT_PRFLM_DATA_1_OFF_S 16 3020 #define GL_PSTEXT_PRFLM_DATA_1_OFF_M MAKEMASK(0x1FF, 16) 3021 #define GL_PSTEXT_PRFLM_DATA_2(_i) (0x0020E374 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 3022 #define GL_PSTEXT_PRFLM_DATA_2_MAX_INDEX 63 3023 #define GL_PSTEXT_PRFLM_DATA_2_PROT_S 0 3024 #define GL_PSTEXT_PRFLM_DATA_2_PROT_M MAKEMASK(0xFF, 0) 3025 #define GL_PSTEXT_PRFLM_DATA_2_OFF_S 16 3026 #define GL_PSTEXT_PRFLM_DATA_2_OFF_M MAKEMASK(0x1FF, 16) 3027 #define GL_PSTEXT_TCAM_L2ADDR(_i) (0x0020E114 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 3028 #define GL_PSTEXT_TCAM_L2ADDR_MAX_INDEX 2 3029 #define GL_PSTEXT_TCAM_L2ADDR_LINE_IDX_S 0 3030 #define GL_PSTEXT_TCAM_L2ADDR_LINE_IDX_M MAKEMASK(0x3FF, 0) 3031 #define GL_PSTEXT_TCAM_L2ADDR_AUTO_INC_S 31 3032 #define GL_PSTEXT_TCAM_L2ADDR_AUTO_INC_M BIT(31) 3033 #define GL_PSTEXT_TCAM_L2DATALSB(_i) (0x0020E120 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 3034 #define GL_PSTEXT_TCAM_L2DATALSB_MAX_INDEX 2 3035 #define GL_PSTEXT_TCAM_L2DATALSB_DATALSB_S 0 3036 #define GL_PSTEXT_TCAM_L2DATALSB_DATALSB_M MAKEMASK(0xFFFFFFFF, 0) 3037 #define GL_PSTEXT_TCAM_L2DATAMSB(_i) (0x0020E12C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 3038 #define GL_PSTEXT_TCAM_L2DATAMSB_MAX_INDEX 2 3039 #define GL_PSTEXT_TCAM_L2DATAMSB_DATAMSB_S 0 3040 #define GL_PSTEXT_TCAM_L2DATAMSB_DATAMSB_M MAKEMASK(0xFF, 0) 3041 #define GL_PSTEXT_XLT0_L1ADDR(_i) (0x0020E03C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 3042 #define GL_PSTEXT_XLT0_L1ADDR_MAX_INDEX 2 3043 #define GL_PSTEXT_XLT0_L1ADDR_LINE_IDX_S 0 3044 #define GL_PSTEXT_XLT0_L1ADDR_LINE_IDX_M MAKEMASK(0xFF, 0) 3045 #define GL_PSTEXT_XLT0_L1ADDR_AUTO_INC_S 31 3046 #define GL_PSTEXT_XLT0_L1ADDR_AUTO_INC_M BIT(31) 3047 #define GL_PSTEXT_XLT0_L1DATA(_i) (0x0020E048 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 3048 #define GL_PSTEXT_XLT0_L1DATA_MAX_INDEX 2 3049 #define GL_PSTEXT_XLT0_L1DATA_DATA_S 0 3050 #define GL_PSTEXT_XLT0_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0) 3051 #define GL_PSTEXT_XLT1_L2ADDR(_i) (0x0020E0C0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 3052 #define GL_PSTEXT_XLT1_L2ADDR_MAX_INDEX 2 3053 #define GL_PSTEXT_XLT1_L2ADDR_LINE_IDX_S 0 3054 #define GL_PSTEXT_XLT1_L2ADDR_LINE_IDX_M MAKEMASK(0x7FF, 0) 3055 #define GL_PSTEXT_XLT1_L2ADDR_AUTO_INC_S 31 3056 #define GL_PSTEXT_XLT1_L2ADDR_AUTO_INC_M BIT(31) 3057 #define GL_PSTEXT_XLT1_L2DATA(_i) (0x0020E0CC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 3058 #define GL_PSTEXT_XLT1_L2DATA_MAX_INDEX 2 3059 #define GL_PSTEXT_XLT1_L2DATA_DATA_S 0 3060 #define GL_PSTEXT_XLT1_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0) 3061 #define GL_PSTEXT_XLT2_L2ADDR(_i) (0x0020E0D8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 3062 #define GL_PSTEXT_XLT2_L2ADDR_MAX_INDEX 2 3063 #define GL_PSTEXT_XLT2_L2ADDR_LINE_IDX_S 0 3064 #define GL_PSTEXT_XLT2_L2ADDR_LINE_IDX_M MAKEMASK(0x1FF, 0) 3065 #define GL_PSTEXT_XLT2_L2ADDR_AUTO_INC_S 31 3066 #define GL_PSTEXT_XLT2_L2ADDR_AUTO_INC_M BIT(31) 3067 #define GL_PSTEXT_XLT2_L2DATA(_i) (0x0020E0E4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 3068 #define GL_PSTEXT_XLT2_L2DATA_MAX_INDEX 2 3069 #define GL_PSTEXT_XLT2_L2DATA_DATA_S 0 3070 #define GL_PSTEXT_XLT2_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0) 3071 #define GLFLXP_PTYPE_TRANSLATION(_i) (0x0045C000 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 3072 #define GLFLXP_PTYPE_TRANSLATION_MAX_INDEX 255 3073 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_S 0 3074 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_M MAKEMASK(0xFF, 0) 3075 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_1_S 8 3076 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_1_M MAKEMASK(0xFF, 8) 3077 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_2_S 16 3078 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_2_M MAKEMASK(0xFF, 16) 3079 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_3_S 24 3080 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_3_M MAKEMASK(0xFF, 24) 3081 #define GLFLXP_RX_CMD_LX_PROT_IDX(_i) (0x0045C400 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 3082 #define GLFLXP_RX_CMD_LX_PROT_IDX_MAX_INDEX 255 3083 #define GLFLXP_RX_CMD_LX_PROT_IDX_INNER_CLOUD_OFFSET_INDEX_S 0 3084 #define GLFLXP_RX_CMD_LX_PROT_IDX_INNER_CLOUD_OFFSET_INDEX_M MAKEMASK(0x7, 0) 3085 #define GLFLXP_RX_CMD_LX_PROT_IDX_L4_OFFSET_INDEX_S 4 3086 #define GLFLXP_RX_CMD_LX_PROT_IDX_L4_OFFSET_INDEX_M MAKEMASK(0x7, 4) 3087 #define GLFLXP_RX_CMD_LX_PROT_IDX_PAYLOAD_OFFSET_INDEX_S 8 3088 #define GLFLXP_RX_CMD_LX_PROT_IDX_PAYLOAD_OFFSET_INDEX_M MAKEMASK(0x7, 8) 3089 #define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_S 12 3090 #define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_M MAKEMASK(0x3, 12) 3091 #define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_S 14 3092 #define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_M MAKEMASK(0x3, 14) 3093 #define GLFLXP_RX_CMD_PROTIDS(_i, _j) (0x0045A000 + ((_i) * 4 + (_j) * 1024)) /* _i=0...255, _j=0...5 */ /* Reset Source: CORER */ 3094 #define GLFLXP_RX_CMD_PROTIDS_MAX_INDEX 255 3095 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_S 0 3096 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_M MAKEMASK(0xFF, 0) 3097 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_1_S 8 3098 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_1_M MAKEMASK(0xFF, 8) 3099 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_2_S 16 3100 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_2_M MAKEMASK(0xFF, 16) 3101 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_3_S 24 3102 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_3_M MAKEMASK(0xFF, 24) 3103 #define GLFLXP_RXDID_FLAGS(_i, _j) (0x0045D000 + ((_i) * 4 + (_j) * 256)) /* _i=0...63, _j=0...4 */ /* Reset Source: CORER */ 3104 #define GLFLXP_RXDID_FLAGS_MAX_INDEX 63 3105 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S 0 3106 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M MAKEMASK(0x3F, 0) 3107 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S 8 3108 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M MAKEMASK(0x3F, 8) 3109 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S 16 3110 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M MAKEMASK(0x3F, 16) 3111 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S 24 3112 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M MAKEMASK(0x3F, 24) 3113 #define GLFLXP_RXDID_FLAGS1_OVERRIDE(_i) (0x0045D600 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 3114 #define GLFLXP_RXDID_FLAGS1_OVERRIDE_MAX_INDEX 63 3115 #define GLFLXP_RXDID_FLAGS1_OVERRIDE_FLEXIFLAGS1_OVERRIDE_S 0 3116 #define GLFLXP_RXDID_FLAGS1_OVERRIDE_FLEXIFLAGS1_OVERRIDE_M MAKEMASK(0xF, 0) 3117 #define GLFLXP_RXDID_FLX_WRD_0(_i) (0x0045C800 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 3118 #define GLFLXP_RXDID_FLX_WRD_0_MAX_INDEX 63 3119 #define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_S 0 3120 #define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_M MAKEMASK(0xFF, 0) 3121 #define GLFLXP_RXDID_FLX_WRD_0_EXTRACTION_OFFSET_S 8 3122 #define GLFLXP_RXDID_FLX_WRD_0_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8) 3123 #define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_S 30 3124 #define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_M MAKEMASK(0x3, 30) 3125 #define GLFLXP_RXDID_FLX_WRD_1(_i) (0x0045C900 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 3126 #define GLFLXP_RXDID_FLX_WRD_1_MAX_INDEX 63 3127 #define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_S 0 3128 #define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_M MAKEMASK(0xFF, 0) 3129 #define GLFLXP_RXDID_FLX_WRD_1_EXTRACTION_OFFSET_S 8 3130 #define GLFLXP_RXDID_FLX_WRD_1_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8) 3131 #define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_S 30 3132 #define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_M MAKEMASK(0x3, 30) 3133 #define GLFLXP_RXDID_FLX_WRD_2(_i) (0x0045CA00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 3134 #define GLFLXP_RXDID_FLX_WRD_2_MAX_INDEX 63 3135 #define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_S 0 3136 #define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_M MAKEMASK(0xFF, 0) 3137 #define GLFLXP_RXDID_FLX_WRD_2_EXTRACTION_OFFSET_S 8 3138 #define GLFLXP_RXDID_FLX_WRD_2_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8) 3139 #define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_S 30 3140 #define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_M MAKEMASK(0x3, 30) 3141 #define GLFLXP_RXDID_FLX_WRD_3(_i) (0x0045CB00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 3142 #define GLFLXP_RXDID_FLX_WRD_3_MAX_INDEX 63 3143 #define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_S 0 3144 #define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_M MAKEMASK(0xFF, 0) 3145 #define GLFLXP_RXDID_FLX_WRD_3_EXTRACTION_OFFSET_S 8 3146 #define GLFLXP_RXDID_FLX_WRD_3_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8) 3147 #define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_S 30 3148 #define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_M MAKEMASK(0x3, 30) 3149 #define GLFLXP_RXDID_FLX_WRD_4(_i) (0x0045CC00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 3150 #define GLFLXP_RXDID_FLX_WRD_4_MAX_INDEX 63 3151 #define GLFLXP_RXDID_FLX_WRD_4_PROT_MDID_S 0 3152 #define GLFLXP_RXDID_FLX_WRD_4_PROT_MDID_M MAKEMASK(0xFF, 0) 3153 #define GLFLXP_RXDID_FLX_WRD_4_EXTRACTION_OFFSET_S 8 3154 #define GLFLXP_RXDID_FLX_WRD_4_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8) 3155 #define GLFLXP_RXDID_FLX_WRD_4_RXDID_OPCODE_S 30 3156 #define GLFLXP_RXDID_FLX_WRD_4_RXDID_OPCODE_M MAKEMASK(0x3, 30) 3157 #define GLFLXP_RXDID_FLX_WRD_5(_i) (0x0045CD00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 3158 #define GLFLXP_RXDID_FLX_WRD_5_MAX_INDEX 63 3159 #define GLFLXP_RXDID_FLX_WRD_5_PROT_MDID_S 0 3160 #define GLFLXP_RXDID_FLX_WRD_5_PROT_MDID_M MAKEMASK(0xFF, 0) 3161 #define GLFLXP_RXDID_FLX_WRD_5_EXTRACTION_OFFSET_S 8 3162 #define GLFLXP_RXDID_FLX_WRD_5_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8) 3163 #define GLFLXP_RXDID_FLX_WRD_5_RXDID_OPCODE_S 30 3164 #define GLFLXP_RXDID_FLX_WRD_5_RXDID_OPCODE_M MAKEMASK(0x3, 30) 3165 #define GLFLXP_TX_SCHED_CORRECT(_i, _j) (0x00458000 + ((_i) * 4 + (_j) * 256)) /* _i=0...63, _j=0...31 */ /* Reset Source: CORER */ 3166 #define GLFLXP_TX_SCHED_CORRECT_MAX_INDEX 63 3167 #define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_S 0 3168 #define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_M MAKEMASK(0xFF, 0) 3169 #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_S 8 3170 #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_M MAKEMASK(0x1F, 8) 3171 #define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_S 16 3172 #define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_M MAKEMASK(0xFF, 16) 3173 #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_1_S 24 3174 #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_1_M MAKEMASK(0x1F, 24) 3175 #define QRXFLXP_CNTXT(_QRX) (0x00480000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */ 3176 #define QRXFLXP_CNTXT_MAX_INDEX 2047 3177 #define QRXFLXP_CNTXT_RXDID_IDX_S 0 3178 #define QRXFLXP_CNTXT_RXDID_IDX_M MAKEMASK(0x3F, 0) 3179 #define QRXFLXP_CNTXT_RXDID_PRIO_S 8 3180 #define QRXFLXP_CNTXT_RXDID_PRIO_M MAKEMASK(0x7, 8) 3181 #define QRXFLXP_CNTXT_TS_S 11 3182 #define QRXFLXP_CNTXT_TS_M BIT(11) 3183 #define GL_FWSTS 0x00083048 /* Reset Source: POR */ 3184 #define GL_FWSTS_FWS0B_S 0 3185 #define GL_FWSTS_FWS0B_M MAKEMASK(0xFF, 0) 3186 #define GL_FWSTS_FWROWD_S 8 3187 #define GL_FWSTS_FWROWD_M BIT(8) 3188 #define GL_FWSTS_FWRI_S 9 3189 #define GL_FWSTS_FWRI_M BIT(9) 3190 #define GL_FWSTS_FWS1B_S 16 3191 #define GL_FWSTS_FWS1B_M MAKEMASK(0xFF, 16) 3192 #define GL_TCVMLR_DRAIN_CNTR_CTL 0x000A21E0 /* Reset Source: CORER */ 3193 #define GL_TCVMLR_DRAIN_CNTR_CTL_OP_S 0 3194 #define GL_TCVMLR_DRAIN_CNTR_CTL_OP_M BIT(0) 3195 #define GL_TCVMLR_DRAIN_CNTR_CTL_PORT_S 1 3196 #define GL_TCVMLR_DRAIN_CNTR_CTL_PORT_M MAKEMASK(0x7, 1) 3197 #define GL_TCVMLR_DRAIN_CNTR_CTL_VALUE_S 4 3198 #define GL_TCVMLR_DRAIN_CNTR_CTL_VALUE_M MAKEMASK(0x3FFF, 4) 3199 #define GL_TCVMLR_DRAIN_DONE_DEC 0x000A21A8 /* Reset Source: CORER */ 3200 #define GL_TCVMLR_DRAIN_DONE_DEC_TARGET_S 0 3201 #define GL_TCVMLR_DRAIN_DONE_DEC_TARGET_M BIT(0) 3202 #define GL_TCVMLR_DRAIN_DONE_DEC_INDEX_S 1 3203 #define GL_TCVMLR_DRAIN_DONE_DEC_INDEX_M MAKEMASK(0x1F, 1) 3204 #define GL_TCVMLR_DRAIN_DONE_DEC_VALUE_S 6 3205 #define GL_TCVMLR_DRAIN_DONE_DEC_VALUE_M MAKEMASK(0xFF, 6) 3206 #define GL_TCVMLR_DRAIN_DONE_TCLAN(_i) (0x000A20A8 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 3207 #define GL_TCVMLR_DRAIN_DONE_TCLAN_MAX_INDEX 31 3208 #define GL_TCVMLR_DRAIN_DONE_TCLAN_COUNT_S 0 3209 #define GL_TCVMLR_DRAIN_DONE_TCLAN_COUNT_M MAKEMASK(0xFF, 0) 3210 #define GL_TCVMLR_DRAIN_DONE_TPB(_i) (0x000A2128 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 3211 #define GL_TCVMLR_DRAIN_DONE_TPB_MAX_INDEX 31 3212 #define GL_TCVMLR_DRAIN_DONE_TPB_COUNT_S 0 3213 #define GL_TCVMLR_DRAIN_DONE_TPB_COUNT_M MAKEMASK(0xFF, 0) 3214 #define GL_TCVMLR_DRAIN_MARKER 0x000A2008 /* Reset Source: CORER */ 3215 #define GL_TCVMLR_DRAIN_MARKER_PORT_S 0 3216 #define GL_TCVMLR_DRAIN_MARKER_PORT_M MAKEMASK(0x7, 0) 3217 #define GL_TCVMLR_DRAIN_MARKER_TC_S 3 3218 #define GL_TCVMLR_DRAIN_MARKER_TC_M MAKEMASK(0x1F, 3) 3219 #define GL_TCVMLR_ERR_STAT 0x000A2024 /* Reset Source: CORER */ 3220 #define GL_TCVMLR_ERR_STAT_ERROR_S 0 3221 #define GL_TCVMLR_ERR_STAT_ERROR_M BIT(0) 3222 #define GL_TCVMLR_ERR_STAT_FW_REQ_S 1 3223 #define GL_TCVMLR_ERR_STAT_FW_REQ_M BIT(1) 3224 #define GL_TCVMLR_ERR_STAT_STAT_S 2 3225 #define GL_TCVMLR_ERR_STAT_STAT_M MAKEMASK(0x7, 2) 3226 #define GL_TCVMLR_ERR_STAT_ENT_TYPE_S 5 3227 #define GL_TCVMLR_ERR_STAT_ENT_TYPE_M MAKEMASK(0x7, 5) 3228 #define GL_TCVMLR_ERR_STAT_ENT_ID_S 8 3229 #define GL_TCVMLR_ERR_STAT_ENT_ID_M MAKEMASK(0x3FFF, 8) 3230 #define GL_TCVMLR_QCFG 0x000A2010 /* Reset Source: CORER */ 3231 #define GL_TCVMLR_QCFG_QID_S 0 3232 #define GL_TCVMLR_QCFG_QID_M MAKEMASK(0x3FFF, 0) 3233 #define GL_TCVMLR_QCFG_OP_S 14 3234 #define GL_TCVMLR_QCFG_OP_M BIT(14) 3235 #define GL_TCVMLR_QCFG_PORT_S 15 3236 #define GL_TCVMLR_QCFG_PORT_M MAKEMASK(0x7, 15) 3237 #define GL_TCVMLR_QCFG_TC_S 18 3238 #define GL_TCVMLR_QCFG_TC_M MAKEMASK(0x1F, 18) 3239 #define GL_TCVMLR_QCFG_RD 0x000A2014 /* Reset Source: CORER */ 3240 #define GL_TCVMLR_QCFG_RD_QID_S 0 3241 #define GL_TCVMLR_QCFG_RD_QID_M MAKEMASK(0x3FFF, 0) 3242 #define GL_TCVMLR_QCFG_RD_PORT_S 14 3243 #define GL_TCVMLR_QCFG_RD_PORT_M MAKEMASK(0x7, 14) 3244 #define GL_TCVMLR_QCFG_RD_TC_S 17 3245 #define GL_TCVMLR_QCFG_RD_TC_M MAKEMASK(0x1F, 17) 3246 #define GL_TCVMLR_QCNTR 0x000A200C /* Reset Source: CORER */ 3247 #define GL_TCVMLR_QCNTR_CNTR_S 0 3248 #define GL_TCVMLR_QCNTR_CNTR_M MAKEMASK(0x7FFF, 0) 3249 #define GL_TCVMLR_QCTL 0x000A2004 /* Reset Source: CORER */ 3250 #define GL_TCVMLR_QCTL_QID_S 0 3251 #define GL_TCVMLR_QCTL_QID_M MAKEMASK(0x3FFF, 0) 3252 #define GL_TCVMLR_QCTL_OP_S 14 3253 #define GL_TCVMLR_QCTL_OP_M BIT(14) 3254 #define GL_TCVMLR_REQ_STAT 0x000A2018 /* Reset Source: CORER */ 3255 #define GL_TCVMLR_REQ_STAT_ENT_TYPE_S 0 3256 #define GL_TCVMLR_REQ_STAT_ENT_TYPE_M MAKEMASK(0x7, 0) 3257 #define GL_TCVMLR_REQ_STAT_ENT_ID_S 3 3258 #define GL_TCVMLR_REQ_STAT_ENT_ID_M MAKEMASK(0x3FFF, 3) 3259 #define GL_TCVMLR_REQ_STAT_OP_S 17 3260 #define GL_TCVMLR_REQ_STAT_OP_M BIT(17) 3261 #define GL_TCVMLR_REQ_STAT_WRITE_STATUS_S 18 3262 #define GL_TCVMLR_REQ_STAT_WRITE_STATUS_M MAKEMASK(0x7, 18) 3263 #define GL_TCVMLR_STAT 0x000A201C /* Reset Source: CORER */ 3264 #define GL_TCVMLR_STAT_ENT_TYPE_S 0 3265 #define GL_TCVMLR_STAT_ENT_TYPE_M MAKEMASK(0x7, 0) 3266 #define GL_TCVMLR_STAT_ENT_ID_S 3 3267 #define GL_TCVMLR_STAT_ENT_ID_M MAKEMASK(0x3FFF, 3) 3268 #define GL_TCVMLR_STAT_STATUS_S 17 3269 #define GL_TCVMLR_STAT_STATUS_M MAKEMASK(0x7, 17) 3270 #define GL_XLR_MARKER_TRIG_TCVMLR 0x000A2000 /* Reset Source: CORER */ 3271 #define GL_XLR_MARKER_TRIG_TCVMLR_VM_VF_NUM_S 0 3272 #define GL_XLR_MARKER_TRIG_TCVMLR_VM_VF_NUM_M MAKEMASK(0x3FF, 0) 3273 #define GL_XLR_MARKER_TRIG_TCVMLR_VM_VF_TYPE_S 10 3274 #define GL_XLR_MARKER_TRIG_TCVMLR_VM_VF_TYPE_M MAKEMASK(0x3, 10) 3275 #define GL_XLR_MARKER_TRIG_TCVMLR_PF_NUM_S 12 3276 #define GL_XLR_MARKER_TRIG_TCVMLR_PF_NUM_M MAKEMASK(0x7, 12) 3277 #define GL_XLR_MARKER_TRIG_TCVMLR_PORT_NUM_S 16 3278 #define GL_XLR_MARKER_TRIG_TCVMLR_PORT_NUM_M MAKEMASK(0x7, 16) 3279 #define GL_XLR_MARKER_TRIG_VMLR 0x00093804 /* Reset Source: CORER */ 3280 #define GL_XLR_MARKER_TRIG_VMLR_VM_VF_NUM_S 0 3281 #define GL_XLR_MARKER_TRIG_VMLR_VM_VF_NUM_M MAKEMASK(0x3FF, 0) 3282 #define GL_XLR_MARKER_TRIG_VMLR_VM_VF_TYPE_S 10 3283 #define GL_XLR_MARKER_TRIG_VMLR_VM_VF_TYPE_M MAKEMASK(0x3, 10) 3284 #define GL_XLR_MARKER_TRIG_VMLR_PF_NUM_S 12 3285 #define GL_XLR_MARKER_TRIG_VMLR_PF_NUM_M MAKEMASK(0x7, 12) 3286 #define GL_XLR_MARKER_TRIG_VMLR_PORT_NUM_S 16 3287 #define GL_XLR_MARKER_TRIG_VMLR_PORT_NUM_M MAKEMASK(0x7, 16) 3288 #define GLGEN_ANA_ABORT_PTYPE 0x0020C21C /* Reset Source: CORER */ 3289 #define GLGEN_ANA_ABORT_PTYPE_ABORT_S 0 3290 #define GLGEN_ANA_ABORT_PTYPE_ABORT_M MAKEMASK(0x3FF, 0) 3291 #define GLGEN_ANA_ALU_ACCSS_OUT_OF_PKT 0x0020C208 /* Reset Source: CORER */ 3292 #define GLGEN_ANA_ALU_ACCSS_OUT_OF_PKT_NPC_S 0 3293 #define GLGEN_ANA_ALU_ACCSS_OUT_OF_PKT_NPC_M MAKEMASK(0xFF, 0) 3294 #define GLGEN_ANA_CFG_CTRL 0x0020C104 /* Reset Source: CORER */ 3295 #define GLGEN_ANA_CFG_CTRL_LINE_IDX_S 0 3296 #define GLGEN_ANA_CFG_CTRL_LINE_IDX_M MAKEMASK(0x3FFFF, 0) 3297 #define GLGEN_ANA_CFG_CTRL_TABLE_ID_S 18 3298 #define GLGEN_ANA_CFG_CTRL_TABLE_ID_M MAKEMASK(0xFF, 18) 3299 #define GLGEN_ANA_CFG_CTRL_RESRVED_S 26 3300 #define GLGEN_ANA_CFG_CTRL_RESRVED_M MAKEMASK(0x7, 26) 3301 #define GLGEN_ANA_CFG_CTRL_OPERATION_ID_S 29 3302 #define GLGEN_ANA_CFG_CTRL_OPERATION_ID_M MAKEMASK(0x7, 29) 3303 #define GLGEN_ANA_CFG_HTBL_LU_RESULT 0x0020C158 /* Reset Source: CORER */ 3304 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_HIT_S 0 3305 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_HIT_M BIT(0) 3306 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_PG_MEM_IDX_S 1 3307 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_PG_MEM_IDX_M MAKEMASK(0x7, 1) 3308 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_ADDR_S 4 3309 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4) 3310 #define GLGEN_ANA_CFG_LU_KEY(_i) (0x0020C14C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 3311 #define GLGEN_ANA_CFG_LU_KEY_MAX_INDEX 2 3312 #define GLGEN_ANA_CFG_LU_KEY_LU_KEY_S 0 3313 #define GLGEN_ANA_CFG_LU_KEY_LU_KEY_M MAKEMASK(0xFFFFFFFF, 0) 3314 #define GLGEN_ANA_CFG_RDDATA(_i) (0x0020C10C + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 3315 #define GLGEN_ANA_CFG_RDDATA_MAX_INDEX 15 3316 #define GLGEN_ANA_CFG_RDDATA_RD_DATA_S 0 3317 #define GLGEN_ANA_CFG_RDDATA_RD_DATA_M MAKEMASK(0xFFFFFFFF, 0) 3318 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT 0x0020C15C /* Reset Source: CORER */ 3319 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_HIT_S 0 3320 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_HIT_M BIT(0) 3321 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_RSV_S 1 3322 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_RSV_M MAKEMASK(0x7, 1) 3323 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_ADDR_S 4 3324 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4) 3325 #define GLGEN_ANA_CFG_WRDATA 0x0020C108 /* Reset Source: CORER */ 3326 #define GLGEN_ANA_CFG_WRDATA_WR_DATA_S 0 3327 #define GLGEN_ANA_CFG_WRDATA_WR_DATA_M MAKEMASK(0xFFFFFFFF, 0) 3328 #define GLGEN_ANA_DEF_PTYPE 0x0020C100 /* Reset Source: CORER */ 3329 #define GLGEN_ANA_DEF_PTYPE_DEF_PTYPE_S 0 3330 #define GLGEN_ANA_DEF_PTYPE_DEF_PTYPE_M MAKEMASK(0x3FF, 0) 3331 #define GLGEN_ANA_ERR_CTRL 0x0020C220 /* Reset Source: CORER */ 3332 #define GLGEN_ANA_ERR_CTRL_ERR_MASK_EN_S 0 3333 #define GLGEN_ANA_ERR_CTRL_ERR_MASK_EN_M MAKEMASK(0xFFFFFFFF, 0) 3334 #define GLGEN_ANA_FLAG_MAP(_i) (0x0020C000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 3335 #define GLGEN_ANA_FLAG_MAP_MAX_INDEX 63 3336 #define GLGEN_ANA_FLAG_MAP_FLAG_EN_S 0 3337 #define GLGEN_ANA_FLAG_MAP_FLAG_EN_M BIT(0) 3338 #define GLGEN_ANA_FLAG_MAP_EXT_FLAG_ID_S 1 3339 #define GLGEN_ANA_FLAG_MAP_EXT_FLAG_ID_M MAKEMASK(0x3F, 1) 3340 #define GLGEN_ANA_INV_NODE_PTYPE 0x0020C210 /* Reset Source: CORER */ 3341 #define GLGEN_ANA_INV_NODE_PTYPE_INV_NODE_PTYPE_S 0 3342 #define GLGEN_ANA_INV_NODE_PTYPE_INV_NODE_PTYPE_M MAKEMASK(0x7FF, 0) 3343 #define GLGEN_ANA_INV_PTYPE_MARKER 0x0020C218 /* Reset Source: CORER */ 3344 #define GLGEN_ANA_INV_PTYPE_MARKER_INV_PTYPE_MARKER_S 0 3345 #define GLGEN_ANA_INV_PTYPE_MARKER_INV_PTYPE_MARKER_M MAKEMASK(0x7F, 0) 3346 #define GLGEN_ANA_LAST_PROT_ID(_i) (0x0020C1E4 + ((_i) * 4)) /* _i=0...5 */ /* Reset Source: CORER */ 3347 #define GLGEN_ANA_LAST_PROT_ID_MAX_INDEX 5 3348 #define GLGEN_ANA_LAST_PROT_ID_EN_S 0 3349 #define GLGEN_ANA_LAST_PROT_ID_EN_M BIT(0) 3350 #define GLGEN_ANA_LAST_PROT_ID_PROT_ID_S 1 3351 #define GLGEN_ANA_LAST_PROT_ID_PROT_ID_M MAKEMASK(0xFF, 1) 3352 #define GLGEN_ANA_NMPG_KEYMASK(_i) (0x0020C1D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */ 3353 #define GLGEN_ANA_NMPG_KEYMASK_MAX_INDEX 3 3354 #define GLGEN_ANA_NMPG_KEYMASK_HASH_KEY_S 0 3355 #define GLGEN_ANA_NMPG_KEYMASK_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0) 3356 #define GLGEN_ANA_NMPG0_HASHKEY(_i) (0x0020C1B0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */ 3357 #define GLGEN_ANA_NMPG0_HASHKEY_MAX_INDEX 3 3358 #define GLGEN_ANA_NMPG0_HASHKEY_HASH_KEY_S 0 3359 #define GLGEN_ANA_NMPG0_HASHKEY_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0) 3360 #define GLGEN_ANA_NO_HIT_PG_NM_PG 0x0020C204 /* Reset Source: CORER */ 3361 #define GLGEN_ANA_NO_HIT_PG_NM_PG_NPC_S 0 3362 #define GLGEN_ANA_NO_HIT_PG_NM_PG_NPC_M MAKEMASK(0xFF, 0) 3363 #define GLGEN_ANA_OUT_OF_PKT 0x0020C200 /* Reset Source: CORER */ 3364 #define GLGEN_ANA_OUT_OF_PKT_NPC_S 0 3365 #define GLGEN_ANA_OUT_OF_PKT_NPC_M MAKEMASK(0xFF, 0) 3366 #define GLGEN_ANA_P2P(_i) (0x0020C160 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 3367 #define GLGEN_ANA_P2P_MAX_INDEX 15 3368 #define GLGEN_ANA_P2P_TARGET_PROF_S 0 3369 #define GLGEN_ANA_P2P_TARGET_PROF_M MAKEMASK(0xF, 0) 3370 #define GLGEN_ANA_PG_KEYMASK(_i) (0x0020C1C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */ 3371 #define GLGEN_ANA_PG_KEYMASK_MAX_INDEX 3 3372 #define GLGEN_ANA_PG_KEYMASK_HASH_KEY_S 0 3373 #define GLGEN_ANA_PG_KEYMASK_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0) 3374 #define GLGEN_ANA_PG0_HASHKEY(_i) (0x0020C1A0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */ 3375 #define GLGEN_ANA_PG0_HASHKEY_MAX_INDEX 3 3376 #define GLGEN_ANA_PG0_HASHKEY_HASH_KEY_S 0 3377 #define GLGEN_ANA_PG0_HASHKEY_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0) 3378 #define GLGEN_ANA_PROFIL_CTRL 0x0020C1FC /* Reset Source: CORER */ 3379 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDID_S 0 3380 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDID_M MAKEMASK(0x1F, 0) 3381 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDSTART_S 5 3382 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDSTART_M MAKEMASK(0xF, 5) 3383 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_S 9 3384 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_M MAKEMASK(0x1F, 9) 3385 #define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_S 14 3386 #define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_M MAKEMASK(0x3, 14) 3387 #define GLGEN_ANA_PROFIL_CTRL_DEF_PROF_ID_S 16 3388 #define GLGEN_ANA_PROFIL_CTRL_DEF_PROF_ID_M MAKEMASK(0xF, 16) 3389 #define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_S 20 3390 #define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_M BIT(20) 3391 #define GLGEN_ANA_TX_ABORT_PTYPE 0x0020D21C /* Reset Source: CORER */ 3392 #define GLGEN_ANA_TX_ABORT_PTYPE_ABORT_S 0 3393 #define GLGEN_ANA_TX_ABORT_PTYPE_ABORT_M MAKEMASK(0x3FF, 0) 3394 #define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT 0x0020D208 /* Reset Source: CORER */ 3395 #define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_S 0 3396 #define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_M MAKEMASK(0xFF, 0) 3397 #define GLGEN_ANA_TX_CFG_CTRL 0x0020D104 /* Reset Source: CORER */ 3398 #define GLGEN_ANA_TX_CFG_CTRL_LINE_IDX_S 0 3399 #define GLGEN_ANA_TX_CFG_CTRL_LINE_IDX_M MAKEMASK(0x3FFFF, 0) 3400 #define GLGEN_ANA_TX_CFG_CTRL_TABLE_ID_S 18 3401 #define GLGEN_ANA_TX_CFG_CTRL_TABLE_ID_M MAKEMASK(0xFF, 18) 3402 #define GLGEN_ANA_TX_CFG_CTRL_RESRVED_S 26 3403 #define GLGEN_ANA_TX_CFG_CTRL_RESRVED_M MAKEMASK(0x7, 26) 3404 #define GLGEN_ANA_TX_CFG_CTRL_OPERATION_ID_S 29 3405 #define GLGEN_ANA_TX_CFG_CTRL_OPERATION_ID_M MAKEMASK(0x7, 29) 3406 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT 0x0020D158 /* Reset Source: CORER */ 3407 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_HIT_S 0 3408 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_HIT_M BIT(0) 3409 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_PG_MEM_IDX_S 1 3410 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_PG_MEM_IDX_M MAKEMASK(0x7, 1) 3411 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_ADDR_S 4 3412 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4) 3413 #define GLGEN_ANA_TX_CFG_LU_KEY(_i) (0x0020D14C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 3414 #define GLGEN_ANA_TX_CFG_LU_KEY_MAX_INDEX 2 3415 #define GLGEN_ANA_TX_CFG_LU_KEY_LU_KEY_S 0 3416 #define GLGEN_ANA_TX_CFG_LU_KEY_LU_KEY_M MAKEMASK(0xFFFFFFFF, 0) 3417 #define GLGEN_ANA_TX_CFG_RDDATA(_i) (0x0020D10C + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 3418 #define GLGEN_ANA_TX_CFG_RDDATA_MAX_INDEX 15 3419 #define GLGEN_ANA_TX_CFG_RDDATA_RD_DATA_S 0 3420 #define GLGEN_ANA_TX_CFG_RDDATA_RD_DATA_M MAKEMASK(0xFFFFFFFF, 0) 3421 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT 0x0020D15C /* Reset Source: CORER */ 3422 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_S 0 3423 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_M BIT(0) 3424 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_S 1 3425 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_M MAKEMASK(0x7, 1) 3426 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_ADDR_S 4 3427 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4) 3428 #define GLGEN_ANA_TX_CFG_WRDATA 0x0020D108 /* Reset Source: CORER */ 3429 #define GLGEN_ANA_TX_CFG_WRDATA_WR_DATA_S 0 3430 #define GLGEN_ANA_TX_CFG_WRDATA_WR_DATA_M MAKEMASK(0xFFFFFFFF, 0) 3431 #define GLGEN_ANA_TX_DEF_PTYPE 0x0020D100 /* Reset Source: CORER */ 3432 #define GLGEN_ANA_TX_DEF_PTYPE_DEF_PTYPE_S 0 3433 #define GLGEN_ANA_TX_DEF_PTYPE_DEF_PTYPE_M MAKEMASK(0x3FF, 0) 3434 #define GLGEN_ANA_TX_DFD_PACE_OUT 0x0020D4CC /* Reset Source: CORER */ 3435 #define GLGEN_ANA_TX_DFD_PACE_OUT_PUSH_S 0 3436 #define GLGEN_ANA_TX_DFD_PACE_OUT_PUSH_M BIT(0) 3437 #define GLGEN_ANA_TX_ERR_CTRL 0x0020D220 /* Reset Source: CORER */ 3438 #define GLGEN_ANA_TX_ERR_CTRL_ERR_MASK_EN_S 0 3439 #define GLGEN_ANA_TX_ERR_CTRL_ERR_MASK_EN_M MAKEMASK(0xFFFFFFFF, 0) 3440 #define GLGEN_ANA_TX_FLAG_MAP(_i) (0x0020D000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 3441 #define GLGEN_ANA_TX_FLAG_MAP_MAX_INDEX 63 3442 #define GLGEN_ANA_TX_FLAG_MAP_FLAG_EN_S 0 3443 #define GLGEN_ANA_TX_FLAG_MAP_FLAG_EN_M BIT(0) 3444 #define GLGEN_ANA_TX_FLAG_MAP_EXT_FLAG_ID_S 1 3445 #define GLGEN_ANA_TX_FLAG_MAP_EXT_FLAG_ID_M MAKEMASK(0x3F, 1) 3446 #define GLGEN_ANA_TX_INV_NODE_PTYPE 0x0020D210 /* Reset Source: CORER */ 3447 #define GLGEN_ANA_TX_INV_NODE_PTYPE_INV_NODE_PTYPE_S 0 3448 #define GLGEN_ANA_TX_INV_NODE_PTYPE_INV_NODE_PTYPE_M MAKEMASK(0x7FF, 0) 3449 #define GLGEN_ANA_TX_INV_PROT_ID 0x0020D214 /* Reset Source: CORER */ 3450 #define GLGEN_ANA_TX_INV_PROT_ID_INV_PROT_ID_S 0 3451 #define GLGEN_ANA_TX_INV_PROT_ID_INV_PROT_ID_M MAKEMASK(0xFF, 0) 3452 #define GLGEN_ANA_TX_INV_PTYPE_MARKER 0x0020D218 /* Reset Source: CORER */ 3453 #define GLGEN_ANA_TX_INV_PTYPE_MARKER_INV_PTYPE_MARKER_S 0 3454 #define GLGEN_ANA_TX_INV_PTYPE_MARKER_INV_PTYPE_MARKER_M MAKEMASK(0x7F, 0) 3455 #define GLGEN_ANA_TX_NMPG_KEYMASK(_i) (0x0020D1D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */ 3456 #define GLGEN_ANA_TX_NMPG_KEYMASK_MAX_INDEX 3 3457 #define GLGEN_ANA_TX_NMPG_KEYMASK_HASH_KEY_S 0 3458 #define GLGEN_ANA_TX_NMPG_KEYMASK_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0) 3459 #define GLGEN_ANA_TX_NMPG0_HASHKEY(_i) (0x0020D1B0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */ 3460 #define GLGEN_ANA_TX_NMPG0_HASHKEY_MAX_INDEX 3 3461 #define GLGEN_ANA_TX_NMPG0_HASHKEY_HASH_KEY_S 0 3462 #define GLGEN_ANA_TX_NMPG0_HASHKEY_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0) 3463 #define GLGEN_ANA_TX_NO_HIT_PG_NM_PG 0x0020D204 /* Reset Source: CORER */ 3464 #define GLGEN_ANA_TX_NO_HIT_PG_NM_PG_NPC_S 0 3465 #define GLGEN_ANA_TX_NO_HIT_PG_NM_PG_NPC_M MAKEMASK(0xFF, 0) 3466 #define GLGEN_ANA_TX_P2P(_i) (0x0020D160 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 3467 #define GLGEN_ANA_TX_P2P_MAX_INDEX 15 3468 #define GLGEN_ANA_TX_P2P_TARGET_PROF_S 0 3469 #define GLGEN_ANA_TX_P2P_TARGET_PROF_M MAKEMASK(0xF, 0) 3470 #define GLGEN_ANA_TX_PG_KEYMASK(_i) (0x0020D1C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */ 3471 #define GLGEN_ANA_TX_PG_KEYMASK_MAX_INDEX 3 3472 #define GLGEN_ANA_TX_PG_KEYMASK_HASH_KEY_S 0 3473 #define GLGEN_ANA_TX_PG_KEYMASK_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0) 3474 #define GLGEN_ANA_TX_PG0_HASHKEY(_i) (0x0020D1A0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */ 3475 #define GLGEN_ANA_TX_PG0_HASHKEY_MAX_INDEX 3 3476 #define GLGEN_ANA_TX_PG0_HASHKEY_HASH_KEY_S 0 3477 #define GLGEN_ANA_TX_PG0_HASHKEY_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0) 3478 #define GLGEN_ANA_TX_PROFIL_CTRL 0x0020D1FC /* Reset Source: CORER */ 3479 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MDID_S 0 3480 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MDID_M MAKEMASK(0x1F, 0) 3481 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MDSTART_S 5 3482 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MDSTART_M MAKEMASK(0xF, 5) 3483 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_S 9 3484 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_M MAKEMASK(0x1F, 9) 3485 #define GLGEN_ANA_TX_PROFIL_CTRL_NUM_CTRL_DOMAIN_S 14 3486 #define GLGEN_ANA_TX_PROFIL_CTRL_NUM_CTRL_DOMAIN_M MAKEMASK(0x3, 14) 3487 #define GLGEN_ANA_TX_PROFIL_CTRL_DEF_PROF_ID_S 16 3488 #define GLGEN_ANA_TX_PROFIL_CTRL_DEF_PROF_ID_M MAKEMASK(0xF, 16) 3489 #define GLGEN_ANA_TX_PROFIL_CTRL_SEL_DEF_PROF_ID_S 20 3490 #define GLGEN_ANA_TX_PROFIL_CTRL_SEL_DEF_PROF_ID_M BIT(20) 3491 #define GLGEN_ASSERT_HLP 0x000B81E4 /* Reset Source: POR */ 3492 #define GLGEN_ASSERT_HLP_CORE_ON_RST_S 0 3493 #define GLGEN_ASSERT_HLP_CORE_ON_RST_M BIT(0) 3494 #define GLGEN_ASSERT_HLP_FULL_ON_RST_S 1 3495 #define GLGEN_ASSERT_HLP_FULL_ON_RST_M BIT(1) 3496 #define GLGEN_CLKSTAT 0x000B8184 /* Reset Source: POR */ 3497 #define GLGEN_CLKSTAT_U_CLK_SPEED_S 0 3498 #define GLGEN_CLKSTAT_U_CLK_SPEED_M MAKEMASK(0x7, 0) 3499 #define GLGEN_CLKSTAT_L_CLK_SPEED_S 3 3500 #define GLGEN_CLKSTAT_L_CLK_SPEED_M MAKEMASK(0x7, 3) 3501 #define GLGEN_CLKSTAT_PSM_CLK_SPEED_S 6 3502 #define GLGEN_CLKSTAT_PSM_CLK_SPEED_M MAKEMASK(0x7, 6) 3503 #define GLGEN_CLKSTAT_RXCTL_CLK_SPEED_S 9 3504 #define GLGEN_CLKSTAT_RXCTL_CLK_SPEED_M MAKEMASK(0x7, 9) 3505 #define GLGEN_CLKSTAT_UANA_CLK_SPEED_S 12 3506 #define GLGEN_CLKSTAT_UANA_CLK_SPEED_M MAKEMASK(0x7, 12) 3507 #define GLGEN_CLKSTAT_PE_CLK_SPEED_S 18 3508 #define GLGEN_CLKSTAT_PE_CLK_SPEED_M MAKEMASK(0x7, 18) 3509 #define GLGEN_CLKSTAT_SRC 0x000B826C /* Reset Source: POR */ 3510 #define GLGEN_CLKSTAT_SRC_U_CLK_SRC_S 0 3511 #define GLGEN_CLKSTAT_SRC_U_CLK_SRC_M MAKEMASK(0x3, 0) 3512 #define GLGEN_CLKSTAT_SRC_L_CLK_SRC_S 2 3513 #define GLGEN_CLKSTAT_SRC_L_CLK_SRC_M MAKEMASK(0x3, 2) 3514 #define GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_S 4 3515 #define GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M MAKEMASK(0x3, 4) 3516 #define GLGEN_CLKSTAT_SRC_RXCTL_CLK_SRC_S 6 3517 #define GLGEN_CLKSTAT_SRC_RXCTL_CLK_SRC_M MAKEMASK(0x3, 6) 3518 #define GLGEN_CLKSTAT_SRC_UANA_CLK_SRC_S 8 3519 #define GLGEN_CLKSTAT_SRC_UANA_CLK_SRC_M MAKEMASK(0xF, 8) 3520 #define GLGEN_ECC_ERR_INT_TOG_MASK_H 0x00093A00 /* Reset Source: CORER */ 3521 #define GLGEN_ECC_ERR_INT_TOG_MASK_H_CLIENT_NUM_S 0 3522 #define GLGEN_ECC_ERR_INT_TOG_MASK_H_CLIENT_NUM_M MAKEMASK(0x7F, 0) 3523 #define GLGEN_ECC_ERR_INT_TOG_MASK_L 0x000939FC /* Reset Source: CORER */ 3524 #define GLGEN_ECC_ERR_INT_TOG_MASK_L_CLIENT_NUM_S 0 3525 #define GLGEN_ECC_ERR_INT_TOG_MASK_L_CLIENT_NUM_M MAKEMASK(0xFFFFFFFF, 0) 3526 #define GLGEN_ECC_ERR_RST_MASK_H 0x000939F8 /* Reset Source: CORER */ 3527 #define GLGEN_ECC_ERR_RST_MASK_H_CLIENT_NUM_S 0 3528 #define GLGEN_ECC_ERR_RST_MASK_H_CLIENT_NUM_M MAKEMASK(0x7F, 0) 3529 #define GLGEN_ECC_ERR_RST_MASK_L 0x000939F4 /* Reset Source: CORER */ 3530 #define GLGEN_ECC_ERR_RST_MASK_L_CLIENT_NUM_S 0 3531 #define GLGEN_ECC_ERR_RST_MASK_L_CLIENT_NUM_M MAKEMASK(0xFFFFFFFF, 0) 3532 #define GLGEN_GPIO_CTL(_i) (0x000880C8 + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: POR */ 3533 #define GLGEN_GPIO_CTL_MAX_INDEX 6 3534 #define GLGEN_GPIO_CTL_IN_VALUE_S 0 3535 #define GLGEN_GPIO_CTL_IN_VALUE_M BIT(0) 3536 #define GLGEN_GPIO_CTL_IN_TRANSIT_S 1 3537 #define GLGEN_GPIO_CTL_IN_TRANSIT_M BIT(1) 3538 #define GLGEN_GPIO_CTL_OUT_VALUE_S 2 3539 #define GLGEN_GPIO_CTL_OUT_VALUE_M BIT(2) 3540 #define GLGEN_GPIO_CTL_NO_P_UP_S 3 3541 #define GLGEN_GPIO_CTL_NO_P_UP_M BIT(3) 3542 #define GLGEN_GPIO_CTL_PIN_DIR_S 4 3543 #define GLGEN_GPIO_CTL_PIN_DIR_M BIT(4) 3544 #define GLGEN_GPIO_CTL_TRI_CTL_S 5 3545 #define GLGEN_GPIO_CTL_TRI_CTL_M BIT(5) 3546 #define GLGEN_GPIO_CTL_PIN_FUNC_S 8 3547 #define GLGEN_GPIO_CTL_PIN_FUNC_M MAKEMASK(0xF, 8) 3548 #define GLGEN_GPIO_CTL_INT_MODE_S 12 3549 #define GLGEN_GPIO_CTL_INT_MODE_M MAKEMASK(0x3, 12) 3550 #define GLGEN_MARKER_COUNT 0x000939E8 /* Reset Source: CORER */ 3551 #define GLGEN_MARKER_COUNT_MARKER_COUNT_S 0 3552 #define GLGEN_MARKER_COUNT_MARKER_COUNT_M MAKEMASK(0xFF, 0) 3553 #define GLGEN_MARKER_COUNT_MARKER_COUNT_EN_S 31 3554 #define GLGEN_MARKER_COUNT_MARKER_COUNT_EN_M BIT(31) 3555 #define GLGEN_RSTAT 0x000B8188 /* Reset Source: POR */ 3556 #define GLGEN_RSTAT_DEVSTATE_S 0 3557 #define GLGEN_RSTAT_DEVSTATE_M MAKEMASK(0x3, 0) 3558 #define GLGEN_RSTAT_RESET_TYPE_S 2 3559 #define GLGEN_RSTAT_RESET_TYPE_M MAKEMASK(0x3, 2) 3560 #define GLGEN_RSTAT_CORERCNT_S 4 3561 #define GLGEN_RSTAT_CORERCNT_M MAKEMASK(0x3, 4) 3562 #define GLGEN_RSTAT_GLOBRCNT_S 6 3563 #define GLGEN_RSTAT_GLOBRCNT_M MAKEMASK(0x3, 6) 3564 #define GLGEN_RSTAT_EMPRCNT_S 8 3565 #define GLGEN_RSTAT_EMPRCNT_M MAKEMASK(0x3, 8) 3566 #define GLGEN_RSTAT_TIME_TO_RST_S 10 3567 #define GLGEN_RSTAT_TIME_TO_RST_M MAKEMASK(0x3F, 10) 3568 #define GLGEN_RSTAT_RTRIG_FLR_S 16 3569 #define GLGEN_RSTAT_RTRIG_FLR_M BIT(16) 3570 #define GLGEN_RSTAT_RTRIG_ECC_S 17 3571 #define GLGEN_RSTAT_RTRIG_ECC_M BIT(17) 3572 #define GLGEN_RSTAT_RTRIG_FW_AUX_S 18 3573 #define GLGEN_RSTAT_RTRIG_FW_AUX_M BIT(18) 3574 #define GLGEN_RSTCTL 0x000B8180 /* Reset Source: POR */ 3575 #define GLGEN_RSTCTL_GRSTDEL_S 0 3576 #define GLGEN_RSTCTL_GRSTDEL_M MAKEMASK(0x3F, 0) 3577 #define GLGEN_RSTCTL_ECC_RST_ENA_S 8 3578 #define GLGEN_RSTCTL_ECC_RST_ENA_M BIT(8) 3579 #define GLGEN_RSTCTL_ECC_RT_EN_S 30 3580 #define GLGEN_RSTCTL_ECC_RT_EN_M BIT(30) 3581 #define GLGEN_RSTCTL_FLR_RT_EN_S 31 3582 #define GLGEN_RSTCTL_FLR_RT_EN_M BIT(31) 3583 #define GLGEN_RTRIG 0x000B8190 /* Reset Source: CORER */ 3584 #define GLGEN_RTRIG_CORER_S 0 3585 #define GLGEN_RTRIG_CORER_M BIT(0) 3586 #define GLGEN_RTRIG_GLOBR_S 1 3587 #define GLGEN_RTRIG_GLOBR_M BIT(1) 3588 #define GLGEN_RTRIG_EMPFWR_S 2 3589 #define GLGEN_RTRIG_EMPFWR_M BIT(2) 3590 #define GLGEN_STAT 0x000B612C /* Reset Source: POR */ 3591 #define GLGEN_STAT_RSVD4FW_S 0 3592 #define GLGEN_STAT_RSVD4FW_M MAKEMASK(0xFF, 0) 3593 #define GLGEN_VFLRSTAT(_i) (0x00093A04 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3594 #define GLGEN_VFLRSTAT_MAX_INDEX 7 3595 #define GLGEN_VFLRSTAT_VFLRS_S 0 3596 #define GLGEN_VFLRSTAT_VFLRS_M MAKEMASK(0xFFFFFFFF, 0) 3597 #define GLGEN_XLR_MSK2HLP_RDY 0x000939F0 /* Reset Source: CORER */ 3598 #define GLGEN_XLR_MSK2HLP_RDY_GLGEN_XLR_MSK2HLP_RDY_S 0 3599 #define GLGEN_XLR_MSK2HLP_RDY_GLGEN_XLR_MSK2HLP_RDY_M BIT(0) 3600 #define GLGEN_XLR_TRNS_WAIT_COUNT 0x000939EC /* Reset Source: CORER */ 3601 #define GLGEN_XLR_TRNS_WAIT_COUNT_W_BTWN_TRNS_COUNT_S 0 3602 #define GLGEN_XLR_TRNS_WAIT_COUNT_W_BTWN_TRNS_COUNT_M MAKEMASK(0x1F, 0) 3603 #define GLGEN_XLR_TRNS_WAIT_COUNT_W_PEND_TRNS_COUNT_S 8 3604 #define GLGEN_XLR_TRNS_WAIT_COUNT_W_PEND_TRNS_COUNT_M MAKEMASK(0xFF, 8) 3605 #define GLVFGEN_TIMER 0x000B8214 /* Reset Source: POR */ 3606 #define GLVFGEN_TIMER_GTIME_S 0 3607 #define GLVFGEN_TIMER_GTIME_M MAKEMASK(0xFFFFFFFF, 0) 3608 #define PFGEN_CTRL 0x00091000 /* Reset Source: CORER */ 3609 #define PFGEN_CTRL_PFSWR_S 0 3610 #define PFGEN_CTRL_PFSWR_M BIT(0) 3611 #define PFGEN_DRUN 0x00091180 /* Reset Source: CORER */ 3612 #define PFGEN_DRUN_DRVUNLD_S 0 3613 #define PFGEN_DRUN_DRVUNLD_M BIT(0) 3614 #define PFGEN_PFRSTAT 0x00091080 /* Reset Source: CORER */ 3615 #define PFGEN_PFRSTAT_PFRD_S 0 3616 #define PFGEN_PFRSTAT_PFRD_M BIT(0) 3617 #define PFGEN_PORTNUM 0x001D2400 /* Reset Source: CORER */ 3618 #define PFGEN_PORTNUM_PORT_NUM_S 0 3619 #define PFGEN_PORTNUM_PORT_NUM_M MAKEMASK(0x7, 0) 3620 #define PFGEN_STATE 0x00088000 /* Reset Source: CORER */ 3621 #define PFGEN_STATE_PFPEEN_S 0 3622 #define PFGEN_STATE_PFPEEN_M BIT(0) 3623 #define PFGEN_STATE_RSVD_S 1 3624 #define PFGEN_STATE_RSVD_M BIT(1) 3625 #define PFGEN_STATE_PFLINKEN_S 2 3626 #define PFGEN_STATE_PFLINKEN_M BIT(2) 3627 #define PFGEN_STATE_PFSCEN_S 3 3628 #define PFGEN_STATE_PFSCEN_M BIT(3) 3629 #define PRT_TCVMLR_DRAIN_CNTR 0x000A21C0 /* Reset Source: CORER */ 3630 #define PRT_TCVMLR_DRAIN_CNTR_CNTR_S 0 3631 #define PRT_TCVMLR_DRAIN_CNTR_CNTR_M MAKEMASK(0x3FFF, 0) 3632 #define PRTGEN_CNF 0x000B8120 /* Reset Source: POR */ 3633 #define PRTGEN_CNF_PORT_DIS_S 0 3634 #define PRTGEN_CNF_PORT_DIS_M BIT(0) 3635 #define PRTGEN_CNF_ALLOW_PORT_DIS_S 1 3636 #define PRTGEN_CNF_ALLOW_PORT_DIS_M BIT(1) 3637 #define PRTGEN_CNF_EMP_PORT_DIS_S 2 3638 #define PRTGEN_CNF_EMP_PORT_DIS_M BIT(2) 3639 #define PRTGEN_CNF2 0x000B8160 /* Reset Source: POR */ 3640 #define PRTGEN_CNF2_ACTIVATE_PORT_LINK_S 0 3641 #define PRTGEN_CNF2_ACTIVATE_PORT_LINK_M BIT(0) 3642 #define PRTGEN_CNF3 0x000B8280 /* Reset Source: POR */ 3643 #define PRTGEN_CNF3_PORT_STAGERING_EN_S 0 3644 #define PRTGEN_CNF3_PORT_STAGERING_EN_M BIT(0) 3645 #define PRTGEN_STATUS 0x000B8100 /* Reset Source: POR */ 3646 #define PRTGEN_STATUS_PORT_VALID_S 0 3647 #define PRTGEN_STATUS_PORT_VALID_M BIT(0) 3648 #define PRTGEN_STATUS_PORT_ACTIVE_S 1 3649 #define PRTGEN_STATUS_PORT_ACTIVE_M BIT(1) 3650 #define VFGEN_RSTAT(_VF) (0x00074000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: VFR */ 3651 #define VFGEN_RSTAT_MAX_INDEX 255 3652 #define VFGEN_RSTAT_VFR_STATE_S 0 3653 #define VFGEN_RSTAT_VFR_STATE_M MAKEMASK(0x3, 0) 3654 #define VPGEN_VFRSTAT(_VF) (0x00090800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 3655 #define VPGEN_VFRSTAT_MAX_INDEX 255 3656 #define VPGEN_VFRSTAT_VFRD_S 0 3657 #define VPGEN_VFRSTAT_VFRD_M BIT(0) 3658 #define VPGEN_VFRTRIG(_VF) (0x00090000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 3659 #define VPGEN_VFRTRIG_MAX_INDEX 255 3660 #define VPGEN_VFRTRIG_VFSWR_S 0 3661 #define VPGEN_VFRTRIG_VFSWR_M BIT(0) 3662 #define VSIGEN_RSTAT(_VSI) (0x00092800 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 3663 #define VSIGEN_RSTAT_MAX_INDEX 767 3664 #define VSIGEN_RSTAT_VMRD_S 0 3665 #define VSIGEN_RSTAT_VMRD_M BIT(0) 3666 #define VSIGEN_RTRIG(_VSI) (0x00091800 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 3667 #define VSIGEN_RTRIG_MAX_INDEX 767 3668 #define VSIGEN_RTRIG_VMSWR_S 0 3669 #define VSIGEN_RTRIG_VMSWR_M BIT(0) 3670 #define GLHMC_APBVTINUSEBASE(_i) (0x00524A00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3671 #define GLHMC_APBVTINUSEBASE_MAX_INDEX 7 3672 #define GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_S 0 3673 #define GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_M MAKEMASK(0xFFFFFF, 0) 3674 #define GLHMC_CEQPART(_i) (0x005031C0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3675 #define GLHMC_CEQPART_MAX_INDEX 7 3676 #define GLHMC_CEQPART_PMCEQBASE_S 0 3677 #define GLHMC_CEQPART_PMCEQBASE_M MAKEMASK(0x3FF, 0) 3678 #define GLHMC_CEQPART_PMCEQSIZE_S 16 3679 #define GLHMC_CEQPART_PMCEQSIZE_M MAKEMASK(0x3FF, 16) 3680 #define GLHMC_DBCQMAX 0x005220F0 /* Reset Source: CORER */ 3681 #define GLHMC_DBCQMAX_GLHMC_DBCQMAX_S 0 3682 #define GLHMC_DBCQMAX_GLHMC_DBCQMAX_M MAKEMASK(0xFFFFF, 0) 3683 #define GLHMC_DBCQPART(_i) (0x00503180 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3684 #define GLHMC_DBCQPART_MAX_INDEX 7 3685 #define GLHMC_DBCQPART_PMDBCQBASE_S 0 3686 #define GLHMC_DBCQPART_PMDBCQBASE_M MAKEMASK(0x3FFF, 0) 3687 #define GLHMC_DBCQPART_PMDBCQSIZE_S 16 3688 #define GLHMC_DBCQPART_PMDBCQSIZE_M MAKEMASK(0x7FFF, 16) 3689 #define GLHMC_DBQPMAX 0x005220EC /* Reset Source: CORER */ 3690 #define GLHMC_DBQPMAX_GLHMC_DBQPMAX_S 0 3691 #define GLHMC_DBQPMAX_GLHMC_DBQPMAX_M MAKEMASK(0x7FFFF, 0) 3692 #define GLHMC_DBQPPART(_i) (0x005044C0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3693 #define GLHMC_DBQPPART_MAX_INDEX 7 3694 #define GLHMC_DBQPPART_PMDBQPBASE_S 0 3695 #define GLHMC_DBQPPART_PMDBQPBASE_M MAKEMASK(0x3FFF, 0) 3696 #define GLHMC_DBQPPART_PMDBQPSIZE_S 16 3697 #define GLHMC_DBQPPART_PMDBQPSIZE_M MAKEMASK(0x7FFF, 16) 3698 #define GLHMC_FSIAVBASE(_i) (0x00525600 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3699 #define GLHMC_FSIAVBASE_MAX_INDEX 7 3700 #define GLHMC_FSIAVBASE_FPMFSIAVBASE_S 0 3701 #define GLHMC_FSIAVBASE_FPMFSIAVBASE_M MAKEMASK(0xFFFFFF, 0) 3702 #define GLHMC_FSIAVCNT(_i) (0x00525700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3703 #define GLHMC_FSIAVCNT_MAX_INDEX 7 3704 #define GLHMC_FSIAVCNT_FPMFSIAVCNT_S 0 3705 #define GLHMC_FSIAVCNT_FPMFSIAVCNT_M MAKEMASK(0x1FFFFFFF, 0) 3706 #define GLHMC_FSIAVMAX 0x00522068 /* Reset Source: CORER */ 3707 #define GLHMC_FSIAVMAX_PMFSIAVMAX_S 0 3708 #define GLHMC_FSIAVMAX_PMFSIAVMAX_M MAKEMASK(0x3FFFF, 0) 3709 #define GLHMC_FSIAVOBJSZ 0x00522064 /* Reset Source: CORER */ 3710 #define GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_S 0 3711 #define GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_M MAKEMASK(0xF, 0) 3712 #define GLHMC_FSIMCBASE(_i) (0x00526000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3713 #define GLHMC_FSIMCBASE_MAX_INDEX 7 3714 #define GLHMC_FSIMCBASE_FPMFSIMCBASE_S 0 3715 #define GLHMC_FSIMCBASE_FPMFSIMCBASE_M MAKEMASK(0xFFFFFF, 0) 3716 #define GLHMC_FSIMCCNT(_i) (0x00526100 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3717 #define GLHMC_FSIMCCNT_MAX_INDEX 7 3718 #define GLHMC_FSIMCCNT_FPMFSIMCSZ_S 0 3719 #define GLHMC_FSIMCCNT_FPMFSIMCSZ_M MAKEMASK(0x1FFFFFFF, 0) 3720 #define GLHMC_FSIMCMAX 0x00522060 /* Reset Source: CORER */ 3721 #define GLHMC_FSIMCMAX_PMFSIMCMAX_S 0 3722 #define GLHMC_FSIMCMAX_PMFSIMCMAX_M MAKEMASK(0x3FFF, 0) 3723 #define GLHMC_FSIMCOBJSZ 0x0052205C /* Reset Source: CORER */ 3724 #define GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_S 0 3725 #define GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_M MAKEMASK(0xF, 0) 3726 #define GLHMC_FWPDINV 0x0052207C /* Reset Source: CORER */ 3727 #define GLHMC_FWPDINV_PMSDIDX_S 0 3728 #define GLHMC_FWPDINV_PMSDIDX_M MAKEMASK(0xFFF, 0) 3729 #define GLHMC_FWPDINV_PMSDPARTSEL_S 15 3730 #define GLHMC_FWPDINV_PMSDPARTSEL_M BIT(15) 3731 #define GLHMC_FWPDINV_PMPDIDX_S 16 3732 #define GLHMC_FWPDINV_PMPDIDX_M MAKEMASK(0x1FF, 16) 3733 #define GLHMC_FWPDINV_FPMAT 0x0010207C /* Reset Source: CORER */ 3734 #define GLHMC_FWPDINV_FPMAT_PMSDIDX_S 0 3735 #define GLHMC_FWPDINV_FPMAT_PMSDIDX_M MAKEMASK(0xFFF, 0) 3736 #define GLHMC_FWPDINV_FPMAT_PMSDPARTSEL_S 15 3737 #define GLHMC_FWPDINV_FPMAT_PMSDPARTSEL_M BIT(15) 3738 #define GLHMC_FWPDINV_FPMAT_PMPDIDX_S 16 3739 #define GLHMC_FWPDINV_FPMAT_PMPDIDX_M MAKEMASK(0x1FF, 16) 3740 #define GLHMC_FWSDDATAHIGH 0x00522078 /* Reset Source: CORER */ 3741 #define GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_S 0 3742 #define GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0) 3743 #define GLHMC_FWSDDATAHIGH_FPMAT 0x00102078 /* Reset Source: CORER */ 3744 #define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0 3745 #define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0) 3746 #define GLHMC_FWSDDATALOW 0x00522074 /* Reset Source: CORER */ 3747 #define GLHMC_FWSDDATALOW_PMSDVALID_S 0 3748 #define GLHMC_FWSDDATALOW_PMSDVALID_M BIT(0) 3749 #define GLHMC_FWSDDATALOW_PMSDTYPE_S 1 3750 #define GLHMC_FWSDDATALOW_PMSDTYPE_M BIT(1) 3751 #define GLHMC_FWSDDATALOW_PMSDBPCOUNT_S 2 3752 #define GLHMC_FWSDDATALOW_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2) 3753 #define GLHMC_FWSDDATALOW_PMSDDATALOW_S 12 3754 #define GLHMC_FWSDDATALOW_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12) 3755 #define GLHMC_FWSDDATALOW_FPMAT 0x00102074 /* Reset Source: CORER */ 3756 #define GLHMC_FWSDDATALOW_FPMAT_PMSDVALID_S 0 3757 #define GLHMC_FWSDDATALOW_FPMAT_PMSDVALID_M BIT(0) 3758 #define GLHMC_FWSDDATALOW_FPMAT_PMSDTYPE_S 1 3759 #define GLHMC_FWSDDATALOW_FPMAT_PMSDTYPE_M BIT(1) 3760 #define GLHMC_FWSDDATALOW_FPMAT_PMSDBPCOUNT_S 2 3761 #define GLHMC_FWSDDATALOW_FPMAT_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2) 3762 #define GLHMC_FWSDDATALOW_FPMAT_PMSDDATALOW_S 12 3763 #define GLHMC_FWSDDATALOW_FPMAT_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12) 3764 #define GLHMC_PEARPBASE(_i) (0x00524800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3765 #define GLHMC_PEARPBASE_MAX_INDEX 7 3766 #define GLHMC_PEARPBASE_FPMPEARPBASE_S 0 3767 #define GLHMC_PEARPBASE_FPMPEARPBASE_M MAKEMASK(0xFFFFFF, 0) 3768 #define GLHMC_PEARPCNT(_i) (0x00524900 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3769 #define GLHMC_PEARPCNT_MAX_INDEX 7 3770 #define GLHMC_PEARPCNT_FPMPEARPCNT_S 0 3771 #define GLHMC_PEARPCNT_FPMPEARPCNT_M MAKEMASK(0x1FFFFFFF, 0) 3772 #define GLHMC_PEARPMAX 0x00522038 /* Reset Source: CORER */ 3773 #define GLHMC_PEARPMAX_PMPEARPMAX_S 0 3774 #define GLHMC_PEARPMAX_PMPEARPMAX_M MAKEMASK(0x1FFFF, 0) 3775 #define GLHMC_PEARPOBJSZ 0x00522034 /* Reset Source: CORER */ 3776 #define GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_S 0 3777 #define GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_M MAKEMASK(0x7, 0) 3778 #define GLHMC_PECQBASE(_i) (0x00524200 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3779 #define GLHMC_PECQBASE_MAX_INDEX 7 3780 #define GLHMC_PECQBASE_FPMPECQBASE_S 0 3781 #define GLHMC_PECQBASE_FPMPECQBASE_M MAKEMASK(0xFFFFFF, 0) 3782 #define GLHMC_PECQCNT(_i) (0x00524300 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3783 #define GLHMC_PECQCNT_MAX_INDEX 7 3784 #define GLHMC_PECQCNT_FPMPECQCNT_S 0 3785 #define GLHMC_PECQCNT_FPMPECQCNT_M MAKEMASK(0x1FFFFFFF, 0) 3786 #define GLHMC_PECQOBJSZ 0x00522020 /* Reset Source: CORER */ 3787 #define GLHMC_PECQOBJSZ_PMPECQOBJSZ_S 0 3788 #define GLHMC_PECQOBJSZ_PMPECQOBJSZ_M MAKEMASK(0xF, 0) 3789 #define GLHMC_PEHDRBASE(_i) (0x00526200 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3790 #define GLHMC_PEHDRBASE_MAX_INDEX 7 3791 #define GLHMC_PEHDRBASE_GLHMC_PEHDRBASE_S 0 3792 #define GLHMC_PEHDRBASE_GLHMC_PEHDRBASE_M MAKEMASK(0xFFFFFFFF, 0) 3793 #define GLHMC_PEHDRCNT(_i) (0x00526300 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3794 #define GLHMC_PEHDRCNT_MAX_INDEX 7 3795 #define GLHMC_PEHDRCNT_GLHMC_PEHDRCNT_S 0 3796 #define GLHMC_PEHDRCNT_GLHMC_PEHDRCNT_M MAKEMASK(0xFFFFFFFF, 0) 3797 #define GLHMC_PEHDRMAX 0x00522008 /* Reset Source: CORER */ 3798 #define GLHMC_PEHDRMAX_PMPEHDRMAX_S 0 3799 #define GLHMC_PEHDRMAX_PMPEHDRMAX_M MAKEMASK(0x7FFFF, 0) 3800 #define GLHMC_PEHDRMAX_RSVD_S 19 3801 #define GLHMC_PEHDRMAX_RSVD_M MAKEMASK(0x1FFF, 19) 3802 #define GLHMC_PEHDROBJSZ 0x00522004 /* Reset Source: CORER */ 3803 #define GLHMC_PEHDROBJSZ_PMPEHDROBJSZ_S 0 3804 #define GLHMC_PEHDROBJSZ_PMPEHDROBJSZ_M MAKEMASK(0xF, 0) 3805 #define GLHMC_PEHDROBJSZ_RSVD_S 4 3806 #define GLHMC_PEHDROBJSZ_RSVD_M MAKEMASK(0xFFFFFFF, 4) 3807 #define GLHMC_PEHTCNT(_i) (0x00524700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3808 #define GLHMC_PEHTCNT_MAX_INDEX 7 3809 #define GLHMC_PEHTCNT_FPMPEHTCNT_S 0 3810 #define GLHMC_PEHTCNT_FPMPEHTCNT_M MAKEMASK(0x1FFFFFFF, 0) 3811 #define GLHMC_PEHTCNT_FPMAT(_i) (0x00104700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3812 #define GLHMC_PEHTCNT_FPMAT_MAX_INDEX 7 3813 #define GLHMC_PEHTCNT_FPMAT_FPMPEHTCNT_S 0 3814 #define GLHMC_PEHTCNT_FPMAT_FPMPEHTCNT_M MAKEMASK(0x1FFFFFFF, 0) 3815 #define GLHMC_PEHTEBASE(_i) (0x00524600 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3816 #define GLHMC_PEHTEBASE_MAX_INDEX 7 3817 #define GLHMC_PEHTEBASE_FPMPEHTEBASE_S 0 3818 #define GLHMC_PEHTEBASE_FPMPEHTEBASE_M MAKEMASK(0xFFFFFF, 0) 3819 #define GLHMC_PEHTEBASE_FPMAT(_i) (0x00104600 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3820 #define GLHMC_PEHTEBASE_FPMAT_MAX_INDEX 7 3821 #define GLHMC_PEHTEBASE_FPMAT_FPMPEHTEBASE_S 0 3822 #define GLHMC_PEHTEBASE_FPMAT_FPMPEHTEBASE_M MAKEMASK(0xFFFFFF, 0) 3823 #define GLHMC_PEHTEOBJSZ 0x0052202C /* Reset Source: CORER */ 3824 #define GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_S 0 3825 #define GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_M MAKEMASK(0xF, 0) 3826 #define GLHMC_PEHTEOBJSZ_FPMAT 0x0010202C /* Reset Source: CORER */ 3827 #define GLHMC_PEHTEOBJSZ_FPMAT_PMPEHTEOBJSZ_S 0 3828 #define GLHMC_PEHTEOBJSZ_FPMAT_PMPEHTEOBJSZ_M MAKEMASK(0xF, 0) 3829 #define GLHMC_PEHTMAX 0x00522030 /* Reset Source: CORER */ 3830 #define GLHMC_PEHTMAX_PMPEHTMAX_S 0 3831 #define GLHMC_PEHTMAX_PMPEHTMAX_M MAKEMASK(0x1FFFFF, 0) 3832 #define GLHMC_PEHTMAX_FPMAT 0x00102030 /* Reset Source: CORER */ 3833 #define GLHMC_PEHTMAX_FPMAT_PMPEHTMAX_S 0 3834 #define GLHMC_PEHTMAX_FPMAT_PMPEHTMAX_M MAKEMASK(0x1FFFFF, 0) 3835 #define GLHMC_PEMDBASE(_i) (0x00526400 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3836 #define GLHMC_PEMDBASE_MAX_INDEX 7 3837 #define GLHMC_PEMDBASE_GLHMC_PEMDBASE_S 0 3838 #define GLHMC_PEMDBASE_GLHMC_PEMDBASE_M MAKEMASK(0xFFFFFFFF, 0) 3839 #define GLHMC_PEMDCNT(_i) (0x00526500 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3840 #define GLHMC_PEMDCNT_MAX_INDEX 7 3841 #define GLHMC_PEMDCNT_GLHMC_PEMDCNT_S 0 3842 #define GLHMC_PEMDCNT_GLHMC_PEMDCNT_M MAKEMASK(0xFFFFFFFF, 0) 3843 #define GLHMC_PEMDMAX 0x00522010 /* Reset Source: CORER */ 3844 #define GLHMC_PEMDMAX_PMPEMDMAX_S 0 3845 #define GLHMC_PEMDMAX_PMPEMDMAX_M MAKEMASK(0xFFFFFF, 0) 3846 #define GLHMC_PEMDMAX_RSVD_S 24 3847 #define GLHMC_PEMDMAX_RSVD_M MAKEMASK(0xFF, 24) 3848 #define GLHMC_PEMDOBJSZ 0x0052200C /* Reset Source: CORER */ 3849 #define GLHMC_PEMDOBJSZ_PMPEMDOBJSZ_S 0 3850 #define GLHMC_PEMDOBJSZ_PMPEMDOBJSZ_M MAKEMASK(0xF, 0) 3851 #define GLHMC_PEMDOBJSZ_RSVD_S 4 3852 #define GLHMC_PEMDOBJSZ_RSVD_M MAKEMASK(0xFFFFFFF, 4) 3853 #define GLHMC_PEMRBASE(_i) (0x00524C00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3854 #define GLHMC_PEMRBASE_MAX_INDEX 7 3855 #define GLHMC_PEMRBASE_FPMPEMRBASE_S 0 3856 #define GLHMC_PEMRBASE_FPMPEMRBASE_M MAKEMASK(0xFFFFFF, 0) 3857 #define GLHMC_PEMRCNT(_i) (0x00524D00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3858 #define GLHMC_PEMRCNT_MAX_INDEX 7 3859 #define GLHMC_PEMRCNT_FPMPEMRSZ_S 0 3860 #define GLHMC_PEMRCNT_FPMPEMRSZ_M MAKEMASK(0x1FFFFFFF, 0) 3861 #define GLHMC_PEMRMAX 0x00522040 /* Reset Source: CORER */ 3862 #define GLHMC_PEMRMAX_PMPEMRMAX_S 0 3863 #define GLHMC_PEMRMAX_PMPEMRMAX_M MAKEMASK(0x7FFFFF, 0) 3864 #define GLHMC_PEMROBJSZ 0x0052203C /* Reset Source: CORER */ 3865 #define GLHMC_PEMROBJSZ_PMPEMROBJSZ_S 0 3866 #define GLHMC_PEMROBJSZ_PMPEMROBJSZ_M MAKEMASK(0xF, 0) 3867 #define GLHMC_PEOOISCBASE(_i) (0x00526600 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3868 #define GLHMC_PEOOISCBASE_MAX_INDEX 7 3869 #define GLHMC_PEOOISCBASE_GLHMC_PEOOISCBASE_S 0 3870 #define GLHMC_PEOOISCBASE_GLHMC_PEOOISCBASE_M MAKEMASK(0xFFFFFFFF, 0) 3871 #define GLHMC_PEOOISCCNT(_i) (0x00526700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3872 #define GLHMC_PEOOISCCNT_MAX_INDEX 7 3873 #define GLHMC_PEOOISCCNT_GLHMC_PEOOISCCNT_S 0 3874 #define GLHMC_PEOOISCCNT_GLHMC_PEOOISCCNT_M MAKEMASK(0xFFFFFFFF, 0) 3875 #define GLHMC_PEOOISCFFLBASE(_i) (0x00526C00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3876 #define GLHMC_PEOOISCFFLBASE_MAX_INDEX 7 3877 #define GLHMC_PEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_S 0 3878 #define GLHMC_PEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_M MAKEMASK(0xFFFFFFFF, 0) 3879 #define GLHMC_PEOOISCFFLCNT_PMAT(_i) (0x00526D00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3880 #define GLHMC_PEOOISCFFLCNT_PMAT_MAX_INDEX 7 3881 #define GLHMC_PEOOISCFFLCNT_PMAT_FPMPEOOISCFLCNT_S 0 3882 #define GLHMC_PEOOISCFFLCNT_PMAT_FPMPEOOISCFLCNT_M MAKEMASK(0x1FFFFFFF, 0) 3883 #define GLHMC_PEOOISCFFLMAX 0x005220A4 /* Reset Source: CORER */ 3884 #define GLHMC_PEOOISCFFLMAX_PMPEOOISCFFLMAX_S 0 3885 #define GLHMC_PEOOISCFFLMAX_PMPEOOISCFFLMAX_M MAKEMASK(0x7FFFF, 0) 3886 #define GLHMC_PEOOISCFFLMAX_RSVD_S 19 3887 #define GLHMC_PEOOISCFFLMAX_RSVD_M MAKEMASK(0x1FFF, 19) 3888 #define GLHMC_PEOOISCMAX 0x00522018 /* Reset Source: CORER */ 3889 #define GLHMC_PEOOISCMAX_PMPEOOISCMAX_S 0 3890 #define GLHMC_PEOOISCMAX_PMPEOOISCMAX_M MAKEMASK(0x7FFFF, 0) 3891 #define GLHMC_PEOOISCMAX_RSVD_S 19 3892 #define GLHMC_PEOOISCMAX_RSVD_M MAKEMASK(0x1FFF, 19) 3893 #define GLHMC_PEOOISCOBJSZ 0x00522014 /* Reset Source: CORER */ 3894 #define GLHMC_PEOOISCOBJSZ_PMPEOOISCOBJSZ_S 0 3895 #define GLHMC_PEOOISCOBJSZ_PMPEOOISCOBJSZ_M MAKEMASK(0xF, 0) 3896 #define GLHMC_PEOOISCOBJSZ_RSVD_S 4 3897 #define GLHMC_PEOOISCOBJSZ_RSVD_M MAKEMASK(0xFFFFFFF, 4) 3898 #define GLHMC_PEPBLBASE(_i) (0x00525800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3899 #define GLHMC_PEPBLBASE_MAX_INDEX 7 3900 #define GLHMC_PEPBLBASE_FPMPEPBLBASE_S 0 3901 #define GLHMC_PEPBLBASE_FPMPEPBLBASE_M MAKEMASK(0xFFFFFF, 0) 3902 #define GLHMC_PEPBLCNT(_i) (0x00525900 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3903 #define GLHMC_PEPBLCNT_MAX_INDEX 7 3904 #define GLHMC_PEPBLCNT_FPMPEPBLCNT_S 0 3905 #define GLHMC_PEPBLCNT_FPMPEPBLCNT_M MAKEMASK(0x1FFFFFFF, 0) 3906 #define GLHMC_PEPBLMAX 0x0052206C /* Reset Source: CORER */ 3907 #define GLHMC_PEPBLMAX_PMPEPBLMAX_S 0 3908 #define GLHMC_PEPBLMAX_PMPEPBLMAX_M MAKEMASK(0x1FFFFFFF, 0) 3909 #define GLHMC_PEQ1BASE(_i) (0x00525200 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3910 #define GLHMC_PEQ1BASE_MAX_INDEX 7 3911 #define GLHMC_PEQ1BASE_FPMPEQ1BASE_S 0 3912 #define GLHMC_PEQ1BASE_FPMPEQ1BASE_M MAKEMASK(0xFFFFFF, 0) 3913 #define GLHMC_PEQ1CNT(_i) (0x00525300 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3914 #define GLHMC_PEQ1CNT_MAX_INDEX 7 3915 #define GLHMC_PEQ1CNT_FPMPEQ1CNT_S 0 3916 #define GLHMC_PEQ1CNT_FPMPEQ1CNT_M MAKEMASK(0x1FFFFFFF, 0) 3917 #define GLHMC_PEQ1FLBASE(_i) (0x00525400 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3918 #define GLHMC_PEQ1FLBASE_MAX_INDEX 7 3919 #define GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_S 0 3920 #define GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_M MAKEMASK(0xFFFFFF, 0) 3921 #define GLHMC_PEQ1FLMAX 0x00522058 /* Reset Source: CORER */ 3922 #define GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_S 0 3923 #define GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_M MAKEMASK(0x3FFFFFF, 0) 3924 #define GLHMC_PEQ1MAX 0x00522054 /* Reset Source: CORER */ 3925 #define GLHMC_PEQ1MAX_PMPEQ1MAX_S 0 3926 #define GLHMC_PEQ1MAX_PMPEQ1MAX_M MAKEMASK(0xFFFFFFF, 0) 3927 #define GLHMC_PEQ1OBJSZ 0x00522050 /* Reset Source: CORER */ 3928 #define GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_S 0 3929 #define GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_M MAKEMASK(0xF, 0) 3930 #define GLHMC_PEQPBASE(_i) (0x00524000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3931 #define GLHMC_PEQPBASE_MAX_INDEX 7 3932 #define GLHMC_PEQPBASE_FPMPEQPBASE_S 0 3933 #define GLHMC_PEQPBASE_FPMPEQPBASE_M MAKEMASK(0xFFFFFF, 0) 3934 #define GLHMC_PEQPCNT(_i) (0x00524100 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3935 #define GLHMC_PEQPCNT_MAX_INDEX 7 3936 #define GLHMC_PEQPCNT_FPMPEQPCNT_S 0 3937 #define GLHMC_PEQPCNT_FPMPEQPCNT_M MAKEMASK(0x1FFFFFFF, 0) 3938 #define GLHMC_PEQPOBJSZ 0x0052201C /* Reset Source: CORER */ 3939 #define GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_S 0 3940 #define GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_M MAKEMASK(0xF, 0) 3941 #define GLHMC_PERRFBASE(_i) (0x00526800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3942 #define GLHMC_PERRFBASE_MAX_INDEX 7 3943 #define GLHMC_PERRFBASE_GLHMC_PERRFBASE_S 0 3944 #define GLHMC_PERRFBASE_GLHMC_PERRFBASE_M MAKEMASK(0xFFFFFFFF, 0) 3945 #define GLHMC_PERRFCNT(_i) (0x00526900 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3946 #define GLHMC_PERRFCNT_MAX_INDEX 7 3947 #define GLHMC_PERRFCNT_GLHMC_PERRFCNT_S 0 3948 #define GLHMC_PERRFCNT_GLHMC_PERRFCNT_M MAKEMASK(0xFFFFFFFF, 0) 3949 #define GLHMC_PERRFFLBASE(_i) (0x00526A00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3950 #define GLHMC_PERRFFLBASE_MAX_INDEX 7 3951 #define GLHMC_PERRFFLBASE_GLHMC_PERRFFLBASE_S 0 3952 #define GLHMC_PERRFFLBASE_GLHMC_PERRFFLBASE_M MAKEMASK(0xFFFFFFFF, 0) 3953 #define GLHMC_PERRFFLCNT_PMAT(_i) (0x00526B00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3954 #define GLHMC_PERRFFLCNT_PMAT_MAX_INDEX 7 3955 #define GLHMC_PERRFFLCNT_PMAT_FPMPERRFFLCNT_S 0 3956 #define GLHMC_PERRFFLCNT_PMAT_FPMPERRFFLCNT_M MAKEMASK(0x1FFFFFFF, 0) 3957 #define GLHMC_PERRFFLMAX 0x005220A0 /* Reset Source: CORER */ 3958 #define GLHMC_PERRFFLMAX_PMPERRFFLMAX_S 0 3959 #define GLHMC_PERRFFLMAX_PMPERRFFLMAX_M MAKEMASK(0x3FFFFFF, 0) 3960 #define GLHMC_PERRFFLMAX_RSVD_S 26 3961 #define GLHMC_PERRFFLMAX_RSVD_M MAKEMASK(0x3F, 26) 3962 #define GLHMC_PERRFMAX 0x0052209C /* Reset Source: CORER */ 3963 #define GLHMC_PERRFMAX_PMPERRFMAX_S 0 3964 #define GLHMC_PERRFMAX_PMPERRFMAX_M MAKEMASK(0xFFFFFFF, 0) 3965 #define GLHMC_PERRFMAX_RSVD_S 28 3966 #define GLHMC_PERRFMAX_RSVD_M MAKEMASK(0xF, 28) 3967 #define GLHMC_PERRFOBJSZ 0x00522098 /* Reset Source: CORER */ 3968 #define GLHMC_PERRFOBJSZ_PMPERRFOBJSZ_S 0 3969 #define GLHMC_PERRFOBJSZ_PMPERRFOBJSZ_M MAKEMASK(0xF, 0) 3970 #define GLHMC_PERRFOBJSZ_RSVD_S 4 3971 #define GLHMC_PERRFOBJSZ_RSVD_M MAKEMASK(0xFFFFFFF, 4) 3972 #define GLHMC_PETIMERBASE(_i) (0x00525A00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3973 #define GLHMC_PETIMERBASE_MAX_INDEX 7 3974 #define GLHMC_PETIMERBASE_FPMPETIMERBASE_S 0 3975 #define GLHMC_PETIMERBASE_FPMPETIMERBASE_M MAKEMASK(0xFFFFFF, 0) 3976 #define GLHMC_PETIMERCNT(_i) (0x00525B00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3977 #define GLHMC_PETIMERCNT_MAX_INDEX 7 3978 #define GLHMC_PETIMERCNT_FPMPETIMERCNT_S 0 3979 #define GLHMC_PETIMERCNT_FPMPETIMERCNT_M MAKEMASK(0x1FFFFFFF, 0) 3980 #define GLHMC_PETIMERMAX 0x00522084 /* Reset Source: CORER */ 3981 #define GLHMC_PETIMERMAX_PMPETIMERMAX_S 0 3982 #define GLHMC_PETIMERMAX_PMPETIMERMAX_M MAKEMASK(0x1FFFFFFF, 0) 3983 #define GLHMC_PETIMEROBJSZ 0x00522080 /* Reset Source: CORER */ 3984 #define GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_S 0 3985 #define GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_M MAKEMASK(0xF, 0) 3986 #define GLHMC_PEXFBASE(_i) (0x00524E00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3987 #define GLHMC_PEXFBASE_MAX_INDEX 7 3988 #define GLHMC_PEXFBASE_FPMPEXFBASE_S 0 3989 #define GLHMC_PEXFBASE_FPMPEXFBASE_M MAKEMASK(0xFFFFFF, 0) 3990 #define GLHMC_PEXFCNT(_i) (0x00524F00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3991 #define GLHMC_PEXFCNT_MAX_INDEX 7 3992 #define GLHMC_PEXFCNT_FPMPEXFCNT_S 0 3993 #define GLHMC_PEXFCNT_FPMPEXFCNT_M MAKEMASK(0x1FFFFFFF, 0) 3994 #define GLHMC_PEXFFLBASE(_i) (0x00525000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 3995 #define GLHMC_PEXFFLBASE_MAX_INDEX 7 3996 #define GLHMC_PEXFFLBASE_FPMPEXFFLBASE_S 0 3997 #define GLHMC_PEXFFLBASE_FPMPEXFFLBASE_M MAKEMASK(0xFFFFFF, 0) 3998 #define GLHMC_PEXFFLMAX 0x0052204C /* Reset Source: CORER */ 3999 #define GLHMC_PEXFFLMAX_PMPEXFFLMAX_S 0 4000 #define GLHMC_PEXFFLMAX_PMPEXFFLMAX_M MAKEMASK(0xFFFFFFF, 0) 4001 #define GLHMC_PEXFMAX 0x00522048 /* Reset Source: CORER */ 4002 #define GLHMC_PEXFMAX_PMPEXFMAX_S 0 4003 #define GLHMC_PEXFMAX_PMPEXFMAX_M MAKEMASK(0xFFFFFFF, 0) 4004 #define GLHMC_PEXFOBJSZ 0x00522044 /* Reset Source: CORER */ 4005 #define GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_S 0 4006 #define GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_M MAKEMASK(0xF, 0) 4007 #define GLHMC_PFPESDPART(_i) (0x00520880 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 4008 #define GLHMC_PFPESDPART_MAX_INDEX 7 4009 #define GLHMC_PFPESDPART_PMSDBASE_S 0 4010 #define GLHMC_PFPESDPART_PMSDBASE_M MAKEMASK(0xFFF, 0) 4011 #define GLHMC_PFPESDPART_PMSDSIZE_S 16 4012 #define GLHMC_PFPESDPART_PMSDSIZE_M MAKEMASK(0x1FFF, 16) 4013 #define GLHMC_PFPESDPART_FPMAT(_i) (0x00100880 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 4014 #define GLHMC_PFPESDPART_FPMAT_MAX_INDEX 7 4015 #define GLHMC_PFPESDPART_FPMAT_PMSDBASE_S 0 4016 #define GLHMC_PFPESDPART_FPMAT_PMSDBASE_M MAKEMASK(0xFFF, 0) 4017 #define GLHMC_PFPESDPART_FPMAT_PMSDSIZE_S 16 4018 #define GLHMC_PFPESDPART_FPMAT_PMSDSIZE_M MAKEMASK(0x1FFF, 16) 4019 #define GLHMC_SDPART(_i) (0x00520800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 4020 #define GLHMC_SDPART_MAX_INDEX 7 4021 #define GLHMC_SDPART_PMSDBASE_S 0 4022 #define GLHMC_SDPART_PMSDBASE_M MAKEMASK(0xFFF, 0) 4023 #define GLHMC_SDPART_PMSDSIZE_S 16 4024 #define GLHMC_SDPART_PMSDSIZE_M MAKEMASK(0x1FFF, 16) 4025 #define GLHMC_SDPART_FPMAT(_i) (0x00100800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 4026 #define GLHMC_SDPART_FPMAT_MAX_INDEX 7 4027 #define GLHMC_SDPART_FPMAT_PMSDBASE_S 0 4028 #define GLHMC_SDPART_FPMAT_PMSDBASE_M MAKEMASK(0xFFF, 0) 4029 #define GLHMC_SDPART_FPMAT_PMSDSIZE_S 16 4030 #define GLHMC_SDPART_FPMAT_PMSDSIZE_M MAKEMASK(0x1FFF, 16) 4031 #define GLHMC_VFAPBVTINUSEBASE(_i) (0x0052CA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4032 #define GLHMC_VFAPBVTINUSEBASE_MAX_INDEX 31 4033 #define GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_S 0 4034 #define GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_M MAKEMASK(0xFFFFFF, 0) 4035 #define GLHMC_VFCEQPART(_i) (0x00502F00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4036 #define GLHMC_VFCEQPART_MAX_INDEX 31 4037 #define GLHMC_VFCEQPART_PMCEQBASE_S 0 4038 #define GLHMC_VFCEQPART_PMCEQBASE_M MAKEMASK(0x3FF, 0) 4039 #define GLHMC_VFCEQPART_PMCEQSIZE_S 16 4040 #define GLHMC_VFCEQPART_PMCEQSIZE_M MAKEMASK(0x3FF, 16) 4041 #define GLHMC_VFDBCQPART(_i) (0x00502E00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4042 #define GLHMC_VFDBCQPART_MAX_INDEX 31 4043 #define GLHMC_VFDBCQPART_PMDBCQBASE_S 0 4044 #define GLHMC_VFDBCQPART_PMDBCQBASE_M MAKEMASK(0x3FFF, 0) 4045 #define GLHMC_VFDBCQPART_PMDBCQSIZE_S 16 4046 #define GLHMC_VFDBCQPART_PMDBCQSIZE_M MAKEMASK(0x7FFF, 16) 4047 #define GLHMC_VFDBQPPART(_i) (0x00504520 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4048 #define GLHMC_VFDBQPPART_MAX_INDEX 31 4049 #define GLHMC_VFDBQPPART_PMDBQPBASE_S 0 4050 #define GLHMC_VFDBQPPART_PMDBQPBASE_M MAKEMASK(0x3FFF, 0) 4051 #define GLHMC_VFDBQPPART_PMDBQPSIZE_S 16 4052 #define GLHMC_VFDBQPPART_PMDBQPSIZE_M MAKEMASK(0x7FFF, 16) 4053 #define GLHMC_VFFSIAVBASE(_i) (0x0052D600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4054 #define GLHMC_VFFSIAVBASE_MAX_INDEX 31 4055 #define GLHMC_VFFSIAVBASE_FPMFSIAVBASE_S 0 4056 #define GLHMC_VFFSIAVBASE_FPMFSIAVBASE_M MAKEMASK(0xFFFFFF, 0) 4057 #define GLHMC_VFFSIAVCNT(_i) (0x0052D700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4058 #define GLHMC_VFFSIAVCNT_MAX_INDEX 31 4059 #define GLHMC_VFFSIAVCNT_FPMFSIAVCNT_S 0 4060 #define GLHMC_VFFSIAVCNT_FPMFSIAVCNT_M MAKEMASK(0x1FFFFFFF, 0) 4061 #define GLHMC_VFFSIMCBASE(_i) (0x0052E000 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4062 #define GLHMC_VFFSIMCBASE_MAX_INDEX 31 4063 #define GLHMC_VFFSIMCBASE_FPMFSIMCBASE_S 0 4064 #define GLHMC_VFFSIMCBASE_FPMFSIMCBASE_M MAKEMASK(0xFFFFFF, 0) 4065 #define GLHMC_VFFSIMCCNT(_i) (0x0052E100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4066 #define GLHMC_VFFSIMCCNT_MAX_INDEX 31 4067 #define GLHMC_VFFSIMCCNT_FPMFSIMCSZ_S 0 4068 #define GLHMC_VFFSIMCCNT_FPMFSIMCSZ_M MAKEMASK(0x1FFFFFFF, 0) 4069 #define GLHMC_VFPDINV(_i) (0x00528300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4070 #define GLHMC_VFPDINV_MAX_INDEX 31 4071 #define GLHMC_VFPDINV_PMSDIDX_S 0 4072 #define GLHMC_VFPDINV_PMSDIDX_M MAKEMASK(0xFFF, 0) 4073 #define GLHMC_VFPDINV_PMSDPARTSEL_S 15 4074 #define GLHMC_VFPDINV_PMSDPARTSEL_M BIT(15) 4075 #define GLHMC_VFPDINV_PMPDIDX_S 16 4076 #define GLHMC_VFPDINV_PMPDIDX_M MAKEMASK(0x1FF, 16) 4077 #define GLHMC_VFPDINV_FPMAT(_i) (0x00108300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4078 #define GLHMC_VFPDINV_FPMAT_MAX_INDEX 31 4079 #define GLHMC_VFPDINV_FPMAT_PMSDIDX_S 0 4080 #define GLHMC_VFPDINV_FPMAT_PMSDIDX_M MAKEMASK(0xFFF, 0) 4081 #define GLHMC_VFPDINV_FPMAT_PMSDPARTSEL_S 15 4082 #define GLHMC_VFPDINV_FPMAT_PMSDPARTSEL_M BIT(15) 4083 #define GLHMC_VFPDINV_FPMAT_PMPDIDX_S 16 4084 #define GLHMC_VFPDINV_FPMAT_PMPDIDX_M MAKEMASK(0x1FF, 16) 4085 #define GLHMC_VFPEARPBASE(_i) (0x0052C800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4086 #define GLHMC_VFPEARPBASE_MAX_INDEX 31 4087 #define GLHMC_VFPEARPBASE_FPMPEARPBASE_S 0 4088 #define GLHMC_VFPEARPBASE_FPMPEARPBASE_M MAKEMASK(0xFFFFFF, 0) 4089 #define GLHMC_VFPEARPCNT(_i) (0x0052C900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4090 #define GLHMC_VFPEARPCNT_MAX_INDEX 31 4091 #define GLHMC_VFPEARPCNT_FPMPEARPCNT_S 0 4092 #define GLHMC_VFPEARPCNT_FPMPEARPCNT_M MAKEMASK(0x1FFFFFFF, 0) 4093 #define GLHMC_VFPECQBASE(_i) (0x0052C200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4094 #define GLHMC_VFPECQBASE_MAX_INDEX 31 4095 #define GLHMC_VFPECQBASE_FPMPECQBASE_S 0 4096 #define GLHMC_VFPECQBASE_FPMPECQBASE_M MAKEMASK(0xFFFFFF, 0) 4097 #define GLHMC_VFPECQCNT(_i) (0x0052C300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4098 #define GLHMC_VFPECQCNT_MAX_INDEX 31 4099 #define GLHMC_VFPECQCNT_FPMPECQCNT_S 0 4100 #define GLHMC_VFPECQCNT_FPMPECQCNT_M MAKEMASK(0x1FFFFFFF, 0) 4101 #define GLHMC_VFPEHDRBASE(_i) (0x0052E200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4102 #define GLHMC_VFPEHDRBASE_MAX_INDEX 31 4103 #define GLHMC_VFPEHDRBASE_GLHMC_PEHDRBASE_S 0 4104 #define GLHMC_VFPEHDRBASE_GLHMC_PEHDRBASE_M MAKEMASK(0xFFFFFFFF, 0) 4105 #define GLHMC_VFPEHDRCNT(_i) (0x0052E300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4106 #define GLHMC_VFPEHDRCNT_MAX_INDEX 31 4107 #define GLHMC_VFPEHDRCNT_GLHMC_PEHDRCNT_S 0 4108 #define GLHMC_VFPEHDRCNT_GLHMC_PEHDRCNT_M MAKEMASK(0xFFFFFFFF, 0) 4109 #define GLHMC_VFPEHTCNT(_i) (0x0052C700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4110 #define GLHMC_VFPEHTCNT_MAX_INDEX 31 4111 #define GLHMC_VFPEHTCNT_FPMPEHTCNT_S 0 4112 #define GLHMC_VFPEHTCNT_FPMPEHTCNT_M MAKEMASK(0x1FFFFFFF, 0) 4113 #define GLHMC_VFPEHTCNT_FPMAT(_i) (0x0010C700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4114 #define GLHMC_VFPEHTCNT_FPMAT_MAX_INDEX 31 4115 #define GLHMC_VFPEHTCNT_FPMAT_FPMPEHTCNT_S 0 4116 #define GLHMC_VFPEHTCNT_FPMAT_FPMPEHTCNT_M MAKEMASK(0x1FFFFFFF, 0) 4117 #define GLHMC_VFPEHTEBASE(_i) (0x0052C600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4118 #define GLHMC_VFPEHTEBASE_MAX_INDEX 31 4119 #define GLHMC_VFPEHTEBASE_FPMPEHTEBASE_S 0 4120 #define GLHMC_VFPEHTEBASE_FPMPEHTEBASE_M MAKEMASK(0xFFFFFF, 0) 4121 #define GLHMC_VFPEHTEBASE_FPMAT(_i) (0x0010C600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4122 #define GLHMC_VFPEHTEBASE_FPMAT_MAX_INDEX 31 4123 #define GLHMC_VFPEHTEBASE_FPMAT_FPMPEHTEBASE_S 0 4124 #define GLHMC_VFPEHTEBASE_FPMAT_FPMPEHTEBASE_M MAKEMASK(0xFFFFFF, 0) 4125 #define GLHMC_VFPEMDBASE(_i) (0x0052E400 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4126 #define GLHMC_VFPEMDBASE_MAX_INDEX 31 4127 #define GLHMC_VFPEMDBASE_GLHMC_PEMDBASE_S 0 4128 #define GLHMC_VFPEMDBASE_GLHMC_PEMDBASE_M MAKEMASK(0xFFFFFFFF, 0) 4129 #define GLHMC_VFPEMDCNT(_i) (0x0052E500 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4130 #define GLHMC_VFPEMDCNT_MAX_INDEX 31 4131 #define GLHMC_VFPEMDCNT_GLHMC_PEMDCNT_S 0 4132 #define GLHMC_VFPEMDCNT_GLHMC_PEMDCNT_M MAKEMASK(0xFFFFFFFF, 0) 4133 #define GLHMC_VFPEMRBASE(_i) (0x0052CC00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4134 #define GLHMC_VFPEMRBASE_MAX_INDEX 31 4135 #define GLHMC_VFPEMRBASE_FPMPEMRBASE_S 0 4136 #define GLHMC_VFPEMRBASE_FPMPEMRBASE_M MAKEMASK(0xFFFFFF, 0) 4137 #define GLHMC_VFPEMRCNT(_i) (0x0052CD00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4138 #define GLHMC_VFPEMRCNT_MAX_INDEX 31 4139 #define GLHMC_VFPEMRCNT_FPMPEMRSZ_S 0 4140 #define GLHMC_VFPEMRCNT_FPMPEMRSZ_M MAKEMASK(0x1FFFFFFF, 0) 4141 #define GLHMC_VFPEOOISCBASE(_i) (0x0052E600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4142 #define GLHMC_VFPEOOISCBASE_MAX_INDEX 31 4143 #define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_S 0 4144 #define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_M MAKEMASK(0xFFFFFFFF, 0) 4145 #define GLHMC_VFPEOOISCCNT(_i) (0x0052E700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4146 #define GLHMC_VFPEOOISCCNT_MAX_INDEX 31 4147 #define GLHMC_VFPEOOISCCNT_GLHMC_PEOOISCCNT_S 0 4148 #define GLHMC_VFPEOOISCCNT_GLHMC_PEOOISCCNT_M MAKEMASK(0xFFFFFFFF, 0) 4149 #define GLHMC_VFPEOOISCFFLBASE(_i) (0x0052EC00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4150 #define GLHMC_VFPEOOISCFFLBASE_MAX_INDEX 31 4151 #define GLHMC_VFPEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_S 0 4152 #define GLHMC_VFPEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_M MAKEMASK(0xFFFFFFFF, 0) 4153 #define GLHMC_VFPEPBLBASE(_i) (0x0052D800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4154 #define GLHMC_VFPEPBLBASE_MAX_INDEX 31 4155 #define GLHMC_VFPEPBLBASE_FPMPEPBLBASE_S 0 4156 #define GLHMC_VFPEPBLBASE_FPMPEPBLBASE_M MAKEMASK(0xFFFFFF, 0) 4157 #define GLHMC_VFPEPBLCNT(_i) (0x0052D900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4158 #define GLHMC_VFPEPBLCNT_MAX_INDEX 31 4159 #define GLHMC_VFPEPBLCNT_FPMPEPBLCNT_S 0 4160 #define GLHMC_VFPEPBLCNT_FPMPEPBLCNT_M MAKEMASK(0x1FFFFFFF, 0) 4161 #define GLHMC_VFPEQ1BASE(_i) (0x0052D200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4162 #define GLHMC_VFPEQ1BASE_MAX_INDEX 31 4163 #define GLHMC_VFPEQ1BASE_FPMPEQ1BASE_S 0 4164 #define GLHMC_VFPEQ1BASE_FPMPEQ1BASE_M MAKEMASK(0xFFFFFF, 0) 4165 #define GLHMC_VFPEQ1CNT(_i) (0x0052D300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4166 #define GLHMC_VFPEQ1CNT_MAX_INDEX 31 4167 #define GLHMC_VFPEQ1CNT_FPMPEQ1CNT_S 0 4168 #define GLHMC_VFPEQ1CNT_FPMPEQ1CNT_M MAKEMASK(0x1FFFFFFF, 0) 4169 #define GLHMC_VFPEQ1FLBASE(_i) (0x0052D400 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4170 #define GLHMC_VFPEQ1FLBASE_MAX_INDEX 31 4171 #define GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_S 0 4172 #define GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_M MAKEMASK(0xFFFFFF, 0) 4173 #define GLHMC_VFPEQPBASE(_i) (0x0052C000 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4174 #define GLHMC_VFPEQPBASE_MAX_INDEX 31 4175 #define GLHMC_VFPEQPBASE_FPMPEQPBASE_S 0 4176 #define GLHMC_VFPEQPBASE_FPMPEQPBASE_M MAKEMASK(0xFFFFFF, 0) 4177 #define GLHMC_VFPEQPCNT(_i) (0x0052C100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4178 #define GLHMC_VFPEQPCNT_MAX_INDEX 31 4179 #define GLHMC_VFPEQPCNT_FPMPEQPCNT_S 0 4180 #define GLHMC_VFPEQPCNT_FPMPEQPCNT_M MAKEMASK(0x1FFFFFFF, 0) 4181 #define GLHMC_VFPERRFBASE(_i) (0x0052E800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4182 #define GLHMC_VFPERRFBASE_MAX_INDEX 31 4183 #define GLHMC_VFPERRFBASE_GLHMC_PERRFBASE_S 0 4184 #define GLHMC_VFPERRFBASE_GLHMC_PERRFBASE_M MAKEMASK(0xFFFFFFFF, 0) 4185 #define GLHMC_VFPERRFCNT(_i) (0x0052E900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4186 #define GLHMC_VFPERRFCNT_MAX_INDEX 31 4187 #define GLHMC_VFPERRFCNT_GLHMC_PERRFCNT_S 0 4188 #define GLHMC_VFPERRFCNT_GLHMC_PERRFCNT_M MAKEMASK(0xFFFFFFFF, 0) 4189 #define GLHMC_VFPERRFFLBASE(_i) (0x0052EA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4190 #define GLHMC_VFPERRFFLBASE_MAX_INDEX 31 4191 #define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_S 0 4192 #define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_M MAKEMASK(0xFFFFFFFF, 0) 4193 #define GLHMC_VFPETIMERBASE(_i) (0x0052DA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4194 #define GLHMC_VFPETIMERBASE_MAX_INDEX 31 4195 #define GLHMC_VFPETIMERBASE_FPMPETIMERBASE_S 0 4196 #define GLHMC_VFPETIMERBASE_FPMPETIMERBASE_M MAKEMASK(0xFFFFFF, 0) 4197 #define GLHMC_VFPETIMERCNT(_i) (0x0052DB00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4198 #define GLHMC_VFPETIMERCNT_MAX_INDEX 31 4199 #define GLHMC_VFPETIMERCNT_FPMPETIMERCNT_S 0 4200 #define GLHMC_VFPETIMERCNT_FPMPETIMERCNT_M MAKEMASK(0x1FFFFFFF, 0) 4201 #define GLHMC_VFPEXFBASE(_i) (0x0052CE00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4202 #define GLHMC_VFPEXFBASE_MAX_INDEX 31 4203 #define GLHMC_VFPEXFBASE_FPMPEXFBASE_S 0 4204 #define GLHMC_VFPEXFBASE_FPMPEXFBASE_M MAKEMASK(0xFFFFFF, 0) 4205 #define GLHMC_VFPEXFCNT(_i) (0x0052CF00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4206 #define GLHMC_VFPEXFCNT_MAX_INDEX 31 4207 #define GLHMC_VFPEXFCNT_FPMPEXFCNT_S 0 4208 #define GLHMC_VFPEXFCNT_FPMPEXFCNT_M MAKEMASK(0x1FFFFFFF, 0) 4209 #define GLHMC_VFPEXFFLBASE(_i) (0x0052D000 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4210 #define GLHMC_VFPEXFFLBASE_MAX_INDEX 31 4211 #define GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_S 0 4212 #define GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_M MAKEMASK(0xFFFFFF, 0) 4213 #define GLHMC_VFSDDATAHIGH(_i) (0x00528200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4214 #define GLHMC_VFSDDATAHIGH_MAX_INDEX 31 4215 #define GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_S 0 4216 #define GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0) 4217 #define GLHMC_VFSDDATAHIGH_FPMAT(_i) (0x00108200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4218 #define GLHMC_VFSDDATAHIGH_FPMAT_MAX_INDEX 31 4219 #define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0 4220 #define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0) 4221 #define GLHMC_VFSDDATALOW(_i) (0x00528100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4222 #define GLHMC_VFSDDATALOW_MAX_INDEX 31 4223 #define GLHMC_VFSDDATALOW_PMSDVALID_S 0 4224 #define GLHMC_VFSDDATALOW_PMSDVALID_M BIT(0) 4225 #define GLHMC_VFSDDATALOW_PMSDTYPE_S 1 4226 #define GLHMC_VFSDDATALOW_PMSDTYPE_M BIT(1) 4227 #define GLHMC_VFSDDATALOW_PMSDBPCOUNT_S 2 4228 #define GLHMC_VFSDDATALOW_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2) 4229 #define GLHMC_VFSDDATALOW_PMSDDATALOW_S 12 4230 #define GLHMC_VFSDDATALOW_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12) 4231 #define GLHMC_VFSDDATALOW_FPMAT(_i) (0x00108100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4232 #define GLHMC_VFSDDATALOW_FPMAT_MAX_INDEX 31 4233 #define GLHMC_VFSDDATALOW_FPMAT_PMSDVALID_S 0 4234 #define GLHMC_VFSDDATALOW_FPMAT_PMSDVALID_M BIT(0) 4235 #define GLHMC_VFSDDATALOW_FPMAT_PMSDTYPE_S 1 4236 #define GLHMC_VFSDDATALOW_FPMAT_PMSDTYPE_M BIT(1) 4237 #define GLHMC_VFSDDATALOW_FPMAT_PMSDBPCOUNT_S 2 4238 #define GLHMC_VFSDDATALOW_FPMAT_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2) 4239 #define GLHMC_VFSDDATALOW_FPMAT_PMSDDATALOW_S 12 4240 #define GLHMC_VFSDDATALOW_FPMAT_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12) 4241 #define GLHMC_VFSDPART(_i) (0x00528800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4242 #define GLHMC_VFSDPART_MAX_INDEX 31 4243 #define GLHMC_VFSDPART_PMSDBASE_S 0 4244 #define GLHMC_VFSDPART_PMSDBASE_M MAKEMASK(0xFFF, 0) 4245 #define GLHMC_VFSDPART_PMSDSIZE_S 16 4246 #define GLHMC_VFSDPART_PMSDSIZE_M MAKEMASK(0x1FFF, 16) 4247 #define GLHMC_VFSDPART_FPMAT(_i) (0x00108800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 4248 #define GLHMC_VFSDPART_FPMAT_MAX_INDEX 31 4249 #define GLHMC_VFSDPART_FPMAT_PMSDBASE_S 0 4250 #define GLHMC_VFSDPART_FPMAT_PMSDBASE_M MAKEMASK(0xFFF, 0) 4251 #define GLHMC_VFSDPART_FPMAT_PMSDSIZE_S 16 4252 #define GLHMC_VFSDPART_FPMAT_PMSDSIZE_M MAKEMASK(0x1FFF, 16) 4253 #define GLMDOC_CACHESIZE 0x0051C06C /* Reset Source: CORER */ 4254 #define GLMDOC_CACHESIZE_WORD_SIZE_S 0 4255 #define GLMDOC_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0) 4256 #define GLMDOC_CACHESIZE_SETS_S 8 4257 #define GLMDOC_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8) 4258 #define GLMDOC_CACHESIZE_WAYS_S 20 4259 #define GLMDOC_CACHESIZE_WAYS_M MAKEMASK(0xF, 20) 4260 #define GLPBLOC0_CACHESIZE 0x00518074 /* Reset Source: CORER */ 4261 #define GLPBLOC0_CACHESIZE_WORD_SIZE_S 0 4262 #define GLPBLOC0_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0) 4263 #define GLPBLOC0_CACHESIZE_SETS_S 8 4264 #define GLPBLOC0_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8) 4265 #define GLPBLOC0_CACHESIZE_WAYS_S 20 4266 #define GLPBLOC0_CACHESIZE_WAYS_M MAKEMASK(0xF, 20) 4267 #define GLPBLOC1_CACHESIZE 0x0051A074 /* Reset Source: CORER */ 4268 #define GLPBLOC1_CACHESIZE_WORD_SIZE_S 0 4269 #define GLPBLOC1_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0) 4270 #define GLPBLOC1_CACHESIZE_SETS_S 8 4271 #define GLPBLOC1_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8) 4272 #define GLPBLOC1_CACHESIZE_WAYS_S 20 4273 #define GLPBLOC1_CACHESIZE_WAYS_M MAKEMASK(0xF, 20) 4274 #define GLPDOC_CACHESIZE 0x00530048 /* Reset Source: CORER */ 4275 #define GLPDOC_CACHESIZE_WORD_SIZE_S 0 4276 #define GLPDOC_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0) 4277 #define GLPDOC_CACHESIZE_SETS_S 8 4278 #define GLPDOC_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8) 4279 #define GLPDOC_CACHESIZE_WAYS_S 20 4280 #define GLPDOC_CACHESIZE_WAYS_M MAKEMASK(0xF, 20) 4281 #define GLPDOC_CACHESIZE_FPMAT 0x00110088 /* Reset Source: CORER */ 4282 #define GLPDOC_CACHESIZE_FPMAT_WORD_SIZE_S 0 4283 #define GLPDOC_CACHESIZE_FPMAT_WORD_SIZE_M MAKEMASK(0xFF, 0) 4284 #define GLPDOC_CACHESIZE_FPMAT_SETS_S 8 4285 #define GLPDOC_CACHESIZE_FPMAT_SETS_M MAKEMASK(0xFFF, 8) 4286 #define GLPDOC_CACHESIZE_FPMAT_WAYS_S 20 4287 #define GLPDOC_CACHESIZE_FPMAT_WAYS_M MAKEMASK(0xF, 20) 4288 #define GLPEOC0_CACHESIZE 0x005140A8 /* Reset Source: CORER */ 4289 #define GLPEOC0_CACHESIZE_WORD_SIZE_S 0 4290 #define GLPEOC0_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0) 4291 #define GLPEOC0_CACHESIZE_SETS_S 8 4292 #define GLPEOC0_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8) 4293 #define GLPEOC0_CACHESIZE_WAYS_S 20 4294 #define GLPEOC0_CACHESIZE_WAYS_M MAKEMASK(0xF, 20) 4295 #define GLPEOC1_CACHESIZE 0x005160A8 /* Reset Source: CORER */ 4296 #define GLPEOC1_CACHESIZE_WORD_SIZE_S 0 4297 #define GLPEOC1_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0) 4298 #define GLPEOC1_CACHESIZE_SETS_S 8 4299 #define GLPEOC1_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8) 4300 #define GLPEOC1_CACHESIZE_WAYS_S 20 4301 #define GLPEOC1_CACHESIZE_WAYS_M MAKEMASK(0xF, 20) 4302 #define PFHMC_ERRORDATA 0x00520500 /* Reset Source: PFR */ 4303 #define PFHMC_ERRORDATA_HMC_ERROR_DATA_S 0 4304 #define PFHMC_ERRORDATA_HMC_ERROR_DATA_M MAKEMASK(0x3FFFFFFF, 0) 4305 #define PFHMC_ERRORDATA_FPMAT 0x00100500 /* Reset Source: PFR */ 4306 #define PFHMC_ERRORDATA_FPMAT_HMC_ERROR_DATA_S 0 4307 #define PFHMC_ERRORDATA_FPMAT_HMC_ERROR_DATA_M MAKEMASK(0x3FFFFFFF, 0) 4308 #define PFHMC_ERRORINFO 0x00520400 /* Reset Source: PFR */ 4309 #define PFHMC_ERRORINFO_PMF_INDEX_S 0 4310 #define PFHMC_ERRORINFO_PMF_INDEX_M MAKEMASK(0x1F, 0) 4311 #define PFHMC_ERRORINFO_PMF_ISVF_S 7 4312 #define PFHMC_ERRORINFO_PMF_ISVF_M BIT(7) 4313 #define PFHMC_ERRORINFO_HMC_ERROR_TYPE_S 8 4314 #define PFHMC_ERRORINFO_HMC_ERROR_TYPE_M MAKEMASK(0xF, 8) 4315 #define PFHMC_ERRORINFO_HMC_OBJECT_TYPE_S 16 4316 #define PFHMC_ERRORINFO_HMC_OBJECT_TYPE_M MAKEMASK(0x1F, 16) 4317 #define PFHMC_ERRORINFO_ERROR_DETECTED_S 31 4318 #define PFHMC_ERRORINFO_ERROR_DETECTED_M BIT(31) 4319 #define PFHMC_ERRORINFO_FPMAT 0x00100400 /* Reset Source: PFR */ 4320 #define PFHMC_ERRORINFO_FPMAT_PMF_INDEX_S 0 4321 #define PFHMC_ERRORINFO_FPMAT_PMF_INDEX_M MAKEMASK(0x1F, 0) 4322 #define PFHMC_ERRORINFO_FPMAT_PMF_ISVF_S 7 4323 #define PFHMC_ERRORINFO_FPMAT_PMF_ISVF_M BIT(7) 4324 #define PFHMC_ERRORINFO_FPMAT_HMC_ERROR_TYPE_S 8 4325 #define PFHMC_ERRORINFO_FPMAT_HMC_ERROR_TYPE_M MAKEMASK(0xF, 8) 4326 #define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_S 16 4327 #define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_M MAKEMASK(0x1F, 16) 4328 #define PFHMC_ERRORINFO_FPMAT_ERROR_DETECTED_S 31 4329 #define PFHMC_ERRORINFO_FPMAT_ERROR_DETECTED_M BIT(31) 4330 #define PFHMC_PDINV 0x00520300 /* Reset Source: PFR */ 4331 #define PFHMC_PDINV_PMSDIDX_S 0 4332 #define PFHMC_PDINV_PMSDIDX_M MAKEMASK(0xFFF, 0) 4333 #define PFHMC_PDINV_PMSDPARTSEL_S 15 4334 #define PFHMC_PDINV_PMSDPARTSEL_M BIT(15) 4335 #define PFHMC_PDINV_PMPDIDX_S 16 4336 #define PFHMC_PDINV_PMPDIDX_M MAKEMASK(0x1FF, 16) 4337 #define PFHMC_PDINV_FPMAT 0x00100300 /* Reset Source: PFR */ 4338 #define PFHMC_PDINV_FPMAT_PMSDIDX_S 0 4339 #define PFHMC_PDINV_FPMAT_PMSDIDX_M MAKEMASK(0xFFF, 0) 4340 #define PFHMC_PDINV_FPMAT_PMSDPARTSEL_S 15 4341 #define PFHMC_PDINV_FPMAT_PMSDPARTSEL_M BIT(15) 4342 #define PFHMC_PDINV_FPMAT_PMPDIDX_S 16 4343 #define PFHMC_PDINV_FPMAT_PMPDIDX_M MAKEMASK(0x1FF, 16) 4344 #define PFHMC_SDCMD 0x00520000 /* Reset Source: PFR */ 4345 #define PFHMC_SDCMD_PMSDIDX_S 0 4346 #define PFHMC_SDCMD_PMSDIDX_M MAKEMASK(0xFFF, 0) 4347 #define PFHMC_SDCMD_PMSDPARTSEL_S 15 4348 #define PFHMC_SDCMD_PMSDPARTSEL_M BIT(15) 4349 #define PFHMC_SDCMD_PMSDWR_S 31 4350 #define PFHMC_SDCMD_PMSDWR_M BIT(31) 4351 #define PFHMC_SDCMD_FPMAT 0x00100000 /* Reset Source: PFR */ 4352 #define PFHMC_SDCMD_FPMAT_PMSDIDX_S 0 4353 #define PFHMC_SDCMD_FPMAT_PMSDIDX_M MAKEMASK(0xFFF, 0) 4354 #define PFHMC_SDCMD_FPMAT_PMSDPARTSEL_S 15 4355 #define PFHMC_SDCMD_FPMAT_PMSDPARTSEL_M BIT(15) 4356 #define PFHMC_SDCMD_FPMAT_PMSDWR_S 31 4357 #define PFHMC_SDCMD_FPMAT_PMSDWR_M BIT(31) 4358 #define PFHMC_SDDATAHIGH 0x00520200 /* Reset Source: PFR */ 4359 #define PFHMC_SDDATAHIGH_PMSDDATAHIGH_S 0 4360 #define PFHMC_SDDATAHIGH_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0) 4361 #define PFHMC_SDDATAHIGH_FPMAT 0x00100200 /* Reset Source: PFR */ 4362 #define PFHMC_SDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0 4363 #define PFHMC_SDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0) 4364 #define PFHMC_SDDATALOW 0x00520100 /* Reset Source: PFR */ 4365 #define PFHMC_SDDATALOW_PMSDVALID_S 0 4366 #define PFHMC_SDDATALOW_PMSDVALID_M BIT(0) 4367 #define PFHMC_SDDATALOW_PMSDTYPE_S 1 4368 #define PFHMC_SDDATALOW_PMSDTYPE_M BIT(1) 4369 #define PFHMC_SDDATALOW_PMSDBPCOUNT_S 2 4370 #define PFHMC_SDDATALOW_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2) 4371 #define PFHMC_SDDATALOW_PMSDDATALOW_S 12 4372 #define PFHMC_SDDATALOW_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12) 4373 #define PFHMC_SDDATALOW_FPMAT 0x00100100 /* Reset Source: PFR */ 4374 #define PFHMC_SDDATALOW_FPMAT_PMSDVALID_S 0 4375 #define PFHMC_SDDATALOW_FPMAT_PMSDVALID_M BIT(0) 4376 #define PFHMC_SDDATALOW_FPMAT_PMSDTYPE_S 1 4377 #define PFHMC_SDDATALOW_FPMAT_PMSDTYPE_M BIT(1) 4378 #define PFHMC_SDDATALOW_FPMAT_PMSDBPCOUNT_S 2 4379 #define PFHMC_SDDATALOW_FPMAT_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2) 4380 #define PFHMC_SDDATALOW_FPMAT_PMSDDATALOW_S 12 4381 #define PFHMC_SDDATALOW_FPMAT_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12) 4382 #define GL_DSI_REPC 0x00294208 /* Reset Source: CORER */ 4383 #define GL_DSI_REPC_NO_DESC_CNT_S 0 4384 #define GL_DSI_REPC_NO_DESC_CNT_M MAKEMASK(0xFFFF, 0) 4385 #define GL_DSI_REPC_ERROR_CNT_S 16 4386 #define GL_DSI_REPC_ERROR_CNT_M MAKEMASK(0xFFFF, 16) 4387 #define GL_MDCK_TDAT_TCLAN 0x000FC0DC /* Reset Source: CORER */ 4388 #define GL_MDCK_TDAT_TCLAN_WRONG_ORDER_FORMAT_DESC_S 0 4389 #define GL_MDCK_TDAT_TCLAN_WRONG_ORDER_FORMAT_DESC_M BIT(0) 4390 #define GL_MDCK_TDAT_TCLAN_UR_S 1 4391 #define GL_MDCK_TDAT_TCLAN_UR_M BIT(1) 4392 #define GL_MDCK_TDAT_TCLAN_TAIL_DESC_NOT_DDESC_EOP_NOP_S 2 4393 #define GL_MDCK_TDAT_TCLAN_TAIL_DESC_NOT_DDESC_EOP_NOP_M BIT(2) 4394 #define GL_MDCK_TDAT_TCLAN_FALSE_SCHEDULING_S 3 4395 #define GL_MDCK_TDAT_TCLAN_FALSE_SCHEDULING_M BIT(3) 4396 #define GL_MDCK_TDAT_TCLAN_TAIL_VALUE_BIGGER_THAN_RING_LEN_S 4 4397 #define GL_MDCK_TDAT_TCLAN_TAIL_VALUE_BIGGER_THAN_RING_LEN_M BIT(4) 4398 #define GL_MDCK_TDAT_TCLAN_MORE_THAN_8_DCMDS_IN_PKT_S 5 4399 #define GL_MDCK_TDAT_TCLAN_MORE_THAN_8_DCMDS_IN_PKT_M BIT(5) 4400 #define GL_MDCK_TDAT_TCLAN_NO_HEAD_UPDATE_IN_QUANTA_S 6 4401 #define GL_MDCK_TDAT_TCLAN_NO_HEAD_UPDATE_IN_QUANTA_M BIT(6) 4402 #define GL_MDCK_TDAT_TCLAN_PKT_LEN_NOT_LEGAL_S 7 4403 #define GL_MDCK_TDAT_TCLAN_PKT_LEN_NOT_LEGAL_M BIT(7) 4404 #define GL_MDCK_TDAT_TCLAN_TSO_TLEN_NOT_COHERENT_WITH_SUM_BUFS_S 8 4405 #define GL_MDCK_TDAT_TCLAN_TSO_TLEN_NOT_COHERENT_WITH_SUM_BUFS_M BIT(8) 4406 #define GL_MDCK_TDAT_TCLAN_TSO_TAIL_REACHED_BEFORE_TLEN_END_S 9 4407 #define GL_MDCK_TDAT_TCLAN_TSO_TAIL_REACHED_BEFORE_TLEN_END_M BIT(9) 4408 #define GL_MDCK_TDAT_TCLAN_TSO_MORE_THAN_3_HDRS_S 10 4409 #define GL_MDCK_TDAT_TCLAN_TSO_MORE_THAN_3_HDRS_M BIT(10) 4410 #define GL_MDCK_TDAT_TCLAN_TSO_SUM_BUFFS_LT_SUM_HDRS_S 11 4411 #define GL_MDCK_TDAT_TCLAN_TSO_SUM_BUFFS_LT_SUM_HDRS_M BIT(11) 4412 #define GL_MDCK_TDAT_TCLAN_TSO_ZERO_MSS_TLEN_HDRS_S 12 4413 #define GL_MDCK_TDAT_TCLAN_TSO_ZERO_MSS_TLEN_HDRS_M BIT(12) 4414 #define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_S 13 4415 #define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_M BIT(13) 4416 #define GL_MDCK_TDAT_TCLAN_SSO_COMS_NOT_WHOLE_PKT_NUM_IN_QUANTA_S 14 4417 #define GL_MDCK_TDAT_TCLAN_SSO_COMS_NOT_WHOLE_PKT_NUM_IN_QUANTA_M BIT(14) 4418 #define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_BYTES_EXCEED_PKTLEN_X_64_S 15 4419 #define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_BYTES_EXCEED_PKTLEN_X_64_M BIT(15) 4420 #define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_CMDS_EXCEED_S 16 4421 #define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_CMDS_EXCEED_M BIT(16) 4422 #define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_LAST_LSO_QUANTA_S 17 4423 #define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_LAST_LSO_QUANTA_M BIT(17) 4424 #define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_TLEN_S 18 4425 #define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_TLEN_M BIT(18) 4426 #define GL_MDCK_TDAT_TCLAN_TSO_COMS_QUANTA_FINISHED_TOO_EARLY_S 19 4427 #define GL_MDCK_TDAT_TCLAN_TSO_COMS_QUANTA_FINISHED_TOO_EARLY_M BIT(19) 4428 #define GL_MDCK_TDAT_TCLAN_COMS_NUM_PKTS_IN_QUANTA_S 20 4429 #define GL_MDCK_TDAT_TCLAN_COMS_NUM_PKTS_IN_QUANTA_M BIT(20) 4430 #define GLCORE_CLKCTL_H 0x000B81E8 /* Reset Source: POR */ 4431 #define GLCORE_CLKCTL_H_UPPER_CLK_SRC_H_S 0 4432 #define GLCORE_CLKCTL_H_UPPER_CLK_SRC_H_M MAKEMASK(0x3, 0) 4433 #define GLCORE_CLKCTL_H_LOWER_CLK_SRC_H_S 2 4434 #define GLCORE_CLKCTL_H_LOWER_CLK_SRC_H_M MAKEMASK(0x3, 2) 4435 #define GLCORE_CLKCTL_H_PSM_CLK_SRC_H_S 4 4436 #define GLCORE_CLKCTL_H_PSM_CLK_SRC_H_M MAKEMASK(0x3, 4) 4437 #define GLCORE_CLKCTL_H_RXCTL_CLK_SRC_H_S 6 4438 #define GLCORE_CLKCTL_H_RXCTL_CLK_SRC_H_M MAKEMASK(0x3, 6) 4439 #define GLCORE_CLKCTL_H_UANA_CLK_SRC_H_S 8 4440 #define GLCORE_CLKCTL_H_UANA_CLK_SRC_H_M MAKEMASK(0x7, 8) 4441 #define GLCORE_CLKCTL_L 0x000B8254 /* Reset Source: POR */ 4442 #define GLCORE_CLKCTL_L_UPPER_CLK_SRC_L_S 0 4443 #define GLCORE_CLKCTL_L_UPPER_CLK_SRC_L_M MAKEMASK(0x3, 0) 4444 #define GLCORE_CLKCTL_L_LOWER_CLK_SRC_L_S 2 4445 #define GLCORE_CLKCTL_L_LOWER_CLK_SRC_L_M MAKEMASK(0x3, 2) 4446 #define GLCORE_CLKCTL_L_PSM_CLK_SRC_L_S 4 4447 #define GLCORE_CLKCTL_L_PSM_CLK_SRC_L_M MAKEMASK(0x3, 4) 4448 #define GLCORE_CLKCTL_L_RXCTL_CLK_SRC_L_S 6 4449 #define GLCORE_CLKCTL_L_RXCTL_CLK_SRC_L_M MAKEMASK(0x3, 6) 4450 #define GLCORE_CLKCTL_L_UANA_CLK_SRC_L_S 8 4451 #define GLCORE_CLKCTL_L_UANA_CLK_SRC_L_M MAKEMASK(0x7, 8) 4452 #define GLCORE_CLKCTL_M 0x000B8258 /* Reset Source: POR */ 4453 #define GLCORE_CLKCTL_M_UPPER_CLK_SRC_M_S 0 4454 #define GLCORE_CLKCTL_M_UPPER_CLK_SRC_M_M MAKEMASK(0x3, 0) 4455 #define GLCORE_CLKCTL_M_LOWER_CLK_SRC_M_S 2 4456 #define GLCORE_CLKCTL_M_LOWER_CLK_SRC_M_M MAKEMASK(0x3, 2) 4457 #define GLCORE_CLKCTL_M_PSM_CLK_SRC_M_S 4 4458 #define GLCORE_CLKCTL_M_PSM_CLK_SRC_M_M MAKEMASK(0x3, 4) 4459 #define GLCORE_CLKCTL_M_RXCTL_CLK_SRC_M_S 6 4460 #define GLCORE_CLKCTL_M_RXCTL_CLK_SRC_M_M MAKEMASK(0x3, 6) 4461 #define GLCORE_CLKCTL_M_UANA_CLK_SRC_M_S 8 4462 #define GLCORE_CLKCTL_M_UANA_CLK_SRC_M_M MAKEMASK(0x7, 8) 4463 #define GLFOC_CACHESIZE 0x000AA074 /* Reset Source: CORER */ 4464 #define GLFOC_CACHESIZE_WORD_SIZE_S 0 4465 #define GLFOC_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0) 4466 #define GLFOC_CACHESIZE_SETS_S 8 4467 #define GLFOC_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8) 4468 #define GLFOC_CACHESIZE_WAYS_S 20 4469 #define GLFOC_CACHESIZE_WAYS_M MAKEMASK(0xF, 20) 4470 #define GLMAC_CLKSTAT 0x000B8210 /* Reset Source: POR */ 4471 #define GLMAC_CLKSTAT_P0_CLK_SPEED_S 0 4472 #define GLMAC_CLKSTAT_P0_CLK_SPEED_M MAKEMASK(0xF, 0) 4473 #define GLMAC_CLKSTAT_P1_CLK_SPEED_S 4 4474 #define GLMAC_CLKSTAT_P1_CLK_SPEED_M MAKEMASK(0xF, 4) 4475 #define GLMAC_CLKSTAT_P2_CLK_SPEED_S 8 4476 #define GLMAC_CLKSTAT_P2_CLK_SPEED_M MAKEMASK(0xF, 8) 4477 #define GLMAC_CLKSTAT_P3_CLK_SPEED_S 12 4478 #define GLMAC_CLKSTAT_P3_CLK_SPEED_M MAKEMASK(0xF, 12) 4479 #define GLMAC_CLKSTAT_P4_CLK_SPEED_S 16 4480 #define GLMAC_CLKSTAT_P4_CLK_SPEED_M MAKEMASK(0xF, 16) 4481 #define GLMAC_CLKSTAT_P5_CLK_SPEED_S 20 4482 #define GLMAC_CLKSTAT_P5_CLK_SPEED_M MAKEMASK(0xF, 20) 4483 #define GLMAC_CLKSTAT_P6_CLK_SPEED_S 24 4484 #define GLMAC_CLKSTAT_P6_CLK_SPEED_M MAKEMASK(0xF, 24) 4485 #define GLMAC_CLKSTAT_P7_CLK_SPEED_S 28 4486 #define GLMAC_CLKSTAT_P7_CLK_SPEED_M MAKEMASK(0xF, 28) 4487 #define GLTPB_100G_MAC_FC_THRESH 0x00099510 /* Reset Source: CORER */ 4488 #define GLTPB_100G_MAC_FC_THRESH_PORT0_FC_THRESH_S 0 4489 #define GLTPB_100G_MAC_FC_THRESH_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0) 4490 #define GLTPB_100G_MAC_FC_THRESH_PORT1_FC_THRESH_S 16 4491 #define GLTPB_100G_MAC_FC_THRESH_PORT1_FC_THRESH_M MAKEMASK(0xFFFF, 16) 4492 #define E800_GLTPB_100G_RPB_FC_THRESH 0x0009963C /* Reset Source: CORER */ 4493 #define E800_GLTPB_100G_RPB_FC_THRESH_PORT0_FC_THRESH_S 0 4494 #define E800_GLTPB_100G_RPB_FC_THRESH_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0) 4495 #define E800_GLTPB_100G_RPB_FC_THRESH_PORT1_FC_THRESH_S 16 4496 #define E800_GLTPB_100G_RPB_FC_THRESH_PORT1_FC_THRESH_M MAKEMASK(0xFFFF, 16) 4497 #define GLTPB_PACING_10G 0x000994E4 /* Reset Source: CORER */ 4498 #define GLTPB_PACING_10G_N_S 0 4499 #define GLTPB_PACING_10G_N_M MAKEMASK(0xFF, 0) 4500 #define GLTPB_PACING_10G_K_S 8 4501 #define GLTPB_PACING_10G_K_M MAKEMASK(0xFF, 8) 4502 #define GLTPB_PACING_10G_S_S 16 4503 #define GLTPB_PACING_10G_S_M MAKEMASK(0x1FF, 16) 4504 #define GLTPB_PACING_25G 0x000994E0 /* Reset Source: CORER */ 4505 #define GLTPB_PACING_25G_N_S 0 4506 #define GLTPB_PACING_25G_N_M MAKEMASK(0xFF, 0) 4507 #define GLTPB_PACING_25G_K_S 8 4508 #define GLTPB_PACING_25G_K_M MAKEMASK(0xFF, 8) 4509 #define GLTPB_PACING_25G_S_S 16 4510 #define GLTPB_PACING_25G_S_M MAKEMASK(0x1FF, 16) 4511 #define GLTPB_PORT_PACING_SPEED 0x000994E8 /* Reset Source: CORER */ 4512 #define GLTPB_PORT_PACING_SPEED_PORT0_SPEED_S 0 4513 #define GLTPB_PORT_PACING_SPEED_PORT0_SPEED_M BIT(0) 4514 #define GLTPB_PORT_PACING_SPEED_PORT1_SPEED_S 1 4515 #define GLTPB_PORT_PACING_SPEED_PORT1_SPEED_M BIT(1) 4516 #define GLTPB_PORT_PACING_SPEED_PORT2_SPEED_S 2 4517 #define GLTPB_PORT_PACING_SPEED_PORT2_SPEED_M BIT(2) 4518 #define GLTPB_PORT_PACING_SPEED_PORT3_SPEED_S 3 4519 #define GLTPB_PORT_PACING_SPEED_PORT3_SPEED_M BIT(3) 4520 #define GLTPB_PORT_PACING_SPEED_PORT4_SPEED_S 4 4521 #define GLTPB_PORT_PACING_SPEED_PORT4_SPEED_M BIT(4) 4522 #define GLTPB_PORT_PACING_SPEED_PORT5_SPEED_S 5 4523 #define GLTPB_PORT_PACING_SPEED_PORT5_SPEED_M BIT(5) 4524 #define GLTPB_PORT_PACING_SPEED_PORT6_SPEED_S 6 4525 #define GLTPB_PORT_PACING_SPEED_PORT6_SPEED_M BIT(6) 4526 #define GLTPB_PORT_PACING_SPEED_PORT7_SPEED_S 7 4527 #define GLTPB_PORT_PACING_SPEED_PORT7_SPEED_M BIT(7) 4528 #define TPB_CFG_SCHEDULED_BC_THRESHOLD 0x00099494 /* Reset Source: CORER */ 4529 #define TPB_CFG_SCHEDULED_BC_THRESHOLD_THRESHOLD_S 0 4530 #define TPB_CFG_SCHEDULED_BC_THRESHOLD_THRESHOLD_M MAKEMASK(0x7FFF, 0) 4531 #define GL_UFUSE_SOC 0x000A400C /* Reset Source: POR */ 4532 #define GL_UFUSE_SOC_PORT_MODE_S 0 4533 #define GL_UFUSE_SOC_PORT_MODE_M MAKEMASK(0x3, 0) 4534 #define GL_UFUSE_SOC_BANDWIDTH_S 2 4535 #define GL_UFUSE_SOC_BANDWIDTH_M MAKEMASK(0x3, 2) 4536 #define GL_UFUSE_SOC_PE_DISABLE_S 4 4537 #define GL_UFUSE_SOC_PE_DISABLE_M BIT(4) 4538 #define GL_UFUSE_SOC_SWITCH_MODE_S 5 4539 #define GL_UFUSE_SOC_SWITCH_MODE_M BIT(5) 4540 #define GL_UFUSE_SOC_CSR_PROTECTION_ENABLE_S 6 4541 #define GL_UFUSE_SOC_CSR_PROTECTION_ENABLE_M BIT(6) 4542 #define GL_UFUSE_SOC_SERIAL_50G_S 7 4543 #define GL_UFUSE_SOC_SERIAL_50G_M BIT(7) 4544 #define GL_UFUSE_SOC_NIC_ID_S 8 4545 #define GL_UFUSE_SOC_NIC_ID_M BIT(8) 4546 #define GL_UFUSE_SOC_BLOCK_BME_TO_FW_S 9 4547 #define GL_UFUSE_SOC_BLOCK_BME_TO_FW_M BIT(9) 4548 #define GL_UFUSE_SOC_SOC_TYPE_S 10 4549 #define GL_UFUSE_SOC_SOC_TYPE_M BIT(10) 4550 #define GL_UFUSE_SOC_BTS_MODE_S 11 4551 #define GL_UFUSE_SOC_BTS_MODE_M BIT(11) 4552 #define E800_GL_UFUSE_SOC_SPARE_FUSES_S 12 4553 #define E800_GL_UFUSE_SOC_SPARE_FUSES_M MAKEMASK(0xF, 12) 4554 #define EMPINT_GPIO_ENA 0x000880C0 /* Reset Source: POR */ 4555 #define EMPINT_GPIO_ENA_GPIO0_ENA_S 0 4556 #define EMPINT_GPIO_ENA_GPIO0_ENA_M BIT(0) 4557 #define EMPINT_GPIO_ENA_GPIO1_ENA_S 1 4558 #define EMPINT_GPIO_ENA_GPIO1_ENA_M BIT(1) 4559 #define EMPINT_GPIO_ENA_GPIO2_ENA_S 2 4560 #define EMPINT_GPIO_ENA_GPIO2_ENA_M BIT(2) 4561 #define EMPINT_GPIO_ENA_GPIO3_ENA_S 3 4562 #define EMPINT_GPIO_ENA_GPIO3_ENA_M BIT(3) 4563 #define EMPINT_GPIO_ENA_GPIO4_ENA_S 4 4564 #define EMPINT_GPIO_ENA_GPIO4_ENA_M BIT(4) 4565 #define EMPINT_GPIO_ENA_GPIO5_ENA_S 5 4566 #define EMPINT_GPIO_ENA_GPIO5_ENA_M BIT(5) 4567 #define EMPINT_GPIO_ENA_GPIO6_ENA_S 6 4568 #define EMPINT_GPIO_ENA_GPIO6_ENA_M BIT(6) 4569 #define GLGEN_MAC_LINK_TOPO 0x000B81DC /* Reset Source: GLOBR */ 4570 #define GLGEN_MAC_LINK_TOPO_LINK_TOPO_S 0 4571 #define GLGEN_MAC_LINK_TOPO_LINK_TOPO_M MAKEMASK(0x3, 0) 4572 #define GLINT_CEQCTL(_INT) (0x0015C000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */ 4573 #define GLINT_CEQCTL_MAX_INDEX 2047 4574 #define GLINT_CEQCTL_MSIX_INDX_S 0 4575 #define GLINT_CEQCTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 4576 #define GLINT_CEQCTL_ITR_INDX_S 11 4577 #define GLINT_CEQCTL_ITR_INDX_M MAKEMASK(0x3, 11) 4578 #define GLINT_CEQCTL_CAUSE_ENA_S 30 4579 #define GLINT_CEQCTL_CAUSE_ENA_M BIT(30) 4580 #define GLINT_CEQCTL_INTEVENT_S 31 4581 #define GLINT_CEQCTL_INTEVENT_M BIT(31) 4582 #define GLINT_CTL 0x0016CC54 /* Reset Source: CORER */ 4583 #define GLINT_CTL_DIS_AUTOMASK_S 0 4584 #define GLINT_CTL_DIS_AUTOMASK_M BIT(0) 4585 #define GLINT_CTL_RSVD_S 1 4586 #define GLINT_CTL_RSVD_M MAKEMASK(0x7FFF, 1) 4587 #define GLINT_CTL_ITR_GRAN_200_S 16 4588 #define GLINT_CTL_ITR_GRAN_200_M MAKEMASK(0xF, 16) 4589 #define GLINT_CTL_ITR_GRAN_100_S 20 4590 #define GLINT_CTL_ITR_GRAN_100_M MAKEMASK(0xF, 20) 4591 #define GLINT_CTL_ITR_GRAN_50_S 24 4592 #define GLINT_CTL_ITR_GRAN_50_M MAKEMASK(0xF, 24) 4593 #define GLINT_CTL_ITR_GRAN_25_S 28 4594 #define GLINT_CTL_ITR_GRAN_25_M MAKEMASK(0xF, 28) 4595 #define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */ 4596 #define GLINT_DYN_CTL_MAX_INDEX 2047 4597 #define GLINT_DYN_CTL_INTENA_S 0 4598 #define GLINT_DYN_CTL_INTENA_M BIT(0) 4599 #define GLINT_DYN_CTL_CLEARPBA_S 1 4600 #define GLINT_DYN_CTL_CLEARPBA_M BIT(1) 4601 #define GLINT_DYN_CTL_SWINT_TRIG_S 2 4602 #define GLINT_DYN_CTL_SWINT_TRIG_M BIT(2) 4603 #define GLINT_DYN_CTL_ITR_INDX_S 3 4604 #define GLINT_DYN_CTL_ITR_INDX_M MAKEMASK(0x3, 3) 4605 #define GLINT_DYN_CTL_INTERVAL_S 5 4606 #define GLINT_DYN_CTL_INTERVAL_M MAKEMASK(0xFFF, 5) 4607 #define GLINT_DYN_CTL_SW_ITR_INDX_ENA_S 24 4608 #define GLINT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(24) 4609 #define GLINT_DYN_CTL_SW_ITR_INDX_S 25 4610 #define GLINT_DYN_CTL_SW_ITR_INDX_M MAKEMASK(0x3, 25) 4611 #define GLINT_DYN_CTL_WB_ON_ITR_S 30 4612 #define GLINT_DYN_CTL_WB_ON_ITR_M BIT(30) 4613 #define GLINT_DYN_CTL_INTENA_MSK_S 31 4614 #define GLINT_DYN_CTL_INTENA_MSK_M BIT(31) 4615 #define GLINT_FW_TOOL_CTL 0x0016C840 /* Reset Source: CORER */ 4616 #define GLINT_FW_TOOL_CTL_MSIX_INDX_S 0 4617 #define GLINT_FW_TOOL_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 4618 #define GLINT_FW_TOOL_CTL_ITR_INDX_S 11 4619 #define GLINT_FW_TOOL_CTL_ITR_INDX_M MAKEMASK(0x3, 11) 4620 #define GLINT_FW_TOOL_CTL_CAUSE_ENA_S 30 4621 #define GLINT_FW_TOOL_CTL_CAUSE_ENA_M BIT(30) 4622 #define GLINT_FW_TOOL_CTL_INTEVENT_S 31 4623 #define GLINT_FW_TOOL_CTL_INTEVENT_M BIT(31) 4624 #define GLINT_ITR(_i, _INT) (0x00154000 + ((_i) * 8192 + (_INT) * 4)) /* _i=0...2, _INT=0...2047 */ /* Reset Source: CORER */ 4625 #define GLINT_ITR_MAX_INDEX 2 4626 #define GLINT_ITR_INTERVAL_S 0 4627 #define GLINT_ITR_INTERVAL_M MAKEMASK(0xFFF, 0) 4628 #define GLINT_RATE(_INT) (0x0015A000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */ 4629 #define GLINT_RATE_MAX_INDEX 2047 4630 #define GLINT_RATE_INTERVAL_S 0 4631 #define GLINT_RATE_INTERVAL_M MAKEMASK(0x3F, 0) 4632 #define GLINT_RATE_INTRL_ENA_S 6 4633 #define GLINT_RATE_INTRL_ENA_M BIT(6) 4634 #define GLINT_TSYN_PFMSTR(_i) (0x0016CCC0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 4635 #define GLINT_TSYN_PFMSTR_MAX_INDEX 1 4636 #define GLINT_TSYN_PFMSTR_PF_MASTER_S 0 4637 #define GLINT_TSYN_PFMSTR_PF_MASTER_M MAKEMASK(0x7, 0) 4638 #define GLINT_TSYN_PHY 0x0016CC50 /* Reset Source: CORER */ 4639 #define GLINT_TSYN_PHY_PHY_INDX_S 0 4640 #define GLINT_TSYN_PHY_PHY_INDX_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLINT_TSYN_PHY_PHY_INDX_M : E800_GLINT_TSYN_PHY_PHY_INDX_M) 4641 #define E800_GLINT_TSYN_PHY_PHY_INDX_M MAKEMASK(0x1F, 0) 4642 #define E830_GLINT_TSYN_PHY_PHY_INDX_M MAKEMASK(0xFF, 0) 4643 #define GLINT_VECT2FUNC(_INT) (0x00162000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */ 4644 #define GLINT_VECT2FUNC_MAX_INDEX 2047 4645 #define GLINT_VECT2FUNC_VF_NUM_S 0 4646 #define GLINT_VECT2FUNC_VF_NUM_M MAKEMASK(0xFF, 0) 4647 #define GLINT_VECT2FUNC_PF_NUM_S 12 4648 #define GLINT_VECT2FUNC_PF_NUM_M MAKEMASK(0x7, 12) 4649 #define GLINT_VECT2FUNC_IS_PF_S 16 4650 #define GLINT_VECT2FUNC_IS_PF_M BIT(16) 4651 #define PF0INT_FW_HLP_CTL 0x0016C844 /* Reset Source: CORER */ 4652 #define PF0INT_FW_HLP_CTL_MSIX_INDX_S 0 4653 #define PF0INT_FW_HLP_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 4654 #define PF0INT_FW_HLP_CTL_ITR_INDX_S 11 4655 #define PF0INT_FW_HLP_CTL_ITR_INDX_M MAKEMASK(0x3, 11) 4656 #define PF0INT_FW_HLP_CTL_CAUSE_ENA_S 30 4657 #define PF0INT_FW_HLP_CTL_CAUSE_ENA_M BIT(30) 4658 #define PF0INT_FW_HLP_CTL_INTEVENT_S 31 4659 #define PF0INT_FW_HLP_CTL_INTEVENT_M BIT(31) 4660 #define PF0INT_FW_PSM_CTL 0x0016C848 /* Reset Source: CORER */ 4661 #define PF0INT_FW_PSM_CTL_MSIX_INDX_S 0 4662 #define PF0INT_FW_PSM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 4663 #define PF0INT_FW_PSM_CTL_ITR_INDX_S 11 4664 #define PF0INT_FW_PSM_CTL_ITR_INDX_M MAKEMASK(0x3, 11) 4665 #define PF0INT_FW_PSM_CTL_CAUSE_ENA_S 30 4666 #define PF0INT_FW_PSM_CTL_CAUSE_ENA_M BIT(30) 4667 #define PF0INT_FW_PSM_CTL_INTEVENT_S 31 4668 #define PF0INT_FW_PSM_CTL_INTEVENT_M BIT(31) 4669 #define PF0INT_MBX_CPM_CTL 0x0016B2C0 /* Reset Source: CORER */ 4670 #define PF0INT_MBX_CPM_CTL_MSIX_INDX_S 0 4671 #define PF0INT_MBX_CPM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 4672 #define PF0INT_MBX_CPM_CTL_ITR_INDX_S 11 4673 #define PF0INT_MBX_CPM_CTL_ITR_INDX_M MAKEMASK(0x3, 11) 4674 #define PF0INT_MBX_CPM_CTL_CAUSE_ENA_S 30 4675 #define PF0INT_MBX_CPM_CTL_CAUSE_ENA_M BIT(30) 4676 #define PF0INT_MBX_CPM_CTL_INTEVENT_S 31 4677 #define PF0INT_MBX_CPM_CTL_INTEVENT_M BIT(31) 4678 #define PF0INT_MBX_HLP_CTL 0x0016B2C4 /* Reset Source: CORER */ 4679 #define PF0INT_MBX_HLP_CTL_MSIX_INDX_S 0 4680 #define PF0INT_MBX_HLP_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 4681 #define PF0INT_MBX_HLP_CTL_ITR_INDX_S 11 4682 #define PF0INT_MBX_HLP_CTL_ITR_INDX_M MAKEMASK(0x3, 11) 4683 #define PF0INT_MBX_HLP_CTL_CAUSE_ENA_S 30 4684 #define PF0INT_MBX_HLP_CTL_CAUSE_ENA_M BIT(30) 4685 #define PF0INT_MBX_HLP_CTL_INTEVENT_S 31 4686 #define PF0INT_MBX_HLP_CTL_INTEVENT_M BIT(31) 4687 #define PF0INT_MBX_PSM_CTL 0x0016B2C8 /* Reset Source: CORER */ 4688 #define PF0INT_MBX_PSM_CTL_MSIX_INDX_S 0 4689 #define PF0INT_MBX_PSM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 4690 #define PF0INT_MBX_PSM_CTL_ITR_INDX_S 11 4691 #define PF0INT_MBX_PSM_CTL_ITR_INDX_M MAKEMASK(0x3, 11) 4692 #define PF0INT_MBX_PSM_CTL_CAUSE_ENA_S 30 4693 #define PF0INT_MBX_PSM_CTL_CAUSE_ENA_M BIT(30) 4694 #define PF0INT_MBX_PSM_CTL_INTEVENT_S 31 4695 #define PF0INT_MBX_PSM_CTL_INTEVENT_M BIT(31) 4696 #define PF0INT_OICR_CPM 0x0016CC40 /* Reset Source: CORER */ 4697 #define PF0INT_OICR_CPM_INTEVENT_S 0 4698 #define PF0INT_OICR_CPM_INTEVENT_M BIT(0) 4699 #define PF0INT_OICR_CPM_QUEUE_S 1 4700 #define PF0INT_OICR_CPM_QUEUE_M BIT(1) 4701 #define PF0INT_OICR_CPM_RSV1_S 2 4702 #define PF0INT_OICR_CPM_RSV1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PF0INT_OICR_CPM_RSV1_M : E800_PF0INT_OICR_CPM_RSV1_M) 4703 #define E800_PF0INT_OICR_CPM_RSV1_M MAKEMASK(0xFF, 2) 4704 #define E830_PF0INT_OICR_CPM_RSV1_M MAKEMASK(0x3F, 2) 4705 #define E800_PF0INT_OICR_CPM_HH_COMP_S 10 4706 #define E800_PF0INT_OICR_CPM_HH_COMP_M BIT(10) 4707 #define PF0INT_OICR_CPM_TSYN_TX_S 11 4708 #define PF0INT_OICR_CPM_TSYN_TX_M BIT(11) 4709 #define PF0INT_OICR_CPM_TSYN_EVNT_S 12 4710 #define PF0INT_OICR_CPM_TSYN_EVNT_M BIT(12) 4711 #define PF0INT_OICR_CPM_TSYN_TGT_S 13 4712 #define PF0INT_OICR_CPM_TSYN_TGT_M BIT(13) 4713 #define PF0INT_OICR_CPM_HLP_RDY_S 14 4714 #define PF0INT_OICR_CPM_HLP_RDY_M BIT(14) 4715 #define PF0INT_OICR_CPM_CPM_RDY_S 15 4716 #define PF0INT_OICR_CPM_CPM_RDY_M BIT(15) 4717 #define PF0INT_OICR_CPM_ECC_ERR_S 16 4718 #define PF0INT_OICR_CPM_ECC_ERR_M BIT(16) 4719 #define PF0INT_OICR_CPM_RSV2_S 17 4720 #define PF0INT_OICR_CPM_RSV2_M MAKEMASK(0x3, 17) 4721 #define PF0INT_OICR_CPM_MAL_DETECT_S 19 4722 #define PF0INT_OICR_CPM_MAL_DETECT_M BIT(19) 4723 #define PF0INT_OICR_CPM_GRST_S 20 4724 #define PF0INT_OICR_CPM_GRST_M BIT(20) 4725 #define PF0INT_OICR_CPM_PCI_EXCEPTION_S 21 4726 #define PF0INT_OICR_CPM_PCI_EXCEPTION_M BIT(21) 4727 #define PF0INT_OICR_CPM_GPIO_S 22 4728 #define PF0INT_OICR_CPM_GPIO_M BIT(22) 4729 #define PF0INT_OICR_CPM_RSV3_S 23 4730 #define PF0INT_OICR_CPM_RSV3_M BIT(23) 4731 #define PF0INT_OICR_CPM_STORM_DETECT_S 24 4732 #define PF0INT_OICR_CPM_STORM_DETECT_M BIT(24) 4733 #define PF0INT_OICR_CPM_LINK_STAT_CHANGE_S 25 4734 #define PF0INT_OICR_CPM_LINK_STAT_CHANGE_M BIT(25) 4735 #define PF0INT_OICR_CPM_HMC_ERR_S 26 4736 #define PF0INT_OICR_CPM_HMC_ERR_M BIT(26) 4737 #define PF0INT_OICR_CPM_PE_PUSH_S 27 4738 #define PF0INT_OICR_CPM_PE_PUSH_M BIT(27) 4739 #define PF0INT_OICR_CPM_PE_CRITERR_S 28 4740 #define PF0INT_OICR_CPM_PE_CRITERR_M BIT(28) 4741 #define PF0INT_OICR_CPM_VFLR_S 29 4742 #define PF0INT_OICR_CPM_VFLR_M BIT(29) 4743 #define PF0INT_OICR_CPM_XLR_HW_DONE_S 30 4744 #define PF0INT_OICR_CPM_XLR_HW_DONE_M BIT(30) 4745 #define PF0INT_OICR_CPM_SWINT_S 31 4746 #define PF0INT_OICR_CPM_SWINT_M BIT(31) 4747 #define PF0INT_OICR_CTL_CPM 0x0016CC48 /* Reset Source: CORER */ 4748 #define PF0INT_OICR_CTL_CPM_MSIX_INDX_S 0 4749 #define PF0INT_OICR_CTL_CPM_MSIX_INDX_M MAKEMASK(0x7FF, 0) 4750 #define PF0INT_OICR_CTL_CPM_ITR_INDX_S 11 4751 #define PF0INT_OICR_CTL_CPM_ITR_INDX_M MAKEMASK(0x3, 11) 4752 #define PF0INT_OICR_CTL_CPM_CAUSE_ENA_S 30 4753 #define PF0INT_OICR_CTL_CPM_CAUSE_ENA_M BIT(30) 4754 #define PF0INT_OICR_CTL_CPM_INTEVENT_S 31 4755 #define PF0INT_OICR_CTL_CPM_INTEVENT_M BIT(31) 4756 #define PF0INT_OICR_CTL_HLP 0x0016CC5C /* Reset Source: CORER */ 4757 #define PF0INT_OICR_CTL_HLP_MSIX_INDX_S 0 4758 #define PF0INT_OICR_CTL_HLP_MSIX_INDX_M MAKEMASK(0x7FF, 0) 4759 #define PF0INT_OICR_CTL_HLP_ITR_INDX_S 11 4760 #define PF0INT_OICR_CTL_HLP_ITR_INDX_M MAKEMASK(0x3, 11) 4761 #define PF0INT_OICR_CTL_HLP_CAUSE_ENA_S 30 4762 #define PF0INT_OICR_CTL_HLP_CAUSE_ENA_M BIT(30) 4763 #define PF0INT_OICR_CTL_HLP_INTEVENT_S 31 4764 #define PF0INT_OICR_CTL_HLP_INTEVENT_M BIT(31) 4765 #define PF0INT_OICR_CTL_PSM 0x0016CC64 /* Reset Source: CORER */ 4766 #define PF0INT_OICR_CTL_PSM_MSIX_INDX_S 0 4767 #define PF0INT_OICR_CTL_PSM_MSIX_INDX_M MAKEMASK(0x7FF, 0) 4768 #define PF0INT_OICR_CTL_PSM_ITR_INDX_S 11 4769 #define PF0INT_OICR_CTL_PSM_ITR_INDX_M MAKEMASK(0x3, 11) 4770 #define PF0INT_OICR_CTL_PSM_CAUSE_ENA_S 30 4771 #define PF0INT_OICR_CTL_PSM_CAUSE_ENA_M BIT(30) 4772 #define PF0INT_OICR_CTL_PSM_INTEVENT_S 31 4773 #define PF0INT_OICR_CTL_PSM_INTEVENT_M BIT(31) 4774 #define PF0INT_OICR_ENA_CPM 0x0016CC60 /* Reset Source: CORER */ 4775 #define PF0INT_OICR_ENA_CPM_RSV0_S 0 4776 #define PF0INT_OICR_ENA_CPM_RSV0_M BIT(0) 4777 #define PF0INT_OICR_ENA_CPM_INT_ENA_S 1 4778 #define PF0INT_OICR_ENA_CPM_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1) 4779 #define PF0INT_OICR_ENA_HLP 0x0016CC4C /* Reset Source: CORER */ 4780 #define PF0INT_OICR_ENA_HLP_RSV0_S 0 4781 #define PF0INT_OICR_ENA_HLP_RSV0_M BIT(0) 4782 #define PF0INT_OICR_ENA_HLP_INT_ENA_S 1 4783 #define PF0INT_OICR_ENA_HLP_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1) 4784 #define PF0INT_OICR_ENA_PSM 0x0016CC58 /* Reset Source: CORER */ 4785 #define PF0INT_OICR_ENA_PSM_RSV0_S 0 4786 #define PF0INT_OICR_ENA_PSM_RSV0_M BIT(0) 4787 #define PF0INT_OICR_ENA_PSM_INT_ENA_S 1 4788 #define PF0INT_OICR_ENA_PSM_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1) 4789 #define PF0INT_OICR_HLP 0x0016CC68 /* Reset Source: CORER */ 4790 #define PF0INT_OICR_HLP_INTEVENT_S 0 4791 #define PF0INT_OICR_HLP_INTEVENT_M BIT(0) 4792 #define PF0INT_OICR_HLP_QUEUE_S 1 4793 #define PF0INT_OICR_HLP_QUEUE_M BIT(1) 4794 #define PF0INT_OICR_HLP_RSV1_S 2 4795 #define PF0INT_OICR_HLP_RSV1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PF0INT_OICR_HLP_RSV1_M : E800_PF0INT_OICR_HLP_RSV1_M) 4796 #define E800_PF0INT_OICR_HLP_RSV1_M MAKEMASK(0xFF, 2) 4797 #define E830_PF0INT_OICR_HLP_RSV1_M MAKEMASK(0x3F, 2) 4798 #define E800_PF0INT_OICR_HLP_HH_COMP_S 10 4799 #define E800_PF0INT_OICR_HLP_HH_COMP_M BIT(10) 4800 #define PF0INT_OICR_HLP_TSYN_TX_S 11 4801 #define PF0INT_OICR_HLP_TSYN_TX_M BIT(11) 4802 #define PF0INT_OICR_HLP_TSYN_EVNT_S 12 4803 #define PF0INT_OICR_HLP_TSYN_EVNT_M BIT(12) 4804 #define PF0INT_OICR_HLP_TSYN_TGT_S 13 4805 #define PF0INT_OICR_HLP_TSYN_TGT_M BIT(13) 4806 #define PF0INT_OICR_HLP_HLP_RDY_S 14 4807 #define PF0INT_OICR_HLP_HLP_RDY_M BIT(14) 4808 #define PF0INT_OICR_HLP_CPM_RDY_S 15 4809 #define PF0INT_OICR_HLP_CPM_RDY_M BIT(15) 4810 #define PF0INT_OICR_HLP_ECC_ERR_S 16 4811 #define PF0INT_OICR_HLP_ECC_ERR_M BIT(16) 4812 #define PF0INT_OICR_HLP_RSV2_S 17 4813 #define PF0INT_OICR_HLP_RSV2_M MAKEMASK(0x3, 17) 4814 #define PF0INT_OICR_HLP_MAL_DETECT_S 19 4815 #define PF0INT_OICR_HLP_MAL_DETECT_M BIT(19) 4816 #define PF0INT_OICR_HLP_GRST_S 20 4817 #define PF0INT_OICR_HLP_GRST_M BIT(20) 4818 #define PF0INT_OICR_HLP_PCI_EXCEPTION_S 21 4819 #define PF0INT_OICR_HLP_PCI_EXCEPTION_M BIT(21) 4820 #define PF0INT_OICR_HLP_GPIO_S 22 4821 #define PF0INT_OICR_HLP_GPIO_M BIT(22) 4822 #define PF0INT_OICR_HLP_RSV3_S 23 4823 #define PF0INT_OICR_HLP_RSV3_M BIT(23) 4824 #define PF0INT_OICR_HLP_STORM_DETECT_S 24 4825 #define PF0INT_OICR_HLP_STORM_DETECT_M BIT(24) 4826 #define PF0INT_OICR_HLP_LINK_STAT_CHANGE_S 25 4827 #define PF0INT_OICR_HLP_LINK_STAT_CHANGE_M BIT(25) 4828 #define PF0INT_OICR_HLP_HMC_ERR_S 26 4829 #define PF0INT_OICR_HLP_HMC_ERR_M BIT(26) 4830 #define PF0INT_OICR_HLP_PE_PUSH_S 27 4831 #define PF0INT_OICR_HLP_PE_PUSH_M BIT(27) 4832 #define PF0INT_OICR_HLP_PE_CRITERR_S 28 4833 #define PF0INT_OICR_HLP_PE_CRITERR_M BIT(28) 4834 #define PF0INT_OICR_HLP_VFLR_S 29 4835 #define PF0INT_OICR_HLP_VFLR_M BIT(29) 4836 #define PF0INT_OICR_HLP_XLR_HW_DONE_S 30 4837 #define PF0INT_OICR_HLP_XLR_HW_DONE_M BIT(30) 4838 #define PF0INT_OICR_HLP_SWINT_S 31 4839 #define PF0INT_OICR_HLP_SWINT_M BIT(31) 4840 #define PF0INT_OICR_PSM 0x0016CC44 /* Reset Source: CORER */ 4841 #define PF0INT_OICR_PSM_INTEVENT_S 0 4842 #define PF0INT_OICR_PSM_INTEVENT_M BIT(0) 4843 #define PF0INT_OICR_PSM_QUEUE_S 1 4844 #define PF0INT_OICR_PSM_QUEUE_M BIT(1) 4845 #define PF0INT_OICR_PSM_RSV1_S 2 4846 #define PF0INT_OICR_PSM_RSV1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PF0INT_OICR_PSM_RSV1_M : E800_PF0INT_OICR_PSM_RSV1_M) 4847 #define E800_PF0INT_OICR_PSM_RSV1_M MAKEMASK(0xFF, 2) 4848 #define E830_PF0INT_OICR_PSM_RSV1_M MAKEMASK(0x3F, 2) 4849 #define E800_PF0INT_OICR_PSM_HH_COMP_S 10 4850 #define E800_PF0INT_OICR_PSM_HH_COMP_M BIT(10) 4851 #define PF0INT_OICR_PSM_TSYN_TX_S 11 4852 #define PF0INT_OICR_PSM_TSYN_TX_M BIT(11) 4853 #define PF0INT_OICR_PSM_TSYN_EVNT_S 12 4854 #define PF0INT_OICR_PSM_TSYN_EVNT_M BIT(12) 4855 #define PF0INT_OICR_PSM_TSYN_TGT_S 13 4856 #define PF0INT_OICR_PSM_TSYN_TGT_M BIT(13) 4857 #define PF0INT_OICR_PSM_HLP_RDY_S 14 4858 #define PF0INT_OICR_PSM_HLP_RDY_M BIT(14) 4859 #define PF0INT_OICR_PSM_CPM_RDY_S 15 4860 #define PF0INT_OICR_PSM_CPM_RDY_M BIT(15) 4861 #define PF0INT_OICR_PSM_ECC_ERR_S 16 4862 #define PF0INT_OICR_PSM_ECC_ERR_M BIT(16) 4863 #define PF0INT_OICR_PSM_RSV2_S 17 4864 #define PF0INT_OICR_PSM_RSV2_M MAKEMASK(0x3, 17) 4865 #define PF0INT_OICR_PSM_MAL_DETECT_S 19 4866 #define PF0INT_OICR_PSM_MAL_DETECT_M BIT(19) 4867 #define PF0INT_OICR_PSM_GRST_S 20 4868 #define PF0INT_OICR_PSM_GRST_M BIT(20) 4869 #define PF0INT_OICR_PSM_PCI_EXCEPTION_S 21 4870 #define PF0INT_OICR_PSM_PCI_EXCEPTION_M BIT(21) 4871 #define PF0INT_OICR_PSM_GPIO_S 22 4872 #define PF0INT_OICR_PSM_GPIO_M BIT(22) 4873 #define PF0INT_OICR_PSM_RSV3_S 23 4874 #define PF0INT_OICR_PSM_RSV3_M BIT(23) 4875 #define PF0INT_OICR_PSM_STORM_DETECT_S 24 4876 #define PF0INT_OICR_PSM_STORM_DETECT_M BIT(24) 4877 #define PF0INT_OICR_PSM_LINK_STAT_CHANGE_S 25 4878 #define PF0INT_OICR_PSM_LINK_STAT_CHANGE_M BIT(25) 4879 #define PF0INT_OICR_PSM_HMC_ERR_S 26 4880 #define PF0INT_OICR_PSM_HMC_ERR_M BIT(26) 4881 #define PF0INT_OICR_PSM_PE_PUSH_S 27 4882 #define PF0INT_OICR_PSM_PE_PUSH_M BIT(27) 4883 #define PF0INT_OICR_PSM_PE_CRITERR_S 28 4884 #define PF0INT_OICR_PSM_PE_CRITERR_M BIT(28) 4885 #define PF0INT_OICR_PSM_VFLR_S 29 4886 #define PF0INT_OICR_PSM_VFLR_M BIT(29) 4887 #define PF0INT_OICR_PSM_XLR_HW_DONE_S 30 4888 #define PF0INT_OICR_PSM_XLR_HW_DONE_M BIT(30) 4889 #define PF0INT_OICR_PSM_SWINT_S 31 4890 #define PF0INT_OICR_PSM_SWINT_M BIT(31) 4891 #define PF0INT_SB_CPM_CTL 0x0016B2CC /* Reset Source: CORER */ 4892 #define PF0INT_SB_CPM_CTL_MSIX_INDX_S 0 4893 #define PF0INT_SB_CPM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 4894 #define PF0INT_SB_CPM_CTL_ITR_INDX_S 11 4895 #define PF0INT_SB_CPM_CTL_ITR_INDX_M MAKEMASK(0x3, 11) 4896 #define PF0INT_SB_CPM_CTL_CAUSE_ENA_S 30 4897 #define PF0INT_SB_CPM_CTL_CAUSE_ENA_M BIT(30) 4898 #define PF0INT_SB_CPM_CTL_INTEVENT_S 31 4899 #define PF0INT_SB_CPM_CTL_INTEVENT_M BIT(31) 4900 #define PF0INT_SB_HLP_CTL 0x0016B640 /* Reset Source: CORER */ 4901 #define PF0INT_SB_HLP_CTL_MSIX_INDX_S 0 4902 #define PF0INT_SB_HLP_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 4903 #define PF0INT_SB_HLP_CTL_ITR_INDX_S 11 4904 #define PF0INT_SB_HLP_CTL_ITR_INDX_M MAKEMASK(0x3, 11) 4905 #define PF0INT_SB_HLP_CTL_CAUSE_ENA_S 30 4906 #define PF0INT_SB_HLP_CTL_CAUSE_ENA_M BIT(30) 4907 #define PF0INT_SB_HLP_CTL_INTEVENT_S 31 4908 #define PF0INT_SB_HLP_CTL_INTEVENT_M BIT(31) 4909 #define PFINT_AEQCTL 0x0016CB00 /* Reset Source: CORER */ 4910 #define PFINT_AEQCTL_MSIX_INDX_S 0 4911 #define PFINT_AEQCTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 4912 #define PFINT_AEQCTL_ITR_INDX_S 11 4913 #define PFINT_AEQCTL_ITR_INDX_M MAKEMASK(0x3, 11) 4914 #define PFINT_AEQCTL_CAUSE_ENA_S 30 4915 #define PFINT_AEQCTL_CAUSE_ENA_M BIT(30) 4916 #define PFINT_AEQCTL_INTEVENT_S 31 4917 #define PFINT_AEQCTL_INTEVENT_M BIT(31) 4918 #define PFINT_ALLOC 0x001D2600 /* Reset Source: CORER */ 4919 #define PFINT_ALLOC_FIRST_S 0 4920 #define PFINT_ALLOC_FIRST_M MAKEMASK(0x7FF, 0) 4921 #define PFINT_ALLOC_LAST_S 12 4922 #define PFINT_ALLOC_LAST_M MAKEMASK(0x7FF, 12) 4923 #define PFINT_ALLOC_VALID_S 31 4924 #define PFINT_ALLOC_VALID_M BIT(31) 4925 #define PFINT_ALLOC_PCI 0x0009D800 /* Reset Source: PCIR */ 4926 #define PFINT_ALLOC_PCI_FIRST_S 0 4927 #define PFINT_ALLOC_PCI_FIRST_M MAKEMASK(0x7FF, 0) 4928 #define PFINT_ALLOC_PCI_LAST_S 12 4929 #define PFINT_ALLOC_PCI_LAST_M MAKEMASK(0x7FF, 12) 4930 #define PFINT_ALLOC_PCI_VALID_S 31 4931 #define PFINT_ALLOC_PCI_VALID_M BIT(31) 4932 #define PFINT_FW_CTL 0x0016C800 /* Reset Source: CORER */ 4933 #define PFINT_FW_CTL_MSIX_INDX_S 0 4934 #define PFINT_FW_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 4935 #define PFINT_FW_CTL_ITR_INDX_S 11 4936 #define PFINT_FW_CTL_ITR_INDX_M MAKEMASK(0x3, 11) 4937 #define PFINT_FW_CTL_CAUSE_ENA_S 30 4938 #define PFINT_FW_CTL_CAUSE_ENA_M BIT(30) 4939 #define PFINT_FW_CTL_INTEVENT_S 31 4940 #define PFINT_FW_CTL_INTEVENT_M BIT(31) 4941 #define PFINT_GPIO_ENA 0x00088080 /* Reset Source: CORER */ 4942 #define PFINT_GPIO_ENA_GPIO0_ENA_S 0 4943 #define PFINT_GPIO_ENA_GPIO0_ENA_M BIT(0) 4944 #define PFINT_GPIO_ENA_GPIO1_ENA_S 1 4945 #define PFINT_GPIO_ENA_GPIO1_ENA_M BIT(1) 4946 #define PFINT_GPIO_ENA_GPIO2_ENA_S 2 4947 #define PFINT_GPIO_ENA_GPIO2_ENA_M BIT(2) 4948 #define PFINT_GPIO_ENA_GPIO3_ENA_S 3 4949 #define PFINT_GPIO_ENA_GPIO3_ENA_M BIT(3) 4950 #define PFINT_GPIO_ENA_GPIO4_ENA_S 4 4951 #define PFINT_GPIO_ENA_GPIO4_ENA_M BIT(4) 4952 #define PFINT_GPIO_ENA_GPIO5_ENA_S 5 4953 #define PFINT_GPIO_ENA_GPIO5_ENA_M BIT(5) 4954 #define PFINT_GPIO_ENA_GPIO6_ENA_S 6 4955 #define PFINT_GPIO_ENA_GPIO6_ENA_M BIT(6) 4956 #define PFINT_MBX_CTL 0x0016B280 /* Reset Source: CORER */ 4957 #define PFINT_MBX_CTL_MSIX_INDX_S 0 4958 #define PFINT_MBX_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 4959 #define PFINT_MBX_CTL_ITR_INDX_S 11 4960 #define PFINT_MBX_CTL_ITR_INDX_M MAKEMASK(0x3, 11) 4961 #define PFINT_MBX_CTL_CAUSE_ENA_S 30 4962 #define PFINT_MBX_CTL_CAUSE_ENA_M BIT(30) 4963 #define PFINT_MBX_CTL_INTEVENT_S 31 4964 #define PFINT_MBX_CTL_INTEVENT_M BIT(31) 4965 #define PFINT_OICR 0x0016CA00 /* Reset Source: CORER */ 4966 #define PFINT_OICR_INTEVENT_S 0 4967 #define PFINT_OICR_INTEVENT_M BIT(0) 4968 #define PFINT_OICR_QUEUE_S 1 4969 #define PFINT_OICR_QUEUE_M BIT(1) 4970 #define PFINT_OICR_RSV1_S 2 4971 #define PFINT_OICR_RSV1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PFINT_OICR_RSV1_M : E800_PFINT_OICR_RSV1_M) 4972 #define E800_PFINT_OICR_RSV1_M MAKEMASK(0xFF, 2) 4973 #define E830_PFINT_OICR_RSV1_M MAKEMASK(0x3F, 2) 4974 #define E800_PFINT_OICR_HH_COMP_S 10 4975 #define E800_PFINT_OICR_HH_COMP_M BIT(10) 4976 #define PFINT_OICR_TSYN_TX_S 11 4977 #define PFINT_OICR_TSYN_TX_M BIT(11) 4978 #define PFINT_OICR_TSYN_EVNT_S 12 4979 #define PFINT_OICR_TSYN_EVNT_M BIT(12) 4980 #define PFINT_OICR_TSYN_TGT_S 13 4981 #define PFINT_OICR_TSYN_TGT_M BIT(13) 4982 #define PFINT_OICR_HLP_RDY_S 14 4983 #define PFINT_OICR_HLP_RDY_M BIT(14) 4984 #define PFINT_OICR_CPM_RDY_S 15 4985 #define PFINT_OICR_CPM_RDY_M BIT(15) 4986 #define PFINT_OICR_ECC_ERR_S 16 4987 #define PFINT_OICR_ECC_ERR_M BIT(16) 4988 #define PFINT_OICR_RSV2_S 17 4989 #define PFINT_OICR_RSV2_M MAKEMASK(0x3, 17) 4990 #define PFINT_OICR_MAL_DETECT_S 19 4991 #define PFINT_OICR_MAL_DETECT_M BIT(19) 4992 #define PFINT_OICR_GRST_S 20 4993 #define PFINT_OICR_GRST_M BIT(20) 4994 #define PFINT_OICR_PCI_EXCEPTION_S 21 4995 #define PFINT_OICR_PCI_EXCEPTION_M BIT(21) 4996 #define PFINT_OICR_GPIO_S 22 4997 #define PFINT_OICR_GPIO_M BIT(22) 4998 #define PFINT_OICR_RSV3_S 23 4999 #define PFINT_OICR_RSV3_M BIT(23) 5000 #define PFINT_OICR_STORM_DETECT_S 24 5001 #define PFINT_OICR_STORM_DETECT_M BIT(24) 5002 #define PFINT_OICR_LINK_STAT_CHANGE_S 25 5003 #define PFINT_OICR_LINK_STAT_CHANGE_M BIT(25) 5004 #define PFINT_OICR_HMC_ERR_S 26 5005 #define PFINT_OICR_HMC_ERR_M BIT(26) 5006 #define PFINT_OICR_PE_PUSH_S 27 5007 #define PFINT_OICR_PE_PUSH_M BIT(27) 5008 #define PFINT_OICR_PE_CRITERR_S 28 5009 #define PFINT_OICR_PE_CRITERR_M BIT(28) 5010 #define PFINT_OICR_VFLR_S 29 5011 #define PFINT_OICR_VFLR_M BIT(29) 5012 #define PFINT_OICR_XLR_HW_DONE_S 30 5013 #define PFINT_OICR_XLR_HW_DONE_M BIT(30) 5014 #define PFINT_OICR_SWINT_S 31 5015 #define PFINT_OICR_SWINT_M BIT(31) 5016 #define PFINT_OICR_CTL 0x0016CA80 /* Reset Source: CORER */ 5017 #define PFINT_OICR_CTL_MSIX_INDX_S 0 5018 #define PFINT_OICR_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 5019 #define PFINT_OICR_CTL_ITR_INDX_S 11 5020 #define PFINT_OICR_CTL_ITR_INDX_M MAKEMASK(0x3, 11) 5021 #define PFINT_OICR_CTL_CAUSE_ENA_S 30 5022 #define PFINT_OICR_CTL_CAUSE_ENA_M BIT(30) 5023 #define PFINT_OICR_CTL_INTEVENT_S 31 5024 #define PFINT_OICR_CTL_INTEVENT_M BIT(31) 5025 #define PFINT_OICR_ENA 0x0016C900 /* Reset Source: CORER */ 5026 #define PFINT_OICR_ENA_RSV0_S 0 5027 #define PFINT_OICR_ENA_RSV0_M BIT(0) 5028 #define PFINT_OICR_ENA_INT_ENA_S 1 5029 #define PFINT_OICR_ENA_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1) 5030 #define PFINT_SB_CTL 0x0016B600 /* Reset Source: CORER */ 5031 #define PFINT_SB_CTL_MSIX_INDX_S 0 5032 #define PFINT_SB_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 5033 #define PFINT_SB_CTL_ITR_INDX_S 11 5034 #define PFINT_SB_CTL_ITR_INDX_M MAKEMASK(0x3, 11) 5035 #define PFINT_SB_CTL_CAUSE_ENA_S 30 5036 #define PFINT_SB_CTL_CAUSE_ENA_M BIT(30) 5037 #define PFINT_SB_CTL_INTEVENT_S 31 5038 #define PFINT_SB_CTL_INTEVENT_M BIT(31) 5039 #define PFINT_TSYN_MSK 0x0016C980 /* Reset Source: CORER */ 5040 #define PFINT_TSYN_MSK_PHY_INDX_S 0 5041 #define PFINT_TSYN_MSK_PHY_INDX_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PFINT_TSYN_MSK_PHY_INDX_M : E800_PFINT_TSYN_MSK_PHY_INDX_M) 5042 #define E800_PFINT_TSYN_MSK_PHY_INDX_M MAKEMASK(0x1F, 0) 5043 #define E830_PFINT_TSYN_MSK_PHY_INDX_M MAKEMASK(0xFF, 0) 5044 #define QINT_RQCTL(_QRX) (0x00150000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */ 5045 #define QINT_RQCTL_MAX_INDEX 2047 5046 #define QINT_RQCTL_MSIX_INDX_S 0 5047 #define QINT_RQCTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 5048 #define QINT_RQCTL_ITR_INDX_S 11 5049 #define QINT_RQCTL_ITR_INDX_M MAKEMASK(0x3, 11) 5050 #define QINT_RQCTL_CAUSE_ENA_S 30 5051 #define QINT_RQCTL_CAUSE_ENA_M BIT(30) 5052 #define QINT_RQCTL_INTEVENT_S 31 5053 #define QINT_RQCTL_INTEVENT_M BIT(31) 5054 #define QINT_TQCTL(_DBQM) (0x00140000 + ((_DBQM) * 4)) /* _i=0...16383 */ /* Reset Source: CORER */ 5055 #define QINT_TQCTL_MAX_INDEX 16383 5056 #define QINT_TQCTL_MSIX_INDX_S 0 5057 #define QINT_TQCTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 5058 #define QINT_TQCTL_ITR_INDX_S 11 5059 #define QINT_TQCTL_ITR_INDX_M MAKEMASK(0x3, 11) 5060 #define QINT_TQCTL_CAUSE_ENA_S 30 5061 #define QINT_TQCTL_CAUSE_ENA_M BIT(30) 5062 #define QINT_TQCTL_INTEVENT_S 31 5063 #define QINT_TQCTL_INTEVENT_M BIT(31) 5064 #define VPINT_AEQCTL(_VF) (0x0016B800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 5065 #define VPINT_AEQCTL_MAX_INDEX 255 5066 #define VPINT_AEQCTL_MSIX_INDX_S 0 5067 #define VPINT_AEQCTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 5068 #define VPINT_AEQCTL_ITR_INDX_S 11 5069 #define VPINT_AEQCTL_ITR_INDX_M MAKEMASK(0x3, 11) 5070 #define VPINT_AEQCTL_CAUSE_ENA_S 30 5071 #define VPINT_AEQCTL_CAUSE_ENA_M BIT(30) 5072 #define VPINT_AEQCTL_INTEVENT_S 31 5073 #define VPINT_AEQCTL_INTEVENT_M BIT(31) 5074 #define VPINT_ALLOC(_VF) (0x001D1000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 5075 #define VPINT_ALLOC_MAX_INDEX 255 5076 #define VPINT_ALLOC_FIRST_S 0 5077 #define VPINT_ALLOC_FIRST_M MAKEMASK(0x7FF, 0) 5078 #define VPINT_ALLOC_LAST_S 12 5079 #define VPINT_ALLOC_LAST_M MAKEMASK(0x7FF, 12) 5080 #define VPINT_ALLOC_VALID_S 31 5081 #define VPINT_ALLOC_VALID_M BIT(31) 5082 #define VPINT_ALLOC_PCI(_VF) (0x0009D000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PCIR */ 5083 #define VPINT_ALLOC_PCI_MAX_INDEX 255 5084 #define VPINT_ALLOC_PCI_FIRST_S 0 5085 #define VPINT_ALLOC_PCI_FIRST_M MAKEMASK(0x7FF, 0) 5086 #define VPINT_ALLOC_PCI_LAST_S 12 5087 #define VPINT_ALLOC_PCI_LAST_M MAKEMASK(0x7FF, 12) 5088 #define VPINT_ALLOC_PCI_VALID_S 31 5089 #define VPINT_ALLOC_PCI_VALID_M BIT(31) 5090 #define VPINT_MBX_CPM_CTL(_VP128) (0x0016B000 + ((_VP128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 5091 #define VPINT_MBX_CPM_CTL_MAX_INDEX 127 5092 #define VPINT_MBX_CPM_CTL_MSIX_INDX_S 0 5093 #define VPINT_MBX_CPM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 5094 #define VPINT_MBX_CPM_CTL_ITR_INDX_S 11 5095 #define VPINT_MBX_CPM_CTL_ITR_INDX_M MAKEMASK(0x3, 11) 5096 #define VPINT_MBX_CPM_CTL_CAUSE_ENA_S 30 5097 #define VPINT_MBX_CPM_CTL_CAUSE_ENA_M BIT(30) 5098 #define VPINT_MBX_CPM_CTL_INTEVENT_S 31 5099 #define VPINT_MBX_CPM_CTL_INTEVENT_M BIT(31) 5100 #define VPINT_MBX_CTL(_VSI) (0x0016A000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 5101 #define VPINT_MBX_CTL_MAX_INDEX 767 5102 #define VPINT_MBX_CTL_MSIX_INDX_S 0 5103 #define VPINT_MBX_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 5104 #define VPINT_MBX_CTL_ITR_INDX_S 11 5105 #define VPINT_MBX_CTL_ITR_INDX_M MAKEMASK(0x3, 11) 5106 #define VPINT_MBX_CTL_CAUSE_ENA_S 30 5107 #define VPINT_MBX_CTL_CAUSE_ENA_M BIT(30) 5108 #define VPINT_MBX_CTL_INTEVENT_S 31 5109 #define VPINT_MBX_CTL_INTEVENT_M BIT(31) 5110 #define VPINT_MBX_HLP_CTL(_VP16) (0x0016B200 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 5111 #define VPINT_MBX_HLP_CTL_MAX_INDEX 15 5112 #define VPINT_MBX_HLP_CTL_MSIX_INDX_S 0 5113 #define VPINT_MBX_HLP_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 5114 #define VPINT_MBX_HLP_CTL_ITR_INDX_S 11 5115 #define VPINT_MBX_HLP_CTL_ITR_INDX_M MAKEMASK(0x3, 11) 5116 #define VPINT_MBX_HLP_CTL_CAUSE_ENA_S 30 5117 #define VPINT_MBX_HLP_CTL_CAUSE_ENA_M BIT(30) 5118 #define VPINT_MBX_HLP_CTL_INTEVENT_S 31 5119 #define VPINT_MBX_HLP_CTL_INTEVENT_M BIT(31) 5120 #define VPINT_MBX_PSM_CTL(_VP16) (0x0016B240 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 5121 #define VPINT_MBX_PSM_CTL_MAX_INDEX 15 5122 #define VPINT_MBX_PSM_CTL_MSIX_INDX_S 0 5123 #define VPINT_MBX_PSM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 5124 #define VPINT_MBX_PSM_CTL_ITR_INDX_S 11 5125 #define VPINT_MBX_PSM_CTL_ITR_INDX_M MAKEMASK(0x3, 11) 5126 #define VPINT_MBX_PSM_CTL_CAUSE_ENA_S 30 5127 #define VPINT_MBX_PSM_CTL_CAUSE_ENA_M BIT(30) 5128 #define VPINT_MBX_PSM_CTL_INTEVENT_S 31 5129 #define VPINT_MBX_PSM_CTL_INTEVENT_M BIT(31) 5130 #define VPINT_SB_CPM_CTL(_VP128) (0x0016B400 + ((_VP128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 5131 #define VPINT_SB_CPM_CTL_MAX_INDEX 127 5132 #define VPINT_SB_CPM_CTL_MSIX_INDX_S 0 5133 #define VPINT_SB_CPM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) 5134 #define VPINT_SB_CPM_CTL_ITR_INDX_S 11 5135 #define VPINT_SB_CPM_CTL_ITR_INDX_M MAKEMASK(0x3, 11) 5136 #define VPINT_SB_CPM_CTL_CAUSE_ENA_S 30 5137 #define VPINT_SB_CPM_CTL_CAUSE_ENA_M BIT(30) 5138 #define VPINT_SB_CPM_CTL_INTEVENT_S 31 5139 #define VPINT_SB_CPM_CTL_INTEVENT_M BIT(31) 5140 #define GL_HLP_PRT_IPG_PREAMBLE_SIZE(_i) (0x00049240 + ((_i) * 4)) /* _i=0...20 */ /* Reset Source: CORER */ 5141 #define GL_HLP_PRT_IPG_PREAMBLE_SIZE_MAX_INDEX 20 5142 #define GL_HLP_PRT_IPG_PREAMBLE_SIZE_IPG_PREAMBLE_SIZE_S 0 5143 #define GL_HLP_PRT_IPG_PREAMBLE_SIZE_IPG_PREAMBLE_SIZE_M MAKEMASK(0xFF, 0) 5144 #define GL_TDPU_PSM_DEFAULT_RECIPE(_i) (0x00049294 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */ 5145 #define GL_TDPU_PSM_DEFAULT_RECIPE_MAX_INDEX 3 5146 #define GL_TDPU_PSM_DEFAULT_RECIPE_ADD_IPG_S 0 5147 #define GL_TDPU_PSM_DEFAULT_RECIPE_ADD_IPG_M BIT(0) 5148 #define GL_TDPU_PSM_DEFAULT_RECIPE_SUB_CRC_S 1 5149 #define GL_TDPU_PSM_DEFAULT_RECIPE_SUB_CRC_M BIT(1) 5150 #define GL_TDPU_PSM_DEFAULT_RECIPE_SUB_ESP_TRAILER_S 2 5151 #define GL_TDPU_PSM_DEFAULT_RECIPE_SUB_ESP_TRAILER_M BIT(2) 5152 #define GL_TDPU_PSM_DEFAULT_RECIPE_INCLUDE_L2_PAD_S 3 5153 #define GL_TDPU_PSM_DEFAULT_RECIPE_INCLUDE_L2_PAD_M BIT(3) 5154 #define GL_TDPU_PSM_DEFAULT_RECIPE_DEFAULT_UPDATE_MODE_S 4 5155 #define GL_TDPU_PSM_DEFAULT_RECIPE_DEFAULT_UPDATE_MODE_M BIT(4) 5156 #define GLLAN_PF_RECIPE(_i) (0x0029420C + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 5157 #define GLLAN_PF_RECIPE_MAX_INDEX 7 5158 #define GLLAN_PF_RECIPE_RECIPE_S 0 5159 #define GLLAN_PF_RECIPE_RECIPE_M MAKEMASK(0x3, 0) 5160 #define GLLAN_RCTL_0 0x002941F8 /* Reset Source: CORER */ 5161 #define GLLAN_RCTL_0_PXE_MODE_S 0 5162 #define GLLAN_RCTL_0_PXE_MODE_M BIT(0) 5163 #define GLLAN_RCTL_1 0x002941FC /* Reset Source: CORER */ 5164 #define GLLAN_RCTL_1_RXMAX_EXPANSION_S 12 5165 #define GLLAN_RCTL_1_RXMAX_EXPANSION_M MAKEMASK(0xF, 12) 5166 #define GLLAN_RCTL_1_RXDRDCTL_S 17 5167 #define GLLAN_RCTL_1_RXDRDCTL_M BIT(17) 5168 #define GLLAN_RCTL_1_RXDESCRDROEN_S 18 5169 #define GLLAN_RCTL_1_RXDESCRDROEN_M BIT(18) 5170 #define GLLAN_RCTL_1_RXDATAWRROEN_S 19 5171 #define GLLAN_RCTL_1_RXDATAWRROEN_M BIT(19) 5172 #define GLLAN_TSOMSK_F 0x00049308 /* Reset Source: CORER */ 5173 #define GLLAN_TSOMSK_F_TCPMSKF_S 0 5174 #define GLLAN_TSOMSK_F_TCPMSKF_M MAKEMASK(0xFFF, 0) 5175 #define GLLAN_TSOMSK_L 0x00049310 /* Reset Source: CORER */ 5176 #define GLLAN_TSOMSK_L_TCPMSKL_S 0 5177 #define GLLAN_TSOMSK_L_TCPMSKL_M MAKEMASK(0xFFF, 0) 5178 #define GLLAN_TSOMSK_M 0x0004930C /* Reset Source: CORER */ 5179 #define GLLAN_TSOMSK_M_TCPMSKM_S 0 5180 #define GLLAN_TSOMSK_M_TCPMSKM_M MAKEMASK(0xFFF, 0) 5181 #define PFLAN_CP_QALLOC 0x00075700 /* Reset Source: CORER */ 5182 #define PFLAN_CP_QALLOC_FIRSTQ_S 0 5183 #define PFLAN_CP_QALLOC_FIRSTQ_M MAKEMASK(0x1FF, 0) 5184 #define PFLAN_CP_QALLOC_LASTQ_S 16 5185 #define PFLAN_CP_QALLOC_LASTQ_M MAKEMASK(0x1FF, 16) 5186 #define PFLAN_CP_QALLOC_VALID_S 31 5187 #define PFLAN_CP_QALLOC_VALID_M BIT(31) 5188 #define PFLAN_DB_QALLOC 0x00075680 /* Reset Source: CORER */ 5189 #define PFLAN_DB_QALLOC_FIRSTQ_S 0 5190 #define PFLAN_DB_QALLOC_FIRSTQ_M MAKEMASK(0xFF, 0) 5191 #define PFLAN_DB_QALLOC_LASTQ_S 16 5192 #define PFLAN_DB_QALLOC_LASTQ_M MAKEMASK(0xFF, 16) 5193 #define PFLAN_DB_QALLOC_VALID_S 31 5194 #define PFLAN_DB_QALLOC_VALID_M BIT(31) 5195 #define PFLAN_RX_QALLOC 0x001D2500 /* Reset Source: CORER */ 5196 #define PFLAN_RX_QALLOC_FIRSTQ_S 0 5197 #define PFLAN_RX_QALLOC_FIRSTQ_M MAKEMASK(0x7FF, 0) 5198 #define PFLAN_RX_QALLOC_LASTQ_S 16 5199 #define PFLAN_RX_QALLOC_LASTQ_M MAKEMASK(0x7FF, 16) 5200 #define PFLAN_RX_QALLOC_VALID_S 31 5201 #define PFLAN_RX_QALLOC_VALID_M BIT(31) 5202 #define PFLAN_TX_QALLOC 0x001D2580 /* Reset Source: CORER */ 5203 #define PFLAN_TX_QALLOC_FIRSTQ_S 0 5204 #define PFLAN_TX_QALLOC_FIRSTQ_M MAKEMASK(0x3FFF, 0) 5205 #define PFLAN_TX_QALLOC_LASTQ_S 16 5206 #define PFLAN_TX_QALLOC_LASTQ_M MAKEMASK(0x3FFF, 16) 5207 #define PFLAN_TX_QALLOC_VALID_S 31 5208 #define PFLAN_TX_QALLOC_VALID_M BIT(31) 5209 #define PRT_TDPUL2TAGSEN 0x00040BA0 /* Reset Source: CORER */ 5210 #define PRT_TDPUL2TAGSEN_ENABLE_S 0 5211 #define PRT_TDPUL2TAGSEN_ENABLE_M MAKEMASK(0xFF, 0) 5212 #define PRT_TDPUL2TAGSEN_NONLAST_TAG_S 8 5213 #define PRT_TDPUL2TAGSEN_NONLAST_TAG_M MAKEMASK(0xFF, 8) 5214 #define QRX_CONTEXT(_i, _QRX) (0x00280000 + ((_i) * 8192 + (_QRX) * 4)) /* _i=0...7, _QRX=0...2047 */ /* Reset Source: CORER */ 5215 #define QRX_CONTEXT_MAX_INDEX 7 5216 #define QRX_CONTEXT_RXQ_CONTEXT_S 0 5217 #define QRX_CONTEXT_RXQ_CONTEXT_M MAKEMASK(0xFFFFFFFF, 0) 5218 #define QRX_CTRL(_QRX) (0x00120000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: PFR */ 5219 #define QRX_CTRL_MAX_INDEX 2047 5220 #define QRX_CTRL_QENA_REQ_S 0 5221 #define QRX_CTRL_QENA_REQ_M BIT(0) 5222 #define QRX_CTRL_FAST_QDIS_S 1 5223 #define QRX_CTRL_FAST_QDIS_M BIT(1) 5224 #define QRX_CTRL_QENA_STAT_S 2 5225 #define QRX_CTRL_QENA_STAT_M BIT(2) 5226 #define QRX_CTRL_CDE_S 3 5227 #define QRX_CTRL_CDE_M BIT(3) 5228 #define QRX_CTRL_CDS_S 4 5229 #define QRX_CTRL_CDS_M BIT(4) 5230 #define QRX_ITR(_QRX) (0x00292000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */ 5231 #define QRX_ITR_MAX_INDEX 2047 5232 #define QRX_ITR_NO_EXPR_S 0 5233 #define QRX_ITR_NO_EXPR_M BIT(0) 5234 #define QRX_TAIL(_QRX) (0x00290000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */ 5235 #define QRX_TAIL_MAX_INDEX 2047 5236 #define QRX_TAIL_TAIL_S 0 5237 #define QRX_TAIL_TAIL_M MAKEMASK(0x1FFF, 0) 5238 #define VPDSI_RX_QTABLE(_i, _VP16) (0x00074C00 + ((_i) * 64 + (_VP16) * 4)) /* _i=0...15, _VP16=0...15 */ /* Reset Source: CORER */ 5239 #define VPDSI_RX_QTABLE_MAX_INDEX 15 5240 #define VPDSI_RX_QTABLE_PAGE_INDEX0_S 0 5241 #define VPDSI_RX_QTABLE_PAGE_INDEX0_M MAKEMASK(0x7F, 0) 5242 #define VPDSI_RX_QTABLE_PAGE_INDEX1_S 8 5243 #define VPDSI_RX_QTABLE_PAGE_INDEX1_M MAKEMASK(0x7F, 8) 5244 #define VPDSI_RX_QTABLE_PAGE_INDEX2_S 16 5245 #define VPDSI_RX_QTABLE_PAGE_INDEX2_M MAKEMASK(0x7F, 16) 5246 #define VPDSI_RX_QTABLE_PAGE_INDEX3_S 24 5247 #define VPDSI_RX_QTABLE_PAGE_INDEX3_M MAKEMASK(0x7F, 24) 5248 #define VPDSI_TX_QTABLE(_i, _VP16) (0x001D2000 + ((_i) * 64 + (_VP16) * 4)) /* _i=0...15, _VP16=0...15 */ /* Reset Source: CORER */ 5249 #define VPDSI_TX_QTABLE_MAX_INDEX 15 5250 #define VPDSI_TX_QTABLE_PAGE_INDEX0_S 0 5251 #define VPDSI_TX_QTABLE_PAGE_INDEX0_M MAKEMASK(0x7F, 0) 5252 #define VPDSI_TX_QTABLE_PAGE_INDEX1_S 8 5253 #define VPDSI_TX_QTABLE_PAGE_INDEX1_M MAKEMASK(0x7F, 8) 5254 #define VPDSI_TX_QTABLE_PAGE_INDEX2_S 16 5255 #define VPDSI_TX_QTABLE_PAGE_INDEX2_M MAKEMASK(0x7F, 16) 5256 #define VPDSI_TX_QTABLE_PAGE_INDEX3_S 24 5257 #define VPDSI_TX_QTABLE_PAGE_INDEX3_M MAKEMASK(0x7F, 24) 5258 #define VPLAN_DB_QTABLE(_i, _VF) (0x00070000 + ((_i) * 2048 + (_VF) * 4)) /* _i=0...3, _VF=0...255 */ /* Reset Source: CORER */ 5259 #define VPLAN_DB_QTABLE_MAX_INDEX 3 5260 #define VPLAN_DB_QTABLE_QINDEX_S 0 5261 #define VPLAN_DB_QTABLE_QINDEX_M MAKEMASK(0x1FF, 0) 5262 #define VPLAN_DSI_VF_MODE(_VP16) (0x002D2C00 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 5263 #define VPLAN_DSI_VF_MODE_MAX_INDEX 15 5264 #define VPLAN_DSI_VF_MODE_LAN_DSI_VF_MODE_S 0 5265 #define VPLAN_DSI_VF_MODE_LAN_DSI_VF_MODE_M BIT(0) 5266 #define VPLAN_RX_QBASE(_VF) (0x00072000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 5267 #define VPLAN_RX_QBASE_MAX_INDEX 255 5268 #define VPLAN_RX_QBASE_VFFIRSTQ_S 0 5269 #define VPLAN_RX_QBASE_VFFIRSTQ_M MAKEMASK(0x7FF, 0) 5270 #define VPLAN_RX_QBASE_VFNUMQ_S 16 5271 #define VPLAN_RX_QBASE_VFNUMQ_M MAKEMASK(0xFF, 16) 5272 #define VPLAN_RX_QBASE_VFQTABLE_ENA_S 31 5273 #define VPLAN_RX_QBASE_VFQTABLE_ENA_M BIT(31) 5274 #define VPLAN_RX_QTABLE(_i, _VF) (0x00060000 + ((_i) * 2048 + (_VF) * 4)) /* _i=0...15, _VF=0...255 */ /* Reset Source: CORER */ 5275 #define VPLAN_RX_QTABLE_MAX_INDEX 15 5276 #define VPLAN_RX_QTABLE_QINDEX_S 0 5277 #define VPLAN_RX_QTABLE_QINDEX_M MAKEMASK(0xFFF, 0) 5278 #define VPLAN_RXQ_MAPENA(_VF) (0x00073000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 5279 #define VPLAN_RXQ_MAPENA_MAX_INDEX 255 5280 #define VPLAN_RXQ_MAPENA_RX_ENA_S 0 5281 #define VPLAN_RXQ_MAPENA_RX_ENA_M BIT(0) 5282 #define VPLAN_TX_QBASE(_VF) (0x001D1800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 5283 #define VPLAN_TX_QBASE_MAX_INDEX 255 5284 #define VPLAN_TX_QBASE_VFFIRSTQ_S 0 5285 #define VPLAN_TX_QBASE_VFFIRSTQ_M MAKEMASK(0x3FFF, 0) 5286 #define VPLAN_TX_QBASE_VFNUMQ_S 16 5287 #define VPLAN_TX_QBASE_VFNUMQ_M MAKEMASK(0xFF, 16) 5288 #define VPLAN_TX_QBASE_VFQTABLE_ENA_S 31 5289 #define VPLAN_TX_QBASE_VFQTABLE_ENA_M BIT(31) 5290 #define VPLAN_TX_QTABLE(_i, _VF) (0x001C0000 + ((_i) * 2048 + (_VF) * 4)) /* _i=0...15, _VF=0...255 */ /* Reset Source: CORER */ 5291 #define VPLAN_TX_QTABLE_MAX_INDEX 15 5292 #define VPLAN_TX_QTABLE_QINDEX_S 0 5293 #define VPLAN_TX_QTABLE_QINDEX_M MAKEMASK(0x7FFF, 0) 5294 #define VPLAN_TXQ_MAPENA(_VF) (0x00073800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 5295 #define VPLAN_TXQ_MAPENA_MAX_INDEX 255 5296 #define VPLAN_TXQ_MAPENA_TX_ENA_S 0 5297 #define VPLAN_TXQ_MAPENA_TX_ENA_M BIT(0) 5298 #define VSILAN_QBASE(_VSI) (0x0044C000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */ 5299 #define VSILAN_QBASE_MAX_INDEX 767 5300 #define VSILAN_QBASE_VSIBASE_S 0 5301 #define VSILAN_QBASE_VSIBASE_M MAKEMASK(0x7FF, 0) 5302 #define VSILAN_QBASE_VSIQTABLE_ENA_S 11 5303 #define VSILAN_QBASE_VSIQTABLE_ENA_M BIT(11) 5304 #define VSILAN_QTABLE(_i, _VSI) (0x00440000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...7, _VSI=0...767 */ /* Reset Source: PFR */ 5305 #define VSILAN_QTABLE_MAX_INDEX 7 5306 #define VSILAN_QTABLE_QINDEX_0_S 0 5307 #define VSILAN_QTABLE_QINDEX_0_M MAKEMASK(0x7FF, 0) 5308 #define VSILAN_QTABLE_QINDEX_1_S 16 5309 #define VSILAN_QTABLE_QINDEX_1_M MAKEMASK(0x7FF, 16) 5310 #define E800_PRTMAC_HSEC_CTL_RX_ENABLE_GCP 0x001E31C0 /* Reset Source: GLOBR */ 5311 #define E800_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_S 0 5312 #define E800_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_M BIT(0) 5313 #define E800_PRTMAC_HSEC_CTL_RX_ENABLE_GPP 0x001E34C0 /* Reset Source: GLOBR */ 5314 #define E800_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_S 0 5315 #define E800_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_M BIT(0) 5316 #define E800_PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E35C0 /* Reset Source: GLOBR */ 5317 #define E800_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_S 0 5318 #define E800_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_M BIT(0) 5319 #define E800_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL 0x001E36C0 /* Reset Source: GLOBR */ 5320 #define E800_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_S 0 5321 #define E800_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_M BIT(0) 5322 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3220 /* Reset Source: GLOBR */ 5323 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_S 0 5324 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_M MAKEMASK(0xFFFFFFFF, 0) 5325 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3240 /* Reset Source: GLOBR */ 5326 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_S 0 5327 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_M MAKEMASK(0xFFFF, 0) 5328 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E3180 /* Reset Source: GLOBR */ 5329 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_S 0 5330 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0) 5331 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1 0x001E3280 /* Reset Source: GLOBR */ 5332 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_S 0 5333 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_M MAKEMASK(0xFFFFFFFF, 0) 5334 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2 0x001E32A0 /* Reset Source: GLOBR */ 5335 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_S 0 5336 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_M MAKEMASK(0xFFFF, 0) 5337 #define E800_PRTMAC_HSEC_CTL_RX_QUANTA_S 0x001E3C40 /* Reset Source: GLOBR */ 5338 #define E800_PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_S 0 5339 #define E800_PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_M MAKEMASK(0xFFFF, 0) 5340 #define E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE 0x001E31A0 /* Reset Source: GLOBR */ 5341 #define E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_S 0 5342 #define E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0) 5343 #define E800_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E36E0 + ((_i) * 32)) /* _i=0...8 */ /* Reset Source: GLOBR */ 5344 #define E800_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8 5345 #define E800_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_S 0 5346 #define E800_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0) 5347 #define E800_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3800 + ((_i) * 32)) /* _i=0...8 */ /* Reset Source: GLOBR */ 5348 #define E800_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8 5349 #define E800_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_S 0 5350 #define E800_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M MAKEMASK(0xFFFF, 0) 5351 #define E800_PRTMAC_HSEC_CTL_TX_SA_PART1 0x001E3960 /* Reset Source: GLOBR */ 5352 #define E800_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_S 0 5353 #define E800_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_M MAKEMASK(0xFFFFFFFF, 0) 5354 #define E800_PRTMAC_HSEC_CTL_TX_SA_PART2 0x001E3980 /* Reset Source: GLOBR */ 5355 #define E800_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_S 0 5356 #define E800_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_M MAKEMASK(0xFFFF, 0) 5357 #define PRTMAC_LINK_DOWN_COUNTER_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_LINK_DOWN_COUNTER : E800_PRTMAC_LINK_DOWN_COUNTER) 5358 #define E800_PRTMAC_LINK_DOWN_COUNTER 0x001E47C0 /* Reset Source: GLOBR */ 5359 #define E830_PRTMAC_LINK_DOWN_COUNTER 0x001E2460 /* Reset Source: GLOBR */ 5360 #define PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_S 0 5361 #define PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_M MAKEMASK(0xFFFF, 0) 5362 #define PRTMAC_MD_OVRRIDE_ENABLE_BY_MAC(hw, _i) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_MD_OVRRIDE_ENABLE(_i) : E800_PRTMAC_MD_OVRRIDE_ENABLE(_i)) 5363 #define E800_PRTMAC_MD_OVRRIDE_ENABLE(_i) (0x001E3C60 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: GLOBR */ 5364 #define E830_PRTMAC_MD_OVRRIDE_ENABLE(_i) (0x001E2500 + ((_i) * 32)) /* _i=0...1 */ /* Reset Source: GLOBR */ 5365 #define PRTMAC_MD_OVRRIDE_ENABLE_MAX_INDEX_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_MD_OVRRIDE_ENABLE_MAX_INDEX : E800_PRTMAC_MD_OVRRIDE_ENABLE_MAX_INDEX) 5366 #define E800_PRTMAC_MD_OVRRIDE_ENABLE_MAX_INDEX 7 5367 #define E830_PRTMAC_MD_OVRRIDE_ENABLE_MAX_INDEX 1 5368 #define PRTMAC_MD_OVRRIDE_ENABLE_PRTMAC_MD_OVRRIDE_ENABLE_S 0 5369 #define PRTMAC_MD_OVRRIDE_ENABLE_PRTMAC_MD_OVRRIDE_ENABLE_M MAKEMASK(0xFFFFFFFF, 0) 5370 #define PRTMAC_MD_OVRRIDE_VAL_BY_MAC(hw, _i) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_MD_OVRRIDE_VAL(_i) : E800_PRTMAC_MD_OVRRIDE_VAL(_i)) 5371 #define E800_PRTMAC_MD_OVRRIDE_VAL(_i) (0x001E3D60 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: GLOBR */ 5372 #define E830_PRTMAC_MD_OVRRIDE_VAL(_i) (0x001E2600 + ((_i) * 32)) /* _i=0...1 */ /* Reset Source: GLOBR */ 5373 #define PRTMAC_MD_OVRRIDE_VAL_MAX_INDEX_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_MD_OVRRIDE_VAL_MAX_INDEX : E800_PRTMAC_MD_OVRRIDE_VAL_MAX_INDEX) 5374 #define E800_PRTMAC_MD_OVRRIDE_VAL_MAX_INDEX 7 5375 #define E830_PRTMAC_MD_OVRRIDE_VAL_MAX_INDEX 1 5376 #define PRTMAC_MD_OVRRIDE_VAL_PRTMAC_MD_OVRRIDE_ENABLE_S 0 5377 #define PRTMAC_MD_OVRRIDE_VAL_PRTMAC_MD_OVRRIDE_ENABLE_M MAKEMASK(0xFFFFFFFF, 0) 5378 #define PRTMAC_RX_CNT_MRKR 0x001E48E0 /* Reset Source: GLOBR */ 5379 #define PRTMAC_RX_CNT_MRKR_RX_CNT_MRKR_S 0 5380 #define PRTMAC_RX_CNT_MRKR_RX_CNT_MRKR_M MAKEMASK(0xFFFF, 0) 5381 #define PRTMAC_RX_PKT_DRP_CNT_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_RX_PKT_DRP_CNT : E800_PRTMAC_RX_PKT_DRP_CNT) 5382 #define E800_PRTMAC_RX_PKT_DRP_CNT 0x001E3C20 /* Reset Source: GLOBR */ 5383 #define E830_PRTMAC_RX_PKT_DRP_CNT 0x001E2420 /* Reset Source: GLOBR */ 5384 #define PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_S 0 5385 #define PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_M : E800_PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_M) 5386 #define E800_PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_M MAKEMASK(0xFFFF, 0) 5387 #define E830_PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_M MAKEMASK(0xFFF, 0) 5388 #define PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_S_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_S : E800_PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_S) 5389 #define E800_PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_S 16 5390 #define E830_PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_S 28 5391 #define PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_M : E800_PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_M) 5392 #define E800_PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_M MAKEMASK(0xFFFF, 16) 5393 #define E830_PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_M MAKEMASK(0xF, 28) 5394 #define PRTMAC_TX_CNT_MRKR 0x001E48C0 /* Reset Source: GLOBR */ 5395 #define PRTMAC_TX_CNT_MRKR_TX_CNT_MRKR_S 0 5396 #define PRTMAC_TX_CNT_MRKR_TX_CNT_MRKR_M MAKEMASK(0xFFFF, 0) 5397 #define PRTMAC_TX_LNK_UP_CNT_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_TX_LNK_UP_CNT : E800_PRTMAC_TX_LNK_UP_CNT) 5398 #define E800_PRTMAC_TX_LNK_UP_CNT 0x001E4840 /* Reset Source: GLOBR */ 5399 #define E830_PRTMAC_TX_LNK_UP_CNT 0x001E2480 /* Reset Source: GLOBR */ 5400 #define PRTMAC_TX_LNK_UP_CNT_TX_LINK_UP_CNT_S 0 5401 #define PRTMAC_TX_LNK_UP_CNT_TX_LINK_UP_CNT_M MAKEMASK(0xFFFF, 0) 5402 #define GL_MDCK_CFG1_TX_PQM 0x002D2DF4 /* Reset Source: CORER */ 5403 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_DATA_LEN_S 0 5404 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_DATA_LEN_M MAKEMASK(0xFF, 0) 5405 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_PKT_CNT_S 8 5406 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_PKT_CNT_M MAKEMASK(0x3F, 8) 5407 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_DESC_CNT_S 16 5408 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_DESC_CNT_M MAKEMASK(0x3F, 16) 5409 #define GL_MDCK_EN_TX_PQM 0x002D2DFC /* Reset Source: CORER */ 5410 #define GL_MDCK_EN_TX_PQM_PCI_DUMMY_COMP_S 0 5411 #define GL_MDCK_EN_TX_PQM_PCI_DUMMY_COMP_M BIT(0) 5412 #define GL_MDCK_EN_TX_PQM_PCI_UR_COMP_S 1 5413 #define GL_MDCK_EN_TX_PQM_PCI_UR_COMP_M BIT(1) 5414 #define GL_MDCK_EN_TX_PQM_RCV_SH_BE_LSO_S 3 5415 #define GL_MDCK_EN_TX_PQM_RCV_SH_BE_LSO_M BIT(3) 5416 #define GL_MDCK_EN_TX_PQM_Q_FL_MNG_EPY_CH_S 4 5417 #define GL_MDCK_EN_TX_PQM_Q_FL_MNG_EPY_CH_M BIT(4) 5418 #define GL_MDCK_EN_TX_PQM_Q_EPY_MNG_FL_CH_S 5 5419 #define GL_MDCK_EN_TX_PQM_Q_EPY_MNG_FL_CH_M BIT(5) 5420 #define GL_MDCK_EN_TX_PQM_LSO_NUMDESCS_ZERO_S 6 5421 #define GL_MDCK_EN_TX_PQM_LSO_NUMDESCS_ZERO_M BIT(6) 5422 #define GL_MDCK_EN_TX_PQM_LSO_LENGTH_ZERO_S 7 5423 #define GL_MDCK_EN_TX_PQM_LSO_LENGTH_ZERO_M BIT(7) 5424 #define GL_MDCK_EN_TX_PQM_LSO_MSS_BELOW_MIN_S 8 5425 #define GL_MDCK_EN_TX_PQM_LSO_MSS_BELOW_MIN_M BIT(8) 5426 #define GL_MDCK_EN_TX_PQM_LSO_MSS_ABOVE_MAX_S 9 5427 #define GL_MDCK_EN_TX_PQM_LSO_MSS_ABOVE_MAX_M BIT(9) 5428 #define GL_MDCK_EN_TX_PQM_LSO_HDR_SIZE_ZERO_S 10 5429 #define GL_MDCK_EN_TX_PQM_LSO_HDR_SIZE_ZERO_M BIT(10) 5430 #define GL_MDCK_EN_TX_PQM_RCV_CNT_BE_LSO_S 11 5431 #define GL_MDCK_EN_TX_PQM_RCV_CNT_BE_LSO_M BIT(11) 5432 #define GL_MDCK_EN_TX_PQM_SKIP_ONE_QT_ONLY_S 12 5433 #define GL_MDCK_EN_TX_PQM_SKIP_ONE_QT_ONLY_M BIT(12) 5434 #define GL_MDCK_EN_TX_PQM_LSO_PKTCNT_ZERO_S 13 5435 #define GL_MDCK_EN_TX_PQM_LSO_PKTCNT_ZERO_M BIT(13) 5436 #define GL_MDCK_EN_TX_PQM_SSO_LENGTH_ZERO_S 14 5437 #define GL_MDCK_EN_TX_PQM_SSO_LENGTH_ZERO_M BIT(14) 5438 #define GL_MDCK_EN_TX_PQM_SSO_LENGTH_EXCEED_S 15 5439 #define GL_MDCK_EN_TX_PQM_SSO_LENGTH_EXCEED_M BIT(15) 5440 #define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_ZERO_S 16 5441 #define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_ZERO_M BIT(16) 5442 #define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_EXCEED_S 17 5443 #define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_EXCEED_M BIT(17) 5444 #define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_ZERO_S 18 5445 #define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_ZERO_M BIT(18) 5446 #define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_S 19 5447 #define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_M BIT(19) 5448 #define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_S 20 5449 #define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_M BIT(20) 5450 #define GL_MDCK_EN_TX_PQM_RESERVED_DBL_TYPE_S 21 5451 #define GL_MDCK_EN_TX_PQM_RESERVED_DBL_TYPE_M BIT(21) 5452 #define GL_MDCK_EN_TX_PQM_ILLEGAL_HEAD_DROP_DBL_S 22 5453 #define GL_MDCK_EN_TX_PQM_ILLEGAL_HEAD_DROP_DBL_M BIT(22) 5454 #define GL_MDCK_EN_TX_PQM_LSO_OVER_COMMS_Q_S 23 5455 #define GL_MDCK_EN_TX_PQM_LSO_OVER_COMMS_Q_M BIT(23) 5456 #define GL_MDCK_EN_TX_PQM_ILLEGAL_VF_QNUM_S 24 5457 #define GL_MDCK_EN_TX_PQM_ILLEGAL_VF_QNUM_M BIT(24) 5458 #define GL_MDCK_EN_TX_PQM_QTAIL_GT_RING_LENGTH_S 25 5459 #define GL_MDCK_EN_TX_PQM_QTAIL_GT_RING_LENGTH_M BIT(25) 5460 #define E800_GL_MDCK_EN_TX_PQM_RSVD_S 26 5461 #define E800_GL_MDCK_EN_TX_PQM_RSVD_M MAKEMASK(0x3F, 26) 5462 #define GL_MDCK_RX 0x0029422C /* Reset Source: CORER */ 5463 #define GL_MDCK_RX_DESC_ADDR_S 0 5464 #define GL_MDCK_RX_DESC_ADDR_M BIT(0) 5465 #define GL_MDCK_TX_TDPU 0x00049348 /* Reset Source: CORER */ 5466 #define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_S 0 5467 #define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_M BIT(0) 5468 #define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_S 1 5469 #define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1) 5470 #define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_S 2 5471 #define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_M BIT(2) 5472 #define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_S 3 5473 #define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_M BIT(3) 5474 #define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_S 4 5475 #define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_M BIT(4) 5476 #define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_S 5 5477 #define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_M BIT(5) 5478 #define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_S 6 5479 #define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_M BIT(6) 5480 #define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_S 7 5481 #define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_M BIT(7) 5482 #define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_S 8 5483 #define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_M BIT(8) 5484 #define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_S 9 5485 #define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_M BIT(9) 5486 #define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_S 10 5487 #define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_M BIT(10) 5488 #define GL_MDET_RX 0x00294C00 /* Reset Source: CORER */ 5489 #define GL_MDET_RX_QNUM_S 0 5490 #define GL_MDET_RX_QNUM_M MAKEMASK(0x7FFF, 0) 5491 #define GL_MDET_RX_VF_NUM_S 15 5492 #define GL_MDET_RX_VF_NUM_M MAKEMASK(0xFF, 15) 5493 #define GL_MDET_RX_PF_NUM_S 23 5494 #define GL_MDET_RX_PF_NUM_M MAKEMASK(0x7, 23) 5495 #define GL_MDET_RX_MAL_TYPE_S 26 5496 #define GL_MDET_RX_MAL_TYPE_M MAKEMASK(0x1F, 26) 5497 #define GL_MDET_RX_VALID_S 31 5498 #define GL_MDET_RX_VALID_M BIT(31) 5499 #define GL_MDET_TX_PQM 0x002D2E00 /* Reset Source: CORER */ 5500 #define GL_MDET_TX_PQM_PF_NUM_S 0 5501 #define GL_MDET_TX_PQM_PF_NUM_M MAKEMASK(0x7, 0) 5502 #define GL_MDET_TX_PQM_VF_NUM_S 4 5503 #define GL_MDET_TX_PQM_VF_NUM_M MAKEMASK(0xFF, 4) 5504 #define GL_MDET_TX_PQM_QNUM_S 12 5505 #define GL_MDET_TX_PQM_QNUM_M MAKEMASK(0x3FFF, 12) 5506 #define GL_MDET_TX_PQM_MAL_TYPE_S 26 5507 #define GL_MDET_TX_PQM_MAL_TYPE_M MAKEMASK(0x1F, 26) 5508 #define GL_MDET_TX_PQM_VALID_S 31 5509 #define GL_MDET_TX_PQM_VALID_M BIT(31) 5510 #define GL_MDET_TX_TCLAN 0x000FC068 /* Reset Source: CORER */ 5511 #define GL_MDET_TX_TCLAN_QNUM_S 0 5512 #define GL_MDET_TX_TCLAN_QNUM_M MAKEMASK(0x7FFF, 0) 5513 #define GL_MDET_TX_TCLAN_VF_NUM_S 15 5514 #define GL_MDET_TX_TCLAN_VF_NUM_M MAKEMASK(0xFF, 15) 5515 #define GL_MDET_TX_TCLAN_PF_NUM_S 23 5516 #define GL_MDET_TX_TCLAN_PF_NUM_M MAKEMASK(0x7, 23) 5517 #define GL_MDET_TX_TCLAN_MAL_TYPE_S 26 5518 #define GL_MDET_TX_TCLAN_MAL_TYPE_M MAKEMASK(0x1F, 26) 5519 #define GL_MDET_TX_TCLAN_VALID_S 31 5520 #define GL_MDET_TX_TCLAN_VALID_M BIT(31) 5521 #define GL_MDET_TX_TDPU 0x00049350 /* Reset Source: CORER */ 5522 #define GL_MDET_TX_TDPU_QNUM_S 0 5523 #define GL_MDET_TX_TDPU_QNUM_M MAKEMASK(0x7FFF, 0) 5524 #define GL_MDET_TX_TDPU_VF_NUM_S 15 5525 #define GL_MDET_TX_TDPU_VF_NUM_M MAKEMASK(0xFF, 15) 5526 #define GL_MDET_TX_TDPU_PF_NUM_S 23 5527 #define GL_MDET_TX_TDPU_PF_NUM_M MAKEMASK(0x7, 23) 5528 #define GL_MDET_TX_TDPU_MAL_TYPE_S 26 5529 #define GL_MDET_TX_TDPU_MAL_TYPE_M MAKEMASK(0x1F, 26) 5530 #define GL_MDET_TX_TDPU_VALID_S 31 5531 #define GL_MDET_TX_TDPU_VALID_M BIT(31) 5532 #define GLRLAN_MDET 0x00294200 /* Reset Source: CORER */ 5533 #define GLRLAN_MDET_PCKT_EXTRCT_ERR_S 0 5534 #define GLRLAN_MDET_PCKT_EXTRCT_ERR_M BIT(0) 5535 #define PF_MDET_RX 0x00294280 /* Reset Source: CORER */ 5536 #define PF_MDET_RX_VALID_S 0 5537 #define PF_MDET_RX_VALID_M BIT(0) 5538 #define PF_MDET_TX_PQM 0x002D2C80 /* Reset Source: CORER */ 5539 #define PF_MDET_TX_PQM_VALID_S 0 5540 #define PF_MDET_TX_PQM_VALID_M BIT(0) 5541 #define PF_MDET_TX_TCLAN 0x000FC000 /* Reset Source: CORER */ 5542 #define PF_MDET_TX_TCLAN_VALID_S 0 5543 #define PF_MDET_TX_TCLAN_VALID_M BIT(0) 5544 #define PF_MDET_TX_TDPU 0x00040800 /* Reset Source: CORER */ 5545 #define PF_MDET_TX_TDPU_VALID_S 0 5546 #define PF_MDET_TX_TDPU_VALID_M BIT(0) 5547 #define VP_MDET_RX(_VF) (0x00294400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 5548 #define VP_MDET_RX_MAX_INDEX 255 5549 #define VP_MDET_RX_VALID_S 0 5550 #define VP_MDET_RX_VALID_M BIT(0) 5551 #define VP_MDET_TX_PQM(_VF) (0x002D2000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 5552 #define VP_MDET_TX_PQM_MAX_INDEX 255 5553 #define VP_MDET_TX_PQM_VALID_S 0 5554 #define VP_MDET_TX_PQM_VALID_M BIT(0) 5555 #define VP_MDET_TX_TCLAN(_VF) (0x000FB800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 5556 #define VP_MDET_TX_TCLAN_MAX_INDEX 255 5557 #define VP_MDET_TX_TCLAN_VALID_S 0 5558 #define VP_MDET_TX_TCLAN_VALID_M BIT(0) 5559 #define VP_MDET_TX_TDPU(_VF) (0x00040000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 5560 #define VP_MDET_TX_TDPU_MAX_INDEX 255 5561 #define VP_MDET_TX_TDPU_VALID_S 0 5562 #define VP_MDET_TX_TDPU_VALID_M BIT(0) 5563 #define GENERAL_MNG_FW_DBG_CSR(_i) (0x000B6180 + ((_i) * 4)) /* _i=0...9 */ /* Reset Source: POR */ 5564 #define GENERAL_MNG_FW_DBG_CSR_MAX_INDEX 9 5565 #define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_S 0 5566 #define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_M MAKEMASK(0xFFFFFFFF, 0) 5567 #define GL_FWRESETCNT 0x00083100 /* Reset Source: POR */ 5568 #define GL_FWRESETCNT_FWRESETCNT_S 0 5569 #define GL_FWRESETCNT_FWRESETCNT_M MAKEMASK(0xFFFFFFFF, 0) 5570 #define GL_MNG_FW_RAM_STAT_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MNG_FW_RAM_STAT : E800_GL_MNG_FW_RAM_STAT) 5571 #define E800_GL_MNG_FW_RAM_STAT 0x0008309C /* Reset Source: POR */ 5572 #define E830_GL_MNG_FW_RAM_STAT 0x000830F4 /* Reset Source: POR */ 5573 #define GL_MNG_FW_RAM_STAT_FW_RAM_RST_STAT_S 0 5574 #define GL_MNG_FW_RAM_STAT_FW_RAM_RST_STAT_M BIT(0) 5575 #define GL_MNG_FW_RAM_STAT_MNG_MEM_ECC_ERR_S 1 5576 #define GL_MNG_FW_RAM_STAT_MNG_MEM_ECC_ERR_M BIT(1) 5577 #define GL_MNG_FWSM 0x000B6134 /* Reset Source: POR */ 5578 #define GL_MNG_FWSM_FW_MODES_S 0 5579 #define GL_MNG_FWSM_FW_MODES_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MNG_FWSM_FW_MODES_M : E800_GL_MNG_FWSM_FW_MODES_M) 5580 #define E800_GL_MNG_FWSM_FW_MODES_M MAKEMASK(0x7, 0) 5581 #define E830_GL_MNG_FWSM_FW_MODES_M MAKEMASK(0x3, 0) 5582 #define GL_MNG_FWSM_RSV0_S_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MNG_FWSM_RSV0_S : E800_GL_MNG_FWSM_RSV0_S) 5583 #define E800_GL_MNG_FWSM_RSV0_S 3 5584 #define E830_GL_MNG_FWSM_RSV0_S 2 5585 #define GL_MNG_FWSM_RSV0_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MNG_FWSM_RSV0_M : E800_GL_MNG_FWSM_RSV0_M) 5586 #define E800_GL_MNG_FWSM_RSV0_M MAKEMASK(0x7F, 3) 5587 #define E830_GL_MNG_FWSM_RSV0_M MAKEMASK(0xFF, 2) 5588 #define GL_MNG_FWSM_EEP_RELOAD_IND_S 10 5589 #define GL_MNG_FWSM_EEP_RELOAD_IND_M BIT(10) 5590 #define GL_MNG_FWSM_RSV1_S 11 5591 #define GL_MNG_FWSM_RSV1_M MAKEMASK(0xF, 11) 5592 #define GL_MNG_FWSM_RSV2_S 15 5593 #define GL_MNG_FWSM_RSV2_M BIT(15) 5594 #define GL_MNG_FWSM_PCIR_AL_FAILURE_S 16 5595 #define GL_MNG_FWSM_PCIR_AL_FAILURE_M BIT(16) 5596 #define GL_MNG_FWSM_POR_AL_FAILURE_S 17 5597 #define GL_MNG_FWSM_POR_AL_FAILURE_M BIT(17) 5598 #define GL_MNG_FWSM_RSV3_S 18 5599 #define GL_MNG_FWSM_RSV3_M BIT(18) 5600 #define GL_MNG_FWSM_EXT_ERR_IND_S 19 5601 #define GL_MNG_FWSM_EXT_ERR_IND_M MAKEMASK(0x3F, 19) 5602 #define GL_MNG_FWSM_RSV4_S 25 5603 #define GL_MNG_FWSM_RSV4_M BIT(25) 5604 #define GL_MNG_FWSM_RESERVED_11_S 26 5605 #define GL_MNG_FWSM_RESERVED_11_M MAKEMASK(0xF, 26) 5606 #define GL_MNG_FWSM_RSV5_S 30 5607 #define GL_MNG_FWSM_RSV5_M MAKEMASK(0x3, 30) 5608 #define GL_MNG_HWARB_CTRL 0x000B6130 /* Reset Source: POR */ 5609 #define GL_MNG_HWARB_CTRL_NCSI_ARB_EN_S 0 5610 #define GL_MNG_HWARB_CTRL_NCSI_ARB_EN_M BIT(0) 5611 #define GL_MNG_SHA_EXTEND_BY_MAC(hw, _i) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MNG_SHA_EXTEND(_i) : E800_GL_MNG_SHA_EXTEND(_i)) 5612 #define E800_GL_MNG_SHA_EXTEND(_i) (0x00083120 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: EMPR */ 5613 #define E830_GL_MNG_SHA_EXTEND(_i) (0x00083340 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: EMPR */ 5614 #define GL_MNG_SHA_EXTEND_MAX_INDEX_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MNG_SHA_EXTEND_MAX_INDEX : E800_GL_MNG_SHA_EXTEND_MAX_INDEX) 5615 #define E800_GL_MNG_SHA_EXTEND_MAX_INDEX 7 5616 #define E830_GL_MNG_SHA_EXTEND_MAX_INDEX 11 5617 #define GL_MNG_SHA_EXTEND_GL_MNG_SHA_EXTEND_S 0 5618 #define GL_MNG_SHA_EXTEND_GL_MNG_SHA_EXTEND_M MAKEMASK(0xFFFFFFFF, 0) 5619 #define GL_MNG_SHA_EXTEND_ROM_BY_MAC(hw, _i) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MNG_SHA_EXTEND_ROM(_i) : E800_GL_MNG_SHA_EXTEND_ROM(_i)) 5620 #define E800_GL_MNG_SHA_EXTEND_ROM(_i) (0x00083160 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: EMPR */ 5621 #define E830_GL_MNG_SHA_EXTEND_ROM(_i) (0x000832C0 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: EMPR */ 5622 #define GL_MNG_SHA_EXTEND_ROM_MAX_INDEX_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MNG_SHA_EXTEND_ROM_MAX_INDEX : E800_GL_MNG_SHA_EXTEND_ROM_MAX_INDEX) 5623 #define E800_GL_MNG_SHA_EXTEND_ROM_MAX_INDEX 7 5624 #define E830_GL_MNG_SHA_EXTEND_ROM_MAX_INDEX 11 5625 #define GL_MNG_SHA_EXTEND_ROM_GL_MNG_SHA_EXTEND_ROM_S 0 5626 #define GL_MNG_SHA_EXTEND_ROM_GL_MNG_SHA_EXTEND_ROM_M MAKEMASK(0xFFFFFFFF, 0) 5627 #define GL_MNG_SHA_EXTEND_STATUS 0x00083148 /* Reset Source: EMPR */ 5628 #define GL_MNG_SHA_EXTEND_STATUS_STAGE_S 0 5629 #define GL_MNG_SHA_EXTEND_STATUS_STAGE_M MAKEMASK(0x7, 0) 5630 #define GL_MNG_SHA_EXTEND_STATUS_FW_HALTED_S 30 5631 #define GL_MNG_SHA_EXTEND_STATUS_FW_HALTED_M BIT(30) 5632 #define GL_MNG_SHA_EXTEND_STATUS_DONE_S 31 5633 #define GL_MNG_SHA_EXTEND_STATUS_DONE_M BIT(31) 5634 #define GL_SWT_PRT2MDEF(_i) (0x00216018 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: POR */ 5635 #define GL_SWT_PRT2MDEF_MAX_INDEX 31 5636 #define GL_SWT_PRT2MDEF_MDEFIDX_S 0 5637 #define GL_SWT_PRT2MDEF_MDEFIDX_M MAKEMASK(0x7, 0) 5638 #define GL_SWT_PRT2MDEF_MDEFENA_S 31 5639 #define GL_SWT_PRT2MDEF_MDEFENA_M BIT(31) 5640 #define PRT_MNG_MANC 0x00214720 /* Reset Source: POR */ 5641 #define PRT_MNG_MANC_FLOW_CONTROL_DISCARD_S 0 5642 #define PRT_MNG_MANC_FLOW_CONTROL_DISCARD_M BIT(0) 5643 #define PRT_MNG_MANC_NCSI_DISCARD_S 1 5644 #define PRT_MNG_MANC_NCSI_DISCARD_M BIT(1) 5645 #define PRT_MNG_MANC_RCV_TCO_EN_S 17 5646 #define PRT_MNG_MANC_RCV_TCO_EN_M BIT(17) 5647 #define PRT_MNG_MANC_RCV_ALL_S 19 5648 #define PRT_MNG_MANC_RCV_ALL_M BIT(19) 5649 #define PRT_MNG_MANC_FIXED_NET_TYPE_S 25 5650 #define PRT_MNG_MANC_FIXED_NET_TYPE_M BIT(25) 5651 #define PRT_MNG_MANC_NET_TYPE_S 26 5652 #define PRT_MNG_MANC_NET_TYPE_M BIT(26) 5653 #define PRT_MNG_MANC_EN_BMC2OS_S 28 5654 #define PRT_MNG_MANC_EN_BMC2OS_M BIT(28) 5655 #define PRT_MNG_MANC_EN_BMC2NET_S 29 5656 #define PRT_MNG_MANC_EN_BMC2NET_M BIT(29) 5657 #define PRT_MNG_MAVTV(_i) (0x00214780 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: POR */ 5658 #define PRT_MNG_MAVTV_MAX_INDEX 7 5659 #define PRT_MNG_MAVTV_VID_S 0 5660 #define PRT_MNG_MAVTV_VID_M MAKEMASK(0xFFF, 0) 5661 #define PRT_MNG_MDEF(_i) (0x00214880 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: POR */ 5662 #define PRT_MNG_MDEF_MAX_INDEX 7 5663 #define PRT_MNG_MDEF_MAC_EXACT_AND_S 0 5664 #define PRT_MNG_MDEF_MAC_EXACT_AND_M MAKEMASK(0xF, 0) 5665 #define PRT_MNG_MDEF_BROADCAST_AND_S 4 5666 #define PRT_MNG_MDEF_BROADCAST_AND_M BIT(4) 5667 #define PRT_MNG_MDEF_VLAN_AND_S 5 5668 #define PRT_MNG_MDEF_VLAN_AND_M MAKEMASK(0xFF, 5) 5669 #define PRT_MNG_MDEF_IPV4_ADDRESS_AND_S 13 5670 #define PRT_MNG_MDEF_IPV4_ADDRESS_AND_M MAKEMASK(0xF, 13) 5671 #define PRT_MNG_MDEF_IPV6_ADDRESS_AND_S 17 5672 #define PRT_MNG_MDEF_IPV6_ADDRESS_AND_M MAKEMASK(0xF, 17) 5673 #define PRT_MNG_MDEF_MAC_EXACT_OR_S 21 5674 #define PRT_MNG_MDEF_MAC_EXACT_OR_M MAKEMASK(0xF, 21) 5675 #define PRT_MNG_MDEF_BROADCAST_OR_S 25 5676 #define PRT_MNG_MDEF_BROADCAST_OR_M BIT(25) 5677 #define PRT_MNG_MDEF_MULTICAST_AND_S 26 5678 #define PRT_MNG_MDEF_MULTICAST_AND_M BIT(26) 5679 #define PRT_MNG_MDEF_ARP_REQUEST_OR_S 27 5680 #define PRT_MNG_MDEF_ARP_REQUEST_OR_M BIT(27) 5681 #define PRT_MNG_MDEF_ARP_RESPONSE_OR_S 28 5682 #define PRT_MNG_MDEF_ARP_RESPONSE_OR_M BIT(28) 5683 #define PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_S 29 5684 #define PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_M BIT(29) 5685 #define PRT_MNG_MDEF_PORT_0X298_OR_S 30 5686 #define PRT_MNG_MDEF_PORT_0X298_OR_M BIT(30) 5687 #define PRT_MNG_MDEF_PORT_0X26F_OR_S 31 5688 #define PRT_MNG_MDEF_PORT_0X26F_OR_M BIT(31) 5689 #define PRT_MNG_MDEF_EXT(_i) (0x00214A00 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: POR */ 5690 #define PRT_MNG_MDEF_EXT_MAX_INDEX 7 5691 #define PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_S 0 5692 #define PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_M MAKEMASK(0xF, 0) 5693 #define PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_S 4 5694 #define PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_M MAKEMASK(0xF, 4) 5695 #define PRT_MNG_MDEF_EXT_FLEX_PORT_OR_S 8 5696 #define PRT_MNG_MDEF_EXT_FLEX_PORT_OR_M MAKEMASK(0xFFFF, 8) 5697 #define PRT_MNG_MDEF_EXT_FLEX_TCO_S 24 5698 #define PRT_MNG_MDEF_EXT_FLEX_TCO_M BIT(24) 5699 #define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_S 25 5700 #define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_M BIT(25) 5701 #define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_S 26 5702 #define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_M BIT(26) 5703 #define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_S 27 5704 #define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_M BIT(27) 5705 #define PRT_MNG_MDEF_EXT_ICMP_OR_S 28 5706 #define PRT_MNG_MDEF_EXT_ICMP_OR_M BIT(28) 5707 #define PRT_MNG_MDEF_EXT_MLD_S 29 5708 #define PRT_MNG_MDEF_EXT_MLD_M BIT(29) 5709 #define PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_S 30 5710 #define PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_M BIT(30) 5711 #define PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_S 31 5712 #define PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_M BIT(31) 5713 #define PRT_MNG_MDEFVSI(_i) (0x00214980 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */ 5714 #define PRT_MNG_MDEFVSI_MAX_INDEX 3 5715 #define PRT_MNG_MDEFVSI_MDEFVSI_2N_S 0 5716 #define PRT_MNG_MDEFVSI_MDEFVSI_2N_M MAKEMASK(0xFFFF, 0) 5717 #define PRT_MNG_MDEFVSI_MDEFVSI_2NP1_S 16 5718 #define PRT_MNG_MDEFVSI_MDEFVSI_2NP1_M MAKEMASK(0xFFFF, 16) 5719 #define PRT_MNG_METF(_i) (0x00214120 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */ 5720 #define PRT_MNG_METF_MAX_INDEX 3 5721 #define PRT_MNG_METF_ETYPE_S 0 5722 #define PRT_MNG_METF_ETYPE_M MAKEMASK(0xFFFF, 0) 5723 #define PRT_MNG_METF_POLARITY_S 30 5724 #define PRT_MNG_METF_POLARITY_M BIT(30) 5725 #define PRT_MNG_MFUTP(_i) (0x00214320 + ((_i) * 32)) /* _i=0...15 */ /* Reset Source: POR */ 5726 #define PRT_MNG_MFUTP_MAX_INDEX 15 5727 #define PRT_MNG_MFUTP_MFUTP_N_S 0 5728 #define PRT_MNG_MFUTP_MFUTP_N_M MAKEMASK(0xFFFF, 0) 5729 #define PRT_MNG_MFUTP_UDP_S 16 5730 #define PRT_MNG_MFUTP_UDP_M BIT(16) 5731 #define PRT_MNG_MFUTP_TCP_S 17 5732 #define PRT_MNG_MFUTP_TCP_M BIT(17) 5733 #define PRT_MNG_MFUTP_SOURCE_DESTINATION_S 18 5734 #define PRT_MNG_MFUTP_SOURCE_DESTINATION_M BIT(18) 5735 #define PRT_MNG_MIPAF4(_i) (0x002141A0 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */ 5736 #define PRT_MNG_MIPAF4_MAX_INDEX 3 5737 #define PRT_MNG_MIPAF4_MIPAF_S 0 5738 #define PRT_MNG_MIPAF4_MIPAF_M MAKEMASK(0xFFFFFFFF, 0) 5739 #define PRT_MNG_MIPAF6(_i) (0x00214520 + ((_i) * 32)) /* _i=0...15 */ /* Reset Source: POR */ 5740 #define PRT_MNG_MIPAF6_MAX_INDEX 15 5741 #define PRT_MNG_MIPAF6_MIPAF_S 0 5742 #define PRT_MNG_MIPAF6_MIPAF_M MAKEMASK(0xFFFFFFFF, 0) 5743 #define PRT_MNG_MMAH(_i) (0x00214220 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */ 5744 #define PRT_MNG_MMAH_MAX_INDEX 3 5745 #define PRT_MNG_MMAH_MMAH_S 0 5746 #define PRT_MNG_MMAH_MMAH_M MAKEMASK(0xFFFF, 0) 5747 #define PRT_MNG_MMAL(_i) (0x002142A0 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */ 5748 #define PRT_MNG_MMAL_MAX_INDEX 3 5749 #define PRT_MNG_MMAL_MMAL_S 0 5750 #define PRT_MNG_MMAL_MMAL_M MAKEMASK(0xFFFFFFFF, 0) 5751 #define PRT_MNG_MNGONLY 0x00214740 /* Reset Source: POR */ 5752 #define PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_S 0 5753 #define PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_M MAKEMASK(0xFF, 0) 5754 #define PRT_MNG_MSFM 0x00214760 /* Reset Source: POR */ 5755 #define PRT_MNG_MSFM_PORT_26F_UDP_S 0 5756 #define PRT_MNG_MSFM_PORT_26F_UDP_M BIT(0) 5757 #define PRT_MNG_MSFM_PORT_26F_TCP_S 1 5758 #define PRT_MNG_MSFM_PORT_26F_TCP_M BIT(1) 5759 #define PRT_MNG_MSFM_PORT_298_UDP_S 2 5760 #define PRT_MNG_MSFM_PORT_298_UDP_M BIT(2) 5761 #define PRT_MNG_MSFM_PORT_298_TCP_S 3 5762 #define PRT_MNG_MSFM_PORT_298_TCP_M BIT(3) 5763 #define PRT_MNG_MSFM_IPV6_0_MASK_S 4 5764 #define PRT_MNG_MSFM_IPV6_0_MASK_M BIT(4) 5765 #define PRT_MNG_MSFM_IPV6_1_MASK_S 5 5766 #define PRT_MNG_MSFM_IPV6_1_MASK_M BIT(5) 5767 #define PRT_MNG_MSFM_IPV6_2_MASK_S 6 5768 #define PRT_MNG_MSFM_IPV6_2_MASK_M BIT(6) 5769 #define PRT_MNG_MSFM_IPV6_3_MASK_S 7 5770 #define PRT_MNG_MSFM_IPV6_3_MASK_M BIT(7) 5771 #define MSIX_PBA_PAGE(_i) (0x02E08000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: FLR */ 5772 #define MSIX_PBA_PAGE_MAX_INDEX 63 5773 #define MSIX_PBA_PAGE_PENBIT_S 0 5774 #define MSIX_PBA_PAGE_PENBIT_M MAKEMASK(0xFFFFFFFF, 0) 5775 #define MSIX_PBA1(_i) (0x00008000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: FLR */ 5776 #define MSIX_PBA1_MAX_INDEX 63 5777 #define MSIX_PBA1_PENBIT_S 0 5778 #define MSIX_PBA1_PENBIT_M MAKEMASK(0xFFFFFFFF, 0) 5779 #define MSIX_TADD_PAGE(_i) (0x02E00000 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */ 5780 #define MSIX_TADD_PAGE_MAX_INDEX 2047 5781 #define MSIX_TADD_PAGE_MSIXTADD10_S 0 5782 #define MSIX_TADD_PAGE_MSIXTADD10_M MAKEMASK(0x3, 0) 5783 #define MSIX_TADD_PAGE_MSIXTADD_S 2 5784 #define MSIX_TADD_PAGE_MSIXTADD_M MAKEMASK(0x3FFFFFFF, 2) 5785 #define MSIX_TADD1(_i) (0x00000000 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */ 5786 #define MSIX_TADD1_MAX_INDEX 2047 5787 #define MSIX_TADD1_MSIXTADD10_S 0 5788 #define MSIX_TADD1_MSIXTADD10_M MAKEMASK(0x3, 0) 5789 #define MSIX_TADD1_MSIXTADD_S 2 5790 #define MSIX_TADD1_MSIXTADD_M MAKEMASK(0x3FFFFFFF, 2) 5791 #define MSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */ 5792 #define MSIX_TMSG_MAX_INDEX 2047 5793 #define MSIX_TMSG_MSIXTMSG_S 0 5794 #define MSIX_TMSG_MSIXTMSG_M MAKEMASK(0xFFFFFFFF, 0) 5795 #define MSIX_TMSG_PAGE(_i) (0x02E00008 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */ 5796 #define MSIX_TMSG_PAGE_MAX_INDEX 2047 5797 #define MSIX_TMSG_PAGE_MSIXTMSG_S 0 5798 #define MSIX_TMSG_PAGE_MSIXTMSG_M MAKEMASK(0xFFFFFFFF, 0) 5799 #define MSIX_TUADD_PAGE(_i) (0x02E00004 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */ 5800 #define MSIX_TUADD_PAGE_MAX_INDEX 2047 5801 #define MSIX_TUADD_PAGE_MSIXTUADD_S 0 5802 #define MSIX_TUADD_PAGE_MSIXTUADD_M MAKEMASK(0xFFFFFFFF, 0) 5803 #define MSIX_TUADD1(_i) (0x00000004 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */ 5804 #define MSIX_TUADD1_MAX_INDEX 2047 5805 #define MSIX_TUADD1_MSIXTUADD_S 0 5806 #define MSIX_TUADD1_MSIXTUADD_M MAKEMASK(0xFFFFFFFF, 0) 5807 #define MSIX_TVCTRL_PAGE(_i) (0x02E0000C + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */ 5808 #define MSIX_TVCTRL_PAGE_MAX_INDEX 2047 5809 #define MSIX_TVCTRL_PAGE_MASK_S 0 5810 #define MSIX_TVCTRL_PAGE_MASK_M BIT(0) 5811 #define MSIX_TVCTRL1(_i) (0x0000000C + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */ 5812 #define MSIX_TVCTRL1_MAX_INDEX 2047 5813 #define MSIX_TVCTRL1_MASK_S 0 5814 #define MSIX_TVCTRL1_MASK_M BIT(0) 5815 #define GLNVM_AL_DONE_HLP 0x000824C4 /* Reset Source: POR */ 5816 #define GLNVM_AL_DONE_HLP_HLP_CORER_S 0 5817 #define GLNVM_AL_DONE_HLP_HLP_CORER_M BIT(0) 5818 #define GLNVM_AL_DONE_HLP_HLP_FULLR_S 1 5819 #define GLNVM_AL_DONE_HLP_HLP_FULLR_M BIT(1) 5820 #define GLNVM_ALTIMERS 0x000B6140 /* Reset Source: POR */ 5821 #define GLNVM_ALTIMERS_PCI_ALTIMER_S 0 5822 #define GLNVM_ALTIMERS_PCI_ALTIMER_M MAKEMASK(0xFFF, 0) 5823 #define GLNVM_ALTIMERS_GEN_ALTIMER_S 12 5824 #define GLNVM_ALTIMERS_GEN_ALTIMER_M MAKEMASK(0xFFFFF, 12) 5825 #define GLNVM_FLA 0x000B6108 /* Reset Source: POR */ 5826 #define GLNVM_FLA_LOCKED_S 6 5827 #define GLNVM_FLA_LOCKED_M BIT(6) 5828 #define GLNVM_GENS 0x000B6100 /* Reset Source: POR */ 5829 #define GLNVM_GENS_NVM_PRES_S 0 5830 #define GLNVM_GENS_NVM_PRES_M BIT(0) 5831 #define GLNVM_GENS_SR_SIZE_S 5 5832 #define GLNVM_GENS_SR_SIZE_M MAKEMASK(0x7, 5) 5833 #define GLNVM_GENS_BANK1VAL_S 8 5834 #define GLNVM_GENS_BANK1VAL_M BIT(8) 5835 #define GLNVM_GENS_ALT_PRST_S 23 5836 #define GLNVM_GENS_ALT_PRST_M BIT(23) 5837 #define GLNVM_GENS_FL_AUTO_RD_S 25 5838 #define GLNVM_GENS_FL_AUTO_RD_M BIT(25) 5839 #define GLNVM_PROTCSR(_i) (0x000B6010 + ((_i) * 4)) /* _i=0...59 */ /* Reset Source: POR */ 5840 #define GLNVM_PROTCSR_MAX_INDEX 59 5841 #define GLNVM_PROTCSR_ADDR_BLOCK_S 0 5842 #define GLNVM_PROTCSR_ADDR_BLOCK_M MAKEMASK(0xFFFFFF, 0) 5843 #define GLNVM_ULD 0x000B6008 /* Reset Source: POR */ 5844 #define GLNVM_ULD_PCIER_DONE_S 0 5845 #define GLNVM_ULD_PCIER_DONE_M BIT(0) 5846 #define GLNVM_ULD_PCIER_DONE_1_S 1 5847 #define GLNVM_ULD_PCIER_DONE_1_M BIT(1) 5848 #define GLNVM_ULD_CORER_DONE_S 3 5849 #define GLNVM_ULD_CORER_DONE_M BIT(3) 5850 #define GLNVM_ULD_GLOBR_DONE_S 4 5851 #define GLNVM_ULD_GLOBR_DONE_M BIT(4) 5852 #define GLNVM_ULD_POR_DONE_S 5 5853 #define GLNVM_ULD_POR_DONE_M BIT(5) 5854 #define GLNVM_ULD_POR_DONE_1_S 8 5855 #define GLNVM_ULD_POR_DONE_1_M BIT(8) 5856 #define GLNVM_ULD_PCIER_DONE_2_S 9 5857 #define GLNVM_ULD_PCIER_DONE_2_M BIT(9) 5858 #define GLNVM_ULD_PE_DONE_S 10 5859 #define GLNVM_ULD_PE_DONE_M BIT(10) 5860 #define GLNVM_ULD_HLP_CORE_DONE_S 11 5861 #define GLNVM_ULD_HLP_CORE_DONE_M BIT(11) 5862 #define GLNVM_ULD_HLP_FULL_DONE_S 12 5863 #define GLNVM_ULD_HLP_FULL_DONE_M BIT(12) 5864 #define GLNVM_ULT 0x000B6154 /* Reset Source: POR */ 5865 #define GLNVM_ULT_CONF_PCIR_AE_S 0 5866 #define GLNVM_ULT_CONF_PCIR_AE_M BIT(0) 5867 #define GLNVM_ULT_CONF_PCIRTL_AE_S 1 5868 #define GLNVM_ULT_CONF_PCIRTL_AE_M BIT(1) 5869 #define GLNVM_ULT_RESERVED_1_S 2 5870 #define GLNVM_ULT_RESERVED_1_M BIT(2) 5871 #define GLNVM_ULT_CONF_CORE_AE_S 3 5872 #define GLNVM_ULT_CONF_CORE_AE_M BIT(3) 5873 #define GLNVM_ULT_CONF_GLOBAL_AE_S 4 5874 #define GLNVM_ULT_CONF_GLOBAL_AE_M BIT(4) 5875 #define GLNVM_ULT_CONF_POR_AE_S 5 5876 #define GLNVM_ULT_CONF_POR_AE_M BIT(5) 5877 #define GLNVM_ULT_RESERVED_2_S 6 5878 #define GLNVM_ULT_RESERVED_2_M BIT(6) 5879 #define GLNVM_ULT_RESERVED_3_S 7 5880 #define GLNVM_ULT_RESERVED_3_M BIT(7) 5881 #define GLNVM_ULT_RESERVED_5_S 8 5882 #define GLNVM_ULT_RESERVED_5_M BIT(8) 5883 #define GLNVM_ULT_CONF_PCIALT_AE_S 9 5884 #define GLNVM_ULT_CONF_PCIALT_AE_M BIT(9) 5885 #define GLNVM_ULT_CONF_PE_AE_S 10 5886 #define GLNVM_ULT_CONF_PE_AE_M BIT(10) 5887 #define GLNVM_ULT_RESERVED_4_S 11 5888 #define GLNVM_ULT_RESERVED_4_M MAKEMASK(0x1FFFFF, 11) 5889 #define GL_COTF_MARKER_STATUS 0x00200200 /* Reset Source: CORER */ 5890 #define GL_COTF_MARKER_STATUS_MRKR_BUSY_S 0 5891 #define GL_COTF_MARKER_STATUS_MRKR_BUSY_M MAKEMASK(0xFF, 0) 5892 #define GL_COTF_MARKER_TRIG_RCU_PRS(_i) (0x002001D4 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 5893 #define GL_COTF_MARKER_TRIG_RCU_PRS_MAX_INDEX 7 5894 #define GL_COTF_MARKER_TRIG_RCU_PRS_SET_RST_S 0 5895 #define GL_COTF_MARKER_TRIG_RCU_PRS_SET_RST_M BIT(0) 5896 #define GL_PRS_MARKER_ERROR 0x00200204 /* Reset Source: CORER */ 5897 #define GL_PRS_MARKER_ERROR_XLR_CFG_ERR_S 0 5898 #define GL_PRS_MARKER_ERROR_XLR_CFG_ERR_M BIT(0) 5899 #define GL_PRS_MARKER_ERROR_QH_CFG_ERR_S 1 5900 #define GL_PRS_MARKER_ERROR_QH_CFG_ERR_M BIT(1) 5901 #define GL_PRS_MARKER_ERROR_COTF_CFG_ERR_S 2 5902 #define GL_PRS_MARKER_ERROR_COTF_CFG_ERR_M BIT(2) 5903 #define GL_PRS_RX_PIPE_INIT0(_i) (0x0020000C + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: CORER */ 5904 #define GL_PRS_RX_PIPE_INIT0_MAX_INDEX 6 5905 #define GL_PRS_RX_PIPE_INIT0_GPCSR_INIT_S 0 5906 #define GL_PRS_RX_PIPE_INIT0_GPCSR_INIT_M MAKEMASK(0xFFFF, 0) 5907 #define GL_PRS_RX_PIPE_INIT1 0x00200028 /* Reset Source: CORER */ 5908 #define GL_PRS_RX_PIPE_INIT1_GPCSR_INIT_S 0 5909 #define GL_PRS_RX_PIPE_INIT1_GPCSR_INIT_M MAKEMASK(0xFFFF, 0) 5910 #define GL_PRS_RX_PIPE_INIT2 0x0020002C /* Reset Source: CORER */ 5911 #define GL_PRS_RX_PIPE_INIT2_GPCSR_INIT_S 0 5912 #define GL_PRS_RX_PIPE_INIT2_GPCSR_INIT_M MAKEMASK(0xFFFF, 0) 5913 #define GL_PRS_RX_SIZE_CTRL 0x00200004 /* Reset Source: CORER */ 5914 #define GL_PRS_RX_SIZE_CTRL_MIN_SIZE_S 0 5915 #define GL_PRS_RX_SIZE_CTRL_MIN_SIZE_M MAKEMASK(0x3FF, 0) 5916 #define GL_PRS_RX_SIZE_CTRL_MIN_SIZE_EN_S 15 5917 #define GL_PRS_RX_SIZE_CTRL_MIN_SIZE_EN_M BIT(15) 5918 #define GL_PRS_RX_SIZE_CTRL_MAX_SIZE_S 16 5919 #define GL_PRS_RX_SIZE_CTRL_MAX_SIZE_M MAKEMASK(0x3FF, 16) 5920 #define GL_PRS_RX_SIZE_CTRL_MAX_SIZE_EN_S 31 5921 #define GL_PRS_RX_SIZE_CTRL_MAX_SIZE_EN_M BIT(31) 5922 #define GL_PRS_TX_PIPE_INIT0(_i) (0x00202018 + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: CORER */ 5923 #define GL_PRS_TX_PIPE_INIT0_MAX_INDEX 6 5924 #define GL_PRS_TX_PIPE_INIT0_GPCSR_INIT_S 0 5925 #define GL_PRS_TX_PIPE_INIT0_GPCSR_INIT_M MAKEMASK(0xFFFF, 0) 5926 #define GL_PRS_TX_PIPE_INIT1 0x00202034 /* Reset Source: CORER */ 5927 #define GL_PRS_TX_PIPE_INIT1_GPCSR_INIT_S 0 5928 #define GL_PRS_TX_PIPE_INIT1_GPCSR_INIT_M MAKEMASK(0xFFFF, 0) 5929 #define GL_PRS_TX_PIPE_INIT2 0x00202038 /* Reset Source: CORER */ 5930 #define GL_PRS_TX_PIPE_INIT2_GPCSR_INIT_S 0 5931 #define GL_PRS_TX_PIPE_INIT2_GPCSR_INIT_M MAKEMASK(0xFFFF, 0) 5932 #define GL_PRS_TX_SIZE_CTRL 0x00202014 /* Reset Source: CORER */ 5933 #define GL_PRS_TX_SIZE_CTRL_MIN_SIZE_S 0 5934 #define GL_PRS_TX_SIZE_CTRL_MIN_SIZE_M MAKEMASK(0x3FF, 0) 5935 #define GL_PRS_TX_SIZE_CTRL_MIN_SIZE_EN_S 15 5936 #define GL_PRS_TX_SIZE_CTRL_MIN_SIZE_EN_M BIT(15) 5937 #define GL_PRS_TX_SIZE_CTRL_MAX_SIZE_S 16 5938 #define GL_PRS_TX_SIZE_CTRL_MAX_SIZE_M MAKEMASK(0x3FF, 16) 5939 #define GL_PRS_TX_SIZE_CTRL_MAX_SIZE_EN_S 31 5940 #define GL_PRS_TX_SIZE_CTRL_MAX_SIZE_EN_M BIT(31) 5941 #define GL_QH_MARKER_STATUS 0x002001FC /* Reset Source: CORER */ 5942 #define GL_QH_MARKER_STATUS_MRKR_BUSY_S 0 5943 #define GL_QH_MARKER_STATUS_MRKR_BUSY_M MAKEMASK(0xF, 0) 5944 #define GL_QH_MARKER_TRIG_RCU_PRS(_i) (0x002001C4 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */ 5945 #define GL_QH_MARKER_TRIG_RCU_PRS_MAX_INDEX 3 5946 #define GL_QH_MARKER_TRIG_RCU_PRS_QPID_S 0 5947 #define GL_QH_MARKER_TRIG_RCU_PRS_QPID_M MAKEMASK(0x3FFFF, 0) 5948 #define GL_QH_MARKER_TRIG_RCU_PRS_PE_TAG_S 18 5949 #define GL_QH_MARKER_TRIG_RCU_PRS_PE_TAG_M MAKEMASK(0xFF, 18) 5950 #define GL_QH_MARKER_TRIG_RCU_PRS_PORT_NUM_S 26 5951 #define GL_QH_MARKER_TRIG_RCU_PRS_PORT_NUM_M MAKEMASK(0x7, 26) 5952 #define GL_QH_MARKER_TRIG_RCU_PRS_SET_RST_S 31 5953 #define GL_QH_MARKER_TRIG_RCU_PRS_SET_RST_M BIT(31) 5954 #define GL_RPRS_ANA_CSR_CTRL 0x00200708 /* Reset Source: CORER */ 5955 #define GL_RPRS_ANA_CSR_CTRL_SELECT_EN_S 0 5956 #define GL_RPRS_ANA_CSR_CTRL_SELECT_EN_M BIT(0) 5957 #define GL_RPRS_ANA_CSR_CTRL_SELECTED_ANA_S 1 5958 #define GL_RPRS_ANA_CSR_CTRL_SELECTED_ANA_M BIT(1) 5959 #define GL_TPRS_ANA_CSR_CTRL 0x00202100 /* Reset Source: CORER */ 5960 #define GL_TPRS_ANA_CSR_CTRL_SELECT_EN_S 0 5961 #define GL_TPRS_ANA_CSR_CTRL_SELECT_EN_M BIT(0) 5962 #define GL_TPRS_ANA_CSR_CTRL_SELECTED_ANA_S 1 5963 #define GL_TPRS_ANA_CSR_CTRL_SELECTED_ANA_M BIT(1) 5964 #define GL_TPRS_MNG_PM_THR 0x00202004 /* Reset Source: CORER */ 5965 #define GL_TPRS_MNG_PM_THR_MNG_PM_THR_S 0 5966 #define GL_TPRS_MNG_PM_THR_MNG_PM_THR_M MAKEMASK(0x3FFF, 0) 5967 #define GL_TPRS_PM_CNT(_i) (0x00202008 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 5968 #define GL_TPRS_PM_CNT_MAX_INDEX 1 5969 #define GL_TPRS_PM_CNT_GL_PRS_PM_CNT_S 0 5970 #define GL_TPRS_PM_CNT_GL_PRS_PM_CNT_M MAKEMASK(0x3FFF, 0) 5971 #define GL_TPRS_PM_THR 0x00202000 /* Reset Source: CORER */ 5972 #define GL_TPRS_PM_THR_PM_THR_S 0 5973 #define GL_TPRS_PM_THR_PM_THR_M MAKEMASK(0x3FFF, 0) 5974 #define GL_XLR_MARKER_LOG_RCU_PRS(_i) (0x00200208 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 5975 #define GL_XLR_MARKER_LOG_RCU_PRS_MAX_INDEX 63 5976 #define GL_XLR_MARKER_LOG_RCU_PRS_XLR_TRIG_S 0 5977 #define GL_XLR_MARKER_LOG_RCU_PRS_XLR_TRIG_M MAKEMASK(0xFFFFFFFF, 0) 5978 #define GL_XLR_MARKER_STATUS(_i) (0x002001F4 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 5979 #define GL_XLR_MARKER_STATUS_MAX_INDEX 1 5980 #define GL_XLR_MARKER_STATUS_MRKR_BUSY_S 0 5981 #define GL_XLR_MARKER_STATUS_MRKR_BUSY_M MAKEMASK(0xFFFFFFFF, 0) 5982 #define GL_XLR_MARKER_TRIG_PE 0x005008C0 /* Reset Source: CORER */ 5983 #define GL_XLR_MARKER_TRIG_PE_VM_VF_NUM_S 0 5984 #define GL_XLR_MARKER_TRIG_PE_VM_VF_NUM_M MAKEMASK(0x3FF, 0) 5985 #define GL_XLR_MARKER_TRIG_PE_VM_VF_TYPE_S 10 5986 #define GL_XLR_MARKER_TRIG_PE_VM_VF_TYPE_M MAKEMASK(0x3, 10) 5987 #define GL_XLR_MARKER_TRIG_PE_PF_NUM_S 12 5988 #define GL_XLR_MARKER_TRIG_PE_PF_NUM_M MAKEMASK(0x7, 12) 5989 #define GL_XLR_MARKER_TRIG_PE_PORT_NUM_S 16 5990 #define GL_XLR_MARKER_TRIG_PE_PORT_NUM_M MAKEMASK(0x7, 16) 5991 #define GL_XLR_MARKER_TRIG_RCU_PRS 0x002001C0 /* Reset Source: CORER */ 5992 #define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_NUM_S 0 5993 #define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_NUM_M MAKEMASK(0x3FF, 0) 5994 #define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_S 10 5995 #define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_M MAKEMASK(0x3, 10) 5996 #define GL_XLR_MARKER_TRIG_RCU_PRS_PF_NUM_S 12 5997 #define GL_XLR_MARKER_TRIG_RCU_PRS_PF_NUM_M MAKEMASK(0x7, 12) 5998 #define GL_XLR_MARKER_TRIG_RCU_PRS_PORT_NUM_S 16 5999 #define GL_XLR_MARKER_TRIG_RCU_PRS_PORT_NUM_M MAKEMASK(0x7, 16) 6000 #define GL_CLKGATE_EVENTS 0x0009DE70 /* Reset Source: PERST */ 6001 #define GL_CLKGATE_EVENTS_PRIMARY_CLKGATE_EVENTS_S 0 6002 #define GL_CLKGATE_EVENTS_PRIMARY_CLKGATE_EVENTS_M MAKEMASK(0xFFFF, 0) 6003 #define GL_CLKGATE_EVENTS_SIDEBAND_CLKGATE_EVENTS_S 16 6004 #define GL_CLKGATE_EVENTS_SIDEBAND_CLKGATE_EVENTS_M MAKEMASK(0xFFFF, 16) 6005 #define GLPCI_BYTCTH_NP_C 0x000BFDA8 /* Reset Source: PCIR */ 6006 #define GLPCI_BYTCTH_NP_C_PCI_COUNT_BW_BCT_S 0 6007 #define GLPCI_BYTCTH_NP_C_PCI_COUNT_BW_BCT_M MAKEMASK(0xFFFFFFFF, 0) 6008 #define GLPCI_BYTCTH_P 0x0009E970 /* Reset Source: PCIR */ 6009 #define GLPCI_BYTCTH_P_PCI_COUNT_BW_BCT_S 0 6010 #define GLPCI_BYTCTH_P_PCI_COUNT_BW_BCT_M MAKEMASK(0xFFFFFFFF, 0) 6011 #define GLPCI_BYTCTL_NP_C 0x000BFDAC /* Reset Source: PCIR */ 6012 #define GLPCI_BYTCTL_NP_C_PCI_COUNT_BW_BCT_S 0 6013 #define GLPCI_BYTCTL_NP_C_PCI_COUNT_BW_BCT_M MAKEMASK(0xFFFFFFFF, 0) 6014 #define GLPCI_BYTCTL_P 0x0009E994 /* Reset Source: PCIR */ 6015 #define GLPCI_BYTCTL_P_PCI_COUNT_BW_BCT_S 0 6016 #define GLPCI_BYTCTL_P_PCI_COUNT_BW_BCT_M MAKEMASK(0xFFFFFFFF, 0) 6017 #define GLPCI_CAPCTRL 0x0009DE88 /* Reset Source: PCIR */ 6018 #define GLPCI_CAPCTRL_VPD_EN_S 0 6019 #define GLPCI_CAPCTRL_VPD_EN_M BIT(0) 6020 #define GLPCI_CAPSUP 0x0009DE8C /* Reset Source: PCIR */ 6021 #define GLPCI_CAPSUP_PCIE_VER_S 0 6022 #define GLPCI_CAPSUP_PCIE_VER_M BIT(0) 6023 #define E800_GLPCI_CAPSUP_RESERVED_2_S 1 6024 #define E800_GLPCI_CAPSUP_RESERVED_2_M BIT(1) 6025 #define GLPCI_CAPSUP_LTR_EN_S 2 6026 #define GLPCI_CAPSUP_LTR_EN_M BIT(2) 6027 #define GLPCI_CAPSUP_TPH_EN_S 3 6028 #define GLPCI_CAPSUP_TPH_EN_M BIT(3) 6029 #define GLPCI_CAPSUP_ARI_EN_S 4 6030 #define GLPCI_CAPSUP_ARI_EN_M BIT(4) 6031 #define GLPCI_CAPSUP_IOV_EN_S 5 6032 #define GLPCI_CAPSUP_IOV_EN_M BIT(5) 6033 #define GLPCI_CAPSUP_ACS_EN_S 6 6034 #define GLPCI_CAPSUP_ACS_EN_M BIT(6) 6035 #define GLPCI_CAPSUP_SEC_EN_S 7 6036 #define GLPCI_CAPSUP_SEC_EN_M BIT(7) 6037 #define GLPCI_CAPSUP_PASID_EN_S 8 6038 #define GLPCI_CAPSUP_PASID_EN_M BIT(8) 6039 #define GLPCI_CAPSUP_DLFE_EN_S 9 6040 #define GLPCI_CAPSUP_DLFE_EN_M BIT(9) 6041 #define GLPCI_CAPSUP_GEN4_EXT_EN_S 10 6042 #define GLPCI_CAPSUP_GEN4_EXT_EN_M BIT(10) 6043 #define GLPCI_CAPSUP_GEN4_MARG_EN_S 11 6044 #define GLPCI_CAPSUP_GEN4_MARG_EN_M BIT(11) 6045 #define GLPCI_CAPSUP_ECRC_GEN_EN_S 16 6046 #define GLPCI_CAPSUP_ECRC_GEN_EN_M BIT(16) 6047 #define GLPCI_CAPSUP_ECRC_CHK_EN_S 17 6048 #define GLPCI_CAPSUP_ECRC_CHK_EN_M BIT(17) 6049 #define GLPCI_CAPSUP_IDO_EN_S 18 6050 #define GLPCI_CAPSUP_IDO_EN_M BIT(18) 6051 #define GLPCI_CAPSUP_MSI_MASK_S 19 6052 #define GLPCI_CAPSUP_MSI_MASK_M BIT(19) 6053 #define GLPCI_CAPSUP_CSR_CONF_EN_S 20 6054 #define GLPCI_CAPSUP_CSR_CONF_EN_M BIT(20) 6055 #define GLPCI_CAPSUP_WAKUP_EN_S 21 6056 #define GLPCI_CAPSUP_WAKUP_EN_M BIT(21) 6057 #define GLPCI_CAPSUP_LOAD_SUBSYS_ID_S 30 6058 #define GLPCI_CAPSUP_LOAD_SUBSYS_ID_M BIT(30) 6059 #define GLPCI_CAPSUP_LOAD_DEV_ID_S 31 6060 #define GLPCI_CAPSUP_LOAD_DEV_ID_M BIT(31) 6061 #define GLPCI_CNF 0x0009DEA0 /* Reset Source: POR */ 6062 #define GLPCI_CNF_FLEX10_S 1 6063 #define GLPCI_CNF_FLEX10_M BIT(1) 6064 #define GLPCI_CNF_WAKE_PIN_EN_S 2 6065 #define GLPCI_CNF_WAKE_PIN_EN_M BIT(2) 6066 #define GLPCI_CNF_MSIX_ECC_BLOCK_DISABLE_S 3 6067 #define GLPCI_CNF_MSIX_ECC_BLOCK_DISABLE_M BIT(3) 6068 #define GLPCI_CNF2 0x000BE004 /* Reset Source: PCIR */ 6069 #define GLPCI_CNF2_RO_DIS_S 0 6070 #define GLPCI_CNF2_RO_DIS_M BIT(0) 6071 #define GLPCI_CNF2_CACHELINE_SIZE_S 1 6072 #define GLPCI_CNF2_CACHELINE_SIZE_M BIT(1) 6073 #define GLPCI_DREVID 0x0009E9AC /* Reset Source: PCIR */ 6074 #define GLPCI_DREVID_DEFAULT_REVID_S 0 6075 #define GLPCI_DREVID_DEFAULT_REVID_M MAKEMASK(0xFF, 0) 6076 #define GLPCI_GSCL_1_NP_C 0x000BFDA4 /* Reset Source: PCIR */ 6077 #define GLPCI_GSCL_1_NP_C_RT_MODE_S 8 6078 #define GLPCI_GSCL_1_NP_C_RT_MODE_M BIT(8) 6079 #define GLPCI_GSCL_1_NP_C_RT_EVENT_S 9 6080 #define GLPCI_GSCL_1_NP_C_RT_EVENT_M MAKEMASK(0x1F, 9) 6081 #define GLPCI_GSCL_1_NP_C_PCI_COUNT_BW_EN_S 14 6082 #define GLPCI_GSCL_1_NP_C_PCI_COUNT_BW_EN_M BIT(14) 6083 #define GLPCI_GSCL_1_NP_C_PCI_COUNT_BW_EV_S 15 6084 #define GLPCI_GSCL_1_NP_C_PCI_COUNT_BW_EV_M MAKEMASK(0x1F, 15) 6085 #define GLPCI_GSCL_1_NP_C_GIO_COUNT_RESET_S 29 6086 #define GLPCI_GSCL_1_NP_C_GIO_COUNT_RESET_M BIT(29) 6087 #define GLPCI_GSCL_1_NP_C_GIO_COUNT_STOP_S 30 6088 #define GLPCI_GSCL_1_NP_C_GIO_COUNT_STOP_M BIT(30) 6089 #define GLPCI_GSCL_1_NP_C_GIO_COUNT_START_S 31 6090 #define GLPCI_GSCL_1_NP_C_GIO_COUNT_START_M BIT(31) 6091 #define GLPCI_GSCL_1_P 0x0009E9B4 /* Reset Source: PCIR */ 6092 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_0_S 0 6093 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_0_M BIT(0) 6094 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_1_S 1 6095 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_1_M BIT(1) 6096 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_2_S 2 6097 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_2_M BIT(2) 6098 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_3_S 3 6099 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_3_M BIT(3) 6100 #define GLPCI_GSCL_1_P_LBC_ENABLE_0_S 4 6101 #define GLPCI_GSCL_1_P_LBC_ENABLE_0_M BIT(4) 6102 #define GLPCI_GSCL_1_P_LBC_ENABLE_1_S 5 6103 #define GLPCI_GSCL_1_P_LBC_ENABLE_1_M BIT(5) 6104 #define GLPCI_GSCL_1_P_LBC_ENABLE_2_S 6 6105 #define GLPCI_GSCL_1_P_LBC_ENABLE_2_M BIT(6) 6106 #define GLPCI_GSCL_1_P_LBC_ENABLE_3_S 7 6107 #define GLPCI_GSCL_1_P_LBC_ENABLE_3_M BIT(7) 6108 #define GLPCI_GSCL_1_P_PCI_COUNT_BW_EN_S 14 6109 #define GLPCI_GSCL_1_P_PCI_COUNT_BW_EN_M BIT(14) 6110 #define GLPCI_GSCL_1_P_GIO_64_BIT_EN_S 28 6111 #define GLPCI_GSCL_1_P_GIO_64_BIT_EN_M BIT(28) 6112 #define GLPCI_GSCL_1_P_GIO_COUNT_RESET_S 29 6113 #define GLPCI_GSCL_1_P_GIO_COUNT_RESET_M BIT(29) 6114 #define GLPCI_GSCL_1_P_GIO_COUNT_STOP_S 30 6115 #define GLPCI_GSCL_1_P_GIO_COUNT_STOP_M BIT(30) 6116 #define GLPCI_GSCL_1_P_GIO_COUNT_START_S 31 6117 #define GLPCI_GSCL_1_P_GIO_COUNT_START_M BIT(31) 6118 #define GLPCI_GSCL_2 0x0009E998 /* Reset Source: PCIR */ 6119 #define GLPCI_GSCL_2_GIO_EVENT_NUM_0_S 0 6120 #define GLPCI_GSCL_2_GIO_EVENT_NUM_0_M MAKEMASK(0xFF, 0) 6121 #define GLPCI_GSCL_2_GIO_EVENT_NUM_1_S 8 6122 #define GLPCI_GSCL_2_GIO_EVENT_NUM_1_M MAKEMASK(0xFF, 8) 6123 #define GLPCI_GSCL_2_GIO_EVENT_NUM_2_S 16 6124 #define GLPCI_GSCL_2_GIO_EVENT_NUM_2_M MAKEMASK(0xFF, 16) 6125 #define GLPCI_GSCL_2_GIO_EVENT_NUM_3_S 24 6126 #define GLPCI_GSCL_2_GIO_EVENT_NUM_3_M MAKEMASK(0xFF, 24) 6127 #define GLPCI_GSCL_5_8(_i) (0x0009E954 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: PCIR */ 6128 #define GLPCI_GSCL_5_8_MAX_INDEX 3 6129 #define GLPCI_GSCL_5_8_LBC_THRESHOLD_N_S 0 6130 #define GLPCI_GSCL_5_8_LBC_THRESHOLD_N_M MAKEMASK(0xFFFF, 0) 6131 #define GLPCI_GSCL_5_8_LBC_TIMER_N_S 16 6132 #define GLPCI_GSCL_5_8_LBC_TIMER_N_M MAKEMASK(0xFFFF, 16) 6133 #define GLPCI_GSCN_0_3(_i) (0x0009E99C + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: PCIR */ 6134 #define GLPCI_GSCN_0_3_MAX_INDEX 3 6135 #define GLPCI_GSCN_0_3_EVENT_COUNTER_S 0 6136 #define GLPCI_GSCN_0_3_EVENT_COUNTER_M MAKEMASK(0xFFFFFFFF, 0) 6137 #define GLPCI_LATCT_NP_C 0x000BFDA0 /* Reset Source: PCIR */ 6138 #define GLPCI_LATCT_NP_C_PCI_LATENCY_COUNT_S 0 6139 #define GLPCI_LATCT_NP_C_PCI_LATENCY_COUNT_M MAKEMASK(0xFFFFFFFF, 0) 6140 #define GLPCI_LBARCTRL 0x0009DE74 /* Reset Source: POR */ 6141 #define GLPCI_LBARCTRL_PREFBAR_S 0 6142 #define GLPCI_LBARCTRL_PREFBAR_M BIT(0) 6143 #define GLPCI_LBARCTRL_BAR32_S 1 6144 #define GLPCI_LBARCTRL_BAR32_M BIT(1) 6145 #define GLPCI_LBARCTRL_PAGES_SPACE_EN_PF_S 2 6146 #define GLPCI_LBARCTRL_PAGES_SPACE_EN_PF_M BIT(2) 6147 #define GLPCI_LBARCTRL_FLASH_EXPOSE_S 3 6148 #define GLPCI_LBARCTRL_FLASH_EXPOSE_M BIT(3) 6149 #define GLPCI_LBARCTRL_PE_DB_SIZE_S 4 6150 #define GLPCI_LBARCTRL_PE_DB_SIZE_M MAKEMASK(0x3, 4) 6151 #define GLPCI_LBARCTRL_PAGES_SPACE_EN_VF_S 9 6152 #define GLPCI_LBARCTRL_PAGES_SPACE_EN_VF_M BIT(9) 6153 #define GLPCI_LBARCTRL_EXROM_SIZE_S 11 6154 #define GLPCI_LBARCTRL_EXROM_SIZE_M MAKEMASK(0x7, 11) 6155 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_S 14 6156 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_M MAKEMASK(0x3, 14) 6157 #define GLPCI_LINKCAP 0x0009DE90 /* Reset Source: PCIR */ 6158 #define GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_S 0 6159 #define GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_M MAKEMASK(0x3F, 0) 6160 #define GLPCI_LINKCAP_MAX_LINK_WIDTH_S 9 6161 #define GLPCI_LINKCAP_MAX_LINK_WIDTH_M MAKEMASK(0xF, 9) 6162 #define GLPCI_NPQ_CFG 0x000BFD80 /* Reset Source: PCIR */ 6163 #define GLPCI_NPQ_CFG_EXTEND_TO_S 0 6164 #define GLPCI_NPQ_CFG_EXTEND_TO_M BIT(0) 6165 #define GLPCI_NPQ_CFG_SMALL_TO_S 1 6166 #define GLPCI_NPQ_CFG_SMALL_TO_M BIT(1) 6167 #define GLPCI_NPQ_CFG_WEIGHT_AVG_S 2 6168 #define GLPCI_NPQ_CFG_WEIGHT_AVG_M MAKEMASK(0xF, 2) 6169 #define GLPCI_NPQ_CFG_NPQ_SPARE_S 6 6170 #define GLPCI_NPQ_CFG_NPQ_SPARE_M MAKEMASK(0x3FF, 6) 6171 #define GLPCI_NPQ_CFG_NPQ_ERR_STAT_S 16 6172 #define GLPCI_NPQ_CFG_NPQ_ERR_STAT_M MAKEMASK(0xF, 16) 6173 #define GLPCI_PKTCT_NP_C 0x000BFD9C /* Reset Source: PCIR */ 6174 #define GLPCI_PKTCT_NP_C_PCI_COUNT_BW_PCT_S 0 6175 #define GLPCI_PKTCT_NP_C_PCI_COUNT_BW_PCT_M MAKEMASK(0xFFFFFFFF, 0) 6176 #define GLPCI_PKTCT_P 0x0009E9B0 /* Reset Source: PCIR */ 6177 #define GLPCI_PKTCT_P_PCI_COUNT_BW_PCT_S 0 6178 #define GLPCI_PKTCT_P_PCI_COUNT_BW_PCT_M MAKEMASK(0xFFFFFFFF, 0) 6179 #define GLPCI_PMSUP 0x0009DE94 /* Reset Source: PCIR */ 6180 #define GLPCI_PMSUP_RESERVED_0_S 0 6181 #define GLPCI_PMSUP_RESERVED_0_M MAKEMASK(0x3, 0) 6182 #define GLPCI_PMSUP_RESERVED_1_S 2 6183 #define GLPCI_PMSUP_RESERVED_1_M MAKEMASK(0x7, 2) 6184 #define GLPCI_PMSUP_RESERVED_2_S 5 6185 #define GLPCI_PMSUP_RESERVED_2_M MAKEMASK(0x7, 5) 6186 #define GLPCI_PMSUP_L0S_ACC_LAT_S 8 6187 #define GLPCI_PMSUP_L0S_ACC_LAT_M MAKEMASK(0x7, 8) 6188 #define GLPCI_PMSUP_L1_ACC_LAT_S 11 6189 #define GLPCI_PMSUP_L1_ACC_LAT_M MAKEMASK(0x7, 11) 6190 #define GLPCI_PMSUP_RESERVED_3_S 14 6191 #define GLPCI_PMSUP_RESERVED_3_M BIT(14) 6192 #define GLPCI_PMSUP_OBFF_SUP_S 15 6193 #define GLPCI_PMSUP_OBFF_SUP_M MAKEMASK(0x3, 15) 6194 #define GLPCI_PUSH_PE_IF_TO_STATUS 0x0009DF44 /* Reset Source: PCIR */ 6195 #define GLPCI_PUSH_PE_IF_TO_STATUS_GLPCI_PUSH_PE_IF_TO_STATUS_S 0 6196 #define GLPCI_PUSH_PE_IF_TO_STATUS_GLPCI_PUSH_PE_IF_TO_STATUS_M BIT(0) 6197 #define GLPCI_PWRDATA 0x0009DE7C /* Reset Source: PCIR */ 6198 #define GLPCI_PWRDATA_D0_POWER_S 0 6199 #define GLPCI_PWRDATA_D0_POWER_M MAKEMASK(0xFF, 0) 6200 #define GLPCI_PWRDATA_COMM_POWER_S 8 6201 #define GLPCI_PWRDATA_COMM_POWER_M MAKEMASK(0xFF, 8) 6202 #define GLPCI_PWRDATA_D3_POWER_S 16 6203 #define GLPCI_PWRDATA_D3_POWER_M MAKEMASK(0xFF, 16) 6204 #define GLPCI_PWRDATA_DATA_SCALE_S 24 6205 #define GLPCI_PWRDATA_DATA_SCALE_M MAKEMASK(0x3, 24) 6206 #define GLPCI_REVID 0x0009DE98 /* Reset Source: PCIR */ 6207 #define GLPCI_REVID_NVM_REVID_S 0 6208 #define GLPCI_REVID_NVM_REVID_M MAKEMASK(0xFF, 0) 6209 #define GLPCI_SERH 0x0009DE84 /* Reset Source: PCIR */ 6210 #define GLPCI_SERH_SER_NUM_H_S 0 6211 #define GLPCI_SERH_SER_NUM_H_M MAKEMASK(0xFFFF, 0) 6212 #define GLPCI_SERL 0x0009DE80 /* Reset Source: PCIR */ 6213 #define GLPCI_SERL_SER_NUM_L_S 0 6214 #define GLPCI_SERL_SER_NUM_L_M MAKEMASK(0xFFFFFFFF, 0) 6215 #define GLPCI_SUBVENID 0x0009DEE8 /* Reset Source: PCIR */ 6216 #define GLPCI_SUBVENID_SUB_VEN_ID_S 0 6217 #define GLPCI_SUBVENID_SUB_VEN_ID_M MAKEMASK(0xFFFF, 0) 6218 #define GLPCI_UPADD 0x000BE0D4 /* Reset Source: PCIR */ 6219 #define GLPCI_UPADD_ADDRESS_S 1 6220 #define GLPCI_UPADD_ADDRESS_M MAKEMASK(0x7FFFFFFF, 1) 6221 #define GLPCI_VENDORID 0x0009DEC8 /* Reset Source: PCIR */ 6222 #define GLPCI_VENDORID_VENDORID_S 0 6223 #define GLPCI_VENDORID_VENDORID_M MAKEMASK(0xFFFF, 0) 6224 #define GLPCI_VFSUP 0x0009DE9C /* Reset Source: PCIR */ 6225 #define GLPCI_VFSUP_VF_PREFETCH_S 0 6226 #define GLPCI_VFSUP_VF_PREFETCH_M BIT(0) 6227 #define GLPCI_VFSUP_VR_BAR_TYPE_S 1 6228 #define GLPCI_VFSUP_VR_BAR_TYPE_M BIT(1) 6229 #define GLPCI_WATMK_CLNT_PIPEMON 0x000BFD90 /* Reset Source: PCIR */ 6230 #define GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_S 0 6231 #define GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_M MAKEMASK(0xFFFF, 0) 6232 #define PF_FUNC_RID 0x0009E880 /* Reset Source: PCIR */ 6233 #define PF_FUNC_RID_FUNCTION_NUMBER_S 0 6234 #define PF_FUNC_RID_FUNCTION_NUMBER_M MAKEMASK(0x7, 0) 6235 #define PF_FUNC_RID_DEVICE_NUMBER_S 3 6236 #define PF_FUNC_RID_DEVICE_NUMBER_M MAKEMASK(0x1F, 3) 6237 #define PF_FUNC_RID_BUS_NUMBER_S 8 6238 #define PF_FUNC_RID_BUS_NUMBER_M MAKEMASK(0xFF, 8) 6239 #define PF_PCI_CIAA 0x0009E580 /* Reset Source: FLR */ 6240 #define PF_PCI_CIAA_ADDRESS_S 0 6241 #define PF_PCI_CIAA_ADDRESS_M MAKEMASK(0xFFF, 0) 6242 #define PF_PCI_CIAA_VF_NUM_S 12 6243 #define PF_PCI_CIAA_VF_NUM_M MAKEMASK(0xFF, 12) 6244 #define PF_PCI_CIAD 0x0009E500 /* Reset Source: FLR */ 6245 #define PF_PCI_CIAD_DATA_S 0 6246 #define PF_PCI_CIAD_DATA_M MAKEMASK(0xFFFFFFFF, 0) 6247 #define PFPCI_CLASS 0x0009DB00 /* Reset Source: PCIR */ 6248 #define PFPCI_CLASS_STORAGE_CLASS_S 0 6249 #define PFPCI_CLASS_STORAGE_CLASS_M BIT(0) 6250 #define PFPCI_CLASS_PF_IS_LAN_S 2 6251 #define PFPCI_CLASS_PF_IS_LAN_M BIT(2) 6252 #define PFPCI_CNF 0x0009DF00 /* Reset Source: PCIR */ 6253 #define PFPCI_CNF_MSI_EN_S 2 6254 #define PFPCI_CNF_MSI_EN_M BIT(2) 6255 #define PFPCI_CNF_EXROM_DIS_S 3 6256 #define PFPCI_CNF_EXROM_DIS_M BIT(3) 6257 #define PFPCI_CNF_IO_BAR_S 4 6258 #define PFPCI_CNF_IO_BAR_M BIT(4) 6259 #define PFPCI_CNF_INT_PIN_S 5 6260 #define PFPCI_CNF_INT_PIN_M MAKEMASK(0x3, 5) 6261 #define PFPCI_DEVID 0x0009DE00 /* Reset Source: PCIR */ 6262 #define PFPCI_DEVID_PF_DEV_ID_S 0 6263 #define PFPCI_DEVID_PF_DEV_ID_M MAKEMASK(0xFFFF, 0) 6264 #define PFPCI_DEVID_VF_DEV_ID_S 16 6265 #define PFPCI_DEVID_VF_DEV_ID_M MAKEMASK(0xFFFF, 16) 6266 #define PFPCI_FACTPS 0x0009E900 /* Reset Source: FLR */ 6267 #define PFPCI_FACTPS_FUNC_POWER_STATE_S 0 6268 #define PFPCI_FACTPS_FUNC_POWER_STATE_M MAKEMASK(0x3, 0) 6269 #define PFPCI_FACTPS_FUNC_AUX_EN_S 3 6270 #define PFPCI_FACTPS_FUNC_AUX_EN_M BIT(3) 6271 #define PFPCI_FUNC 0x0009D980 /* Reset Source: POR */ 6272 #define PFPCI_FUNC_FUNC_DIS_S 0 6273 #define PFPCI_FUNC_FUNC_DIS_M BIT(0) 6274 #define PFPCI_FUNC_ALLOW_FUNC_DIS_S 1 6275 #define PFPCI_FUNC_ALLOW_FUNC_DIS_M BIT(1) 6276 #define PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_S 2 6277 #define PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_M BIT(2) 6278 #define PFPCI_PF_FLUSH_DONE 0x0009E400 /* Reset Source: PCIR */ 6279 #define PFPCI_PF_FLUSH_DONE_FLUSH_DONE_S 0 6280 #define PFPCI_PF_FLUSH_DONE_FLUSH_DONE_M BIT(0) 6281 #define PFPCI_PM 0x0009DA80 /* Reset Source: POR */ 6282 #define PFPCI_PM_PME_EN_S 0 6283 #define PFPCI_PM_PME_EN_M BIT(0) 6284 #define PFPCI_STATUS1 0x0009DA00 /* Reset Source: POR */ 6285 #define PFPCI_STATUS1_FUNC_VALID_S 0 6286 #define PFPCI_STATUS1_FUNC_VALID_M BIT(0) 6287 #define PFPCI_SUBSYSID 0x0009D880 /* Reset Source: PCIR */ 6288 #define PFPCI_SUBSYSID_PF_SUBSYS_ID_S 0 6289 #define PFPCI_SUBSYSID_PF_SUBSYS_ID_M MAKEMASK(0xFFFF, 0) 6290 #define PFPCI_SUBSYSID_VF_SUBSYS_ID_S 16 6291 #define PFPCI_SUBSYSID_VF_SUBSYS_ID_M MAKEMASK(0xFFFF, 16) 6292 #define PFPCI_VF_FLUSH_DONE(_VF) (0x0009E000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PCIR */ 6293 #define PFPCI_VF_FLUSH_DONE_MAX_INDEX 255 6294 #define PFPCI_VF_FLUSH_DONE_FLUSH_DONE_S 0 6295 #define PFPCI_VF_FLUSH_DONE_FLUSH_DONE_M BIT(0) 6296 #define PFPCI_VM_FLUSH_DONE 0x0009E480 /* Reset Source: PCIR */ 6297 #define PFPCI_VM_FLUSH_DONE_FLUSH_DONE_S 0 6298 #define PFPCI_VM_FLUSH_DONE_FLUSH_DONE_M BIT(0) 6299 #define PFPCI_VMINDEX 0x0009E600 /* Reset Source: PCIR */ 6300 #define PFPCI_VMINDEX_VMINDEX_S 0 6301 #define PFPCI_VMINDEX_VMINDEX_M MAKEMASK(0x3FF, 0) 6302 #define PFPCI_VMPEND 0x0009E800 /* Reset Source: PCIR */ 6303 #define PFPCI_VMPEND_PENDING_S 0 6304 #define PFPCI_VMPEND_PENDING_M BIT(0) 6305 #define PQ_FIFO_STATUS 0x0009DF40 /* Reset Source: PCIR */ 6306 #define PQ_FIFO_STATUS_PQ_FIFO_COUNT_S 0 6307 #define PQ_FIFO_STATUS_PQ_FIFO_COUNT_M MAKEMASK(0x7FFFFFFF, 0) 6308 #define PQ_FIFO_STATUS_PQ_FIFO_EMPTY_S 31 6309 #define PQ_FIFO_STATUS_PQ_FIFO_EMPTY_M BIT(31) 6310 #define GLPE_CPUSTATUS0 0x0050BA5C /* Reset Source: CORER */ 6311 #define GLPE_CPUSTATUS0_PECPUSTATUS0_S 0 6312 #define GLPE_CPUSTATUS0_PECPUSTATUS0_M MAKEMASK(0xFFFFFFFF, 0) 6313 #define GLPE_CPUSTATUS1 0x0050BA60 /* Reset Source: CORER */ 6314 #define GLPE_CPUSTATUS1_PECPUSTATUS1_S 0 6315 #define GLPE_CPUSTATUS1_PECPUSTATUS1_M MAKEMASK(0xFFFFFFFF, 0) 6316 #define GLPE_CPUSTATUS2 0x0050BA64 /* Reset Source: CORER */ 6317 #define GLPE_CPUSTATUS2_PECPUSTATUS2_S 0 6318 #define GLPE_CPUSTATUS2_PECPUSTATUS2_M MAKEMASK(0xFFFFFFFF, 0) 6319 #define GLPE_MDQ_BASE(_i) (0x00536000 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 6320 #define GLPE_MDQ_BASE_MAX_INDEX 511 6321 #define GLPE_MDQ_BASE_MDOC_INDEX_S 0 6322 #define GLPE_MDQ_BASE_MDOC_INDEX_M MAKEMASK(0xFFFFFFF, 0) 6323 #define GLPE_MDQ_PTR(_i) (0x00537000 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 6324 #define GLPE_MDQ_PTR_MAX_INDEX 511 6325 #define GLPE_MDQ_PTR_MDQ_HEAD_S 0 6326 #define GLPE_MDQ_PTR_MDQ_HEAD_M MAKEMASK(0x3FFF, 0) 6327 #define GLPE_MDQ_PTR_MDQ_TAIL_S 16 6328 #define GLPE_MDQ_PTR_MDQ_TAIL_M MAKEMASK(0x3FFF, 16) 6329 #define GLPE_MDQ_SIZE(_i) (0x00536800 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: CORER */ 6330 #define GLPE_MDQ_SIZE_MAX_INDEX 511 6331 #define GLPE_MDQ_SIZE_MDQ_SIZE_S 0 6332 #define GLPE_MDQ_SIZE_MDQ_SIZE_M MAKEMASK(0x3FFF, 0) 6333 #define GLPE_PEPM_CTRL 0x0050C000 /* Reset Source: PERST */ 6334 #define GLPE_PEPM_CTRL_PEPM_ENABLE_S 0 6335 #define GLPE_PEPM_CTRL_PEPM_ENABLE_M BIT(0) 6336 #define GLPE_PEPM_CTRL_PEPM_HALT_S 8 6337 #define GLPE_PEPM_CTRL_PEPM_HALT_M BIT(8) 6338 #define GLPE_PEPM_CTRL_PEPM_PUSH_MARGIN_S 16 6339 #define GLPE_PEPM_CTRL_PEPM_PUSH_MARGIN_M MAKEMASK(0xFF, 16) 6340 #define GLPE_PEPM_DEALLOC 0x0050C004 /* Reset Source: PERST */ 6341 #define GLPE_PEPM_DEALLOC_MDQ_CREDITS_S 0 6342 #define GLPE_PEPM_DEALLOC_MDQ_CREDITS_M MAKEMASK(0x3FFF, 0) 6343 #define GLPE_PEPM_DEALLOC_PSQ_CREDITS_S 14 6344 #define GLPE_PEPM_DEALLOC_PSQ_CREDITS_M MAKEMASK(0x1F, 14) 6345 #define GLPE_PEPM_DEALLOC_PQID_S 19 6346 #define GLPE_PEPM_DEALLOC_PQID_M MAKEMASK(0x1FF, 19) 6347 #define GLPE_PEPM_DEALLOC_PORT_S 28 6348 #define GLPE_PEPM_DEALLOC_PORT_M MAKEMASK(0x7, 28) 6349 #define GLPE_PEPM_DEALLOC_DEALLOC_RDY_S 31 6350 #define GLPE_PEPM_DEALLOC_DEALLOC_RDY_M BIT(31) 6351 #define GLPE_PEPM_PSQ_COUNT 0x0050C020 /* Reset Source: PERST */ 6352 #define GLPE_PEPM_PSQ_COUNT_PEPM_PSQ_COUNT_S 0 6353 #define GLPE_PEPM_PSQ_COUNT_PEPM_PSQ_COUNT_M MAKEMASK(0xFFFF, 0) 6354 #define GLPE_PEPM_THRESH(_i) (0x0050C840 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: PERST */ 6355 #define GLPE_PEPM_THRESH_MAX_INDEX 511 6356 #define GLPE_PEPM_THRESH_PEPM_PSQ_THRESH_S 0 6357 #define GLPE_PEPM_THRESH_PEPM_PSQ_THRESH_M MAKEMASK(0x1F, 0) 6358 #define GLPE_PEPM_THRESH_PEPM_MDQ_THRESH_S 16 6359 #define GLPE_PEPM_THRESH_PEPM_MDQ_THRESH_M MAKEMASK(0x3FFF, 16) 6360 #define GLPE_PFAEQEDROPCNT(_i) (0x00503240 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 6361 #define GLPE_PFAEQEDROPCNT_MAX_INDEX 7 6362 #define GLPE_PFAEQEDROPCNT_AEQEDROPCNT_S 0 6363 #define GLPE_PFAEQEDROPCNT_AEQEDROPCNT_M MAKEMASK(0xFFFF, 0) 6364 #define GLPE_PFCEQEDROPCNT(_i) (0x00503220 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 6365 #define GLPE_PFCEQEDROPCNT_MAX_INDEX 7 6366 #define GLPE_PFCEQEDROPCNT_CEQEDROPCNT_S 0 6367 #define GLPE_PFCEQEDROPCNT_CEQEDROPCNT_M MAKEMASK(0xFFFF, 0) 6368 #define GLPE_PFCQEDROPCNT(_i) (0x00503200 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 6369 #define GLPE_PFCQEDROPCNT_MAX_INDEX 7 6370 #define GLPE_PFCQEDROPCNT_CQEDROPCNT_S 0 6371 #define GLPE_PFCQEDROPCNT_CQEDROPCNT_M MAKEMASK(0xFFFF, 0) 6372 #define GLPE_PFFLMOOISCALLOCERR(_i) (0x0050B960 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 6373 #define GLPE_PFFLMOOISCALLOCERR_MAX_INDEX 7 6374 #define GLPE_PFFLMOOISCALLOCERR_ERROR_COUNT_S 0 6375 #define GLPE_PFFLMOOISCALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0) 6376 #define GLPE_PFFLMQ1ALLOCERR(_i) (0x0050B920 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 6377 #define GLPE_PFFLMQ1ALLOCERR_MAX_INDEX 7 6378 #define GLPE_PFFLMQ1ALLOCERR_ERROR_COUNT_S 0 6379 #define GLPE_PFFLMQ1ALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0) 6380 #define GLPE_PFFLMRRFALLOCERR(_i) (0x0050B940 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 6381 #define GLPE_PFFLMRRFALLOCERR_MAX_INDEX 7 6382 #define GLPE_PFFLMRRFALLOCERR_ERROR_COUNT_S 0 6383 #define GLPE_PFFLMRRFALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0) 6384 #define GLPE_PFFLMXMITALLOCERR(_i) (0x0050B900 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 6385 #define GLPE_PFFLMXMITALLOCERR_MAX_INDEX 7 6386 #define GLPE_PFFLMXMITALLOCERR_ERROR_COUNT_S 0 6387 #define GLPE_PFFLMXMITALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0) 6388 #define GLPE_PFTCPNOW50USCNT(_i) (0x0050B8C0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 6389 #define GLPE_PFTCPNOW50USCNT_MAX_INDEX 7 6390 #define GLPE_PFTCPNOW50USCNT_CNT_S 0 6391 #define GLPE_PFTCPNOW50USCNT_CNT_M MAKEMASK(0xFFFFFFFF, 0) 6392 #define GLPE_PUSH_PEPM 0x0053241C /* Reset Source: CORER */ 6393 #define GLPE_PUSH_PEPM_MDQ_CREDITS_S 0 6394 #define GLPE_PUSH_PEPM_MDQ_CREDITS_M MAKEMASK(0xFF, 0) 6395 #define GLPE_VFAEQEDROPCNT(_i) (0x00503100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 6396 #define GLPE_VFAEQEDROPCNT_MAX_INDEX 31 6397 #define GLPE_VFAEQEDROPCNT_AEQEDROPCNT_S 0 6398 #define GLPE_VFAEQEDROPCNT_AEQEDROPCNT_M MAKEMASK(0xFFFF, 0) 6399 #define GLPE_VFCEQEDROPCNT(_i) (0x00503080 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 6400 #define GLPE_VFCEQEDROPCNT_MAX_INDEX 31 6401 #define GLPE_VFCEQEDROPCNT_CEQEDROPCNT_S 0 6402 #define GLPE_VFCEQEDROPCNT_CEQEDROPCNT_M MAKEMASK(0xFFFF, 0) 6403 #define GLPE_VFCQEDROPCNT(_i) (0x00503000 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 6404 #define GLPE_VFCQEDROPCNT_MAX_INDEX 31 6405 #define GLPE_VFCQEDROPCNT_CQEDROPCNT_S 0 6406 #define GLPE_VFCQEDROPCNT_CQEDROPCNT_M MAKEMASK(0xFFFF, 0) 6407 #define GLPE_VFFLMOOISCALLOCERR(_i) (0x0050B580 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 6408 #define GLPE_VFFLMOOISCALLOCERR_MAX_INDEX 31 6409 #define GLPE_VFFLMOOISCALLOCERR_ERROR_COUNT_S 0 6410 #define GLPE_VFFLMOOISCALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0) 6411 #define GLPE_VFFLMQ1ALLOCERR(_i) (0x0050B480 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 6412 #define GLPE_VFFLMQ1ALLOCERR_MAX_INDEX 31 6413 #define GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_S 0 6414 #define GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0) 6415 #define GLPE_VFFLMRRFALLOCERR(_i) (0x0050B500 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 6416 #define GLPE_VFFLMRRFALLOCERR_MAX_INDEX 31 6417 #define GLPE_VFFLMRRFALLOCERR_ERROR_COUNT_S 0 6418 #define GLPE_VFFLMRRFALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0) 6419 #define GLPE_VFFLMXMITALLOCERR(_i) (0x0050B400 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 6420 #define GLPE_VFFLMXMITALLOCERR_MAX_INDEX 31 6421 #define GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_S 0 6422 #define GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0) 6423 #define GLPE_VFTCPNOW50USCNT(_i) (0x0050B300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: PE_CORER */ 6424 #define GLPE_VFTCPNOW50USCNT_MAX_INDEX 31 6425 #define GLPE_VFTCPNOW50USCNT_CNT_S 0 6426 #define GLPE_VFTCPNOW50USCNT_CNT_M MAKEMASK(0xFFFFFFFF, 0) 6427 #define PFPE_AEQALLOC 0x00502D00 /* Reset Source: PFR */ 6428 #define PFPE_AEQALLOC_AECOUNT_S 0 6429 #define PFPE_AEQALLOC_AECOUNT_M MAKEMASK(0xFFFFFFFF, 0) 6430 #define PFPE_CCQPHIGH 0x0050A100 /* Reset Source: PFR */ 6431 #define PFPE_CCQPHIGH_PECCQPHIGH_S 0 6432 #define PFPE_CCQPHIGH_PECCQPHIGH_M MAKEMASK(0xFFFFFFFF, 0) 6433 #define PFPE_CCQPLOW 0x0050A080 /* Reset Source: PFR */ 6434 #define PFPE_CCQPLOW_PECCQPLOW_S 0 6435 #define PFPE_CCQPLOW_PECCQPLOW_M MAKEMASK(0xFFFFFFFF, 0) 6436 #define PFPE_CCQPSTATUS 0x0050A000 /* Reset Source: PFR */ 6437 #define PFPE_CCQPSTATUS_CCQP_DONE_S 0 6438 #define PFPE_CCQPSTATUS_CCQP_DONE_M BIT(0) 6439 #define PFPE_CCQPSTATUS_HMC_PROFILE_S 4 6440 #define PFPE_CCQPSTATUS_HMC_PROFILE_M MAKEMASK(0x7, 4) 6441 #define PFPE_CCQPSTATUS_RDMA_EN_VFS_S 16 6442 #define PFPE_CCQPSTATUS_RDMA_EN_VFS_M MAKEMASK(0x3F, 16) 6443 #define PFPE_CCQPSTATUS_CCQP_ERR_S 31 6444 #define PFPE_CCQPSTATUS_CCQP_ERR_M BIT(31) 6445 #define PFPE_CQACK 0x00502C80 /* Reset Source: PFR */ 6446 #define PFPE_CQACK_PECQID_S 0 6447 #define PFPE_CQACK_PECQID_M MAKEMASK(0x7FFFF, 0) 6448 #define PFPE_CQARM 0x00502C00 /* Reset Source: PFR */ 6449 #define PFPE_CQARM_PECQID_S 0 6450 #define PFPE_CQARM_PECQID_M MAKEMASK(0x7FFFF, 0) 6451 #define PFPE_CQPDB 0x00500800 /* Reset Source: PFR */ 6452 #define PFPE_CQPDB_WQHEAD_S 0 6453 #define PFPE_CQPDB_WQHEAD_M MAKEMASK(0x7FF, 0) 6454 #define PFPE_CQPERRCODES 0x0050A200 /* Reset Source: PFR */ 6455 #define PFPE_CQPERRCODES_CQP_MINOR_CODE_S 0 6456 #define PFPE_CQPERRCODES_CQP_MINOR_CODE_M MAKEMASK(0xFFFF, 0) 6457 #define PFPE_CQPERRCODES_CQP_MAJOR_CODE_S 16 6458 #define PFPE_CQPERRCODES_CQP_MAJOR_CODE_M MAKEMASK(0xFFFF, 16) 6459 #define PFPE_CQPTAIL 0x00500880 /* Reset Source: PFR */ 6460 #define PFPE_CQPTAIL_WQTAIL_S 0 6461 #define PFPE_CQPTAIL_WQTAIL_M MAKEMASK(0x7FF, 0) 6462 #define PFPE_CQPTAIL_CQP_OP_ERR_S 31 6463 #define PFPE_CQPTAIL_CQP_OP_ERR_M BIT(31) 6464 #define PFPE_IPCONFIG0 0x0050A180 /* Reset Source: PFR */ 6465 #define PFPE_IPCONFIG0_PEIPID_S 0 6466 #define PFPE_IPCONFIG0_PEIPID_M MAKEMASK(0xFFFF, 0) 6467 #define PFPE_IPCONFIG0_USEENTIREIDRANGE_S 16 6468 #define PFPE_IPCONFIG0_USEENTIREIDRANGE_M BIT(16) 6469 #define PFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_S 17 6470 #define PFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_M BIT(17) 6471 #define PFPE_MRTEIDXMASK 0x0050A300 /* Reset Source: PFR */ 6472 #define PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_S 0 6473 #define PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_M MAKEMASK(0x1F, 0) 6474 #define E800_PFPE_RCVUNEXPECTEDERROR 0x0050A380 /* Reset Source: PFR */ 6475 #define E800_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_S 0 6476 #define E800_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0) 6477 #define PFPE_TCPNOWTIMER 0x0050A280 /* Reset Source: PFR */ 6478 #define PFPE_TCPNOWTIMER_TCP_NOW_S 0 6479 #define PFPE_TCPNOWTIMER_TCP_NOW_M MAKEMASK(0xFFFFFFFF, 0) 6480 #define PFPE_WQEALLOC 0x00504400 /* Reset Source: PFR */ 6481 #define PFPE_WQEALLOC_PEQPID_S 0 6482 #define PFPE_WQEALLOC_PEQPID_M MAKEMASK(0x3FFFF, 0) 6483 #define PFPE_WQEALLOC_WQE_DESC_INDEX_S 20 6484 #define PFPE_WQEALLOC_WQE_DESC_INDEX_M MAKEMASK(0xFFF, 20) 6485 #define PRT_PEPM_COUNT(_i) (0x0050C040 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: PERST */ 6486 #define PRT_PEPM_COUNT_MAX_INDEX 511 6487 #define PRT_PEPM_COUNT_PEPM_PSQ_COUNT_S 0 6488 #define PRT_PEPM_COUNT_PEPM_PSQ_COUNT_M MAKEMASK(0x1F, 0) 6489 #define PRT_PEPM_COUNT_PEPM_MDQ_COUNT_S 16 6490 #define PRT_PEPM_COUNT_PEPM_MDQ_COUNT_M MAKEMASK(0x3FFF, 16) 6491 #define VFPE_AEQALLOC(_VF) (0x00502800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */ 6492 #define VFPE_AEQALLOC_MAX_INDEX 255 6493 #define VFPE_AEQALLOC_AECOUNT_S 0 6494 #define VFPE_AEQALLOC_AECOUNT_M MAKEMASK(0xFFFFFFFF, 0) 6495 #define VFPE_CCQPHIGH(_VF) (0x00508800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */ 6496 #define VFPE_CCQPHIGH_MAX_INDEX 255 6497 #define VFPE_CCQPHIGH_PECCQPHIGH_S 0 6498 #define VFPE_CCQPHIGH_PECCQPHIGH_M MAKEMASK(0xFFFFFFFF, 0) 6499 #define VFPE_CCQPLOW(_VF) (0x00508400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */ 6500 #define VFPE_CCQPLOW_MAX_INDEX 255 6501 #define VFPE_CCQPLOW_PECCQPLOW_S 0 6502 #define VFPE_CCQPLOW_PECCQPLOW_M MAKEMASK(0xFFFFFFFF, 0) 6503 #define VFPE_CCQPSTATUS(_VF) (0x00508000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */ 6504 #define VFPE_CCQPSTATUS_MAX_INDEX 255 6505 #define VFPE_CCQPSTATUS_CCQP_DONE_S 0 6506 #define VFPE_CCQPSTATUS_CCQP_DONE_M BIT(0) 6507 #define VFPE_CCQPSTATUS_HMC_PROFILE_S 4 6508 #define VFPE_CCQPSTATUS_HMC_PROFILE_M MAKEMASK(0x7, 4) 6509 #define VFPE_CCQPSTATUS_RDMA_EN_VFS_S 16 6510 #define VFPE_CCQPSTATUS_RDMA_EN_VFS_M MAKEMASK(0x3F, 16) 6511 #define VFPE_CCQPSTATUS_CCQP_ERR_S 31 6512 #define VFPE_CCQPSTATUS_CCQP_ERR_M BIT(31) 6513 #define VFPE_CQACK(_VF) (0x00502400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */ 6514 #define VFPE_CQACK_MAX_INDEX 255 6515 #define VFPE_CQACK_PECQID_S 0 6516 #define VFPE_CQACK_PECQID_M MAKEMASK(0x7FFFF, 0) 6517 #define VFPE_CQARM(_VF) (0x00502000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */ 6518 #define VFPE_CQARM_MAX_INDEX 255 6519 #define VFPE_CQARM_PECQID_S 0 6520 #define VFPE_CQARM_PECQID_M MAKEMASK(0x7FFFF, 0) 6521 #define VFPE_CQPDB(_VF) (0x00500000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */ 6522 #define VFPE_CQPDB_MAX_INDEX 255 6523 #define VFPE_CQPDB_WQHEAD_S 0 6524 #define VFPE_CQPDB_WQHEAD_M MAKEMASK(0x7FF, 0) 6525 #define VFPE_CQPERRCODES(_VF) (0x00509000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */ 6526 #define VFPE_CQPERRCODES_MAX_INDEX 255 6527 #define VFPE_CQPERRCODES_CQP_MINOR_CODE_S 0 6528 #define VFPE_CQPERRCODES_CQP_MINOR_CODE_M MAKEMASK(0xFFFF, 0) 6529 #define VFPE_CQPERRCODES_CQP_MAJOR_CODE_S 16 6530 #define VFPE_CQPERRCODES_CQP_MAJOR_CODE_M MAKEMASK(0xFFFF, 16) 6531 #define VFPE_CQPTAIL(_VF) (0x00500400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */ 6532 #define VFPE_CQPTAIL_MAX_INDEX 255 6533 #define VFPE_CQPTAIL_WQTAIL_S 0 6534 #define VFPE_CQPTAIL_WQTAIL_M MAKEMASK(0x7FF, 0) 6535 #define VFPE_CQPTAIL_CQP_OP_ERR_S 31 6536 #define VFPE_CQPTAIL_CQP_OP_ERR_M BIT(31) 6537 #define VFPE_IPCONFIG0(_VF) (0x00508C00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */ 6538 #define VFPE_IPCONFIG0_MAX_INDEX 255 6539 #define VFPE_IPCONFIG0_PEIPID_S 0 6540 #define VFPE_IPCONFIG0_PEIPID_M MAKEMASK(0xFFFF, 0) 6541 #define VFPE_IPCONFIG0_USEENTIREIDRANGE_S 16 6542 #define VFPE_IPCONFIG0_USEENTIREIDRANGE_M BIT(16) 6543 #define VFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_S 17 6544 #define VFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_M BIT(17) 6545 #define E800_VFPE_RCVUNEXPECTEDERROR(_VF) (0x00509C00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */ 6546 #define E800_VFPE_RCVUNEXPECTEDERROR_MAX_INDEX 255 6547 #define E800_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_S 0 6548 #define E800_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0) 6549 #define VFPE_TCPNOWTIMER(_VF) (0x00509400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */ 6550 #define VFPE_TCPNOWTIMER_MAX_INDEX 255 6551 #define VFPE_TCPNOWTIMER_TCP_NOW_S 0 6552 #define VFPE_TCPNOWTIMER_TCP_NOW_M MAKEMASK(0xFFFFFFFF, 0) 6553 #define VFPE_WQEALLOC(_VF) (0x00504000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */ 6554 #define VFPE_WQEALLOC_MAX_INDEX 255 6555 #define VFPE_WQEALLOC_PEQPID_S 0 6556 #define VFPE_WQEALLOC_PEQPID_M MAKEMASK(0x3FFFF, 0) 6557 #define VFPE_WQEALLOC_WQE_DESC_INDEX_S 20 6558 #define VFPE_WQEALLOC_WQE_DESC_INDEX_M MAKEMASK(0xFFF, 20) 6559 #define GLPES_PFIP4RXDISCARD(_i) (0x00541400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 6560 #define GLPES_PFIP4RXDISCARD_MAX_INDEX 127 6561 #define GLPES_PFIP4RXDISCARD_IP4RXDISCARD_S 0 6562 #define GLPES_PFIP4RXDISCARD_IP4RXDISCARD_M MAKEMASK(0xFFFFFFFF, 0) 6563 #define GLPES_PFIP4RXFRAGSHI(_i) (0x00541C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6564 #define GLPES_PFIP4RXFRAGSHI_MAX_INDEX 127 6565 #define GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_S 0 6566 #define GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_M MAKEMASK(0xFFFF, 0) 6567 #define GLPES_PFIP4RXFRAGSLO(_i) (0x00541C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6568 #define GLPES_PFIP4RXFRAGSLO_MAX_INDEX 127 6569 #define GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_S 0 6570 #define GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_M MAKEMASK(0xFFFFFFFF, 0) 6571 #define GLPES_PFIP4RXMCOCTSHI(_i) (0x00542404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6572 #define GLPES_PFIP4RXMCOCTSHI_MAX_INDEX 127 6573 #define GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_S 0 6574 #define GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_M MAKEMASK(0xFFFF, 0) 6575 #define GLPES_PFIP4RXMCOCTSLO(_i) (0x00542400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6576 #define GLPES_PFIP4RXMCOCTSLO_MAX_INDEX 127 6577 #define GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_S 0 6578 #define GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_M MAKEMASK(0xFFFFFFFF, 0) 6579 #define GLPES_PFIP4RXMCPKTSHI(_i) (0x00542C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6580 #define GLPES_PFIP4RXMCPKTSHI_MAX_INDEX 127 6581 #define GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_S 0 6582 #define GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_M MAKEMASK(0xFFFF, 0) 6583 #define GLPES_PFIP4RXMCPKTSLO(_i) (0x00542C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6584 #define GLPES_PFIP4RXMCPKTSLO_MAX_INDEX 127 6585 #define GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_S 0 6586 #define GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_M MAKEMASK(0xFFFFFFFF, 0) 6587 #define GLPES_PFIP4RXOCTSHI(_i) (0x00540404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6588 #define GLPES_PFIP4RXOCTSHI_MAX_INDEX 127 6589 #define GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_S 0 6590 #define GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_M MAKEMASK(0xFFFF, 0) 6591 #define GLPES_PFIP4RXOCTSLO(_i) (0x00540400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6592 #define GLPES_PFIP4RXOCTSLO_MAX_INDEX 127 6593 #define GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_S 0 6594 #define GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_M MAKEMASK(0xFFFFFFFF, 0) 6595 #define GLPES_PFIP4RXPKTSHI(_i) (0x00540C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6596 #define GLPES_PFIP4RXPKTSHI_MAX_INDEX 127 6597 #define GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_S 0 6598 #define GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_M MAKEMASK(0xFFFF, 0) 6599 #define GLPES_PFIP4RXPKTSLO(_i) (0x00540C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6600 #define GLPES_PFIP4RXPKTSLO_MAX_INDEX 127 6601 #define GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_S 0 6602 #define GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0) 6603 #define GLPES_PFIP4RXTRUNC(_i) (0x00541800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 6604 #define GLPES_PFIP4RXTRUNC_MAX_INDEX 127 6605 #define GLPES_PFIP4RXTRUNC_IP4RXTRUNC_S 0 6606 #define GLPES_PFIP4RXTRUNC_IP4RXTRUNC_M MAKEMASK(0xFFFFFFFF, 0) 6607 #define GLPES_PFIP4TXFRAGSHI(_i) (0x00547404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6608 #define GLPES_PFIP4TXFRAGSHI_MAX_INDEX 127 6609 #define GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_S 0 6610 #define GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_M MAKEMASK(0xFFFF, 0) 6611 #define GLPES_PFIP4TXFRAGSLO(_i) (0x00547400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6612 #define GLPES_PFIP4TXFRAGSLO_MAX_INDEX 127 6613 #define GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_S 0 6614 #define GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_M MAKEMASK(0xFFFFFFFF, 0) 6615 #define GLPES_PFIP4TXMCOCTSHI(_i) (0x00547C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6616 #define GLPES_PFIP4TXMCOCTSHI_MAX_INDEX 127 6617 #define GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_S 0 6618 #define GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_M MAKEMASK(0xFFFF, 0) 6619 #define GLPES_PFIP4TXMCOCTSLO(_i) (0x00547C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6620 #define GLPES_PFIP4TXMCOCTSLO_MAX_INDEX 127 6621 #define GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_S 0 6622 #define GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_M MAKEMASK(0xFFFFFFFF, 0) 6623 #define GLPES_PFIP4TXMCPKTSHI(_i) (0x00548404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6624 #define GLPES_PFIP4TXMCPKTSHI_MAX_INDEX 127 6625 #define GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_S 0 6626 #define GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_M MAKEMASK(0xFFFF, 0) 6627 #define GLPES_PFIP4TXMCPKTSLO(_i) (0x00548400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6628 #define GLPES_PFIP4TXMCPKTSLO_MAX_INDEX 127 6629 #define GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_S 0 6630 #define GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_M MAKEMASK(0xFFFFFFFF, 0) 6631 #define GLPES_PFIP4TXNOROUTE(_i) (0x0054B400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 6632 #define GLPES_PFIP4TXNOROUTE_MAX_INDEX 127 6633 #define GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_S 0 6634 #define GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_M MAKEMASK(0xFFFFFF, 0) 6635 #define GLPES_PFIP4TXOCTSHI(_i) (0x00546404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6636 #define GLPES_PFIP4TXOCTSHI_MAX_INDEX 127 6637 #define GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_S 0 6638 #define GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_M MAKEMASK(0xFFFF, 0) 6639 #define GLPES_PFIP4TXOCTSLO(_i) (0x00546400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6640 #define GLPES_PFIP4TXOCTSLO_MAX_INDEX 127 6641 #define GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_S 0 6642 #define GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_M MAKEMASK(0xFFFFFFFF, 0) 6643 #define GLPES_PFIP4TXPKTSHI(_i) (0x00546C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6644 #define GLPES_PFIP4TXPKTSHI_MAX_INDEX 127 6645 #define GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_S 0 6646 #define GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_M MAKEMASK(0xFFFF, 0) 6647 #define GLPES_PFIP4TXPKTSLO(_i) (0x00546C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6648 #define GLPES_PFIP4TXPKTSLO_MAX_INDEX 127 6649 #define GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_S 0 6650 #define GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0) 6651 #define GLPES_PFIP6RXDISCARD(_i) (0x00544400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 6652 #define GLPES_PFIP6RXDISCARD_MAX_INDEX 127 6653 #define GLPES_PFIP6RXDISCARD_IP6RXDISCARD_S 0 6654 #define GLPES_PFIP6RXDISCARD_IP6RXDISCARD_M MAKEMASK(0xFFFFFFFF, 0) 6655 #define GLPES_PFIP6RXFRAGSHI(_i) (0x00544C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6656 #define GLPES_PFIP6RXFRAGSHI_MAX_INDEX 127 6657 #define GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_S 0 6658 #define GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_M MAKEMASK(0xFFFF, 0) 6659 #define GLPES_PFIP6RXFRAGSLO(_i) (0x00544C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6660 #define GLPES_PFIP6RXFRAGSLO_MAX_INDEX 127 6661 #define GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_S 0 6662 #define GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_M MAKEMASK(0xFFFFFFFF, 0) 6663 #define GLPES_PFIP6RXMCOCTSHI(_i) (0x00545404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6664 #define GLPES_PFIP6RXMCOCTSHI_MAX_INDEX 127 6665 #define GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_S 0 6666 #define GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_M MAKEMASK(0xFFFF, 0) 6667 #define GLPES_PFIP6RXMCOCTSLO(_i) (0x00545400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6668 #define GLPES_PFIP6RXMCOCTSLO_MAX_INDEX 127 6669 #define GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_S 0 6670 #define GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_M MAKEMASK(0xFFFFFFFF, 0) 6671 #define GLPES_PFIP6RXMCPKTSHI(_i) (0x00545C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6672 #define GLPES_PFIP6RXMCPKTSHI_MAX_INDEX 127 6673 #define GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_S 0 6674 #define GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_M MAKEMASK(0xFFFF, 0) 6675 #define GLPES_PFIP6RXMCPKTSLO(_i) (0x00545C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6676 #define GLPES_PFIP6RXMCPKTSLO_MAX_INDEX 127 6677 #define GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_S 0 6678 #define GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_M MAKEMASK(0xFFFFFFFF, 0) 6679 #define GLPES_PFIP6RXOCTSHI(_i) (0x00543404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6680 #define GLPES_PFIP6RXOCTSHI_MAX_INDEX 127 6681 #define GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_S 0 6682 #define GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_M MAKEMASK(0xFFFF, 0) 6683 #define GLPES_PFIP6RXOCTSLO(_i) (0x00543400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6684 #define GLPES_PFIP6RXOCTSLO_MAX_INDEX 127 6685 #define GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_S 0 6686 #define GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_M MAKEMASK(0xFFFFFFFF, 0) 6687 #define GLPES_PFIP6RXPKTSHI(_i) (0x00543C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6688 #define GLPES_PFIP6RXPKTSHI_MAX_INDEX 127 6689 #define GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_S 0 6690 #define GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_M MAKEMASK(0xFFFF, 0) 6691 #define GLPES_PFIP6RXPKTSLO(_i) (0x00543C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6692 #define GLPES_PFIP6RXPKTSLO_MAX_INDEX 127 6693 #define GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_S 0 6694 #define GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0) 6695 #define GLPES_PFIP6RXTRUNC(_i) (0x00544800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 6696 #define GLPES_PFIP6RXTRUNC_MAX_INDEX 127 6697 #define GLPES_PFIP6RXTRUNC_IP6RXTRUNC_S 0 6698 #define GLPES_PFIP6RXTRUNC_IP6RXTRUNC_M MAKEMASK(0xFFFFFFFF, 0) 6699 #define GLPES_PFIP6TXFRAGSHI(_i) (0x00549C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6700 #define GLPES_PFIP6TXFRAGSHI_MAX_INDEX 127 6701 #define GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_S 0 6702 #define GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_M MAKEMASK(0xFFFF, 0) 6703 #define GLPES_PFIP6TXFRAGSLO(_i) (0x00549C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6704 #define GLPES_PFIP6TXFRAGSLO_MAX_INDEX 127 6705 #define GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_S 0 6706 #define GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_M MAKEMASK(0xFFFFFFFF, 0) 6707 #define GLPES_PFIP6TXMCOCTSHI(_i) (0x0054A404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6708 #define GLPES_PFIP6TXMCOCTSHI_MAX_INDEX 127 6709 #define GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_S 0 6710 #define GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_M MAKEMASK(0xFFFF, 0) 6711 #define GLPES_PFIP6TXMCOCTSLO(_i) (0x0054A400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6712 #define GLPES_PFIP6TXMCOCTSLO_MAX_INDEX 127 6713 #define GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_S 0 6714 #define GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_M MAKEMASK(0xFFFFFFFF, 0) 6715 #define GLPES_PFIP6TXMCPKTSHI(_i) (0x0054AC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6716 #define GLPES_PFIP6TXMCPKTSHI_MAX_INDEX 127 6717 #define GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_S 0 6718 #define GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_M MAKEMASK(0xFFFF, 0) 6719 #define GLPES_PFIP6TXMCPKTSLO(_i) (0x0054AC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6720 #define GLPES_PFIP6TXMCPKTSLO_MAX_INDEX 127 6721 #define GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_S 0 6722 #define GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_M MAKEMASK(0xFFFFFFFF, 0) 6723 #define GLPES_PFIP6TXNOROUTE(_i) (0x0054B800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 6724 #define GLPES_PFIP6TXNOROUTE_MAX_INDEX 127 6725 #define GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_S 0 6726 #define GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_M MAKEMASK(0xFFFFFF, 0) 6727 #define GLPES_PFIP6TXOCTSHI(_i) (0x00548C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6728 #define GLPES_PFIP6TXOCTSHI_MAX_INDEX 127 6729 #define GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_S 0 6730 #define GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_M MAKEMASK(0xFFFF, 0) 6731 #define GLPES_PFIP6TXOCTSLO(_i) (0x00548C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6732 #define GLPES_PFIP6TXOCTSLO_MAX_INDEX 127 6733 #define GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_S 0 6734 #define GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_M MAKEMASK(0xFFFFFFFF, 0) 6735 #define GLPES_PFIP6TXPKTSHI(_i) (0x00549404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6736 #define GLPES_PFIP6TXPKTSHI_MAX_INDEX 127 6737 #define GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_S 0 6738 #define GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_M MAKEMASK(0xFFFF, 0) 6739 #define GLPES_PFIP6TXPKTSLO(_i) (0x00549400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6740 #define GLPES_PFIP6TXPKTSLO_MAX_INDEX 127 6741 #define GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_S 0 6742 #define GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0) 6743 #define GLPES_PFRDMARXRDSHI(_i) (0x0054EC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6744 #define GLPES_PFRDMARXRDSHI_MAX_INDEX 127 6745 #define GLPES_PFRDMARXRDSHI_RDMARXRDSHI_S 0 6746 #define GLPES_PFRDMARXRDSHI_RDMARXRDSHI_M MAKEMASK(0xFFFF, 0) 6747 #define GLPES_PFRDMARXRDSLO(_i) (0x0054EC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6748 #define GLPES_PFRDMARXRDSLO_MAX_INDEX 127 6749 #define GLPES_PFRDMARXRDSLO_RDMARXRDSLO_S 0 6750 #define GLPES_PFRDMARXRDSLO_RDMARXRDSLO_M MAKEMASK(0xFFFFFFFF, 0) 6751 #define GLPES_PFRDMARXSNDSHI(_i) (0x0054F404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6752 #define GLPES_PFRDMARXSNDSHI_MAX_INDEX 127 6753 #define GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_S 0 6754 #define GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_M MAKEMASK(0xFFFF, 0) 6755 #define GLPES_PFRDMARXSNDSLO(_i) (0x0054F400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6756 #define GLPES_PFRDMARXSNDSLO_MAX_INDEX 127 6757 #define GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_S 0 6758 #define GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_M MAKEMASK(0xFFFFFFFF, 0) 6759 #define GLPES_PFRDMARXWRSHI(_i) (0x0054E404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6760 #define GLPES_PFRDMARXWRSHI_MAX_INDEX 127 6761 #define GLPES_PFRDMARXWRSHI_RDMARXWRSHI_S 0 6762 #define GLPES_PFRDMARXWRSHI_RDMARXWRSHI_M MAKEMASK(0xFFFF, 0) 6763 #define GLPES_PFRDMARXWRSLO(_i) (0x0054E400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6764 #define GLPES_PFRDMARXWRSLO_MAX_INDEX 127 6765 #define GLPES_PFRDMARXWRSLO_RDMARXWRSLO_S 0 6766 #define GLPES_PFRDMARXWRSLO_RDMARXWRSLO_M MAKEMASK(0xFFFFFFFF, 0) 6767 #define GLPES_PFRDMATXRDSHI(_i) (0x00550404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6768 #define GLPES_PFRDMATXRDSHI_MAX_INDEX 127 6769 #define GLPES_PFRDMATXRDSHI_RDMARXRDSHI_S 0 6770 #define GLPES_PFRDMATXRDSHI_RDMARXRDSHI_M MAKEMASK(0xFFFF, 0) 6771 #define GLPES_PFRDMATXRDSLO(_i) (0x00550400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6772 #define GLPES_PFRDMATXRDSLO_MAX_INDEX 127 6773 #define GLPES_PFRDMATXRDSLO_RDMARXRDSLO_S 0 6774 #define GLPES_PFRDMATXRDSLO_RDMARXRDSLO_M MAKEMASK(0xFFFFFFFF, 0) 6775 #define GLPES_PFRDMATXSNDSHI(_i) (0x00550C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6776 #define GLPES_PFRDMATXSNDSHI_MAX_INDEX 127 6777 #define GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_S 0 6778 #define GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_M MAKEMASK(0xFFFF, 0) 6779 #define GLPES_PFRDMATXSNDSLO(_i) (0x00550C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6780 #define GLPES_PFRDMATXSNDSLO_MAX_INDEX 127 6781 #define GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_S 0 6782 #define GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_M MAKEMASK(0xFFFFFFFF, 0) 6783 #define GLPES_PFRDMATXWRSHI(_i) (0x0054FC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6784 #define GLPES_PFRDMATXWRSHI_MAX_INDEX 127 6785 #define GLPES_PFRDMATXWRSHI_RDMARXWRSHI_S 0 6786 #define GLPES_PFRDMATXWRSHI_RDMARXWRSHI_M MAKEMASK(0xFFFF, 0) 6787 #define GLPES_PFRDMATXWRSLO(_i) (0x0054FC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6788 #define GLPES_PFRDMATXWRSLO_MAX_INDEX 127 6789 #define GLPES_PFRDMATXWRSLO_RDMARXWRSLO_S 0 6790 #define GLPES_PFRDMATXWRSLO_RDMARXWRSLO_M MAKEMASK(0xFFFFFFFF, 0) 6791 #define GLPES_PFRDMAVBNDHI(_i) (0x00551404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6792 #define GLPES_PFRDMAVBNDHI_MAX_INDEX 127 6793 #define GLPES_PFRDMAVBNDHI_RDMAVBNDHI_S 0 6794 #define GLPES_PFRDMAVBNDHI_RDMAVBNDHI_M MAKEMASK(0xFFFF, 0) 6795 #define GLPES_PFRDMAVBNDLO(_i) (0x00551400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6796 #define GLPES_PFRDMAVBNDLO_MAX_INDEX 127 6797 #define GLPES_PFRDMAVBNDLO_RDMAVBNDLO_S 0 6798 #define GLPES_PFRDMAVBNDLO_RDMAVBNDLO_M MAKEMASK(0xFFFFFFFF, 0) 6799 #define GLPES_PFRDMAVINVHI(_i) (0x00551C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6800 #define GLPES_PFRDMAVINVHI_MAX_INDEX 127 6801 #define GLPES_PFRDMAVINVHI_RDMAVINVHI_S 0 6802 #define GLPES_PFRDMAVINVHI_RDMAVINVHI_M MAKEMASK(0xFFFF, 0) 6803 #define GLPES_PFRDMAVINVLO(_i) (0x00551C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6804 #define GLPES_PFRDMAVINVLO_MAX_INDEX 127 6805 #define GLPES_PFRDMAVINVLO_RDMAVINVLO_S 0 6806 #define GLPES_PFRDMAVINVLO_RDMAVINVLO_M MAKEMASK(0xFFFFFFFF, 0) 6807 #define GLPES_PFRXVLANERR(_i) (0x00540000 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 6808 #define GLPES_PFRXVLANERR_MAX_INDEX 127 6809 #define GLPES_PFRXVLANERR_RXVLANERR_S 0 6810 #define GLPES_PFRXVLANERR_RXVLANERR_M MAKEMASK(0xFFFFFF, 0) 6811 #define GLPES_PFTCPRTXSEG(_i) (0x00552400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 6812 #define GLPES_PFTCPRTXSEG_MAX_INDEX 127 6813 #define GLPES_PFTCPRTXSEG_TCPRTXSEG_S 0 6814 #define GLPES_PFTCPRTXSEG_TCPRTXSEG_M MAKEMASK(0xFFFFFFFF, 0) 6815 #define GLPES_PFTCPRXOPTERR(_i) (0x0054C400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 6816 #define GLPES_PFTCPRXOPTERR_MAX_INDEX 127 6817 #define GLPES_PFTCPRXOPTERR_TCPRXOPTERR_S 0 6818 #define GLPES_PFTCPRXOPTERR_TCPRXOPTERR_M MAKEMASK(0xFFFFFF, 0) 6819 #define GLPES_PFTCPRXPROTOERR(_i) (0x0054C800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 6820 #define GLPES_PFTCPRXPROTOERR_MAX_INDEX 127 6821 #define GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_S 0 6822 #define GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_M MAKEMASK(0xFFFFFF, 0) 6823 #define GLPES_PFTCPRXSEGSHI(_i) (0x0054BC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6824 #define GLPES_PFTCPRXSEGSHI_MAX_INDEX 127 6825 #define GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_S 0 6826 #define GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_M MAKEMASK(0xFFFF, 0) 6827 #define GLPES_PFTCPRXSEGSLO(_i) (0x0054BC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6828 #define GLPES_PFTCPRXSEGSLO_MAX_INDEX 127 6829 #define GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_S 0 6830 #define GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_M MAKEMASK(0xFFFFFFFF, 0) 6831 #define GLPES_PFTCPTXSEGHI(_i) (0x0054CC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6832 #define GLPES_PFTCPTXSEGHI_MAX_INDEX 127 6833 #define GLPES_PFTCPTXSEGHI_TCPTXSEGHI_S 0 6834 #define GLPES_PFTCPTXSEGHI_TCPTXSEGHI_M MAKEMASK(0xFFFF, 0) 6835 #define GLPES_PFTCPTXSEGLO(_i) (0x0054CC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6836 #define GLPES_PFTCPTXSEGLO_MAX_INDEX 127 6837 #define GLPES_PFTCPTXSEGLO_TCPTXSEGLO_S 0 6838 #define GLPES_PFTCPTXSEGLO_TCPTXSEGLO_M MAKEMASK(0xFFFFFFFF, 0) 6839 #define GLPES_PFUDPRXPKTSHI(_i) (0x0054D404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6840 #define GLPES_PFUDPRXPKTSHI_MAX_INDEX 127 6841 #define GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_S 0 6842 #define GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_M MAKEMASK(0xFFFF, 0) 6843 #define GLPES_PFUDPRXPKTSLO(_i) (0x0054D400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6844 #define GLPES_PFUDPRXPKTSLO_MAX_INDEX 127 6845 #define GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_S 0 6846 #define GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0) 6847 #define GLPES_PFUDPTXPKTSHI(_i) (0x0054DC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6848 #define GLPES_PFUDPTXPKTSHI_MAX_INDEX 127 6849 #define GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_S 0 6850 #define GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_M MAKEMASK(0xFFFF, 0) 6851 #define GLPES_PFUDPTXPKTSLO(_i) (0x0054DC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 6852 #define GLPES_PFUDPTXPKTSLO_MAX_INDEX 127 6853 #define GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_S 0 6854 #define GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0) 6855 #define GLPES_RDMARXMULTFPDUSHI 0x0055E00C /* Reset Source: CORER */ 6856 #define GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_S 0 6857 #define GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_M MAKEMASK(0xFFFFFF, 0) 6858 #define GLPES_RDMARXMULTFPDUSLO 0x0055E008 /* Reset Source: CORER */ 6859 #define GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_S 0 6860 #define GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_M MAKEMASK(0xFFFFFFFF, 0) 6861 #define GLPES_RDMARXOOODDPHI 0x0055E014 /* Reset Source: CORER */ 6862 #define GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_S 0 6863 #define GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_M MAKEMASK(0xFFFFFF, 0) 6864 #define GLPES_RDMARXOOODDPLO 0x0055E010 /* Reset Source: CORER */ 6865 #define GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_S 0 6866 #define GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_M MAKEMASK(0xFFFFFFFF, 0) 6867 #define GLPES_RDMARXOOONOMARK 0x0055E004 /* Reset Source: CORER */ 6868 #define GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_S 0 6869 #define GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_M MAKEMASK(0xFFFFFFFF, 0) 6870 #define GLPES_RDMARXUNALIGN 0x0055E000 /* Reset Source: CORER */ 6871 #define GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_S 0 6872 #define GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_M MAKEMASK(0xFFFFFFFF, 0) 6873 #define GLPES_TCPRXFOURHOLEHI 0x0055E03C /* Reset Source: CORER */ 6874 #define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_S 0 6875 #define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_M MAKEMASK(0xFFFFFF, 0) 6876 #define GLPES_TCPRXFOURHOLELO 0x0055E038 /* Reset Source: CORER */ 6877 #define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_S 0 6878 #define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_M MAKEMASK(0xFFFFFFFF, 0) 6879 #define GLPES_TCPRXONEHOLEHI 0x0055E024 /* Reset Source: CORER */ 6880 #define GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_S 0 6881 #define GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_M MAKEMASK(0xFFFFFF, 0) 6882 #define GLPES_TCPRXONEHOLELO 0x0055E020 /* Reset Source: CORER */ 6883 #define GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_S 0 6884 #define GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_M MAKEMASK(0xFFFFFFFF, 0) 6885 #define GLPES_TCPRXPUREACKHI 0x0055E01C /* Reset Source: CORER */ 6886 #define GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_S 0 6887 #define GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_M MAKEMASK(0xFFFFFF, 0) 6888 #define GLPES_TCPRXPUREACKSLO 0x0055E018 /* Reset Source: CORER */ 6889 #define GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_S 0 6890 #define GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_M MAKEMASK(0xFFFFFFFF, 0) 6891 #define GLPES_TCPRXTHREEHOLEHI 0x0055E034 /* Reset Source: CORER */ 6892 #define GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_S 0 6893 #define GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_M MAKEMASK(0xFFFFFF, 0) 6894 #define GLPES_TCPRXTHREEHOLELO 0x0055E030 /* Reset Source: CORER */ 6895 #define GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_S 0 6896 #define GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_M MAKEMASK(0xFFFFFFFF, 0) 6897 #define GLPES_TCPRXTWOHOLEHI 0x0055E02C /* Reset Source: CORER */ 6898 #define GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_S 0 6899 #define GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_M MAKEMASK(0xFFFFFF, 0) 6900 #define GLPES_TCPRXTWOHOLELO 0x0055E028 /* Reset Source: CORER */ 6901 #define GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_S 0 6902 #define GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_M MAKEMASK(0xFFFFFFFF, 0) 6903 #define GLPES_TCPTXRETRANSFASTHI 0x0055E044 /* Reset Source: CORER */ 6904 #define GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_S 0 6905 #define GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_M MAKEMASK(0xFFFFFF, 0) 6906 #define GLPES_TCPTXRETRANSFASTLO 0x0055E040 /* Reset Source: CORER */ 6907 #define GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_S 0 6908 #define GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_M MAKEMASK(0xFFFFFFFF, 0) 6909 #define GLPES_TCPTXTOUTSFASTHI 0x0055E04C /* Reset Source: CORER */ 6910 #define GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_S 0 6911 #define GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_M MAKEMASK(0xFFFFFF, 0) 6912 #define GLPES_TCPTXTOUTSFASTLO 0x0055E048 /* Reset Source: CORER */ 6913 #define GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_S 0 6914 #define GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_M MAKEMASK(0xFFFFFFFF, 0) 6915 #define GLPES_TCPTXTOUTSHI 0x0055E054 /* Reset Source: CORER */ 6916 #define GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_S 0 6917 #define GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_M MAKEMASK(0xFFFFFF, 0) 6918 #define GLPES_TCPTXTOUTSLO 0x0055E050 /* Reset Source: CORER */ 6919 #define GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_S 0 6920 #define GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_M MAKEMASK(0xFFFFFFFF, 0) 6921 #define GL_PWR_MODE_CTL 0x000B820C /* Reset Source: POR */ 6922 #define GL_PWR_MODE_CTL_SWITCH_PWR_MODE_EN_S 0 6923 #define GL_PWR_MODE_CTL_SWITCH_PWR_MODE_EN_M BIT(0) 6924 #define GL_PWR_MODE_CTL_NIC_PWR_MODE_EN_S 1 6925 #define GL_PWR_MODE_CTL_NIC_PWR_MODE_EN_M BIT(1) 6926 #define GL_PWR_MODE_CTL_S5_PWR_MODE_EN_S 2 6927 #define GL_PWR_MODE_CTL_S5_PWR_MODE_EN_M BIT(2) 6928 #define GL_PWR_MODE_CTL_CAR_MAX_SW_CONFIG_S 3 6929 #define GL_PWR_MODE_CTL_CAR_MAX_SW_CONFIG_M MAKEMASK(0x3, 3) 6930 #define GL_PWR_MODE_CTL_CAR_MAX_BW_S 30 6931 #define GL_PWR_MODE_CTL_CAR_MAX_BW_M MAKEMASK(0x3, 30) 6932 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT 0x000B825C /* Reset Source: POR */ 6933 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_PECLK_S 0 6934 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_PECLK_M MAKEMASK(0x7, 0) 6935 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_UCLK_S 3 6936 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_UCLK_M MAKEMASK(0x7, 3) 6937 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_LCLK_S 6 6938 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_LCLK_M MAKEMASK(0x7, 6) 6939 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_PSM_S 9 6940 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_PSM_M MAKEMASK(0x7, 9) 6941 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_RXCTL_S 12 6942 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_RXCTL_M MAKEMASK(0x7, 12) 6943 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_UANA_S 15 6944 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_UANA_M MAKEMASK(0x7, 15) 6945 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_S5_S 18 6946 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_S5_M MAKEMASK(0x7, 18) 6947 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT 0x000B8218 /* Reset Source: POR */ 6948 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_PECLK_S 0 6949 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_PECLK_M MAKEMASK(0x7, 0) 6950 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_UCLK_S 3 6951 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_UCLK_M MAKEMASK(0x7, 3) 6952 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_LCLK_S 6 6953 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_LCLK_M MAKEMASK(0x7, 6) 6954 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_PSM_S 9 6955 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_PSM_M MAKEMASK(0x7, 9) 6956 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_RXCTL_S 12 6957 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_RXCTL_M MAKEMASK(0x7, 12) 6958 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_UANA_S 15 6959 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_UANA_M MAKEMASK(0x7, 15) 6960 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_S5_S 18 6961 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_S5_M MAKEMASK(0x7, 18) 6962 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT 0x000B8260 /* Reset Source: POR */ 6963 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_PECLK_S 0 6964 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_PECLK_M MAKEMASK(0x7, 0) 6965 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_UCLK_S 3 6966 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_UCLK_M MAKEMASK(0x7, 3) 6967 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_LCLK_S 6 6968 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_LCLK_M MAKEMASK(0x7, 6) 6969 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_PSM_S 9 6970 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_PSM_M MAKEMASK(0x7, 9) 6971 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_RXCTL_S 12 6972 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_RXCTL_M MAKEMASK(0x7, 12) 6973 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_UANA_S 15 6974 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_UANA_M MAKEMASK(0x7, 15) 6975 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_S5_S 18 6976 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_S5_M MAKEMASK(0x7, 18) 6977 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK 0x000B8200 /* Reset Source: POR */ 6978 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_50G_H_S 0 6979 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0) 6980 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_25G_H_S 3 6981 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3) 6982 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_10G_H_S 6 6983 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6) 6984 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_4G_H_S 9 6985 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9) 6986 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_A50G_H_S 12 6987 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12) 6988 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK 0x000B81F0 /* Reset Source: POR */ 6989 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_50G_H_S 0 6990 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0) 6991 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_25G_H_S 3 6992 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3) 6993 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_10G_H_S 6 6994 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6) 6995 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_4G_H_S 9 6996 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9) 6997 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_A50G_H_S 12 6998 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12) 6999 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM 0x000B81FC /* Reset Source: POR */ 7000 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_50G_H_S 0 7001 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0) 7002 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_25G_H_S 3 7003 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3) 7004 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_10G_H_S 6 7005 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6) 7006 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_4G_H_S 9 7007 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9) 7008 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_A50G_H_S 12 7009 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12) 7010 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL 0x000B81F8 /* Reset Source: POR */ 7011 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_50G_H_S 0 7012 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0) 7013 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_25G_H_S 3 7014 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3) 7015 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_10G_H_S 6 7016 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6) 7017 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_4G_H_S 9 7018 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9) 7019 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_A50G_H_S 12 7020 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12) 7021 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA 0x000B8208 /* Reset Source: POR */ 7022 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_50G_H_S 0 7023 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0) 7024 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_25G_H_S 3 7025 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3) 7026 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_10G_H_S 6 7027 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6) 7028 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_4G_H_S 9 7029 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9) 7030 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_A50G_H_S 12 7031 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12) 7032 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK 0x000B81F4 /* Reset Source: POR */ 7033 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_50G_H_S 0 7034 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0) 7035 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_25G_H_S 3 7036 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3) 7037 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_10G_H_S 6 7038 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6) 7039 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_4G_H_S 9 7040 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9) 7041 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_A50G_H_S 12 7042 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12) 7043 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK 0x000B8244 /* Reset Source: POR */ 7044 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_50G_L_S 0 7045 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0) 7046 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_25G_L_S 3 7047 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3) 7048 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_10G_L_S 6 7049 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6) 7050 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_4G_L_S 9 7051 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9) 7052 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_A50G_L_S 12 7053 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12) 7054 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK 0x000B8220 /* Reset Source: POR */ 7055 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_50G_L_S 0 7056 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0) 7057 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_25G_L_S 3 7058 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3) 7059 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_10G_L_S 6 7060 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6) 7061 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_4G_L_S 9 7062 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9) 7063 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_A50G_L_S 12 7064 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12) 7065 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM 0x000B8240 /* Reset Source: POR */ 7066 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_50G_L_S 0 7067 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0) 7068 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_25G_L_S 3 7069 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3) 7070 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_10G_L_S 6 7071 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6) 7072 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_4G_L_S 9 7073 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9) 7074 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_A50G_L_S 12 7075 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12) 7076 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL 0x000B823C /* Reset Source: POR */ 7077 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_50G_L_S 0 7078 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0) 7079 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_25G_L_S 3 7080 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3) 7081 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_10G_L_S 6 7082 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6) 7083 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_4G_L_S 9 7084 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9) 7085 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_A50G_L_S 12 7086 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12) 7087 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA 0x000B8248 /* Reset Source: POR */ 7088 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_50G_L_S 0 7089 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0) 7090 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_25G_L_S 3 7091 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3) 7092 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_10G_L_S 6 7093 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6) 7094 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_4G_L_S 9 7095 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9) 7096 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_A50G_L_S 12 7097 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12) 7098 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK 0x000B8238 /* Reset Source: POR */ 7099 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_50G_L_S 0 7100 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0) 7101 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_25G_L_S 3 7102 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3) 7103 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_10G_L_S 6 7104 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6) 7105 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_4G_L_S 9 7106 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9) 7107 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_A50G_L_S 12 7108 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12) 7109 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK 0x000B8230 /* Reset Source: POR */ 7110 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_50G_M_S 0 7111 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0) 7112 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_25G_M_S 3 7113 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3) 7114 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_10G_M_S 6 7115 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6) 7116 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_4G_M_S 9 7117 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9) 7118 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_A50G_M_S 12 7119 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12) 7120 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK 0x000B821C /* Reset Source: POR */ 7121 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_50G_M_S 0 7122 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0) 7123 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_25G_M_S 3 7124 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3) 7125 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_10G_M_S 6 7126 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6) 7127 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_4G_M_S 9 7128 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9) 7129 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_A50G_M_S 12 7130 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12) 7131 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM 0x000B822C /* Reset Source: POR */ 7132 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_50G_M_S 0 7133 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0) 7134 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_25G_M_S 3 7135 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3) 7136 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_10G_M_S 6 7137 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6) 7138 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_4G_M_S 9 7139 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9) 7140 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_A50G_M_S 12 7141 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12) 7142 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL 0x000B8228 /* Reset Source: POR */ 7143 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_50G_M_S 0 7144 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0) 7145 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_25G_M_S 3 7146 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3) 7147 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_10G_M_S 6 7148 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6) 7149 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_4G_M_S 9 7150 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9) 7151 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_A50G_M_S 12 7152 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12) 7153 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA 0x000B8234 /* Reset Source: POR */ 7154 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_50G_M_S 0 7155 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0) 7156 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_25G_M_S 3 7157 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3) 7158 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_10G_M_S 6 7159 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6) 7160 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_4G_M_S 9 7161 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9) 7162 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_A50G_M_S 12 7163 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12) 7164 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK 0x000B8224 /* Reset Source: POR */ 7165 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_50G_M_S 0 7166 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0) 7167 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_25G_M_S 3 7168 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3) 7169 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_10G_M_S 6 7170 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6) 7171 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_4G_M_S 9 7172 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9) 7173 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_A50G_M_S 12 7174 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12) 7175 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL 0x000B81EC /* Reset Source: POR */ 7176 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_50G_H_S 0 7177 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0) 7178 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_25G_H_S 3 7179 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3) 7180 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_10G_H_S 6 7181 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6) 7182 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_4G_H_S 9 7183 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9) 7184 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_A50G_H_S 12 7185 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12) 7186 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL 0x000B824C /* Reset Source: POR */ 7187 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_50G_L_S 0 7188 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0) 7189 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_25G_L_S 3 7190 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3) 7191 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_10G_L_S 6 7192 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6) 7193 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_4G_L_S 9 7194 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9) 7195 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_A50G_L_S 12 7196 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12) 7197 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL 0x000B8250 /* Reset Source: POR */ 7198 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_50G_M_S 0 7199 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0) 7200 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_25G_M_S 3 7201 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3) 7202 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_10G_M_S 6 7203 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6) 7204 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_4G_M_S 9 7205 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9) 7206 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_A50G_M_S 12 7207 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12) 7208 #define GL_S5_PWR_MODE_EXIT_CTL 0x000B8270 /* Reset Source: POR */ 7209 #define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_AUTO_EXIT_S 0 7210 #define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_AUTO_EXIT_M BIT(0) 7211 #define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_FW_EXIT_S 1 7212 #define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_FW_EXIT_M BIT(1) 7213 #define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_PRST_FLOWS_ON_CORER_S 3 7214 #define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_PRST_FLOWS_ON_CORER_M BIT(3) 7215 #define GLGEN_PME_TO 0x000B81BC /* Reset Source: POR */ 7216 #define GLGEN_PME_TO_PME_TO_FOR_PE_S 0 7217 #define GLGEN_PME_TO_PME_TO_FOR_PE_M BIT(0) 7218 #define PRTPM_EEE_STAT 0x001E4320 /* Reset Source: GLOBR */ 7219 #define PRTPM_EEE_STAT_EEE_NEG_S 29 7220 #define PRTPM_EEE_STAT_EEE_NEG_M BIT(29) 7221 #define PRTPM_EEE_STAT_RX_LPI_STATUS_S 30 7222 #define PRTPM_EEE_STAT_RX_LPI_STATUS_M BIT(30) 7223 #define PRTPM_EEE_STAT_TX_LPI_STATUS_S 31 7224 #define PRTPM_EEE_STAT_TX_LPI_STATUS_M BIT(31) 7225 #define PRTPM_EEEC 0x001E4380 /* Reset Source: GLOBR */ 7226 #define PRTPM_EEEC_TW_WAKE_MIN_S 16 7227 #define PRTPM_EEEC_TW_WAKE_MIN_M MAKEMASK(0x3F, 16) 7228 #define PRTPM_EEEC_TX_LU_LPI_DLY_S 24 7229 #define PRTPM_EEEC_TX_LU_LPI_DLY_M MAKEMASK(0x3, 24) 7230 #define PRTPM_EEEC_TEEE_DLY_S 26 7231 #define PRTPM_EEEC_TEEE_DLY_M MAKEMASK(0x3F, 26) 7232 #define PRTPM_EEEFWD 0x001E4400 /* Reset Source: GLOBR */ 7233 #define PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_S 31 7234 #define PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_M BIT(31) 7235 #define PRTPM_EEER 0x001E4360 /* Reset Source: GLOBR */ 7236 #define PRTPM_EEER_TW_SYSTEM_S 0 7237 #define PRTPM_EEER_TW_SYSTEM_M MAKEMASK(0xFFFF, 0) 7238 #define PRTPM_EEER_TX_LPI_EN_S 16 7239 #define PRTPM_EEER_TX_LPI_EN_M BIT(16) 7240 #define PRTPM_EEETXC 0x001E43E0 /* Reset Source: GLOBR */ 7241 #define PRTPM_EEETXC_TW_PHY_S 0 7242 #define PRTPM_EEETXC_TW_PHY_M MAKEMASK(0xFFFF, 0) 7243 #define PRTPM_RLPIC 0x001E43A0 /* Reset Source: GLOBR */ 7244 #define PRTPM_RLPIC_ERLPIC_S 0 7245 #define PRTPM_RLPIC_ERLPIC_M MAKEMASK(0xFFFFFFFF, 0) 7246 #define PRTPM_TLPIC 0x001E43C0 /* Reset Source: GLOBR */ 7247 #define PRTPM_TLPIC_ETLPIC_S 0 7248 #define PRTPM_TLPIC_ETLPIC_M MAKEMASK(0xFFFFFFFF, 0) 7249 #define GLRPB_DHW(_i) (0x000AC000 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 7250 #define GLRPB_DHW_MAX_INDEX 15 7251 #define GLRPB_DHW_DHW_TCN_S 0 7252 #define GLRPB_DHW_DHW_TCN_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLRPB_DHW_DHW_TCN_M : E800_GLRPB_DHW_DHW_TCN_M) 7253 #define E800_GLRPB_DHW_DHW_TCN_M MAKEMASK(0xFFFFF, 0) 7254 #define E830_GLRPB_DHW_DHW_TCN_M MAKEMASK(0x3FFFFF, 0) 7255 #define GLRPB_DLW(_i) (0x000AC044 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 7256 #define GLRPB_DLW_MAX_INDEX 15 7257 #define GLRPB_DLW_DLW_TCN_S 0 7258 #define GLRPB_DLW_DLW_TCN_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLRPB_DLW_DLW_TCN_M : E800_GLRPB_DLW_DLW_TCN_M) 7259 #define E800_GLRPB_DLW_DLW_TCN_M MAKEMASK(0xFFFFF, 0) 7260 #define E830_GLRPB_DLW_DLW_TCN_M MAKEMASK(0x3FFFFF, 0) 7261 #define GLRPB_DPS(_i) (0x000AC084 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 7262 #define GLRPB_DPS_MAX_INDEX 15 7263 #define GLRPB_DPS_DPS_TCN_S 0 7264 #define GLRPB_DPS_DPS_TCN_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLRPB_DPS_DPS_TCN_M : E800_GLRPB_DPS_DPS_TCN_M) 7265 #define E800_GLRPB_DPS_DPS_TCN_M MAKEMASK(0xFFFFF, 0) 7266 #define E830_GLRPB_DPS_DPS_TCN_M MAKEMASK(0x3FFFFF, 0) 7267 #define GLRPB_DSI_EN 0x000AC324 /* Reset Source: CORER */ 7268 #define GLRPB_DSI_EN_DSI_EN_S 0 7269 #define GLRPB_DSI_EN_DSI_EN_M BIT(0) 7270 #define GLRPB_DSI_EN_DSI_L2_MAC_ERR_DROP_EN_S 1 7271 #define GLRPB_DSI_EN_DSI_L2_MAC_ERR_DROP_EN_M BIT(1) 7272 #define GLRPB_SHW(_i) (0x000AC120 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 7273 #define GLRPB_SHW_MAX_INDEX 7 7274 #define GLRPB_SHW_SHW_S 0 7275 #define GLRPB_SHW_SHW_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLRPB_SHW_SHW_M : E800_GLRPB_SHW_SHW_M) 7276 #define E800_GLRPB_SHW_SHW_M MAKEMASK(0xFFFFF, 0) 7277 #define E830_GLRPB_SHW_SHW_M MAKEMASK(0x3FFFFF, 0) 7278 #define GLRPB_SLW(_i) (0x000AC140 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 7279 #define GLRPB_SLW_MAX_INDEX 7 7280 #define GLRPB_SLW_SLW_S 0 7281 #define GLRPB_SLW_SLW_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLRPB_SLW_SLW_M : E800_GLRPB_SLW_SLW_M) 7282 #define E800_GLRPB_SLW_SLW_M MAKEMASK(0xFFFFF, 0) 7283 #define E830_GLRPB_SLW_SLW_M MAKEMASK(0x3FFFFF, 0) 7284 #define GLRPB_SPS(_i) (0x000AC0C4 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 7285 #define GLRPB_SPS_MAX_INDEX 7 7286 #define GLRPB_SPS_SPS_TCN_S 0 7287 #define GLRPB_SPS_SPS_TCN_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLRPB_SPS_SPS_TCN_M : E800_GLRPB_SPS_SPS_TCN_M) 7288 #define E800_GLRPB_SPS_SPS_TCN_M MAKEMASK(0xFFFFF, 0) 7289 #define E830_GLRPB_SPS_SPS_TCN_M MAKEMASK(0x3FFFFF, 0) 7290 #define GLRPB_TC_CFG(_i) (0x000AC2A4 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 7291 #define GLRPB_TC_CFG_MAX_INDEX 31 7292 #define GLRPB_TC_CFG_D_POOL_S 0 7293 #define GLRPB_TC_CFG_D_POOL_M MAKEMASK(0xFFFF, 0) 7294 #define GLRPB_TC_CFG_S_POOL_S 16 7295 #define GLRPB_TC_CFG_S_POOL_M MAKEMASK(0xFFFF, 16) 7296 #define GLRPB_TCHW(_i) (0x000AC330 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 7297 #define GLRPB_TCHW_MAX_INDEX 31 7298 #define GLRPB_TCHW_TCHW_S 0 7299 #define GLRPB_TCHW_TCHW_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLRPB_TCHW_TCHW_M : E800_GLRPB_TCHW_TCHW_M) 7300 #define E800_GLRPB_TCHW_TCHW_M MAKEMASK(0xFFFFF, 0) 7301 #define E830_GLRPB_TCHW_TCHW_M MAKEMASK(0x3FFFFF, 0) 7302 #define GLRPB_TCLW(_i) (0x000AC3B0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 7303 #define GLRPB_TCLW_MAX_INDEX 31 7304 #define GLRPB_TCLW_TCLW_S 0 7305 #define GLRPB_TCLW_TCLW_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLRPB_TCLW_TCLW_M : E800_GLRPB_TCLW_TCLW_M) 7306 #define E800_GLRPB_TCLW_TCLW_M MAKEMASK(0xFFFFF, 0) 7307 #define E830_GLRPB_TCLW_TCLW_M MAKEMASK(0x3FFFFF, 0) 7308 #define GLQF_APBVT(_i) (0x00450000 + ((_i) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */ 7309 #define GLQF_APBVT_MAX_INDEX 2047 7310 #define GLQF_APBVT_APBVT_S 0 7311 #define GLQF_APBVT_APBVT_M MAKEMASK(0xFFFFFFFF, 0) 7312 #define GLQF_FD_CLSN_0 0x00460028 /* Reset Source: CORER */ 7313 #define GLQF_FD_CLSN_0_HITSBCNT_S 0 7314 #define GLQF_FD_CLSN_0_HITSBCNT_M MAKEMASK(0xFFFFFFFF, 0) 7315 #define GLQF_FD_CLSN1 0x00460030 /* Reset Source: CORER */ 7316 #define GLQF_FD_CLSN1_HITLBCNT_S 0 7317 #define GLQF_FD_CLSN1_HITLBCNT_M MAKEMASK(0xFFFFFFFF, 0) 7318 #define GLQF_FD_CNT 0x00460018 /* Reset Source: CORER */ 7319 #define GLQF_FD_CNT_FD_GCNT_S 0 7320 #define GLQF_FD_CNT_FD_GCNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLQF_FD_CNT_FD_GCNT_M : E800_GLQF_FD_CNT_FD_GCNT_M) 7321 #define E800_GLQF_FD_CNT_FD_GCNT_M MAKEMASK(0x7FFF, 0) 7322 #define E830_GLQF_FD_CNT_FD_GCNT_M MAKEMASK(0xFFFF, 0) 7323 #define GLQF_FD_CNT_FD_BCNT_S 16 7324 #define GLQF_FD_CNT_FD_BCNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLQF_FD_CNT_FD_BCNT_M : E800_GLQF_FD_CNT_FD_BCNT_M) 7325 #define E800_GLQF_FD_CNT_FD_BCNT_M MAKEMASK(0x7FFF, 16) 7326 #define E830_GLQF_FD_CNT_FD_BCNT_M MAKEMASK(0xFFFF, 16) 7327 #define GLQF_FD_CTL 0x00460000 /* Reset Source: CORER */ 7328 #define GLQF_FD_CTL_FDLONG_S 0 7329 #define GLQF_FD_CTL_FDLONG_M MAKEMASK(0xF, 0) 7330 #define GLQF_FD_CTL_HASH_REPORT_S 4 7331 #define GLQF_FD_CTL_HASH_REPORT_M BIT(4) 7332 #define GLQF_FD_CTL_FLT_ADDR_REPORT_S 5 7333 #define GLQF_FD_CTL_FLT_ADDR_REPORT_M BIT(5) 7334 #define GLQF_FD_SIZE 0x00460010 /* Reset Source: CORER */ 7335 #define GLQF_FD_SIZE_FD_GSIZE_S 0 7336 #define GLQF_FD_SIZE_FD_GSIZE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLQF_FD_SIZE_FD_GSIZE_M : E800_GLQF_FD_SIZE_FD_GSIZE_M) 7337 #define E800_GLQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0x7FFF, 0) 7338 #define E830_GLQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0xFFFF, 0) 7339 #define GLQF_FD_SIZE_FD_BSIZE_S 16 7340 #define GLQF_FD_SIZE_FD_BSIZE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLQF_FD_SIZE_FD_BSIZE_M : E800_GLQF_FD_SIZE_FD_BSIZE_M) 7341 #define E800_GLQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0x7FFF, 16) 7342 #define E830_GLQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0xFFFF, 16) 7343 #define GLQF_FDCNT_0 0x00460020 /* Reset Source: CORER */ 7344 #define GLQF_FDCNT_0_BUCKETCNT_S 0 7345 #define GLQF_FDCNT_0_BUCKETCNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLQF_FDCNT_0_BUCKETCNT_M : E800_GLQF_FDCNT_0_BUCKETCNT_M) 7346 #define E800_GLQF_FDCNT_0_BUCKETCNT_M MAKEMASK(0x7FFF, 0) 7347 #define E830_GLQF_FDCNT_0_BUCKETCNT_M MAKEMASK(0xFFFF, 0) 7348 #define GLQF_FDCNT_0_CNT_NOT_VLD_S 31 7349 #define GLQF_FDCNT_0_CNT_NOT_VLD_M BIT(31) 7350 #define GLQF_FDEVICTENA(_i) (0x00452000 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */ 7351 #define GLQF_FDEVICTENA_MAX_INDEX 3 7352 #define GLQF_FDEVICTENA_FDEVICTENA_S 0 7353 #define GLQF_FDEVICTENA_FDEVICTENA_M MAKEMASK(0xFFFFFFFF, 0) 7354 #define GLQF_FDINSET(_i, _j) (0x00412000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...5 */ /* Reset Source: CORER */ 7355 #define GLQF_FDINSET_MAX_INDEX 127 7356 #define GLQF_FDINSET_FV_WORD_INDX0_S 0 7357 #define GLQF_FDINSET_FV_WORD_INDX0_M MAKEMASK(0x1F, 0) 7358 #define GLQF_FDINSET_FV_WORD_VAL0_S 7 7359 #define GLQF_FDINSET_FV_WORD_VAL0_M BIT(7) 7360 #define GLQF_FDINSET_FV_WORD_INDX1_S 8 7361 #define GLQF_FDINSET_FV_WORD_INDX1_M MAKEMASK(0x1F, 8) 7362 #define GLQF_FDINSET_FV_WORD_VAL1_S 15 7363 #define GLQF_FDINSET_FV_WORD_VAL1_M BIT(15) 7364 #define GLQF_FDINSET_FV_WORD_INDX2_S 16 7365 #define GLQF_FDINSET_FV_WORD_INDX2_M MAKEMASK(0x1F, 16) 7366 #define GLQF_FDINSET_FV_WORD_VAL2_S 23 7367 #define GLQF_FDINSET_FV_WORD_VAL2_M BIT(23) 7368 #define GLQF_FDINSET_FV_WORD_INDX3_S 24 7369 #define GLQF_FDINSET_FV_WORD_INDX3_M MAKEMASK(0x1F, 24) 7370 #define GLQF_FDINSET_FV_WORD_VAL3_S 31 7371 #define GLQF_FDINSET_FV_WORD_VAL3_M BIT(31) 7372 #define GLQF_FDMASK(_i) (0x00410800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 7373 #define GLQF_FDMASK_MAX_INDEX 31 7374 #define GLQF_FDMASK_MSK_INDEX_S 0 7375 #define GLQF_FDMASK_MSK_INDEX_M MAKEMASK(0x1F, 0) 7376 #define GLQF_FDMASK_MASK_S 16 7377 #define GLQF_FDMASK_MASK_M MAKEMASK(0xFFFF, 16) 7378 #define GLQF_FDMASK_SEL(_i) (0x00410400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 7379 #define GLQF_FDMASK_SEL_MAX_INDEX 127 7380 #define GLQF_FDMASK_SEL_MASK_SEL_S 0 7381 #define GLQF_FDMASK_SEL_MASK_SEL_M MAKEMASK(0xFFFFFFFF, 0) 7382 #define GLQF_FDSWAP(_i, _j) (0x00413000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...5 */ /* Reset Source: CORER */ 7383 #define GLQF_FDSWAP_MAX_INDEX 127 7384 #define GLQF_FDSWAP_FV_WORD_INDX0_S 0 7385 #define GLQF_FDSWAP_FV_WORD_INDX0_M MAKEMASK(0x1F, 0) 7386 #define GLQF_FDSWAP_FV_WORD_VAL0_S 7 7387 #define GLQF_FDSWAP_FV_WORD_VAL0_M BIT(7) 7388 #define GLQF_FDSWAP_FV_WORD_INDX1_S 8 7389 #define GLQF_FDSWAP_FV_WORD_INDX1_M MAKEMASK(0x1F, 8) 7390 #define GLQF_FDSWAP_FV_WORD_VAL1_S 15 7391 #define GLQF_FDSWAP_FV_WORD_VAL1_M BIT(15) 7392 #define GLQF_FDSWAP_FV_WORD_INDX2_S 16 7393 #define GLQF_FDSWAP_FV_WORD_INDX2_M MAKEMASK(0x1F, 16) 7394 #define GLQF_FDSWAP_FV_WORD_VAL2_S 23 7395 #define GLQF_FDSWAP_FV_WORD_VAL2_M BIT(23) 7396 #define GLQF_FDSWAP_FV_WORD_INDX3_S 24 7397 #define GLQF_FDSWAP_FV_WORD_INDX3_M MAKEMASK(0x1F, 24) 7398 #define GLQF_FDSWAP_FV_WORD_VAL3_S 31 7399 #define GLQF_FDSWAP_FV_WORD_VAL3_M BIT(31) 7400 #define GLQF_HINSET(_i, _j) (0x0040E000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...5 */ /* Reset Source: CORER */ 7401 #define GLQF_HINSET_MAX_INDEX 127 7402 #define GLQF_HINSET_FV_WORD_INDX0_S 0 7403 #define GLQF_HINSET_FV_WORD_INDX0_M MAKEMASK(0x1F, 0) 7404 #define GLQF_HINSET_FV_WORD_VAL0_S 7 7405 #define GLQF_HINSET_FV_WORD_VAL0_M BIT(7) 7406 #define GLQF_HINSET_FV_WORD_INDX1_S 8 7407 #define GLQF_HINSET_FV_WORD_INDX1_M MAKEMASK(0x1F, 8) 7408 #define GLQF_HINSET_FV_WORD_VAL1_S 15 7409 #define GLQF_HINSET_FV_WORD_VAL1_M BIT(15) 7410 #define GLQF_HINSET_FV_WORD_INDX2_S 16 7411 #define GLQF_HINSET_FV_WORD_INDX2_M MAKEMASK(0x1F, 16) 7412 #define GLQF_HINSET_FV_WORD_VAL2_S 23 7413 #define GLQF_HINSET_FV_WORD_VAL2_M BIT(23) 7414 #define GLQF_HINSET_FV_WORD_INDX3_S 24 7415 #define GLQF_HINSET_FV_WORD_INDX3_M MAKEMASK(0x1F, 24) 7416 #define GLQF_HINSET_FV_WORD_VAL3_S 31 7417 #define GLQF_HINSET_FV_WORD_VAL3_M BIT(31) 7418 #define GLQF_HKEY(_i) (0x00456000 + ((_i) * 4)) /* _i=0...12 */ /* Reset Source: CORER */ 7419 #define GLQF_HKEY_MAX_INDEX 12 7420 #define GLQF_HKEY_KEY_0_S 0 7421 #define GLQF_HKEY_KEY_0_M MAKEMASK(0xFF, 0) 7422 #define GLQF_HKEY_KEY_1_S 8 7423 #define GLQF_HKEY_KEY_1_M MAKEMASK(0xFF, 8) 7424 #define GLQF_HKEY_KEY_2_S 16 7425 #define GLQF_HKEY_KEY_2_M MAKEMASK(0xFF, 16) 7426 #define GLQF_HKEY_KEY_3_S 24 7427 #define GLQF_HKEY_KEY_3_M MAKEMASK(0xFF, 24) 7428 #define GLQF_HLUT(_i, _j) (0x00438000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...15 */ /* Reset Source: CORER */ 7429 #define GLQF_HLUT_MAX_INDEX 127 7430 #define GLQF_HLUT_LUT0_S 0 7431 #define GLQF_HLUT_LUT0_M MAKEMASK(0x3F, 0) 7432 #define GLQF_HLUT_LUT1_S 8 7433 #define GLQF_HLUT_LUT1_M MAKEMASK(0x3F, 8) 7434 #define GLQF_HLUT_LUT2_S 16 7435 #define GLQF_HLUT_LUT2_M MAKEMASK(0x3F, 16) 7436 #define GLQF_HLUT_LUT3_S 24 7437 #define GLQF_HLUT_LUT3_M MAKEMASK(0x3F, 24) 7438 #define GLQF_HLUT_SIZE(_i) (0x00455400 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 7439 #define GLQF_HLUT_SIZE_MAX_INDEX 15 7440 #define GLQF_HLUT_SIZE_HSIZE_S 0 7441 #define GLQF_HLUT_SIZE_HSIZE_M BIT(0) 7442 #define GLQF_HMASK(_i) (0x0040FC00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 7443 #define GLQF_HMASK_MAX_INDEX 31 7444 #define GLQF_HMASK_MSK_INDEX_S 0 7445 #define GLQF_HMASK_MSK_INDEX_M MAKEMASK(0x1F, 0) 7446 #define GLQF_HMASK_MASK_S 16 7447 #define GLQF_HMASK_MASK_M MAKEMASK(0xFFFF, 16) 7448 #define GLQF_HMASK_SEL(_i) (0x00410000 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 7449 #define GLQF_HMASK_SEL_MAX_INDEX 127 7450 #define GLQF_HMASK_SEL_MASK_SEL_S 0 7451 #define GLQF_HMASK_SEL_MASK_SEL_M MAKEMASK(0xFFFFFFFF, 0) 7452 #define GLQF_HSYMM(_i, _j) (0x0040F000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...5 */ /* Reset Source: CORER */ 7453 #define GLQF_HSYMM_MAX_INDEX 127 7454 #define GLQF_HSYMM_FV_SYMM_INDX0_S 0 7455 #define GLQF_HSYMM_FV_SYMM_INDX0_M MAKEMASK(0x1F, 0) 7456 #define GLQF_HSYMM_SYMM0_ENA_S 7 7457 #define GLQF_HSYMM_SYMM0_ENA_M BIT(7) 7458 #define GLQF_HSYMM_FV_SYMM_INDX1_S 8 7459 #define GLQF_HSYMM_FV_SYMM_INDX1_M MAKEMASK(0x1F, 8) 7460 #define GLQF_HSYMM_SYMM1_ENA_S 15 7461 #define GLQF_HSYMM_SYMM1_ENA_M BIT(15) 7462 #define GLQF_HSYMM_FV_SYMM_INDX2_S 16 7463 #define GLQF_HSYMM_FV_SYMM_INDX2_M MAKEMASK(0x1F, 16) 7464 #define GLQF_HSYMM_SYMM2_ENA_S 23 7465 #define GLQF_HSYMM_SYMM2_ENA_M BIT(23) 7466 #define GLQF_HSYMM_FV_SYMM_INDX3_S 24 7467 #define GLQF_HSYMM_FV_SYMM_INDX3_M MAKEMASK(0x1F, 24) 7468 #define GLQF_HSYMM_SYMM3_ENA_S 31 7469 #define GLQF_HSYMM_SYMM3_ENA_M BIT(31) 7470 #define GLQF_PE_APBVT_CNT 0x00455500 /* Reset Source: CORER */ 7471 #define GLQF_PE_APBVT_CNT_APBVT_LAN_S 0 7472 #define GLQF_PE_APBVT_CNT_APBVT_LAN_M MAKEMASK(0xFFFFFFFF, 0) 7473 #define GLQF_PE_CMD 0x00471080 /* Reset Source: CORER */ 7474 #define GLQF_PE_CMD_ADDREM_STS_S 0 7475 #define GLQF_PE_CMD_ADDREM_STS_M MAKEMASK(0xFFFFFF, 0) 7476 #define GLQF_PE_CMD_ADDREM_ID_S 28 7477 #define GLQF_PE_CMD_ADDREM_ID_M MAKEMASK(0xF, 28) 7478 #define GLQF_PE_CTL 0x004710C0 /* Reset Source: CORER */ 7479 #define GLQF_PE_CTL_PELONG_S 0 7480 #define GLQF_PE_CTL_PELONG_M MAKEMASK(0xF, 0) 7481 #define GLQF_PE_CTL2(_i) (0x00455200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 7482 #define GLQF_PE_CTL2_MAX_INDEX 31 7483 #define GLQF_PE_CTL2_TO_QH_S 0 7484 #define GLQF_PE_CTL2_TO_QH_M MAKEMASK(0x3, 0) 7485 #define GLQF_PE_CTL2_APBVT_ENA_S 2 7486 #define GLQF_PE_CTL2_APBVT_ENA_M BIT(2) 7487 #define GLQF_PE_FVE 0x0020E514 /* Reset Source: CORER */ 7488 #define GLQF_PE_FVE_W_ENA_S 0 7489 #define GLQF_PE_FVE_W_ENA_M MAKEMASK(0xFFFFFF, 0) 7490 #define GLQF_PE_OSR_STS 0x00471040 /* Reset Source: CORER */ 7491 #define GLQF_PE_OSR_STS_QH_SRCH_MAXOSR_S 0 7492 #define GLQF_PE_OSR_STS_QH_SRCH_MAXOSR_M MAKEMASK(0x3FF, 0) 7493 #define GLQF_PE_OSR_STS_QH_CMD_MAXOSR_S 16 7494 #define GLQF_PE_OSR_STS_QH_CMD_MAXOSR_M MAKEMASK(0x3FF, 16) 7495 #define GLQF_PEINSET(_i, _j) (0x00415000 + ((_i) * 4 + (_j) * 128)) /* _i=0...31, _j=0...5 */ /* Reset Source: CORER */ 7496 #define GLQF_PEINSET_MAX_INDEX 31 7497 #define GLQF_PEINSET_FV_WORD_INDX0_S 0 7498 #define GLQF_PEINSET_FV_WORD_INDX0_M MAKEMASK(0x1F, 0) 7499 #define GLQF_PEINSET_FV_WORD_VAL0_S 7 7500 #define GLQF_PEINSET_FV_WORD_VAL0_M BIT(7) 7501 #define GLQF_PEINSET_FV_WORD_INDX1_S 8 7502 #define GLQF_PEINSET_FV_WORD_INDX1_M MAKEMASK(0x1F, 8) 7503 #define GLQF_PEINSET_FV_WORD_VAL1_S 15 7504 #define GLQF_PEINSET_FV_WORD_VAL1_M BIT(15) 7505 #define GLQF_PEINSET_FV_WORD_INDX2_S 16 7506 #define GLQF_PEINSET_FV_WORD_INDX2_M MAKEMASK(0x1F, 16) 7507 #define GLQF_PEINSET_FV_WORD_VAL2_S 23 7508 #define GLQF_PEINSET_FV_WORD_VAL2_M BIT(23) 7509 #define GLQF_PEINSET_FV_WORD_INDX3_S 24 7510 #define GLQF_PEINSET_FV_WORD_INDX3_M MAKEMASK(0x1F, 24) 7511 #define GLQF_PEINSET_FV_WORD_VAL3_S 31 7512 #define GLQF_PEINSET_FV_WORD_VAL3_M BIT(31) 7513 #define GLQF_PEMASK(_i) (0x00415400 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 7514 #define GLQF_PEMASK_MAX_INDEX 15 7515 #define GLQF_PEMASK_MSK_INDEX_S 0 7516 #define GLQF_PEMASK_MSK_INDEX_M MAKEMASK(0x1F, 0) 7517 #define GLQF_PEMASK_MASK_S 16 7518 #define GLQF_PEMASK_MASK_M MAKEMASK(0xFFFF, 16) 7519 #define GLQF_PEMASK_SEL(_i) (0x00415500 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 7520 #define GLQF_PEMASK_SEL_MAX_INDEX 31 7521 #define GLQF_PEMASK_SEL_MASK_SEL_S 0 7522 #define GLQF_PEMASK_SEL_MASK_SEL_M MAKEMASK(0xFFFF, 0) 7523 #define GLQF_PETABLE_CLR(_i) (0x000AA078 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 7524 #define GLQF_PETABLE_CLR_MAX_INDEX 1 7525 #define GLQF_PETABLE_CLR_VM_VF_NUM_S 0 7526 #define GLQF_PETABLE_CLR_VM_VF_NUM_M MAKEMASK(0x3FF, 0) 7527 #define GLQF_PETABLE_CLR_VM_VF_TYPE_S 10 7528 #define GLQF_PETABLE_CLR_VM_VF_TYPE_M MAKEMASK(0x3, 10) 7529 #define GLQF_PETABLE_CLR_PF_NUM_S 12 7530 #define GLQF_PETABLE_CLR_PF_NUM_M MAKEMASK(0x7, 12) 7531 #define GLQF_PETABLE_CLR_PE_BUSY_S 16 7532 #define GLQF_PETABLE_CLR_PE_BUSY_M BIT(16) 7533 #define GLQF_PETABLE_CLR_PE_CLEAR_S 17 7534 #define GLQF_PETABLE_CLR_PE_CLEAR_M BIT(17) 7535 #define GLQF_PROF2TC(_i, _j) (0x0044D000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...3 */ /* Reset Source: CORER */ 7536 #define GLQF_PROF2TC_MAX_INDEX 127 7537 #define GLQF_PROF2TC_OVERRIDE_ENA_0_S 0 7538 #define GLQF_PROF2TC_OVERRIDE_ENA_0_M BIT(0) 7539 #define GLQF_PROF2TC_REGION_0_S 1 7540 #define GLQF_PROF2TC_REGION_0_M MAKEMASK(0x7, 1) 7541 #define GLQF_PROF2TC_OVERRIDE_ENA_1_S 4 7542 #define GLQF_PROF2TC_OVERRIDE_ENA_1_M BIT(4) 7543 #define GLQF_PROF2TC_REGION_1_S 5 7544 #define GLQF_PROF2TC_REGION_1_M MAKEMASK(0x7, 5) 7545 #define GLQF_PROF2TC_OVERRIDE_ENA_2_S 8 7546 #define GLQF_PROF2TC_OVERRIDE_ENA_2_M BIT(8) 7547 #define GLQF_PROF2TC_REGION_2_S 9 7548 #define GLQF_PROF2TC_REGION_2_M MAKEMASK(0x7, 9) 7549 #define GLQF_PROF2TC_OVERRIDE_ENA_3_S 12 7550 #define GLQF_PROF2TC_OVERRIDE_ENA_3_M BIT(12) 7551 #define GLQF_PROF2TC_REGION_3_S 13 7552 #define GLQF_PROF2TC_REGION_3_M MAKEMASK(0x7, 13) 7553 #define GLQF_PROF2TC_OVERRIDE_ENA_4_S 16 7554 #define GLQF_PROF2TC_OVERRIDE_ENA_4_M BIT(16) 7555 #define GLQF_PROF2TC_REGION_4_S 17 7556 #define GLQF_PROF2TC_REGION_4_M MAKEMASK(0x7, 17) 7557 #define GLQF_PROF2TC_OVERRIDE_ENA_5_S 20 7558 #define GLQF_PROF2TC_OVERRIDE_ENA_5_M BIT(20) 7559 #define GLQF_PROF2TC_REGION_5_S 21 7560 #define GLQF_PROF2TC_REGION_5_M MAKEMASK(0x7, 21) 7561 #define GLQF_PROF2TC_OVERRIDE_ENA_6_S 24 7562 #define GLQF_PROF2TC_OVERRIDE_ENA_6_M BIT(24) 7563 #define GLQF_PROF2TC_REGION_6_S 25 7564 #define GLQF_PROF2TC_REGION_6_M MAKEMASK(0x7, 25) 7565 #define GLQF_PROF2TC_OVERRIDE_ENA_7_S 28 7566 #define GLQF_PROF2TC_OVERRIDE_ENA_7_M BIT(28) 7567 #define GLQF_PROF2TC_REGION_7_S 29 7568 #define GLQF_PROF2TC_REGION_7_M MAKEMASK(0x7, 29) 7569 #define PFQF_FD_CNT 0x00460180 /* Reset Source: CORER */ 7570 #define PFQF_FD_CNT_FD_GCNT_S 0 7571 #define PFQF_FD_CNT_FD_GCNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PFQF_FD_CNT_FD_GCNT_M : E800_PFQF_FD_CNT_FD_GCNT_M) 7572 #define E800_PFQF_FD_CNT_FD_GCNT_M MAKEMASK(0x7FFF, 0) 7573 #define E830_PFQF_FD_CNT_FD_GCNT_M MAKEMASK(0xFFFF, 0) 7574 #define PFQF_FD_CNT_FD_BCNT_S 16 7575 #define PFQF_FD_CNT_FD_BCNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PFQF_FD_CNT_FD_BCNT_M : E800_PFQF_FD_CNT_FD_BCNT_M) 7576 #define E800_PFQF_FD_CNT_FD_BCNT_M MAKEMASK(0x7FFF, 16) 7577 #define E830_PFQF_FD_CNT_FD_BCNT_M MAKEMASK(0xFFFF, 16) 7578 #define PFQF_FD_ENA 0x0043A000 /* Reset Source: CORER */ 7579 #define PFQF_FD_ENA_FD_ENA_S 0 7580 #define PFQF_FD_ENA_FD_ENA_M BIT(0) 7581 #define PFQF_FD_SIZE 0x00460100 /* Reset Source: CORER */ 7582 #define PFQF_FD_SIZE_FD_GSIZE_S 0 7583 #define PFQF_FD_SIZE_FD_GSIZE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PFQF_FD_SIZE_FD_GSIZE_M : E800_PFQF_FD_SIZE_FD_GSIZE_M) 7584 #define E800_PFQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0x7FFF, 0) 7585 #define E830_PFQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0xFFFF, 0) 7586 #define PFQF_FD_SIZE_FD_BSIZE_S 16 7587 #define PFQF_FD_SIZE_FD_BSIZE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PFQF_FD_SIZE_FD_BSIZE_M : E800_PFQF_FD_SIZE_FD_BSIZE_M) 7588 #define E800_PFQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0x7FFF, 16) 7589 #define E830_PFQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0xFFFF, 16) 7590 #define PFQF_FD_SUBTRACT 0x00460200 /* Reset Source: CORER */ 7591 #define PFQF_FD_SUBTRACT_FD_GCNT_S 0 7592 #define PFQF_FD_SUBTRACT_FD_GCNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PFQF_FD_SUBTRACT_FD_GCNT_M : E800_PFQF_FD_SUBTRACT_FD_GCNT_M) 7593 #define E800_PFQF_FD_SUBTRACT_FD_GCNT_M MAKEMASK(0x7FFF, 0) 7594 #define E830_PFQF_FD_SUBTRACT_FD_GCNT_M MAKEMASK(0xFFFF, 0) 7595 #define PFQF_FD_SUBTRACT_FD_BCNT_S 16 7596 #define PFQF_FD_SUBTRACT_FD_BCNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PFQF_FD_SUBTRACT_FD_BCNT_M : E800_PFQF_FD_SUBTRACT_FD_BCNT_M) 7597 #define E800_PFQF_FD_SUBTRACT_FD_BCNT_M MAKEMASK(0x7FFF, 16) 7598 #define E830_PFQF_FD_SUBTRACT_FD_BCNT_M MAKEMASK(0xFFFF, 16) 7599 #define PFQF_HLUT(_i) (0x00430000 + ((_i) * 64)) /* _i=0...511 */ /* Reset Source: CORER */ 7600 #define PFQF_HLUT_MAX_INDEX 511 7601 #define PFQF_HLUT_LUT0_S 0 7602 #define PFQF_HLUT_LUT0_M MAKEMASK(0xFF, 0) 7603 #define PFQF_HLUT_LUT1_S 8 7604 #define PFQF_HLUT_LUT1_M MAKEMASK(0xFF, 8) 7605 #define PFQF_HLUT_LUT2_S 16 7606 #define PFQF_HLUT_LUT2_M MAKEMASK(0xFF, 16) 7607 #define PFQF_HLUT_LUT3_S 24 7608 #define PFQF_HLUT_LUT3_M MAKEMASK(0xFF, 24) 7609 #define PFQF_HLUT_SIZE 0x00455480 /* Reset Source: CORER */ 7610 #define PFQF_HLUT_SIZE_HSIZE_S 0 7611 #define PFQF_HLUT_SIZE_HSIZE_M MAKEMASK(0x3, 0) 7612 #define PFQF_PE_CLSN0 0x00470480 /* Reset Source: CORER */ 7613 #define PFQF_PE_CLSN0_HITSBCNT_S 0 7614 #define PFQF_PE_CLSN0_HITSBCNT_M MAKEMASK(0xFFFFFFFF, 0) 7615 #define PFQF_PE_CLSN1 0x00470500 /* Reset Source: CORER */ 7616 #define PFQF_PE_CLSN1_HITLBCNT_S 0 7617 #define PFQF_PE_CLSN1_HITLBCNT_M MAKEMASK(0xFFFFFFFF, 0) 7618 #define PFQF_PE_CTL1 0x00470000 /* Reset Source: CORER */ 7619 #define PFQF_PE_CTL1_PEHSIZE_S 0 7620 #define PFQF_PE_CTL1_PEHSIZE_M MAKEMASK(0xF, 0) 7621 #define PFQF_PE_CTL2 0x00470040 /* Reset Source: CORER */ 7622 #define PFQF_PE_CTL2_PEDSIZE_S 0 7623 #define PFQF_PE_CTL2_PEDSIZE_M MAKEMASK(0xF, 0) 7624 #define PFQF_PE_FILTERING_ENA 0x0043A080 /* Reset Source: CORER */ 7625 #define PFQF_PE_FILTERING_ENA_PE_ENA_S 0 7626 #define PFQF_PE_FILTERING_ENA_PE_ENA_M BIT(0) 7627 #define PFQF_PE_FLHD 0x00470100 /* Reset Source: CORER */ 7628 #define PFQF_PE_FLHD_FLHD_S 0 7629 #define PFQF_PE_FLHD_FLHD_M MAKEMASK(0xFFFFFF, 0) 7630 #define PFQF_PE_ST_CTL 0x00470400 /* Reset Source: CORER */ 7631 #define PFQF_PE_ST_CTL_PF_CNT_EN_S 0 7632 #define PFQF_PE_ST_CTL_PF_CNT_EN_M BIT(0) 7633 #define PFQF_PE_ST_CTL_VFS_CNT_EN_S 1 7634 #define PFQF_PE_ST_CTL_VFS_CNT_EN_M BIT(1) 7635 #define PFQF_PE_ST_CTL_VF_CNT_EN_S 2 7636 #define PFQF_PE_ST_CTL_VF_CNT_EN_M BIT(2) 7637 #define PFQF_PE_ST_CTL_VF_NUM_S 16 7638 #define PFQF_PE_ST_CTL_VF_NUM_M MAKEMASK(0xFF, 16) 7639 #define PFQF_PE_TC_CTL 0x00452080 /* Reset Source: CORER */ 7640 #define PFQF_PE_TC_CTL_TC_EN_PF_S 0 7641 #define PFQF_PE_TC_CTL_TC_EN_PF_M MAKEMASK(0xFF, 0) 7642 #define PFQF_PE_TC_CTL_TC_EN_VF_S 16 7643 #define PFQF_PE_TC_CTL_TC_EN_VF_M MAKEMASK(0xFF, 16) 7644 #define PFQF_PECNT_0 0x00470200 /* Reset Source: CORER */ 7645 #define PFQF_PECNT_0_BUCKETCNT_S 0 7646 #define PFQF_PECNT_0_BUCKETCNT_M MAKEMASK(0x3FFFF, 0) 7647 #define PFQF_PECNT_1 0x00470300 /* Reset Source: CORER */ 7648 #define PFQF_PECNT_1_FLTCNT_S 0 7649 #define PFQF_PECNT_1_FLTCNT_M MAKEMASK(0x3FFFF, 0) 7650 #define VPQF_PE_CTL1(_VF) (0x00474000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 7651 #define VPQF_PE_CTL1_MAX_INDEX 255 7652 #define VPQF_PE_CTL1_PEHSIZE_S 0 7653 #define VPQF_PE_CTL1_PEHSIZE_M MAKEMASK(0xF, 0) 7654 #define VPQF_PE_CTL2(_VF) (0x00474800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 7655 #define VPQF_PE_CTL2_MAX_INDEX 255 7656 #define VPQF_PE_CTL2_PEDSIZE_S 0 7657 #define VPQF_PE_CTL2_PEDSIZE_M MAKEMASK(0xF, 0) 7658 #define VPQF_PE_FILTERING_ENA(_VF) (0x00455800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 7659 #define VPQF_PE_FILTERING_ENA_MAX_INDEX 255 7660 #define VPQF_PE_FILTERING_ENA_PE_ENA_S 0 7661 #define VPQF_PE_FILTERING_ENA_PE_ENA_M BIT(0) 7662 #define VPQF_PE_FLHD(_VF) (0x00472000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 7663 #define VPQF_PE_FLHD_MAX_INDEX 255 7664 #define VPQF_PE_FLHD_FLHD_S 0 7665 #define VPQF_PE_FLHD_FLHD_M MAKEMASK(0xFFFFFF, 0) 7666 #define VPQF_PECNT_0(_VF) (0x00472800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 7667 #define VPQF_PECNT_0_MAX_INDEX 255 7668 #define VPQF_PECNT_0_BUCKETCNT_S 0 7669 #define VPQF_PECNT_0_BUCKETCNT_M MAKEMASK(0x3FFFF, 0) 7670 #define VPQF_PECNT_1(_VF) (0x00473000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 7671 #define VPQF_PECNT_1_MAX_INDEX 255 7672 #define VPQF_PECNT_1_FLTCNT_S 0 7673 #define VPQF_PECNT_1_FLTCNT_M MAKEMASK(0x3FFFF, 0) 7674 #define GLDCB_RMPMC 0x001223C8 /* Reset Source: CORER */ 7675 #define GLDCB_RMPMC_RSPM_S 0 7676 #define GLDCB_RMPMC_RSPM_M MAKEMASK(0x3F, 0) 7677 #define GLDCB_RMPMC_MIQ_NODROP_MODE_S 6 7678 #define GLDCB_RMPMC_MIQ_NODROP_MODE_M MAKEMASK(0x1F, 6) 7679 #define GLDCB_RMPMC_RPM_DIS_S 31 7680 #define GLDCB_RMPMC_RPM_DIS_M BIT(31) 7681 #define GLDCB_RMPMS 0x001223CC /* Reset Source: CORER */ 7682 #define GLDCB_RMPMS_RMPM_S 0 7683 #define GLDCB_RMPMS_RMPM_M MAKEMASK(0xFFFF, 0) 7684 #define GLDCB_RPCC 0x00122260 /* Reset Source: CORER */ 7685 #define GLDCB_RPCC_EN_S 0 7686 #define GLDCB_RPCC_EN_M BIT(0) 7687 #define GLDCB_RPCC_SCL_FACT_S 4 7688 #define GLDCB_RPCC_SCL_FACT_M MAKEMASK(0x1F, 4) 7689 #define GLDCB_RPCC_THRSH_S 16 7690 #define GLDCB_RPCC_THRSH_M MAKEMASK(0xFFF, 16) 7691 #define GLDCB_RSPMC 0x001223C4 /* Reset Source: CORER */ 7692 #define GLDCB_RSPMC_RSPM_S 0 7693 #define GLDCB_RSPMC_RSPM_M MAKEMASK(0xFF, 0) 7694 #define GLDCB_RSPMC_RPM_MODE_S 8 7695 #define GLDCB_RSPMC_RPM_MODE_M MAKEMASK(0x3, 8) 7696 #define GLDCB_RSPMC_PRR_MAX_EXP_S 10 7697 #define GLDCB_RSPMC_PRR_MAX_EXP_M MAKEMASK(0xF, 10) 7698 #define GLDCB_RSPMC_PFCTIMER_S 14 7699 #define GLDCB_RSPMC_PFCTIMER_M MAKEMASK(0x3FFF, 14) 7700 #define GLDCB_RSPMC_RPM_DIS_S 31 7701 #define GLDCB_RSPMC_RPM_DIS_M BIT(31) 7702 #define GLDCB_RSPMS 0x001223C0 /* Reset Source: CORER */ 7703 #define GLDCB_RSPMS_RSPM_S 0 7704 #define GLDCB_RSPMS_RSPM_M MAKEMASK(0x3FFFF, 0) 7705 #define GLDCB_RTCTI 0x001223D0 /* Reset Source: CORER */ 7706 #define GLDCB_RTCTI_PFCTIMEOUT_TC_S 0 7707 #define GLDCB_RTCTI_PFCTIMEOUT_TC_M MAKEMASK(0xFFFFFFFF, 0) 7708 #define GLDCB_RTCTQ(_i) (0x001222C0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 7709 #define GLDCB_RTCTQ_MAX_INDEX 31 7710 #define GLDCB_RTCTQ_RXQNUM_S 0 7711 #define GLDCB_RTCTQ_RXQNUM_M MAKEMASK(0x7FF, 0) 7712 #define GLDCB_RTCTQ_IS_PF_Q_S 16 7713 #define GLDCB_RTCTQ_IS_PF_Q_M BIT(16) 7714 #define GLDCB_RTCTS(_i) (0x00122340 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 7715 #define GLDCB_RTCTS_MAX_INDEX 31 7716 #define GLDCB_RTCTS_PFCTIMER_S 0 7717 #define GLDCB_RTCTS_PFCTIMER_M MAKEMASK(0x3FFF, 0) 7718 #define GLRCB_CFG_COTF_CNT(_i) (0x001223D4 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 7719 #define GLRCB_CFG_COTF_CNT_MAX_INDEX 7 7720 #define GLRCB_CFG_COTF_CNT_MRKR_COTF_CNT_S 0 7721 #define GLRCB_CFG_COTF_CNT_MRKR_COTF_CNT_M MAKEMASK(0x3F, 0) 7722 #define GLRCB_CFG_COTF_ST 0x001223F4 /* Reset Source: CORER */ 7723 #define GLRCB_CFG_COTF_ST_MRKR_COTF_ST_S 0 7724 #define GLRCB_CFG_COTF_ST_MRKR_COTF_ST_M MAKEMASK(0xFF, 0) 7725 #define GLRPRS_PMCFG_DHW(_i) (0x00200388 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 7726 #define GLRPRS_PMCFG_DHW_MAX_INDEX 15 7727 #define GLRPRS_PMCFG_DHW_DHW_S 0 7728 #define GLRPRS_PMCFG_DHW_DHW_M MAKEMASK(0xFFFFF, 0) 7729 #define GLRPRS_PMCFG_DLW(_i) (0x002003C8 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 7730 #define GLRPRS_PMCFG_DLW_MAX_INDEX 15 7731 #define GLRPRS_PMCFG_DLW_DLW_S 0 7732 #define GLRPRS_PMCFG_DLW_DLW_M MAKEMASK(0xFFFFF, 0) 7733 #define GLRPRS_PMCFG_DPS(_i) (0x00200308 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ 7734 #define GLRPRS_PMCFG_DPS_MAX_INDEX 15 7735 #define GLRPRS_PMCFG_DPS_DPS_S 0 7736 #define GLRPRS_PMCFG_DPS_DPS_M MAKEMASK(0xFFFFF, 0) 7737 #define GLRPRS_PMCFG_SHW(_i) (0x00200448 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 7738 #define GLRPRS_PMCFG_SHW_MAX_INDEX 7 7739 #define GLRPRS_PMCFG_SHW_SHW_S 0 7740 #define GLRPRS_PMCFG_SHW_SHW_M MAKEMASK(0xFFFFF, 0) 7741 #define GLRPRS_PMCFG_SLW(_i) (0x00200468 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 7742 #define GLRPRS_PMCFG_SLW_MAX_INDEX 7 7743 #define GLRPRS_PMCFG_SLW_SLW_S 0 7744 #define GLRPRS_PMCFG_SLW_SLW_M MAKEMASK(0xFFFFF, 0) 7745 #define GLRPRS_PMCFG_SPS(_i) (0x00200408 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 7746 #define GLRPRS_PMCFG_SPS_MAX_INDEX 7 7747 #define GLRPRS_PMCFG_SPS_SPS_S 0 7748 #define GLRPRS_PMCFG_SPS_SPS_M MAKEMASK(0xFFFFF, 0) 7749 #define GLRPRS_PMCFG_TC_CFG(_i) (0x00200488 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 7750 #define GLRPRS_PMCFG_TC_CFG_MAX_INDEX 31 7751 #define GLRPRS_PMCFG_TC_CFG_D_POOL_S 0 7752 #define GLRPRS_PMCFG_TC_CFG_D_POOL_M MAKEMASK(0xF, 0) 7753 #define GLRPRS_PMCFG_TC_CFG_S_POOL_S 16 7754 #define GLRPRS_PMCFG_TC_CFG_S_POOL_M MAKEMASK(0x7, 16) 7755 #define GLRPRS_PMCFG_TCHW(_i) (0x00200588 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 7756 #define GLRPRS_PMCFG_TCHW_MAX_INDEX 31 7757 #define GLRPRS_PMCFG_TCHW_TCHW_S 0 7758 #define GLRPRS_PMCFG_TCHW_TCHW_M MAKEMASK(0xFFFFF, 0) 7759 #define GLRPRS_PMCFG_TCLW(_i) (0x00200608 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 7760 #define GLRPRS_PMCFG_TCLW_MAX_INDEX 31 7761 #define GLRPRS_PMCFG_TCLW_TCLW_S 0 7762 #define GLRPRS_PMCFG_TCLW_TCLW_M MAKEMASK(0xFFFFF, 0) 7763 #define GLSWT_PMCFG_TC_CFG(_i) (0x00204900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 7764 #define GLSWT_PMCFG_TC_CFG_MAX_INDEX 31 7765 #define GLSWT_PMCFG_TC_CFG_D_POOL_S 0 7766 #define GLSWT_PMCFG_TC_CFG_D_POOL_M MAKEMASK(0xF, 0) 7767 #define GLSWT_PMCFG_TC_CFG_S_POOL_S 16 7768 #define GLSWT_PMCFG_TC_CFG_S_POOL_M MAKEMASK(0x7, 16) 7769 #define PRTDCB_RLANPMS 0x00122280 /* Reset Source: CORER */ 7770 #define PRTDCB_RLANPMS_LANRPPM_S 0 7771 #define PRTDCB_RLANPMS_LANRPPM_M MAKEMASK(0x3FFFF, 0) 7772 #define PRTDCB_RPPMC 0x00122240 /* Reset Source: CORER */ 7773 #define PRTDCB_RPPMC_LANRPPM_S 0 7774 #define PRTDCB_RPPMC_LANRPPM_M MAKEMASK(0xFF, 0) 7775 #define PRTDCB_RPPMC_RDMARPPM_S 8 7776 #define PRTDCB_RPPMC_RDMARPPM_M MAKEMASK(0xFF, 8) 7777 #define PRTDCB_RRDMAPMS 0x00122120 /* Reset Source: CORER */ 7778 #define PRTDCB_RRDMAPMS_RDMARPPM_S 0 7779 #define PRTDCB_RRDMAPMS_RDMARPPM_M MAKEMASK(0x3FFFF, 0) 7780 #define GL_STAT_SWR_BPCH(_i) (0x00347804 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 7781 #define GL_STAT_SWR_BPCH_MAX_INDEX 127 7782 #define GL_STAT_SWR_BPCH_VLBPCH_S 0 7783 #define GL_STAT_SWR_BPCH_VLBPCH_M MAKEMASK(0xFF, 0) 7784 #define GL_STAT_SWR_BPCL(_i) (0x00347800 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 7785 #define GL_STAT_SWR_BPCL_MAX_INDEX 127 7786 #define GL_STAT_SWR_BPCL_VLBPCL_S 0 7787 #define GL_STAT_SWR_BPCL_VLBPCL_M MAKEMASK(0xFFFFFFFF, 0) 7788 #define GL_STAT_SWR_GORCH(_i) (0x00342004 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 7789 #define GL_STAT_SWR_GORCH_MAX_INDEX 127 7790 #define GL_STAT_SWR_GORCH_VLBCH_S 0 7791 #define GL_STAT_SWR_GORCH_VLBCH_M MAKEMASK(0xFF, 0) 7792 #define GL_STAT_SWR_GORCL(_i) (0x00342000 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 7793 #define GL_STAT_SWR_GORCL_MAX_INDEX 127 7794 #define GL_STAT_SWR_GORCL_VLBCL_S 0 7795 #define GL_STAT_SWR_GORCL_VLBCL_M MAKEMASK(0xFFFFFFFF, 0) 7796 #define GL_STAT_SWR_GOTCH(_i) (0x00304004 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 7797 #define GL_STAT_SWR_GOTCH_MAX_INDEX 127 7798 #define GL_STAT_SWR_GOTCH_VLBCH_S 0 7799 #define GL_STAT_SWR_GOTCH_VLBCH_M MAKEMASK(0xFF, 0) 7800 #define GL_STAT_SWR_GOTCL(_i) (0x00304000 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 7801 #define GL_STAT_SWR_GOTCL_MAX_INDEX 127 7802 #define GL_STAT_SWR_GOTCL_VLBCL_S 0 7803 #define GL_STAT_SWR_GOTCL_VLBCL_M MAKEMASK(0xFFFFFFFF, 0) 7804 #define GL_STAT_SWR_MPCH(_i) (0x00347404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 7805 #define GL_STAT_SWR_MPCH_MAX_INDEX 127 7806 #define GL_STAT_SWR_MPCH_VLMPCH_S 0 7807 #define GL_STAT_SWR_MPCH_VLMPCH_M MAKEMASK(0xFF, 0) 7808 #define GL_STAT_SWR_MPCL(_i) (0x00347400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 7809 #define GL_STAT_SWR_MPCL_MAX_INDEX 127 7810 #define GL_STAT_SWR_MPCL_VLMPCL_S 0 7811 #define GL_STAT_SWR_MPCL_VLMPCL_M MAKEMASK(0xFFFFFFFF, 0) 7812 #define GL_STAT_SWR_UPCH(_i) (0x00347004 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 7813 #define GL_STAT_SWR_UPCH_MAX_INDEX 127 7814 #define GL_STAT_SWR_UPCH_VLUPCH_S 0 7815 #define GL_STAT_SWR_UPCH_VLUPCH_M MAKEMASK(0xFF, 0) 7816 #define GL_STAT_SWR_UPCL(_i) (0x00347000 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 7817 #define GL_STAT_SWR_UPCL_MAX_INDEX 127 7818 #define GL_STAT_SWR_UPCL_VLUPCL_S 0 7819 #define GL_STAT_SWR_UPCL_VLUPCL_M MAKEMASK(0xFFFFFFFF, 0) 7820 #define GLPRT_AORCL(_i) (0x003812C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7821 #define GLPRT_AORCL_MAX_INDEX 7 7822 #define GLPRT_AORCL_AORCL_S 0 7823 #define GLPRT_AORCL_AORCL_M MAKEMASK(0xFFFFFFFF, 0) 7824 #define GLPRT_BPRCH(_i) (0x00381384 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7825 #define GLPRT_BPRCH_MAX_INDEX 7 7826 #define E800_GLPRT_BPRCH_UPRCH_S 0 7827 #define E800_GLPRT_BPRCH_UPRCH_M MAKEMASK(0xFF, 0) 7828 #define GLPRT_BPRCL(_i) (0x00381380 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7829 #define GLPRT_BPRCL_MAX_INDEX 7 7830 #define E800_GLPRT_BPRCL_UPRCH_S 0 7831 #define E800_GLPRT_BPRCL_UPRCH_M MAKEMASK(0xFFFFFFFF, 0) 7832 #define GLPRT_BPTCH(_i) (0x00381244 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7833 #define GLPRT_BPTCH_MAX_INDEX 7 7834 #define E800_GLPRT_BPTCH_UPRCH_S 0 7835 #define E800_GLPRT_BPTCH_UPRCH_M MAKEMASK(0xFF, 0) 7836 #define GLPRT_BPTCL(_i) (0x00381240 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7837 #define GLPRT_BPTCL_MAX_INDEX 7 7838 #define E800_GLPRT_BPTCL_UPRCH_S 0 7839 #define E800_GLPRT_BPTCL_UPRCH_M MAKEMASK(0xFFFFFFFF, 0) 7840 #define GLPRT_CRCERRS(_i) (0x00380100 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7841 #define GLPRT_CRCERRS_MAX_INDEX 7 7842 #define GLPRT_CRCERRS_CRCERRS_S 0 7843 #define GLPRT_CRCERRS_CRCERRS_M MAKEMASK(0xFFFFFFFF, 0) 7844 #define GLPRT_CRCERRS_H(_i) (0x00380104 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7845 #define GLPRT_CRCERRS_H_MAX_INDEX 7 7846 #define GLPRT_CRCERRS_H_CRCERRS_S 0 7847 #define GLPRT_CRCERRS_H_CRCERRS_M MAKEMASK(0xFFFFFFFF, 0) 7848 #define GLPRT_GORCH(_i) (0x00380004 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7849 #define GLPRT_GORCH_MAX_INDEX 7 7850 #define GLPRT_GORCH_GORCH_S 0 7851 #define GLPRT_GORCH_GORCH_M MAKEMASK(0xFF, 0) 7852 #define GLPRT_GORCL(_i) (0x00380000 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7853 #define GLPRT_GORCL_MAX_INDEX 7 7854 #define GLPRT_GORCL_GORCL_S 0 7855 #define GLPRT_GORCL_GORCL_M MAKEMASK(0xFFFFFFFF, 0) 7856 #define GLPRT_GOTCH(_i) (0x00380B44 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7857 #define GLPRT_GOTCH_MAX_INDEX 7 7858 #define GLPRT_GOTCH_GOTCH_S 0 7859 #define GLPRT_GOTCH_GOTCH_M MAKEMASK(0xFF, 0) 7860 #define GLPRT_GOTCL(_i) (0x00380B40 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7861 #define GLPRT_GOTCL_MAX_INDEX 7 7862 #define GLPRT_GOTCL_GOTCL_S 0 7863 #define GLPRT_GOTCL_GOTCL_M MAKEMASK(0xFFFFFFFF, 0) 7864 #define GLPRT_ILLERRC(_i) (0x003801C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7865 #define GLPRT_ILLERRC_MAX_INDEX 7 7866 #define GLPRT_ILLERRC_ILLERRC_S 0 7867 #define GLPRT_ILLERRC_ILLERRC_M MAKEMASK(0xFFFFFFFF, 0) 7868 #define GLPRT_ILLERRC_H(_i) (0x003801C4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7869 #define GLPRT_ILLERRC_H_MAX_INDEX 7 7870 #define GLPRT_ILLERRC_H_ILLERRC_S 0 7871 #define GLPRT_ILLERRC_H_ILLERRC_M MAKEMASK(0xFFFFFFFF, 0) 7872 #define GLPRT_LXOFFRXC(_i) (0x003802C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7873 #define GLPRT_LXOFFRXC_MAX_INDEX 7 7874 #define GLPRT_LXOFFRXC_LXOFFRXCNT_S 0 7875 #define GLPRT_LXOFFRXC_LXOFFRXCNT_M MAKEMASK(0xFFFFFFFF, 0) 7876 #define GLPRT_LXOFFRXC_H(_i) (0x003802C4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7877 #define GLPRT_LXOFFRXC_H_MAX_INDEX 7 7878 #define GLPRT_LXOFFRXC_H_LXOFFRXCNT_S 0 7879 #define GLPRT_LXOFFRXC_H_LXOFFRXCNT_M MAKEMASK(0xFFFFFFFF, 0) 7880 #define GLPRT_LXOFFTXC(_i) (0x00381180 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7881 #define GLPRT_LXOFFTXC_MAX_INDEX 7 7882 #define GLPRT_LXOFFTXC_LXOFFTXC_S 0 7883 #define GLPRT_LXOFFTXC_LXOFFTXC_M MAKEMASK(0xFFFFFFFF, 0) 7884 #define GLPRT_LXOFFTXC_H(_i) (0x00381184 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7885 #define GLPRT_LXOFFTXC_H_MAX_INDEX 7 7886 #define GLPRT_LXOFFTXC_H_LXOFFTXC_S 0 7887 #define GLPRT_LXOFFTXC_H_LXOFFTXC_M MAKEMASK(0xFFFFFFFF, 0) 7888 #define GLPRT_LXONRXC(_i) (0x00380280 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7889 #define GLPRT_LXONRXC_MAX_INDEX 7 7890 #define GLPRT_LXONRXC_LXONRXCNT_S 0 7891 #define GLPRT_LXONRXC_LXONRXCNT_M MAKEMASK(0xFFFFFFFF, 0) 7892 #define GLPRT_LXONRXC_H(_i) (0x00380284 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7893 #define GLPRT_LXONRXC_H_MAX_INDEX 7 7894 #define GLPRT_LXONRXC_H_LXONRXCNT_S 0 7895 #define GLPRT_LXONRXC_H_LXONRXCNT_M MAKEMASK(0xFFFFFFFF, 0) 7896 #define GLPRT_LXONTXC(_i) (0x00381140 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7897 #define GLPRT_LXONTXC_MAX_INDEX 7 7898 #define GLPRT_LXONTXC_LXONTXC_S 0 7899 #define GLPRT_LXONTXC_LXONTXC_M MAKEMASK(0xFFFFFFFF, 0) 7900 #define GLPRT_LXONTXC_H(_i) (0x00381144 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7901 #define GLPRT_LXONTXC_H_MAX_INDEX 7 7902 #define GLPRT_LXONTXC_H_LXONTXC_S 0 7903 #define GLPRT_LXONTXC_H_LXONTXC_M MAKEMASK(0xFFFFFFFF, 0) 7904 #define GLPRT_MLFC(_i) (0x00380040 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7905 #define GLPRT_MLFC_MAX_INDEX 7 7906 #define GLPRT_MLFC_MLFC_S 0 7907 #define GLPRT_MLFC_MLFC_M MAKEMASK(0xFFFFFFFF, 0) 7908 #define GLPRT_MLFC_H(_i) (0x00380044 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7909 #define GLPRT_MLFC_H_MAX_INDEX 7 7910 #define GLPRT_MLFC_H_MLFC_S 0 7911 #define GLPRT_MLFC_H_MLFC_M MAKEMASK(0xFFFFFFFF, 0) 7912 #define GLPRT_MPRCH(_i) (0x00381344 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7913 #define GLPRT_MPRCH_MAX_INDEX 7 7914 #define GLPRT_MPRCH_MPRCH_S 0 7915 #define GLPRT_MPRCH_MPRCH_M MAKEMASK(0xFF, 0) 7916 #define GLPRT_MPRCL(_i) (0x00381340 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7917 #define GLPRT_MPRCL_MAX_INDEX 7 7918 #define GLPRT_MPRCL_MPRCL_S 0 7919 #define GLPRT_MPRCL_MPRCL_M MAKEMASK(0xFFFFFFFF, 0) 7920 #define GLPRT_MPTCH(_i) (0x00381204 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7921 #define GLPRT_MPTCH_MAX_INDEX 7 7922 #define GLPRT_MPTCH_MPTCH_S 0 7923 #define GLPRT_MPTCH_MPTCH_M MAKEMASK(0xFF, 0) 7924 #define GLPRT_MPTCL(_i) (0x00381200 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7925 #define GLPRT_MPTCL_MAX_INDEX 7 7926 #define GLPRT_MPTCL_MPTCL_S 0 7927 #define GLPRT_MPTCL_MPTCL_M MAKEMASK(0xFFFFFFFF, 0) 7928 #define GLPRT_MRFC(_i) (0x00380080 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7929 #define GLPRT_MRFC_MAX_INDEX 7 7930 #define GLPRT_MRFC_MRFC_S 0 7931 #define GLPRT_MRFC_MRFC_M MAKEMASK(0xFFFFFFFF, 0) 7932 #define GLPRT_MRFC_H(_i) (0x00380084 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7933 #define GLPRT_MRFC_H_MAX_INDEX 7 7934 #define GLPRT_MRFC_H_MRFC_S 0 7935 #define GLPRT_MRFC_H_MRFC_M MAKEMASK(0xFFFFFFFF, 0) 7936 #define GLPRT_PRC1023H(_i) (0x00380A04 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7937 #define GLPRT_PRC1023H_MAX_INDEX 7 7938 #define GLPRT_PRC1023H_PRC1023H_S 0 7939 #define GLPRT_PRC1023H_PRC1023H_M MAKEMASK(0xFF, 0) 7940 #define GLPRT_PRC1023L(_i) (0x00380A00 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7941 #define GLPRT_PRC1023L_MAX_INDEX 7 7942 #define GLPRT_PRC1023L_PRC1023L_S 0 7943 #define GLPRT_PRC1023L_PRC1023L_M MAKEMASK(0xFFFFFFFF, 0) 7944 #define GLPRT_PRC127H(_i) (0x00380944 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7945 #define GLPRT_PRC127H_MAX_INDEX 7 7946 #define GLPRT_PRC127H_PRC127H_S 0 7947 #define GLPRT_PRC127H_PRC127H_M MAKEMASK(0xFF, 0) 7948 #define GLPRT_PRC127L(_i) (0x00380940 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7949 #define GLPRT_PRC127L_MAX_INDEX 7 7950 #define GLPRT_PRC127L_PRC127L_S 0 7951 #define GLPRT_PRC127L_PRC127L_M MAKEMASK(0xFFFFFFFF, 0) 7952 #define GLPRT_PRC1522H(_i) (0x00380A44 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7953 #define GLPRT_PRC1522H_MAX_INDEX 7 7954 #define GLPRT_PRC1522H_PRC1522H_S 0 7955 #define GLPRT_PRC1522H_PRC1522H_M MAKEMASK(0xFF, 0) 7956 #define GLPRT_PRC1522L(_i) (0x00380A40 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7957 #define GLPRT_PRC1522L_MAX_INDEX 7 7958 #define GLPRT_PRC1522L_PRC1522L_S 0 7959 #define GLPRT_PRC1522L_PRC1522L_M MAKEMASK(0xFFFFFFFF, 0) 7960 #define GLPRT_PRC255H(_i) (0x00380984 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7961 #define GLPRT_PRC255H_MAX_INDEX 7 7962 #define GLPRT_PRC255H_PRTPRC255H_S 0 7963 #define GLPRT_PRC255H_PRTPRC255H_M MAKEMASK(0xFF, 0) 7964 #define GLPRT_PRC255L(_i) (0x00380980 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7965 #define GLPRT_PRC255L_MAX_INDEX 7 7966 #define GLPRT_PRC255L_PRC255L_S 0 7967 #define GLPRT_PRC255L_PRC255L_M MAKEMASK(0xFFFFFFFF, 0) 7968 #define GLPRT_PRC511H(_i) (0x003809C4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7969 #define GLPRT_PRC511H_MAX_INDEX 7 7970 #define GLPRT_PRC511H_PRC511H_S 0 7971 #define GLPRT_PRC511H_PRC511H_M MAKEMASK(0xFF, 0) 7972 #define GLPRT_PRC511L(_i) (0x003809C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7973 #define GLPRT_PRC511L_MAX_INDEX 7 7974 #define GLPRT_PRC511L_PRC511L_S 0 7975 #define GLPRT_PRC511L_PRC511L_M MAKEMASK(0xFFFFFFFF, 0) 7976 #define GLPRT_PRC64H(_i) (0x00380904 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7977 #define GLPRT_PRC64H_MAX_INDEX 7 7978 #define GLPRT_PRC64H_PRC64H_S 0 7979 #define GLPRT_PRC64H_PRC64H_M MAKEMASK(0xFF, 0) 7980 #define GLPRT_PRC64L(_i) (0x00380900 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7981 #define GLPRT_PRC64L_MAX_INDEX 7 7982 #define GLPRT_PRC64L_PRC64L_S 0 7983 #define GLPRT_PRC64L_PRC64L_M MAKEMASK(0xFFFFFFFF, 0) 7984 #define GLPRT_PRC9522H(_i) (0x00380A84 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7985 #define GLPRT_PRC9522H_MAX_INDEX 7 7986 #define GLPRT_PRC9522H_PRC1522H_S 0 7987 #define GLPRT_PRC9522H_PRC1522H_M MAKEMASK(0xFF, 0) 7988 #define GLPRT_PRC9522L(_i) (0x00380A80 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7989 #define GLPRT_PRC9522L_MAX_INDEX 7 7990 #define GLPRT_PRC9522L_PRC1522L_S 0 7991 #define GLPRT_PRC9522L_PRC1522L_M MAKEMASK(0xFFFFFFFF, 0) 7992 #define GLPRT_PTC1023H(_i) (0x00380C84 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7993 #define GLPRT_PTC1023H_MAX_INDEX 7 7994 #define GLPRT_PTC1023H_PTC1023H_S 0 7995 #define GLPRT_PTC1023H_PTC1023H_M MAKEMASK(0xFF, 0) 7996 #define GLPRT_PTC1023L(_i) (0x00380C80 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 7997 #define GLPRT_PTC1023L_MAX_INDEX 7 7998 #define GLPRT_PTC1023L_PTC1023L_S 0 7999 #define GLPRT_PTC1023L_PTC1023L_M MAKEMASK(0xFFFFFFFF, 0) 8000 #define GLPRT_PTC127H(_i) (0x00380BC4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8001 #define GLPRT_PTC127H_MAX_INDEX 7 8002 #define GLPRT_PTC127H_PTC127H_S 0 8003 #define GLPRT_PTC127H_PTC127H_M MAKEMASK(0xFF, 0) 8004 #define GLPRT_PTC127L(_i) (0x00380BC0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8005 #define GLPRT_PTC127L_MAX_INDEX 7 8006 #define GLPRT_PTC127L_PTC127L_S 0 8007 #define GLPRT_PTC127L_PTC127L_M MAKEMASK(0xFFFFFFFF, 0) 8008 #define GLPRT_PTC1522H(_i) (0x00380CC4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8009 #define GLPRT_PTC1522H_MAX_INDEX 7 8010 #define GLPRT_PTC1522H_PTC1522H_S 0 8011 #define GLPRT_PTC1522H_PTC1522H_M MAKEMASK(0xFF, 0) 8012 #define GLPRT_PTC1522L(_i) (0x00380CC0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8013 #define GLPRT_PTC1522L_MAX_INDEX 7 8014 #define GLPRT_PTC1522L_PTC1522L_S 0 8015 #define GLPRT_PTC1522L_PTC1522L_M MAKEMASK(0xFFFFFFFF, 0) 8016 #define GLPRT_PTC255H(_i) (0x00380C04 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8017 #define GLPRT_PTC255H_MAX_INDEX 7 8018 #define GLPRT_PTC255H_PTC255H_S 0 8019 #define GLPRT_PTC255H_PTC255H_M MAKEMASK(0xFF, 0) 8020 #define GLPRT_PTC255L(_i) (0x00380C00 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8021 #define GLPRT_PTC255L_MAX_INDEX 7 8022 #define GLPRT_PTC255L_PTC255L_S 0 8023 #define GLPRT_PTC255L_PTC255L_M MAKEMASK(0xFFFFFFFF, 0) 8024 #define GLPRT_PTC511H(_i) (0x00380C44 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8025 #define GLPRT_PTC511H_MAX_INDEX 7 8026 #define GLPRT_PTC511H_PTC511H_S 0 8027 #define GLPRT_PTC511H_PTC511H_M MAKEMASK(0xFF, 0) 8028 #define GLPRT_PTC511L(_i) (0x00380C40 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8029 #define GLPRT_PTC511L_MAX_INDEX 7 8030 #define GLPRT_PTC511L_PTC511L_S 0 8031 #define GLPRT_PTC511L_PTC511L_M MAKEMASK(0xFFFFFFFF, 0) 8032 #define GLPRT_PTC64H(_i) (0x00380B84 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8033 #define GLPRT_PTC64H_MAX_INDEX 7 8034 #define GLPRT_PTC64H_PTC64H_S 0 8035 #define GLPRT_PTC64H_PTC64H_M MAKEMASK(0xFF, 0) 8036 #define GLPRT_PTC64L(_i) (0x00380B80 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8037 #define GLPRT_PTC64L_MAX_INDEX 7 8038 #define GLPRT_PTC64L_PTC64L_S 0 8039 #define GLPRT_PTC64L_PTC64L_M MAKEMASK(0xFFFFFFFF, 0) 8040 #define GLPRT_PTC9522H(_i) (0x00380D04 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8041 #define GLPRT_PTC9522H_MAX_INDEX 7 8042 #define GLPRT_PTC9522H_PTC9522H_S 0 8043 #define GLPRT_PTC9522H_PTC9522H_M MAKEMASK(0xFF, 0) 8044 #define GLPRT_PTC9522L(_i) (0x00380D00 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8045 #define GLPRT_PTC9522L_MAX_INDEX 7 8046 #define GLPRT_PTC9522L_PTC9522L_S 0 8047 #define GLPRT_PTC9522L_PTC9522L_M MAKEMASK(0xFFFFFFFF, 0) 8048 #define GLPRT_PXOFFRXC(_i, _j) (0x00380500 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */ 8049 #define GLPRT_PXOFFRXC_MAX_INDEX 7 8050 #define GLPRT_PXOFFRXC_PRPXOFFRXCNT_S 0 8051 #define GLPRT_PXOFFRXC_PRPXOFFRXCNT_M MAKEMASK(0xFFFFFFFF, 0) 8052 #define GLPRT_PXOFFRXC_H(_i, _j) (0x00380504 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */ 8053 #define GLPRT_PXOFFRXC_H_MAX_INDEX 7 8054 #define GLPRT_PXOFFRXC_H_PRPXOFFRXCNT_S 0 8055 #define GLPRT_PXOFFRXC_H_PRPXOFFRXCNT_M MAKEMASK(0xFFFFFFFF, 0) 8056 #define GLPRT_PXOFFTXC(_i, _j) (0x00380F40 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */ 8057 #define GLPRT_PXOFFTXC_MAX_INDEX 7 8058 #define GLPRT_PXOFFTXC_PRPXOFFTXCNT_S 0 8059 #define GLPRT_PXOFFTXC_PRPXOFFTXCNT_M MAKEMASK(0xFFFFFFFF, 0) 8060 #define GLPRT_PXOFFTXC_H(_i, _j) (0x00380F44 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */ 8061 #define GLPRT_PXOFFTXC_H_MAX_INDEX 7 8062 #define GLPRT_PXOFFTXC_H_PRPXOFFTXCNT_S 0 8063 #define GLPRT_PXOFFTXC_H_PRPXOFFTXCNT_M MAKEMASK(0xFFFFFFFF, 0) 8064 #define GLPRT_PXONRXC(_i, _j) (0x00380300 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */ 8065 #define GLPRT_PXONRXC_MAX_INDEX 7 8066 #define GLPRT_PXONRXC_PRPXONRXCNT_S 0 8067 #define GLPRT_PXONRXC_PRPXONRXCNT_M MAKEMASK(0xFFFFFFFF, 0) 8068 #define GLPRT_PXONRXC_H(_i, _j) (0x00380304 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */ 8069 #define GLPRT_PXONRXC_H_MAX_INDEX 7 8070 #define GLPRT_PXONRXC_H_PRPXONRXCNT_S 0 8071 #define GLPRT_PXONRXC_H_PRPXONRXCNT_M MAKEMASK(0xFFFFFFFF, 0) 8072 #define GLPRT_PXONTXC(_i, _j) (0x00380D40 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */ 8073 #define GLPRT_PXONTXC_MAX_INDEX 7 8074 #define GLPRT_PXONTXC_PRPXONTXC_S 0 8075 #define GLPRT_PXONTXC_PRPXONTXC_M MAKEMASK(0xFFFFFFFF, 0) 8076 #define GLPRT_PXONTXC_H(_i, _j) (0x00380D44 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */ 8077 #define GLPRT_PXONTXC_H_MAX_INDEX 7 8078 #define GLPRT_PXONTXC_H_PRPXONTXC_S 0 8079 #define GLPRT_PXONTXC_H_PRPXONTXC_M MAKEMASK(0xFFFFFFFF, 0) 8080 #define GLPRT_RFC(_i) (0x00380AC0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8081 #define GLPRT_RFC_MAX_INDEX 7 8082 #define GLPRT_RFC_RFC_S 0 8083 #define GLPRT_RFC_RFC_M MAKEMASK(0xFFFFFFFF, 0) 8084 #define GLPRT_RFC_H(_i) (0x00380AC4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8085 #define GLPRT_RFC_H_MAX_INDEX 7 8086 #define GLPRT_RFC_H_RFC_S 0 8087 #define GLPRT_RFC_H_RFC_M MAKEMASK(0xFFFFFFFF, 0) 8088 #define GLPRT_RJC(_i) (0x00380B00 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8089 #define GLPRT_RJC_MAX_INDEX 7 8090 #define GLPRT_RJC_RJC_S 0 8091 #define GLPRT_RJC_RJC_M MAKEMASK(0xFFFFFFFF, 0) 8092 #define GLPRT_RJC_H(_i) (0x00380B04 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8093 #define GLPRT_RJC_H_MAX_INDEX 7 8094 #define GLPRT_RJC_H_RJC_S 0 8095 #define GLPRT_RJC_H_RJC_M MAKEMASK(0xFFFFFFFF, 0) 8096 #define GLPRT_RLEC(_i) (0x00380140 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8097 #define GLPRT_RLEC_MAX_INDEX 7 8098 #define GLPRT_RLEC_RLEC_S 0 8099 #define GLPRT_RLEC_RLEC_M MAKEMASK(0xFFFFFFFF, 0) 8100 #define GLPRT_RLEC_H(_i) (0x00380144 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8101 #define GLPRT_RLEC_H_MAX_INDEX 7 8102 #define GLPRT_RLEC_H_RLEC_S 0 8103 #define GLPRT_RLEC_H_RLEC_M MAKEMASK(0xFFFFFFFF, 0) 8104 #define GLPRT_ROC(_i) (0x00380240 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8105 #define GLPRT_ROC_MAX_INDEX 7 8106 #define GLPRT_ROC_ROC_S 0 8107 #define GLPRT_ROC_ROC_M MAKEMASK(0xFFFFFFFF, 0) 8108 #define GLPRT_ROC_H(_i) (0x00380244 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8109 #define GLPRT_ROC_H_MAX_INDEX 7 8110 #define GLPRT_ROC_H_ROC_S 0 8111 #define GLPRT_ROC_H_ROC_M MAKEMASK(0xFFFFFFFF, 0) 8112 #define GLPRT_RUC(_i) (0x00380200 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8113 #define GLPRT_RUC_MAX_INDEX 7 8114 #define GLPRT_RUC_RUC_S 0 8115 #define GLPRT_RUC_RUC_M MAKEMASK(0xFFFFFFFF, 0) 8116 #define GLPRT_RUC_H(_i) (0x00380204 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8117 #define GLPRT_RUC_H_MAX_INDEX 7 8118 #define GLPRT_RUC_H_RUC_S 0 8119 #define GLPRT_RUC_H_RUC_M MAKEMASK(0xFFFFFFFF, 0) 8120 #define GLPRT_RXON2OFFCNT(_i, _j) (0x00380700 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */ 8121 #define GLPRT_RXON2OFFCNT_MAX_INDEX 7 8122 #define GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_S 0 8123 #define GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_M MAKEMASK(0xFFFFFFFF, 0) 8124 #define GLPRT_RXON2OFFCNT_H(_i, _j) (0x00380704 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */ 8125 #define GLPRT_RXON2OFFCNT_H_MAX_INDEX 7 8126 #define GLPRT_RXON2OFFCNT_H_PRRXON2OFFCNT_S 0 8127 #define GLPRT_RXON2OFFCNT_H_PRRXON2OFFCNT_M MAKEMASK(0xFFFFFFFF, 0) 8128 #define GLPRT_STDC(_i) (0x00340000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 8129 #define GLPRT_STDC_MAX_INDEX 7 8130 #define GLPRT_STDC_STDC_S 0 8131 #define GLPRT_STDC_STDC_M MAKEMASK(0xFFFFFFFF, 0) 8132 #define GLPRT_TDOLD(_i) (0x00381280 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8133 #define GLPRT_TDOLD_MAX_INDEX 7 8134 #define GLPRT_TDOLD_GLPRT_TDOLD_S 0 8135 #define GLPRT_TDOLD_GLPRT_TDOLD_M MAKEMASK(0xFFFFFFFF, 0) 8136 #define GLPRT_TDOLD_H(_i) (0x00381284 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8137 #define GLPRT_TDOLD_H_MAX_INDEX 7 8138 #define GLPRT_TDOLD_H_GLPRT_TDOLD_S 0 8139 #define GLPRT_TDOLD_H_GLPRT_TDOLD_M MAKEMASK(0xFFFFFFFF, 0) 8140 #define GLPRT_UPRCH(_i) (0x00381304 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8141 #define GLPRT_UPRCH_MAX_INDEX 7 8142 #define GLPRT_UPRCH_UPRCH_S 0 8143 #define GLPRT_UPRCH_UPRCH_M MAKEMASK(0xFF, 0) 8144 #define GLPRT_UPRCL(_i) (0x00381300 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8145 #define GLPRT_UPRCL_MAX_INDEX 7 8146 #define GLPRT_UPRCL_UPRCL_S 0 8147 #define GLPRT_UPRCL_UPRCL_M MAKEMASK(0xFFFFFFFF, 0) 8148 #define GLPRT_UPTCH(_i) (0x003811C4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8149 #define GLPRT_UPTCH_MAX_INDEX 7 8150 #define GLPRT_UPTCH_UPTCH_S 0 8151 #define GLPRT_UPTCH_UPTCH_M MAKEMASK(0xFF, 0) 8152 #define GLPRT_UPTCL(_i) (0x003811C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */ 8153 #define GLPRT_UPTCL_MAX_INDEX 7 8154 #define E800_GLPRT_UPTCL_VUPTCH_S 0 8155 #define E800_GLPRT_UPTCL_VUPTCH_M MAKEMASK(0xFFFFFFFF, 0) 8156 #define GLSTAT_ACL_CNT_0_H(_i) (0x00388004 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */ 8157 #define GLSTAT_ACL_CNT_0_H_MAX_INDEX 511 8158 #define GLSTAT_ACL_CNT_0_H_CNT_MSB_S 0 8159 #define GLSTAT_ACL_CNT_0_H_CNT_MSB_M MAKEMASK(0xFF, 0) 8160 #define GLSTAT_ACL_CNT_0_L(_i) (0x00388000 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */ 8161 #define GLSTAT_ACL_CNT_0_L_MAX_INDEX 511 8162 #define GLSTAT_ACL_CNT_0_L_CNT_LSB_S 0 8163 #define GLSTAT_ACL_CNT_0_L_CNT_LSB_M MAKEMASK(0xFFFFFFFF, 0) 8164 #define GLSTAT_ACL_CNT_1_H(_i) (0x00389004 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */ 8165 #define GLSTAT_ACL_CNT_1_H_MAX_INDEX 511 8166 #define GLSTAT_ACL_CNT_1_H_CNT_MSB_S 0 8167 #define GLSTAT_ACL_CNT_1_H_CNT_MSB_M MAKEMASK(0xFF, 0) 8168 #define GLSTAT_ACL_CNT_1_L(_i) (0x00389000 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */ 8169 #define GLSTAT_ACL_CNT_1_L_MAX_INDEX 511 8170 #define GLSTAT_ACL_CNT_1_L_CNT_LSB_S 0 8171 #define GLSTAT_ACL_CNT_1_L_CNT_LSB_M MAKEMASK(0xFFFFFFFF, 0) 8172 #define GLSTAT_ACL_CNT_2_H(_i) (0x0038A004 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */ 8173 #define GLSTAT_ACL_CNT_2_H_MAX_INDEX 511 8174 #define GLSTAT_ACL_CNT_2_H_CNT_MSB_S 0 8175 #define GLSTAT_ACL_CNT_2_H_CNT_MSB_M MAKEMASK(0xFF, 0) 8176 #define GLSTAT_ACL_CNT_2_L(_i) (0x0038A000 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */ 8177 #define GLSTAT_ACL_CNT_2_L_MAX_INDEX 511 8178 #define GLSTAT_ACL_CNT_2_L_CNT_LSB_S 0 8179 #define GLSTAT_ACL_CNT_2_L_CNT_LSB_M MAKEMASK(0xFFFFFFFF, 0) 8180 #define GLSTAT_ACL_CNT_3_H(_i) (0x0038B004 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */ 8181 #define GLSTAT_ACL_CNT_3_H_MAX_INDEX 511 8182 #define GLSTAT_ACL_CNT_3_H_CNT_MSB_S 0 8183 #define GLSTAT_ACL_CNT_3_H_CNT_MSB_M MAKEMASK(0xFF, 0) 8184 #define GLSTAT_ACL_CNT_3_L(_i) (0x0038B000 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */ 8185 #define GLSTAT_ACL_CNT_3_L_MAX_INDEX 511 8186 #define GLSTAT_ACL_CNT_3_L_CNT_LSB_S 0 8187 #define GLSTAT_ACL_CNT_3_L_CNT_LSB_M MAKEMASK(0xFFFFFFFF, 0) 8188 #define GLSTAT_FD_CNT0H(_i) (0x003A0004 + ((_i) * 8)) /* _i=0...4095 */ /* Reset Source: CORER */ 8189 #define GLSTAT_FD_CNT0H_MAX_INDEX 4095 8190 #define GLSTAT_FD_CNT0H_FD0_CNT_H_S 0 8191 #define GLSTAT_FD_CNT0H_FD0_CNT_H_M MAKEMASK(0xFF, 0) 8192 #define GLSTAT_FD_CNT0L(_i) (0x003A0000 + ((_i) * 8)) /* _i=0...4095 */ /* Reset Source: CORER */ 8193 #define GLSTAT_FD_CNT0L_MAX_INDEX 4095 8194 #define GLSTAT_FD_CNT0L_FD0_CNT_L_S 0 8195 #define GLSTAT_FD_CNT0L_FD0_CNT_L_M MAKEMASK(0xFFFFFFFF, 0) 8196 #define GLSTAT_FD_CNT1H(_i) (0x003A8004 + ((_i) * 8)) /* _i=0...4095 */ /* Reset Source: CORER */ 8197 #define GLSTAT_FD_CNT1H_MAX_INDEX 4095 8198 #define GLSTAT_FD_CNT1H_FD0_CNT_H_S 0 8199 #define GLSTAT_FD_CNT1H_FD0_CNT_H_M MAKEMASK(0xFF, 0) 8200 #define GLSTAT_FD_CNT1L(_i) (0x003A8000 + ((_i) * 8)) /* _i=0...4095 */ /* Reset Source: CORER */ 8201 #define GLSTAT_FD_CNT1L_MAX_INDEX 4095 8202 #define GLSTAT_FD_CNT1L_FD0_CNT_L_S 0 8203 #define GLSTAT_FD_CNT1L_FD0_CNT_L_M MAKEMASK(0xFFFFFFFF, 0) 8204 #define GLSW_BPRCH(_i) (0x00346204 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */ 8205 #define GLSW_BPRCH_MAX_INDEX 31 8206 #define GLSW_BPRCH_BPRCH_S 0 8207 #define GLSW_BPRCH_BPRCH_M MAKEMASK(0xFF, 0) 8208 #define GLSW_BPRCL(_i) (0x00346200 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */ 8209 #define GLSW_BPRCL_MAX_INDEX 31 8210 #define GLSW_BPRCL_BPRCL_S 0 8211 #define GLSW_BPRCL_BPRCL_M MAKEMASK(0xFFFFFFFF, 0) 8212 #define GLSW_BPTCH(_i) (0x00310204 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */ 8213 #define GLSW_BPTCH_MAX_INDEX 31 8214 #define GLSW_BPTCH_BPTCH_S 0 8215 #define GLSW_BPTCH_BPTCH_M MAKEMASK(0xFF, 0) 8216 #define GLSW_BPTCL(_i) (0x00310200 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */ 8217 #define GLSW_BPTCL_MAX_INDEX 31 8218 #define GLSW_BPTCL_BPTCL_S 0 8219 #define GLSW_BPTCL_BPTCL_M MAKEMASK(0xFFFFFFFF, 0) 8220 #define GLSW_GORCH(_i) (0x00341004 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */ 8221 #define GLSW_GORCH_MAX_INDEX 31 8222 #define GLSW_GORCH_GORCH_S 0 8223 #define GLSW_GORCH_GORCH_M MAKEMASK(0xFF, 0) 8224 #define GLSW_GORCL(_i) (0x00341000 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */ 8225 #define GLSW_GORCL_MAX_INDEX 31 8226 #define GLSW_GORCL_GORCL_S 0 8227 #define GLSW_GORCL_GORCL_M MAKEMASK(0xFFFFFFFF, 0) 8228 #define GLSW_GOTCH(_i) (0x00302004 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */ 8229 #define GLSW_GOTCH_MAX_INDEX 31 8230 #define GLSW_GOTCH_GOTCH_S 0 8231 #define GLSW_GOTCH_GOTCH_M MAKEMASK(0xFF, 0) 8232 #define GLSW_GOTCL(_i) (0x00302000 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */ 8233 #define GLSW_GOTCL_MAX_INDEX 31 8234 #define GLSW_GOTCL_GOTCL_S 0 8235 #define GLSW_GOTCL_GOTCL_M MAKEMASK(0xFFFFFFFF, 0) 8236 #define GLSW_MPRCH(_i) (0x00346104 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */ 8237 #define GLSW_MPRCH_MAX_INDEX 31 8238 #define GLSW_MPRCH_MPRCH_S 0 8239 #define GLSW_MPRCH_MPRCH_M MAKEMASK(0xFF, 0) 8240 #define GLSW_MPRCL(_i) (0x00346100 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */ 8241 #define GLSW_MPRCL_MAX_INDEX 31 8242 #define GLSW_MPRCL_MPRCL_S 0 8243 #define GLSW_MPRCL_MPRCL_M MAKEMASK(0xFFFFFFFF, 0) 8244 #define GLSW_MPTCH(_i) (0x00310104 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */ 8245 #define GLSW_MPTCH_MAX_INDEX 31 8246 #define GLSW_MPTCH_MPTCH_S 0 8247 #define GLSW_MPTCH_MPTCH_M MAKEMASK(0xFF, 0) 8248 #define GLSW_MPTCL(_i) (0x00310100 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */ 8249 #define GLSW_MPTCL_MAX_INDEX 31 8250 #define GLSW_MPTCL_MPTCL_S 0 8251 #define GLSW_MPTCL_MPTCL_M MAKEMASK(0xFFFFFFFF, 0) 8252 #define GLSW_UPRCH(_i) (0x00346004 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */ 8253 #define GLSW_UPRCH_MAX_INDEX 31 8254 #define GLSW_UPRCH_UPRCH_S 0 8255 #define GLSW_UPRCH_UPRCH_M MAKEMASK(0xFF, 0) 8256 #define GLSW_UPRCL(_i) (0x00346000 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */ 8257 #define GLSW_UPRCL_MAX_INDEX 31 8258 #define GLSW_UPRCL_UPRCL_S 0 8259 #define GLSW_UPRCL_UPRCL_M MAKEMASK(0xFFFFFFFF, 0) 8260 #define GLSW_UPTCH(_i) (0x00310004 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */ 8261 #define GLSW_UPTCH_MAX_INDEX 31 8262 #define GLSW_UPTCH_UPTCH_S 0 8263 #define GLSW_UPTCH_UPTCH_M MAKEMASK(0xFF, 0) 8264 #define GLSW_UPTCL(_i) (0x00310000 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */ 8265 #define GLSW_UPTCL_MAX_INDEX 31 8266 #define GLSW_UPTCL_UPTCL_S 0 8267 #define GLSW_UPTCL_UPTCL_M MAKEMASK(0xFFFFFFFF, 0) 8268 #define GLSWID_RUPP(_i) (0x00345000 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 8269 #define GLSWID_RUPP_MAX_INDEX 255 8270 #define GLSWID_RUPP_RUPP_S 0 8271 #define GLSWID_RUPP_RUPP_M MAKEMASK(0xFFFFFFFF, 0) 8272 #define GLV_BPRCH(_i) (0x003B6004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */ 8273 #define GLV_BPRCH_MAX_INDEX 767 8274 #define GLV_BPRCH_BPRCH_S 0 8275 #define GLV_BPRCH_BPRCH_M MAKEMASK(0xFF, 0) 8276 #define GLV_BPRCL(_i) (0x003B6000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */ 8277 #define GLV_BPRCL_MAX_INDEX 767 8278 #define GLV_BPRCL_BPRCL_S 0 8279 #define GLV_BPRCL_BPRCL_M MAKEMASK(0xFFFFFFFF, 0) 8280 #define GLV_BPTCH(_i) (0x0030E004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */ 8281 #define GLV_BPTCH_MAX_INDEX 767 8282 #define GLV_BPTCH_BPTCH_S 0 8283 #define GLV_BPTCH_BPTCH_M MAKEMASK(0xFF, 0) 8284 #define GLV_BPTCL(_i) (0x0030E000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */ 8285 #define GLV_BPTCL_MAX_INDEX 767 8286 #define GLV_BPTCL_BPTCL_S 0 8287 #define GLV_BPTCL_BPTCL_M MAKEMASK(0xFFFFFFFF, 0) 8288 #define GLV_GORCH(_i) (0x003B0004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */ 8289 #define GLV_GORCH_MAX_INDEX 767 8290 #define GLV_GORCH_GORCH_S 0 8291 #define GLV_GORCH_GORCH_M MAKEMASK(0xFF, 0) 8292 #define GLV_GORCL(_i) (0x003B0000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */ 8293 #define GLV_GORCL_MAX_INDEX 767 8294 #define GLV_GORCL_GORCL_S 0 8295 #define GLV_GORCL_GORCL_M MAKEMASK(0xFFFFFFFF, 0) 8296 #define GLV_GOTCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */ 8297 #define GLV_GOTCH_MAX_INDEX 767 8298 #define GLV_GOTCH_GOTCH_S 0 8299 #define GLV_GOTCH_GOTCH_M MAKEMASK(0xFF, 0) 8300 #define GLV_GOTCL(_i) (0x00300000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */ 8301 #define GLV_GOTCL_MAX_INDEX 767 8302 #define GLV_GOTCL_GOTCL_S 0 8303 #define GLV_GOTCL_GOTCL_M MAKEMASK(0xFFFFFFFF, 0) 8304 #define GLV_MPRCH(_i) (0x003B4004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */ 8305 #define GLV_MPRCH_MAX_INDEX 767 8306 #define GLV_MPRCH_MPRCH_S 0 8307 #define GLV_MPRCH_MPRCH_M MAKEMASK(0xFF, 0) 8308 #define GLV_MPRCL(_i) (0x003B4000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */ 8309 #define GLV_MPRCL_MAX_INDEX 767 8310 #define GLV_MPRCL_MPRCL_S 0 8311 #define GLV_MPRCL_MPRCL_M MAKEMASK(0xFFFFFFFF, 0) 8312 #define GLV_MPTCH(_i) (0x0030C004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */ 8313 #define GLV_MPTCH_MAX_INDEX 767 8314 #define GLV_MPTCH_MPTCH_S 0 8315 #define GLV_MPTCH_MPTCH_M MAKEMASK(0xFF, 0) 8316 #define GLV_MPTCL(_i) (0x0030C000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */ 8317 #define GLV_MPTCL_MAX_INDEX 767 8318 #define GLV_MPTCL_MPTCL_S 0 8319 #define GLV_MPTCL_MPTCL_M MAKEMASK(0xFFFFFFFF, 0) 8320 #define GLV_RDPC(_i) (0x00294C04 + ((_i) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 8321 #define GLV_RDPC_MAX_INDEX 767 8322 #define GLV_RDPC_RDPC_S 0 8323 #define GLV_RDPC_RDPC_M MAKEMASK(0xFFFFFFFF, 0) 8324 #define GLV_REPC(_i) (0x00295804 + ((_i) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 8325 #define GLV_REPC_MAX_INDEX 767 8326 #define GLV_REPC_NO_DESC_CNT_S 0 8327 #define GLV_REPC_NO_DESC_CNT_M MAKEMASK(0xFFFF, 0) 8328 #define GLV_REPC_ERROR_CNT_S 16 8329 #define GLV_REPC_ERROR_CNT_M MAKEMASK(0xFFFF, 16) 8330 #define GLV_TEPC(_VSI) (0x00312000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 8331 #define GLV_TEPC_MAX_INDEX 767 8332 #define GLV_TEPC_TEPC_S 0 8333 #define GLV_TEPC_TEPC_M MAKEMASK(0xFFFFFFFF, 0) 8334 #define GLV_UPRCH(_i) (0x003B2004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */ 8335 #define GLV_UPRCH_MAX_INDEX 767 8336 #define GLV_UPRCH_UPRCH_S 0 8337 #define GLV_UPRCH_UPRCH_M MAKEMASK(0xFF, 0) 8338 #define GLV_UPRCL(_i) (0x003B2000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */ 8339 #define GLV_UPRCL_MAX_INDEX 767 8340 #define GLV_UPRCL_UPRCL_S 0 8341 #define GLV_UPRCL_UPRCL_M MAKEMASK(0xFFFFFFFF, 0) 8342 #define GLV_UPTCH(_i) (0x0030A004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */ 8343 #define GLV_UPTCH_MAX_INDEX 767 8344 #define GLV_UPTCH_GLVUPTCH_S 0 8345 #define GLV_UPTCH_GLVUPTCH_M MAKEMASK(0xFF, 0) 8346 #define GLV_UPTCL(_i) (0x0030A000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */ 8347 #define GLV_UPTCL_MAX_INDEX 767 8348 #define GLV_UPTCL_UPTCL_S 0 8349 #define GLV_UPTCL_UPTCL_M MAKEMASK(0xFFFFFFFF, 0) 8350 #define GLVEBUP_RBCH(_i, _j) (0x00343004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */ 8351 #define GLVEBUP_RBCH_MAX_INDEX 7 8352 #define GLVEBUP_RBCH_UPBCH_S 0 8353 #define GLVEBUP_RBCH_UPBCH_M MAKEMASK(0xFF, 0) 8354 #define GLVEBUP_RBCL(_i, _j) (0x00343000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */ 8355 #define GLVEBUP_RBCL_MAX_INDEX 7 8356 #define GLVEBUP_RBCL_UPBCL_S 0 8357 #define GLVEBUP_RBCL_UPBCL_M MAKEMASK(0xFFFFFFFF, 0) 8358 #define GLVEBUP_RPCH(_i, _j) (0x00344004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */ 8359 #define GLVEBUP_RPCH_MAX_INDEX 7 8360 #define GLVEBUP_RPCH_UPPCH_S 0 8361 #define GLVEBUP_RPCH_UPPCH_M MAKEMASK(0xFF, 0) 8362 #define GLVEBUP_RPCL(_i, _j) (0x00344000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */ 8363 #define GLVEBUP_RPCL_MAX_INDEX 7 8364 #define GLVEBUP_RPCL_UPPCL_S 0 8365 #define GLVEBUP_RPCL_UPPCL_M MAKEMASK(0xFFFFFFFF, 0) 8366 #define GLVEBUP_TBCH(_i, _j) (0x00306004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */ 8367 #define GLVEBUP_TBCH_MAX_INDEX 7 8368 #define GLVEBUP_TBCH_UPBCH_S 0 8369 #define GLVEBUP_TBCH_UPBCH_M MAKEMASK(0xFF, 0) 8370 #define GLVEBUP_TBCL(_i, _j) (0x00306000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */ 8371 #define GLVEBUP_TBCL_MAX_INDEX 7 8372 #define GLVEBUP_TBCL_UPBCL_S 0 8373 #define GLVEBUP_TBCL_UPBCL_M MAKEMASK(0xFFFFFFFF, 0) 8374 #define GLVEBUP_TPCH(_i, _j) (0x00308004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */ 8375 #define GLVEBUP_TPCH_MAX_INDEX 7 8376 #define GLVEBUP_TPCH_UPPCH_S 0 8377 #define GLVEBUP_TPCH_UPPCH_M MAKEMASK(0xFF, 0) 8378 #define GLVEBUP_TPCL(_i, _j) (0x00308000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */ 8379 #define GLVEBUP_TPCL_MAX_INDEX 7 8380 #define GLVEBUP_TPCL_UPPCL_S 0 8381 #define GLVEBUP_TPCL_UPPCL_M MAKEMASK(0xFFFFFFFF, 0) 8382 #define PRTRPB_LDPC 0x000AC280 /* Reset Source: CORER */ 8383 #define PRTRPB_LDPC_CRCERRS_S 0 8384 #define PRTRPB_LDPC_CRCERRS_M MAKEMASK(0xFFFFFFFF, 0) 8385 #define PRTRPB_RDPC 0x000AC260 /* Reset Source: CORER */ 8386 #define PRTRPB_RDPC_CRCERRS_S 0 8387 #define PRTRPB_RDPC_CRCERRS_M MAKEMASK(0xFFFFFFFF, 0) 8388 #define PRTTPB_STAT_TC_BYTES_SENTL(_i) (0x00098200 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 8389 #define PRTTPB_STAT_TC_BYTES_SENTL_MAX_INDEX 63 8390 #define PRTTPB_STAT_TC_BYTES_SENTL_TCCNT_S 0 8391 #define PRTTPB_STAT_TC_BYTES_SENTL_TCCNT_M MAKEMASK(0xFFFFFFFF, 0) 8392 #define TPB_PRTTPB_STAT_PKT_SENT(_i) (0x00099470 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 8393 #define TPB_PRTTPB_STAT_PKT_SENT_MAX_INDEX 7 8394 #define TPB_PRTTPB_STAT_PKT_SENT_PKTCNT_S 0 8395 #define TPB_PRTTPB_STAT_PKT_SENT_PKTCNT_M MAKEMASK(0xFFFFFFFF, 0) 8396 #define TPB_PRTTPB_STAT_TC_BYTES_SENT(_i) (0x00099094 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 8397 #define TPB_PRTTPB_STAT_TC_BYTES_SENT_MAX_INDEX 63 8398 #define TPB_PRTTPB_STAT_TC_BYTES_SENT_TCCNT_S 0 8399 #define TPB_PRTTPB_STAT_TC_BYTES_SENT_TCCNT_M MAKEMASK(0xFFFFFFFF, 0) 8400 #define EMP_SWT_PRUNIND 0x00204020 /* Reset Source: CORER */ 8401 #define EMP_SWT_PRUNIND_OPCODE_S 0 8402 #define EMP_SWT_PRUNIND_OPCODE_M MAKEMASK(0xF, 0) 8403 #define EMP_SWT_PRUNIND_LIST_INDEX_NUM_S 4 8404 #define EMP_SWT_PRUNIND_LIST_INDEX_NUM_M MAKEMASK(0x3FF, 4) 8405 #define EMP_SWT_PRUNIND_VSI_NUM_S 16 8406 #define EMP_SWT_PRUNIND_VSI_NUM_M MAKEMASK(0x3FF, 16) 8407 #define EMP_SWT_PRUNIND_BIT_VALUE_S 31 8408 #define EMP_SWT_PRUNIND_BIT_VALUE_M BIT(31) 8409 #define EMP_SWT_REPIND 0x0020401C /* Reset Source: CORER */ 8410 #define EMP_SWT_REPIND_OPCODE_S 0 8411 #define EMP_SWT_REPIND_OPCODE_M MAKEMASK(0xF, 0) 8412 #define EMP_SWT_REPIND_LIST_INDEX_NUMBER_S 4 8413 #define EMP_SWT_REPIND_LIST_INDEX_NUMBER_M MAKEMASK(0x3FF, 4) 8414 #define EMP_SWT_REPIND_VSI_NUM_S 16 8415 #define EMP_SWT_REPIND_VSI_NUM_M MAKEMASK(0x3FF, 16) 8416 #define EMP_SWT_REPIND_BIT_VALUE_S 31 8417 #define EMP_SWT_REPIND_BIT_VALUE_M BIT(31) 8418 #define GL_OVERRIDEC 0x002040A4 /* Reset Source: CORER */ 8419 #define GL_OVERRIDEC_OVERRIDE_ATTEMPTC_S 0 8420 #define GL_OVERRIDEC_OVERRIDE_ATTEMPTC_M MAKEMASK(0xFFFF, 0) 8421 #define GL_OVERRIDEC_LAST_VSI_S 16 8422 #define GL_OVERRIDEC_LAST_VSI_M MAKEMASK(0x3FF, 16) 8423 #define GL_PLG_AVG_CALC_CFG 0x0020A5AC /* Reset Source: CORER */ 8424 #define GL_PLG_AVG_CALC_CFG_CYCLE_LEN_S 0 8425 #define GL_PLG_AVG_CALC_CFG_CYCLE_LEN_M MAKEMASK(0x7FFFFFFF, 0) 8426 #define GL_PLG_AVG_CALC_CFG_MODE_S 31 8427 #define GL_PLG_AVG_CALC_CFG_MODE_M BIT(31) 8428 #define GL_PLG_AVG_CALC_ST 0x0020A5B0 /* Reset Source: CORER */ 8429 #define GL_PLG_AVG_CALC_ST_IN_DATA_S 0 8430 #define GL_PLG_AVG_CALC_ST_IN_DATA_M MAKEMASK(0x7FFF, 0) 8431 #define GL_PLG_AVG_CALC_ST_OUT_DATA_S 16 8432 #define GL_PLG_AVG_CALC_ST_OUT_DATA_M MAKEMASK(0x7FFF, 16) 8433 #define GL_PLG_AVG_CALC_ST_VALID_S 31 8434 #define GL_PLG_AVG_CALC_ST_VALID_M BIT(31) 8435 #define GL_PRE_CFG_CMD 0x00214090 /* Reset Source: CORER */ 8436 #define GL_PRE_CFG_CMD_ADDR_S 0 8437 #define GL_PRE_CFG_CMD_ADDR_M MAKEMASK(0x1FFF, 0) 8438 #define GL_PRE_CFG_CMD_TBLIDX_S 16 8439 #define GL_PRE_CFG_CMD_TBLIDX_M MAKEMASK(0x7, 16) 8440 #define GL_PRE_CFG_CMD_CMD_S 29 8441 #define GL_PRE_CFG_CMD_CMD_M BIT(29) 8442 #define GL_PRE_CFG_CMD_DONE_S 31 8443 #define GL_PRE_CFG_CMD_DONE_M BIT(31) 8444 #define GL_PRE_CFG_DATA(_i) (0x00214074 + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: CORER */ 8445 #define GL_PRE_CFG_DATA_MAX_INDEX 6 8446 #define GL_PRE_CFG_DATA_GL_PRE_RCP_DATA_S 0 8447 #define GL_PRE_CFG_DATA_GL_PRE_RCP_DATA_M MAKEMASK(0xFFFFFFFF, 0) 8448 #define GL_SWT_FUNCFILT 0x001D2698 /* Reset Source: CORER */ 8449 #define GL_SWT_FUNCFILT_FUNCFILT_S 0 8450 #define GL_SWT_FUNCFILT_FUNCFILT_M BIT(0) 8451 #define GL_SWT_FW_STS(_i) (0x00216000 + ((_i) * 4)) /* _i=0...5 */ /* Reset Source: CORER */ 8452 #define GL_SWT_FW_STS_MAX_INDEX 5 8453 #define GL_SWT_FW_STS_GL_SWT_FW_STS_S 0 8454 #define GL_SWT_FW_STS_GL_SWT_FW_STS_M MAKEMASK(0xFFFFFFFF, 0) 8455 #define GL_SWT_LAT_DOUBLE 0x00204004 /* Reset Source: CORER */ 8456 #define GL_SWT_LAT_DOUBLE_BASE_S 0 8457 #define GL_SWT_LAT_DOUBLE_BASE_M MAKEMASK(0x7FF, 0) 8458 #define GL_SWT_LAT_DOUBLE_SIZE_S 16 8459 #define GL_SWT_LAT_DOUBLE_SIZE_M MAKEMASK(0x7FF, 16) 8460 #define GL_SWT_LAT_QUAD 0x00204008 /* Reset Source: CORER */ 8461 #define GL_SWT_LAT_QUAD_BASE_S 0 8462 #define GL_SWT_LAT_QUAD_BASE_M MAKEMASK(0x7FF, 0) 8463 #define GL_SWT_LAT_QUAD_SIZE_S 16 8464 #define GL_SWT_LAT_QUAD_SIZE_M MAKEMASK(0x7FF, 16) 8465 #define GL_SWT_LAT_SINGLE 0x00204000 /* Reset Source: CORER */ 8466 #define GL_SWT_LAT_SINGLE_BASE_S 0 8467 #define GL_SWT_LAT_SINGLE_BASE_M MAKEMASK(0x7FF, 0) 8468 #define GL_SWT_LAT_SINGLE_SIZE_S 16 8469 #define GL_SWT_LAT_SINGLE_SIZE_M MAKEMASK(0x7FF, 16) 8470 #define GL_SWT_MD_PRI 0x002040AC /* Reset Source: CORER */ 8471 #define GL_SWT_MD_PRI_VSI_PRI_S 0 8472 #define GL_SWT_MD_PRI_VSI_PRI_M MAKEMASK(0x7, 0) 8473 #define GL_SWT_MD_PRI_LB_PRI_S 4 8474 #define GL_SWT_MD_PRI_LB_PRI_M MAKEMASK(0x7, 4) 8475 #define GL_SWT_MD_PRI_LAN_EN_PRI_S 8 8476 #define GL_SWT_MD_PRI_LAN_EN_PRI_M MAKEMASK(0x7, 8) 8477 #define GL_SWT_MD_PRI_QH_PRI_S 12 8478 #define GL_SWT_MD_PRI_QH_PRI_M MAKEMASK(0x7, 12) 8479 #define GL_SWT_MD_PRI_QL_PRI_S 16 8480 #define GL_SWT_MD_PRI_QL_PRI_M MAKEMASK(0x7, 16) 8481 #define GL_SWT_MIRTARVSI(_i) (0x00204500 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 8482 #define GL_SWT_MIRTARVSI_MAX_INDEX 63 8483 #define GL_SWT_MIRTARVSI_VFVMNUMBER_S 0 8484 #define GL_SWT_MIRTARVSI_VFVMNUMBER_M MAKEMASK(0x3FF, 0) 8485 #define GL_SWT_MIRTARVSI_FUNCTIONTYPE_S 10 8486 #define GL_SWT_MIRTARVSI_FUNCTIONTYPE_M MAKEMASK(0x3, 10) 8487 #define GL_SWT_MIRTARVSI_PFNUMBER_S 12 8488 #define GL_SWT_MIRTARVSI_PFNUMBER_M MAKEMASK(0x7, 12) 8489 #define GL_SWT_MIRTARVSI_TARGETVSI_S 20 8490 #define GL_SWT_MIRTARVSI_TARGETVSI_M MAKEMASK(0x3FF, 20) 8491 #define GL_SWT_MIRTARVSI_RULEENABLE_S 31 8492 #define GL_SWT_MIRTARVSI_RULEENABLE_M BIT(31) 8493 #define GL_SWT_SWIDFVIDX 0x00214114 /* Reset Source: CORER */ 8494 #define GL_SWT_SWIDFVIDX_SWIDFVIDX_S 0 8495 #define GL_SWT_SWIDFVIDX_SWIDFVIDX_M MAKEMASK(0x3F, 0) 8496 #define GL_SWT_SWIDFVIDX_PORT_TYPE_S 31 8497 #define GL_SWT_SWIDFVIDX_PORT_TYPE_M BIT(31) 8498 #define GL_VP_SWITCHID(_i) (0x00214094 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 8499 #define GL_VP_SWITCHID_MAX_INDEX 31 8500 #define GL_VP_SWITCHID_SWITCHID_S 0 8501 #define GL_VP_SWITCHID_SWITCHID_M MAKEMASK(0xFF, 0) 8502 #define GLSWID_STAT_BLOCK(_i) (0x0020A1A4 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: PFR */ 8503 #define GLSWID_STAT_BLOCK_MAX_INDEX 255 8504 #define GLSWID_STAT_BLOCK_VEBID_S 0 8505 #define GLSWID_STAT_BLOCK_VEBID_M MAKEMASK(0x1F, 0) 8506 #define GLSWID_STAT_BLOCK_VEBID_VALID_S 31 8507 #define GLSWID_STAT_BLOCK_VEBID_VALID_M BIT(31) 8508 #define GLSWT_ACT_RESP_0 0x0020A5A4 /* Reset Source: CORER */ 8509 #define GLSWT_ACT_RESP_0_GLSWT_ACT_RESP_S 0 8510 #define GLSWT_ACT_RESP_0_GLSWT_ACT_RESP_M MAKEMASK(0xFFFFFFFF, 0) 8511 #define GLSWT_ACT_RESP_1 0x0020A5A8 /* Reset Source: CORER */ 8512 #define GLSWT_ACT_RESP_1_GLSWT_ACT_RESP_S 0 8513 #define GLSWT_ACT_RESP_1_GLSWT_ACT_RESP_M MAKEMASK(0xFFFFFFFF, 0) 8514 #define GLSWT_ARB_MODE 0x0020A674 /* Reset Source: CORER */ 8515 #define GLSWT_ARB_MODE_FLU_PRI_SHM_S 0 8516 #define GLSWT_ARB_MODE_FLU_PRI_SHM_M BIT(0) 8517 #define GLSWT_ARB_MODE_TX_RX_FWD_PRI_S 1 8518 #define GLSWT_ARB_MODE_TX_RX_FWD_PRI_M BIT(1) 8519 #define PRT_SBPVSI 0x00204120 /* Reset Source: CORER */ 8520 #define PRT_SBPVSI_BAD_FRAMES_VSI_S 0 8521 #define PRT_SBPVSI_BAD_FRAMES_VSI_M MAKEMASK(0x3FF, 0) 8522 #define PRT_SBPVSI_SBP_S 31 8523 #define PRT_SBPVSI_SBP_M BIT(31) 8524 #define PRT_SCSTS 0x00204140 /* Reset Source: CORER */ 8525 #define PRT_SCSTS_BSCA_S 0 8526 #define PRT_SCSTS_BSCA_M BIT(0) 8527 #define PRT_SCSTS_BSCAP_S 1 8528 #define PRT_SCSTS_BSCAP_M BIT(1) 8529 #define PRT_SCSTS_MSCA_S 2 8530 #define PRT_SCSTS_MSCA_M BIT(2) 8531 #define PRT_SCSTS_MSCAP_S 3 8532 #define PRT_SCSTS_MSCAP_M BIT(3) 8533 #define PRT_SWT_BSCCNT 0x00204160 /* Reset Source: CORER */ 8534 #define PRT_SWT_BSCCNT_CCOUNT_S 0 8535 #define PRT_SWT_BSCCNT_CCOUNT_M MAKEMASK(0x1FFFFFF, 0) 8536 #define PRT_SWT_BSCTRH 0x00204180 /* Reset Source: CORER */ 8537 #define PRT_SWT_BSCTRH_UTRESH_S 0 8538 #define PRT_SWT_BSCTRH_UTRESH_M MAKEMASK(0x7FFFF, 0) 8539 #define PRT_SWT_MIREG 0x002042A0 /* Reset Source: CORER */ 8540 #define PRT_SWT_MIREG_MIRRULE_S 0 8541 #define PRT_SWT_MIREG_MIRRULE_M MAKEMASK(0x3F, 0) 8542 #define PRT_SWT_MIREG_MIRENA_S 7 8543 #define PRT_SWT_MIREG_MIRENA_M BIT(7) 8544 #define PRT_SWT_MIRIG 0x00204280 /* Reset Source: CORER */ 8545 #define PRT_SWT_MIRIG_MIRRULE_S 0 8546 #define PRT_SWT_MIRIG_MIRRULE_M MAKEMASK(0x3F, 0) 8547 #define PRT_SWT_MIRIG_MIRENA_S 7 8548 #define PRT_SWT_MIRIG_MIRENA_M BIT(7) 8549 #define PRT_SWT_MSCCNT 0x00204100 /* Reset Source: CORER */ 8550 #define PRT_SWT_MSCCNT_CCOUNT_S 0 8551 #define PRT_SWT_MSCCNT_CCOUNT_M MAKEMASK(0x1FFFFFF, 0) 8552 #define PRT_SWT_MSCTRH 0x002041C0 /* Reset Source: CORER */ 8553 #define PRT_SWT_MSCTRH_UTRESH_S 0 8554 #define PRT_SWT_MSCTRH_UTRESH_M MAKEMASK(0x7FFFF, 0) 8555 #define PRT_SWT_SCBI 0x002041E0 /* Reset Source: CORER */ 8556 #define PRT_SWT_SCBI_BI_S 0 8557 #define PRT_SWT_SCBI_BI_M MAKEMASK(0x1FFFFFF, 0) 8558 #define PRT_SWT_SCCRL 0x00204200 /* Reset Source: CORER */ 8559 #define PRT_SWT_SCCRL_MDIPW_S 0 8560 #define PRT_SWT_SCCRL_MDIPW_M BIT(0) 8561 #define PRT_SWT_SCCRL_MDICW_S 1 8562 #define PRT_SWT_SCCRL_MDICW_M BIT(1) 8563 #define PRT_SWT_SCCRL_BDIPW_S 2 8564 #define PRT_SWT_SCCRL_BDIPW_M BIT(2) 8565 #define PRT_SWT_SCCRL_BDICW_S 3 8566 #define PRT_SWT_SCCRL_BDICW_M BIT(3) 8567 #define PRT_SWT_SCCRL_INTERVAL_S 8 8568 #define PRT_SWT_SCCRL_INTERVAL_M MAKEMASK(0xFFFFF, 8) 8569 #define PRT_TCTUPR(_i) (0x00040840 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 8570 #define PRT_TCTUPR_MAX_INDEX 31 8571 #define PRT_TCTUPR_UP0_S 0 8572 #define PRT_TCTUPR_UP0_M MAKEMASK(0x7, 0) 8573 #define PRT_TCTUPR_UP1_S 4 8574 #define PRT_TCTUPR_UP1_M MAKEMASK(0x7, 4) 8575 #define PRT_TCTUPR_UP2_S 8 8576 #define PRT_TCTUPR_UP2_M MAKEMASK(0x7, 8) 8577 #define PRT_TCTUPR_UP3_S 12 8578 #define PRT_TCTUPR_UP3_M MAKEMASK(0x7, 12) 8579 #define PRT_TCTUPR_UP4_S 16 8580 #define PRT_TCTUPR_UP4_M MAKEMASK(0x7, 16) 8581 #define PRT_TCTUPR_UP5_S 20 8582 #define PRT_TCTUPR_UP5_M MAKEMASK(0x7, 20) 8583 #define PRT_TCTUPR_UP6_S 24 8584 #define PRT_TCTUPR_UP6_M MAKEMASK(0x7, 24) 8585 #define PRT_TCTUPR_UP7_S 28 8586 #define PRT_TCTUPR_UP7_M MAKEMASK(0x7, 28) 8587 #define GLHH_ART_CTL 0x000A41D4 /* Reset Source: POR */ 8588 #define GLHH_ART_CTL_ACTIVE_S 0 8589 #define GLHH_ART_CTL_ACTIVE_M BIT(0) 8590 #define GLHH_ART_CTL_TIME_OUT1_S 1 8591 #define GLHH_ART_CTL_TIME_OUT1_M BIT(1) 8592 #define GLHH_ART_CTL_TIME_OUT2_S 2 8593 #define GLHH_ART_CTL_TIME_OUT2_M BIT(2) 8594 #define GLHH_ART_CTL_RESET_HH_S 31 8595 #define GLHH_ART_CTL_RESET_HH_M BIT(31) 8596 #define GLHH_ART_DATA 0x000A41E0 /* Reset Source: POR */ 8597 #define GLHH_ART_DATA_AGENT_TYPE_S 0 8598 #define GLHH_ART_DATA_AGENT_TYPE_M MAKEMASK(0x7, 0) 8599 #define GLHH_ART_DATA_SYNC_TYPE_S 3 8600 #define GLHH_ART_DATA_SYNC_TYPE_M BIT(3) 8601 #define GLHH_ART_DATA_MAX_DELAY_S 4 8602 #define GLHH_ART_DATA_MAX_DELAY_M MAKEMASK(0xF, 4) 8603 #define GLHH_ART_DATA_TIME_BASE_S 8 8604 #define GLHH_ART_DATA_TIME_BASE_M MAKEMASK(0xF, 8) 8605 #define GLHH_ART_DATA_RSV_DATA_S 12 8606 #define GLHH_ART_DATA_RSV_DATA_M MAKEMASK(0xFFFFF, 12) 8607 #define GLHH_ART_TIME_H 0x000A41D8 /* Reset Source: POR */ 8608 #define GLHH_ART_TIME_H_ART_TIME_H_S 0 8609 #define GLHH_ART_TIME_H_ART_TIME_H_M MAKEMASK(0xFFFFFFFF, 0) 8610 #define GLHH_ART_TIME_L 0x000A41DC /* Reset Source: POR */ 8611 #define GLHH_ART_TIME_L_ART_TIME_L_S 0 8612 #define GLHH_ART_TIME_L_ART_TIME_L_M MAKEMASK(0xFFFFFFFF, 0) 8613 #define GLTSYN_AUX_IN_0(_i) (0x000889D8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8614 #define GLTSYN_AUX_IN_0_MAX_INDEX 1 8615 #define GLTSYN_AUX_IN_0_EVNTLVL_S 0 8616 #define GLTSYN_AUX_IN_0_EVNTLVL_M MAKEMASK(0x3, 0) 8617 #define GLTSYN_AUX_IN_0_INT_ENA_S 4 8618 #define GLTSYN_AUX_IN_0_INT_ENA_M BIT(4) 8619 #define GLTSYN_AUX_IN_1(_i) (0x000889E0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8620 #define GLTSYN_AUX_IN_1_MAX_INDEX 1 8621 #define GLTSYN_AUX_IN_1_EVNTLVL_S 0 8622 #define GLTSYN_AUX_IN_1_EVNTLVL_M MAKEMASK(0x3, 0) 8623 #define GLTSYN_AUX_IN_1_INT_ENA_S 4 8624 #define GLTSYN_AUX_IN_1_INT_ENA_M BIT(4) 8625 #define GLTSYN_AUX_IN_2(_i) (0x000889E8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8626 #define GLTSYN_AUX_IN_2_MAX_INDEX 1 8627 #define GLTSYN_AUX_IN_2_EVNTLVL_S 0 8628 #define GLTSYN_AUX_IN_2_EVNTLVL_M MAKEMASK(0x3, 0) 8629 #define GLTSYN_AUX_IN_2_INT_ENA_S 4 8630 #define GLTSYN_AUX_IN_2_INT_ENA_M BIT(4) 8631 #define GLTSYN_AUX_OUT_0(_i) (0x00088998 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8632 #define GLTSYN_AUX_OUT_0_MAX_INDEX 1 8633 #define GLTSYN_AUX_OUT_0_OUT_ENA_S 0 8634 #define GLTSYN_AUX_OUT_0_OUT_ENA_M BIT(0) 8635 #define GLTSYN_AUX_OUT_0_OUTMOD_S 1 8636 #define GLTSYN_AUX_OUT_0_OUTMOD_M MAKEMASK(0x3, 1) 8637 #define GLTSYN_AUX_OUT_0_OUTLVL_S 3 8638 #define GLTSYN_AUX_OUT_0_OUTLVL_M BIT(3) 8639 #define GLTSYN_AUX_OUT_0_INT_ENA_S 4 8640 #define GLTSYN_AUX_OUT_0_INT_ENA_M BIT(4) 8641 #define GLTSYN_AUX_OUT_0_PULSEW_S 8 8642 #define GLTSYN_AUX_OUT_0_PULSEW_M MAKEMASK(0xF, 8) 8643 #define GLTSYN_AUX_OUT_1(_i) (0x000889A0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8644 #define GLTSYN_AUX_OUT_1_MAX_INDEX 1 8645 #define GLTSYN_AUX_OUT_1_OUT_ENA_S 0 8646 #define GLTSYN_AUX_OUT_1_OUT_ENA_M BIT(0) 8647 #define GLTSYN_AUX_OUT_1_OUTMOD_S 1 8648 #define GLTSYN_AUX_OUT_1_OUTMOD_M MAKEMASK(0x3, 1) 8649 #define GLTSYN_AUX_OUT_1_OUTLVL_S 3 8650 #define GLTSYN_AUX_OUT_1_OUTLVL_M BIT(3) 8651 #define GLTSYN_AUX_OUT_1_INT_ENA_S 4 8652 #define GLTSYN_AUX_OUT_1_INT_ENA_M BIT(4) 8653 #define GLTSYN_AUX_OUT_1_PULSEW_S 8 8654 #define GLTSYN_AUX_OUT_1_PULSEW_M MAKEMASK(0xF, 8) 8655 #define GLTSYN_AUX_OUT_2(_i) (0x000889A8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8656 #define GLTSYN_AUX_OUT_2_MAX_INDEX 1 8657 #define GLTSYN_AUX_OUT_2_OUT_ENA_S 0 8658 #define GLTSYN_AUX_OUT_2_OUT_ENA_M BIT(0) 8659 #define GLTSYN_AUX_OUT_2_OUTMOD_S 1 8660 #define GLTSYN_AUX_OUT_2_OUTMOD_M MAKEMASK(0x3, 1) 8661 #define GLTSYN_AUX_OUT_2_OUTLVL_S 3 8662 #define GLTSYN_AUX_OUT_2_OUTLVL_M BIT(3) 8663 #define GLTSYN_AUX_OUT_2_INT_ENA_S 4 8664 #define GLTSYN_AUX_OUT_2_INT_ENA_M BIT(4) 8665 #define GLTSYN_AUX_OUT_2_PULSEW_S 8 8666 #define GLTSYN_AUX_OUT_2_PULSEW_M MAKEMASK(0xF, 8) 8667 #define GLTSYN_AUX_OUT_3(_i) (0x000889B0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8668 #define GLTSYN_AUX_OUT_3_MAX_INDEX 1 8669 #define GLTSYN_AUX_OUT_3_OUT_ENA_S 0 8670 #define GLTSYN_AUX_OUT_3_OUT_ENA_M BIT(0) 8671 #define GLTSYN_AUX_OUT_3_OUTMOD_S 1 8672 #define GLTSYN_AUX_OUT_3_OUTMOD_M MAKEMASK(0x3, 1) 8673 #define GLTSYN_AUX_OUT_3_OUTLVL_S 3 8674 #define GLTSYN_AUX_OUT_3_OUTLVL_M BIT(3) 8675 #define GLTSYN_AUX_OUT_3_INT_ENA_S 4 8676 #define GLTSYN_AUX_OUT_3_INT_ENA_M BIT(4) 8677 #define GLTSYN_AUX_OUT_3_PULSEW_S 8 8678 #define GLTSYN_AUX_OUT_3_PULSEW_M MAKEMASK(0xF, 8) 8679 #define GLTSYN_CLKO_0(_i) (0x000889B8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8680 #define GLTSYN_CLKO_0_MAX_INDEX 1 8681 #define GLTSYN_CLKO_0_TSYNCLKO_S 0 8682 #define GLTSYN_CLKO_0_TSYNCLKO_M MAKEMASK(0xFFFFFFFF, 0) 8683 #define GLTSYN_CLKO_1(_i) (0x000889C0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8684 #define GLTSYN_CLKO_1_MAX_INDEX 1 8685 #define GLTSYN_CLKO_1_TSYNCLKO_S 0 8686 #define GLTSYN_CLKO_1_TSYNCLKO_M MAKEMASK(0xFFFFFFFF, 0) 8687 #define GLTSYN_CLKO_2(_i) (0x000889C8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8688 #define GLTSYN_CLKO_2_MAX_INDEX 1 8689 #define GLTSYN_CLKO_2_TSYNCLKO_S 0 8690 #define GLTSYN_CLKO_2_TSYNCLKO_M MAKEMASK(0xFFFFFFFF, 0) 8691 #define GLTSYN_CLKO_3(_i) (0x000889D0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8692 #define GLTSYN_CLKO_3_MAX_INDEX 1 8693 #define GLTSYN_CLKO_3_TSYNCLKO_S 0 8694 #define GLTSYN_CLKO_3_TSYNCLKO_M MAKEMASK(0xFFFFFFFF, 0) 8695 #define GLTSYN_CMD 0x00088810 /* Reset Source: CORER */ 8696 #define GLTSYN_CMD_CMD_S 0 8697 #define GLTSYN_CMD_CMD_M MAKEMASK(0xFF, 0) 8698 #define GLTSYN_CMD_SEL_MASTER_S 8 8699 #define GLTSYN_CMD_SEL_MASTER_M BIT(8) 8700 #define GLTSYN_CMD_SYNC 0x00088814 /* Reset Source: CORER */ 8701 #define GLTSYN_CMD_SYNC_SYNC_S 0 8702 #define GLTSYN_CMD_SYNC_SYNC_M MAKEMASK(0x3, 0) 8703 #define GLTSYN_ENA(_i) (0x00088808 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8704 #define GLTSYN_ENA_MAX_INDEX 1 8705 #define GLTSYN_ENA_TSYN_ENA_S 0 8706 #define GLTSYN_ENA_TSYN_ENA_M BIT(0) 8707 #define GLTSYN_EVNT_H_0(_i) (0x00088970 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8708 #define GLTSYN_EVNT_H_0_MAX_INDEX 1 8709 #define GLTSYN_EVNT_H_0_TSYNEVNT_H_S 0 8710 #define GLTSYN_EVNT_H_0_TSYNEVNT_H_M MAKEMASK(0xFFFFFFFF, 0) 8711 #define GLTSYN_EVNT_H_1(_i) (0x00088980 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8712 #define GLTSYN_EVNT_H_1_MAX_INDEX 1 8713 #define GLTSYN_EVNT_H_1_TSYNEVNT_H_S 0 8714 #define GLTSYN_EVNT_H_1_TSYNEVNT_H_M MAKEMASK(0xFFFFFFFF, 0) 8715 #define GLTSYN_EVNT_H_2(_i) (0x00088990 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8716 #define GLTSYN_EVNT_H_2_MAX_INDEX 1 8717 #define GLTSYN_EVNT_H_2_TSYNEVNT_H_S 0 8718 #define GLTSYN_EVNT_H_2_TSYNEVNT_H_M MAKEMASK(0xFFFFFFFF, 0) 8719 #define GLTSYN_EVNT_L_0(_i) (0x00088968 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8720 #define GLTSYN_EVNT_L_0_MAX_INDEX 1 8721 #define GLTSYN_EVNT_L_0_TSYNEVNT_L_S 0 8722 #define GLTSYN_EVNT_L_0_TSYNEVNT_L_M MAKEMASK(0xFFFFFFFF, 0) 8723 #define GLTSYN_EVNT_L_1(_i) (0x00088978 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8724 #define GLTSYN_EVNT_L_1_MAX_INDEX 1 8725 #define GLTSYN_EVNT_L_1_TSYNEVNT_L_S 0 8726 #define GLTSYN_EVNT_L_1_TSYNEVNT_L_M MAKEMASK(0xFFFFFFFF, 0) 8727 #define GLTSYN_EVNT_L_2(_i) (0x00088988 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8728 #define GLTSYN_EVNT_L_2_MAX_INDEX 1 8729 #define GLTSYN_EVNT_L_2_TSYNEVNT_L_S 0 8730 #define GLTSYN_EVNT_L_2_TSYNEVNT_L_M MAKEMASK(0xFFFFFFFF, 0) 8731 #define GLTSYN_HHTIME_H(_i) (0x00088900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8732 #define GLTSYN_HHTIME_H_MAX_INDEX 1 8733 #define GLTSYN_HHTIME_H_TSYNEVNT_H_S 0 8734 #define GLTSYN_HHTIME_H_TSYNEVNT_H_M MAKEMASK(0xFFFFFFFF, 0) 8735 #define GLTSYN_HHTIME_L(_i) (0x000888F8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8736 #define GLTSYN_HHTIME_L_MAX_INDEX 1 8737 #define GLTSYN_HHTIME_L_TSYNEVNT_L_S 0 8738 #define GLTSYN_HHTIME_L_TSYNEVNT_L_M MAKEMASK(0xFFFFFFFF, 0) 8739 #define GLTSYN_INCVAL_H(_i) (0x00088920 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8740 #define GLTSYN_INCVAL_H_MAX_INDEX 1 8741 #define GLTSYN_INCVAL_H_INCVAL_H_S 0 8742 #define GLTSYN_INCVAL_H_INCVAL_H_M MAKEMASK(0xFF, 0) 8743 #define GLTSYN_INCVAL_L(_i) (0x00088918 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8744 #define GLTSYN_INCVAL_L_MAX_INDEX 1 8745 #define GLTSYN_INCVAL_L_INCVAL_L_S 0 8746 #define GLTSYN_INCVAL_L_INCVAL_L_M MAKEMASK(0xFFFFFFFF, 0) 8747 #define GLTSYN_SHADJ_H(_i) (0x00088910 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8748 #define GLTSYN_SHADJ_H_MAX_INDEX 1 8749 #define GLTSYN_SHADJ_H_ADJUST_H_S 0 8750 #define GLTSYN_SHADJ_H_ADJUST_H_M MAKEMASK(0xFFFFFFFF, 0) 8751 #define GLTSYN_SHADJ_L(_i) (0x00088908 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8752 #define GLTSYN_SHADJ_L_MAX_INDEX 1 8753 #define GLTSYN_SHADJ_L_ADJUST_L_S 0 8754 #define GLTSYN_SHADJ_L_ADJUST_L_M MAKEMASK(0xFFFFFFFF, 0) 8755 #define GLTSYN_SHTIME_0(_i) (0x000888E0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8756 #define GLTSYN_SHTIME_0_MAX_INDEX 1 8757 #define GLTSYN_SHTIME_0_TSYNTIME_0_S 0 8758 #define GLTSYN_SHTIME_0_TSYNTIME_0_M MAKEMASK(0xFFFFFFFF, 0) 8759 #define GLTSYN_SHTIME_H(_i) (0x000888F0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8760 #define GLTSYN_SHTIME_H_MAX_INDEX 1 8761 #define GLTSYN_SHTIME_H_TSYNTIME_H_S 0 8762 #define GLTSYN_SHTIME_H_TSYNTIME_H_M MAKEMASK(0xFFFFFFFF, 0) 8763 #define GLTSYN_SHTIME_L(_i) (0x000888E8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8764 #define GLTSYN_SHTIME_L_MAX_INDEX 1 8765 #define GLTSYN_SHTIME_L_TSYNTIME_L_S 0 8766 #define GLTSYN_SHTIME_L_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0) 8767 #define GLTSYN_STAT(_i) (0x000888C0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8768 #define GLTSYN_STAT_MAX_INDEX 1 8769 #define GLTSYN_STAT_EVENT0_S 0 8770 #define GLTSYN_STAT_EVENT0_M BIT(0) 8771 #define GLTSYN_STAT_EVENT1_S 1 8772 #define GLTSYN_STAT_EVENT1_M BIT(1) 8773 #define GLTSYN_STAT_EVENT2_S 2 8774 #define GLTSYN_STAT_EVENT2_M BIT(2) 8775 #define GLTSYN_STAT_TGT0_S 4 8776 #define GLTSYN_STAT_TGT0_M BIT(4) 8777 #define GLTSYN_STAT_TGT1_S 5 8778 #define GLTSYN_STAT_TGT1_M BIT(5) 8779 #define GLTSYN_STAT_TGT2_S 6 8780 #define GLTSYN_STAT_TGT2_M BIT(6) 8781 #define GLTSYN_STAT_TGT3_S 7 8782 #define GLTSYN_STAT_TGT3_M BIT(7) 8783 #define GLTSYN_SYNC_DLAY 0x00088818 /* Reset Source: CORER */ 8784 #define GLTSYN_SYNC_DLAY_SYNC_DELAY_S 0 8785 #define GLTSYN_SYNC_DLAY_SYNC_DELAY_M MAKEMASK(0x1F, 0) 8786 #define GLTSYN_TGT_H_0(_i) (0x00088930 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8787 #define GLTSYN_TGT_H_0_MAX_INDEX 1 8788 #define GLTSYN_TGT_H_0_TSYNTGTT_H_S 0 8789 #define GLTSYN_TGT_H_0_TSYNTGTT_H_M MAKEMASK(0xFFFFFFFF, 0) 8790 #define GLTSYN_TGT_H_1(_i) (0x00088940 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8791 #define GLTSYN_TGT_H_1_MAX_INDEX 1 8792 #define GLTSYN_TGT_H_1_TSYNTGTT_H_S 0 8793 #define GLTSYN_TGT_H_1_TSYNTGTT_H_M MAKEMASK(0xFFFFFFFF, 0) 8794 #define GLTSYN_TGT_H_2(_i) (0x00088950 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8795 #define GLTSYN_TGT_H_2_MAX_INDEX 1 8796 #define GLTSYN_TGT_H_2_TSYNTGTT_H_S 0 8797 #define GLTSYN_TGT_H_2_TSYNTGTT_H_M MAKEMASK(0xFFFFFFFF, 0) 8798 #define GLTSYN_TGT_H_3(_i) (0x00088960 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8799 #define GLTSYN_TGT_H_3_MAX_INDEX 1 8800 #define GLTSYN_TGT_H_3_TSYNTGTT_H_S 0 8801 #define GLTSYN_TGT_H_3_TSYNTGTT_H_M MAKEMASK(0xFFFFFFFF, 0) 8802 #define GLTSYN_TGT_L_0(_i) (0x00088928 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8803 #define GLTSYN_TGT_L_0_MAX_INDEX 1 8804 #define GLTSYN_TGT_L_0_TSYNTGTT_L_S 0 8805 #define GLTSYN_TGT_L_0_TSYNTGTT_L_M MAKEMASK(0xFFFFFFFF, 0) 8806 #define GLTSYN_TGT_L_1(_i) (0x00088938 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8807 #define GLTSYN_TGT_L_1_MAX_INDEX 1 8808 #define GLTSYN_TGT_L_1_TSYNTGTT_L_S 0 8809 #define GLTSYN_TGT_L_1_TSYNTGTT_L_M MAKEMASK(0xFFFFFFFF, 0) 8810 #define GLTSYN_TGT_L_2(_i) (0x00088948 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8811 #define GLTSYN_TGT_L_2_MAX_INDEX 1 8812 #define GLTSYN_TGT_L_2_TSYNTGTT_L_S 0 8813 #define GLTSYN_TGT_L_2_TSYNTGTT_L_M MAKEMASK(0xFFFFFFFF, 0) 8814 #define GLTSYN_TGT_L_3(_i) (0x00088958 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8815 #define GLTSYN_TGT_L_3_MAX_INDEX 1 8816 #define GLTSYN_TGT_L_3_TSYNTGTT_L_S 0 8817 #define GLTSYN_TGT_L_3_TSYNTGTT_L_M MAKEMASK(0xFFFFFFFF, 0) 8818 #define GLTSYN_TIME_0(_i) (0x000888C8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8819 #define GLTSYN_TIME_0_MAX_INDEX 1 8820 #define GLTSYN_TIME_0_TSYNTIME_0_S 0 8821 #define GLTSYN_TIME_0_TSYNTIME_0_M MAKEMASK(0xFFFFFFFF, 0) 8822 #define GLTSYN_TIME_H(_i) (0x000888D8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8823 #define GLTSYN_TIME_H_MAX_INDEX 1 8824 #define GLTSYN_TIME_H_TSYNTIME_H_S 0 8825 #define GLTSYN_TIME_H_TSYNTIME_H_M MAKEMASK(0xFFFFFFFF, 0) 8826 #define GLTSYN_TIME_L(_i) (0x000888D0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 8827 #define GLTSYN_TIME_L_MAX_INDEX 1 8828 #define GLTSYN_TIME_L_TSYNTIME_L_S 0 8829 #define GLTSYN_TIME_L_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0) 8830 #define PFHH_SEM 0x000A4200 /* Reset Source: PFR */ 8831 #define PFHH_SEM_BUSY_S 0 8832 #define PFHH_SEM_BUSY_M BIT(0) 8833 #define PFHH_SEM_PF_OWNER_S 4 8834 #define PFHH_SEM_PF_OWNER_M MAKEMASK(0x7, 4) 8835 #define PFTSYN_SEM 0x00088880 /* Reset Source: PFR */ 8836 #define PFTSYN_SEM_BUSY_S 0 8837 #define PFTSYN_SEM_BUSY_M BIT(0) 8838 #define PFTSYN_SEM_PF_OWNER_S 4 8839 #define PFTSYN_SEM_PF_OWNER_M MAKEMASK(0x7, 4) 8840 #define GLPE_TSCD_FLR(_i) (0x0051E24C + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */ 8841 #define GLPE_TSCD_FLR_MAX_INDEX 3 8842 #define GLPE_TSCD_FLR_DRAIN_VCTR_ID_S 0 8843 #define GLPE_TSCD_FLR_DRAIN_VCTR_ID_M MAKEMASK(0x3, 0) 8844 #define GLPE_TSCD_FLR_PORT_S 2 8845 #define GLPE_TSCD_FLR_PORT_M MAKEMASK(0x7, 2) 8846 #define GLPE_TSCD_FLR_PF_NUM_S 5 8847 #define GLPE_TSCD_FLR_PF_NUM_M MAKEMASK(0x7, 5) 8848 #define GLPE_TSCD_FLR_VM_VF_TYPE_S 8 8849 #define GLPE_TSCD_FLR_VM_VF_TYPE_M MAKEMASK(0x3, 8) 8850 #define GLPE_TSCD_FLR_VM_VF_NUM_S 16 8851 #define GLPE_TSCD_FLR_VM_VF_NUM_M MAKEMASK(0x3FF, 16) 8852 #define GLPE_TSCD_FLR_VLD_S 31 8853 #define GLPE_TSCD_FLR_VLD_M BIT(31) 8854 #define GLPE_TSCD_PEPM 0x0051E228 /* Reset Source: CORER */ 8855 #define GLPE_TSCD_PEPM_MDQ_CREDITS_S 0 8856 #define GLPE_TSCD_PEPM_MDQ_CREDITS_M MAKEMASK(0xFF, 0) 8857 #define PF_VIRT_VSTATUS 0x0009E680 /* Reset Source: PFR */ 8858 #define PF_VIRT_VSTATUS_NUM_VFS_S 0 8859 #define PF_VIRT_VSTATUS_NUM_VFS_M MAKEMASK(0xFF, 0) 8860 #define PF_VIRT_VSTATUS_TOTAL_VFS_S 8 8861 #define PF_VIRT_VSTATUS_TOTAL_VFS_M MAKEMASK(0xFF, 8) 8862 #define PF_VIRT_VSTATUS_IOV_ACTIVE_S 16 8863 #define PF_VIRT_VSTATUS_IOV_ACTIVE_M BIT(16) 8864 #define PF_VT_PFALLOC 0x001D2480 /* Reset Source: CORER */ 8865 #define PF_VT_PFALLOC_FIRSTVF_S 0 8866 #define PF_VT_PFALLOC_FIRSTVF_M MAKEMASK(0xFF, 0) 8867 #define PF_VT_PFALLOC_LASTVF_S 8 8868 #define PF_VT_PFALLOC_LASTVF_M MAKEMASK(0xFF, 8) 8869 #define PF_VT_PFALLOC_VALID_S 31 8870 #define PF_VT_PFALLOC_VALID_M BIT(31) 8871 #define PF_VT_PFALLOC_HIF 0x0009DD80 /* Reset Source: PCIR */ 8872 #define PF_VT_PFALLOC_HIF_FIRSTVF_S 0 8873 #define PF_VT_PFALLOC_HIF_FIRSTVF_M MAKEMASK(0xFF, 0) 8874 #define PF_VT_PFALLOC_HIF_LASTVF_S 8 8875 #define PF_VT_PFALLOC_HIF_LASTVF_M MAKEMASK(0xFF, 8) 8876 #define PF_VT_PFALLOC_HIF_VALID_S 31 8877 #define PF_VT_PFALLOC_HIF_VALID_M BIT(31) 8878 #define PF_VT_PFALLOC_PCIE 0x000BE080 /* Reset Source: PCIR */ 8879 #define PF_VT_PFALLOC_PCIE_FIRSTVF_S 0 8880 #define PF_VT_PFALLOC_PCIE_FIRSTVF_M MAKEMASK(0xFF, 0) 8881 #define PF_VT_PFALLOC_PCIE_LASTVF_S 8 8882 #define PF_VT_PFALLOC_PCIE_LASTVF_M MAKEMASK(0xFF, 8) 8883 #define PF_VT_PFALLOC_PCIE_VALID_S 31 8884 #define PF_VT_PFALLOC_PCIE_VALID_M BIT(31) 8885 #define VSI_L2TAGSTXVALID(_VSI) (0x00046000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 8886 #define VSI_L2TAGSTXVALID_MAX_INDEX 767 8887 #define VSI_L2TAGSTXVALID_L2TAG1INSERTID_S 0 8888 #define VSI_L2TAGSTXVALID_L2TAG1INSERTID_M MAKEMASK(0x7, 0) 8889 #define VSI_L2TAGSTXVALID_L2TAG1INSERTID_VALID_S 3 8890 #define VSI_L2TAGSTXVALID_L2TAG1INSERTID_VALID_M BIT(3) 8891 #define VSI_L2TAGSTXVALID_L2TAG2INSERTID_S 4 8892 #define VSI_L2TAGSTXVALID_L2TAG2INSERTID_M MAKEMASK(0x7, 4) 8893 #define VSI_L2TAGSTXVALID_L2TAG2INSERTID_VALID_S 7 8894 #define VSI_L2TAGSTXVALID_L2TAG2INSERTID_VALID_M BIT(7) 8895 #define VSI_L2TAGSTXVALID_TIR0INSERTID_S 16 8896 #define VSI_L2TAGSTXVALID_TIR0INSERTID_M MAKEMASK(0x7, 16) 8897 #define VSI_L2TAGSTXVALID_TIR0_INSERT_S 19 8898 #define VSI_L2TAGSTXVALID_TIR0_INSERT_M BIT(19) 8899 #define VSI_L2TAGSTXVALID_TIR1INSERTID_S 20 8900 #define VSI_L2TAGSTXVALID_TIR1INSERTID_M MAKEMASK(0x7, 20) 8901 #define VSI_L2TAGSTXVALID_TIR1_INSERT_S 23 8902 #define VSI_L2TAGSTXVALID_TIR1_INSERT_M BIT(23) 8903 #define VSI_L2TAGSTXVALID_TIR2INSERTID_S 24 8904 #define VSI_L2TAGSTXVALID_TIR2INSERTID_M MAKEMASK(0x7, 24) 8905 #define VSI_L2TAGSTXVALID_TIR2_INSERT_S 27 8906 #define VSI_L2TAGSTXVALID_TIR2_INSERT_M BIT(27) 8907 #define VSI_PASID(_VSI) (0x0009C000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */ 8908 #define VSI_PASID_MAX_INDEX 767 8909 #define VSI_PASID_PASID_S 0 8910 #define VSI_PASID_PASID_M MAKEMASK(0xFFFFF, 0) 8911 #define VSI_PASID_EN_S 31 8912 #define VSI_PASID_EN_M BIT(31) 8913 #define VSI_RUPR(_VSI) (0x00050000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 8914 #define VSI_RUPR_MAX_INDEX 767 8915 #define VSI_RUPR_UP0_S 0 8916 #define VSI_RUPR_UP0_M MAKEMASK(0x7, 0) 8917 #define VSI_RUPR_UP1_S 3 8918 #define VSI_RUPR_UP1_M MAKEMASK(0x7, 3) 8919 #define VSI_RUPR_UP2_S 6 8920 #define VSI_RUPR_UP2_M MAKEMASK(0x7, 6) 8921 #define VSI_RUPR_UP3_S 9 8922 #define VSI_RUPR_UP3_M MAKEMASK(0x7, 9) 8923 #define VSI_RUPR_UP4_S 12 8924 #define VSI_RUPR_UP4_M MAKEMASK(0x7, 12) 8925 #define VSI_RUPR_UP5_S 15 8926 #define VSI_RUPR_UP5_M MAKEMASK(0x7, 15) 8927 #define VSI_RUPR_UP6_S 18 8928 #define VSI_RUPR_UP6_M MAKEMASK(0x7, 18) 8929 #define VSI_RUPR_UP7_S 21 8930 #define VSI_RUPR_UP7_M MAKEMASK(0x7, 21) 8931 #define VSI_RXSWCTRL(_VSI) (0x00205000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 8932 #define VSI_RXSWCTRL_MAX_INDEX 767 8933 #define VSI_RXSWCTRL_MACVSIPRUNEENABLE_S 8 8934 #define VSI_RXSWCTRL_MACVSIPRUNEENABLE_M BIT(8) 8935 #define VSI_RXSWCTRL_PRUNEENABLE_S 9 8936 #define VSI_RXSWCTRL_PRUNEENABLE_M MAKEMASK(0xF, 9) 8937 #define VSI_RXSWCTRL_SRCPRUNEENABLE_S 13 8938 #define VSI_RXSWCTRL_SRCPRUNEENABLE_M BIT(13) 8939 #define VSI_SRCSWCTRL(_VSI) (0x00209000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 8940 #define VSI_SRCSWCTRL_MAX_INDEX 767 8941 #define VSI_SRCSWCTRL_ALLOWDESTOVERRIDE_S 0 8942 #define VSI_SRCSWCTRL_ALLOWDESTOVERRIDE_M BIT(0) 8943 #define VSI_SRCSWCTRL_ALLOWLOOPBACK_S 1 8944 #define VSI_SRCSWCTRL_ALLOWLOOPBACK_M BIT(1) 8945 #define VSI_SRCSWCTRL_LANENABLE_S 2 8946 #define VSI_SRCSWCTRL_LANENABLE_M BIT(2) 8947 #define VSI_SRCSWCTRL_MACAS_S 3 8948 #define VSI_SRCSWCTRL_MACAS_M BIT(3) 8949 #define VSI_SRCSWCTRL_PRUNEENABLE_S 4 8950 #define VSI_SRCSWCTRL_PRUNEENABLE_M MAKEMASK(0xF, 4) 8951 #define VSI_SWITCHID(_VSI) (0x00215000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 8952 #define VSI_SWITCHID_MAX_INDEX 767 8953 #define VSI_SWITCHID_SWITCHID_S 0 8954 #define VSI_SWITCHID_SWITCHID_M MAKEMASK(0xFF, 0) 8955 #define VSI_SWT_MIREG(_VSI) (0x00207000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 8956 #define VSI_SWT_MIREG_MAX_INDEX 767 8957 #define VSI_SWT_MIREG_MIRRULE_S 0 8958 #define VSI_SWT_MIREG_MIRRULE_M MAKEMASK(0x3F, 0) 8959 #define VSI_SWT_MIREG_MIRENA_S 7 8960 #define VSI_SWT_MIREG_MIRENA_M BIT(7) 8961 #define VSI_SWT_MIRIG(_VSI) (0x00208000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 8962 #define VSI_SWT_MIRIG_MAX_INDEX 767 8963 #define VSI_SWT_MIRIG_MIRRULE_S 0 8964 #define VSI_SWT_MIRIG_MIRRULE_M MAKEMASK(0x3F, 0) 8965 #define VSI_SWT_MIRIG_MIRENA_S 7 8966 #define VSI_SWT_MIRIG_MIRENA_M BIT(7) 8967 #define VSI_TAIR(_VSI) (0x00044000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */ 8968 #define VSI_TAIR_MAX_INDEX 767 8969 #define VSI_TAIR_PORT_TAG_ID_S 0 8970 #define VSI_TAIR_PORT_TAG_ID_M MAKEMASK(0xFFFF, 0) 8971 #define VSI_TAR(_VSI) (0x00045000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 8972 #define VSI_TAR_MAX_INDEX 767 8973 #define VSI_TAR_ACCEPTTAGGED_S 0 8974 #define VSI_TAR_ACCEPTTAGGED_M MAKEMASK(0x3FF, 0) 8975 #define VSI_TAR_ACCEPTUNTAGGED_S 16 8976 #define VSI_TAR_ACCEPTUNTAGGED_M MAKEMASK(0x3FF, 16) 8977 #define VSI_TIR_0(_VSI) (0x00041000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 8978 #define VSI_TIR_0_MAX_INDEX 767 8979 #define VSI_TIR_0_PORT_TAG_ID_S 0 8980 #define VSI_TIR_0_PORT_TAG_ID_M MAKEMASK(0xFFFF, 0) 8981 #define VSI_TIR_1(_VSI) (0x00042000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 8982 #define VSI_TIR_1_MAX_INDEX 767 8983 #define VSI_TIR_1_PORT_TAG_ID_S 0 8984 #define VSI_TIR_1_PORT_TAG_ID_M MAKEMASK(0xFFFFFFFF, 0) 8985 #define VSI_TIR_2(_VSI) (0x00043000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 8986 #define VSI_TIR_2_MAX_INDEX 767 8987 #define VSI_TIR_2_PORT_TAG_ID_S 0 8988 #define VSI_TIR_2_PORT_TAG_ID_M MAKEMASK(0xFFFF, 0) 8989 #define VSI_TSR(_VSI) (0x00051000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 8990 #define VSI_TSR_MAX_INDEX 767 8991 #define VSI_TSR_STRIPTAG_S 0 8992 #define VSI_TSR_STRIPTAG_M MAKEMASK(0x3FF, 0) 8993 #define VSI_TSR_SHOWTAG_S 10 8994 #define VSI_TSR_SHOWTAG_M MAKEMASK(0x3FF, 10) 8995 #define VSI_TSR_SHOWPRIONLY_S 20 8996 #define VSI_TSR_SHOWPRIONLY_M MAKEMASK(0x3FF, 20) 8997 #define VSI_TUPIOM(_VSI) (0x00048000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 8998 #define VSI_TUPIOM_MAX_INDEX 767 8999 #define VSI_TUPIOM_UP0_S 0 9000 #define VSI_TUPIOM_UP0_M MAKEMASK(0x7, 0) 9001 #define VSI_TUPIOM_UP1_S 3 9002 #define VSI_TUPIOM_UP1_M MAKEMASK(0x7, 3) 9003 #define VSI_TUPIOM_UP2_S 6 9004 #define VSI_TUPIOM_UP2_M MAKEMASK(0x7, 6) 9005 #define VSI_TUPIOM_UP3_S 9 9006 #define VSI_TUPIOM_UP3_M MAKEMASK(0x7, 9) 9007 #define VSI_TUPIOM_UP4_S 12 9008 #define VSI_TUPIOM_UP4_M MAKEMASK(0x7, 12) 9009 #define VSI_TUPIOM_UP5_S 15 9010 #define VSI_TUPIOM_UP5_M MAKEMASK(0x7, 15) 9011 #define VSI_TUPIOM_UP6_S 18 9012 #define VSI_TUPIOM_UP6_M MAKEMASK(0x7, 18) 9013 #define VSI_TUPIOM_UP7_S 21 9014 #define VSI_TUPIOM_UP7_M MAKEMASK(0x7, 21) 9015 #define VSI_TUPR(_VSI) (0x00047000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 9016 #define VSI_TUPR_MAX_INDEX 767 9017 #define VSI_TUPR_UP0_S 0 9018 #define VSI_TUPR_UP0_M MAKEMASK(0x7, 0) 9019 #define VSI_TUPR_UP1_S 3 9020 #define VSI_TUPR_UP1_M MAKEMASK(0x7, 3) 9021 #define VSI_TUPR_UP2_S 6 9022 #define VSI_TUPR_UP2_M MAKEMASK(0x7, 6) 9023 #define VSI_TUPR_UP3_S 9 9024 #define VSI_TUPR_UP3_M MAKEMASK(0x7, 9) 9025 #define VSI_TUPR_UP4_S 12 9026 #define VSI_TUPR_UP4_M MAKEMASK(0x7, 12) 9027 #define VSI_TUPR_UP5_S 15 9028 #define VSI_TUPR_UP5_M MAKEMASK(0x7, 15) 9029 #define VSI_TUPR_UP6_S 18 9030 #define VSI_TUPR_UP6_M MAKEMASK(0x7, 18) 9031 #define VSI_TUPR_UP7_S 21 9032 #define VSI_TUPR_UP7_M MAKEMASK(0x7, 21) 9033 #define VSI_VSI2F(_VSI) (0x001D0000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */ 9034 #define VSI_VSI2F_MAX_INDEX 767 9035 #define VSI_VSI2F_VFVMNUMBER_S 0 9036 #define VSI_VSI2F_VFVMNUMBER_M MAKEMASK(0x3FF, 0) 9037 #define VSI_VSI2F_FUNCTIONTYPE_S 10 9038 #define VSI_VSI2F_FUNCTIONTYPE_M MAKEMASK(0x3, 10) 9039 #define VSI_VSI2F_PFNUMBER_S 12 9040 #define VSI_VSI2F_PFNUMBER_M MAKEMASK(0x7, 12) 9041 #define VSI_VSI2F_BUFFERNUMBER_S 16 9042 #define VSI_VSI2F_BUFFERNUMBER_M MAKEMASK(0x7, 16) 9043 #define VSI_VSI2F_VSI_NUMBER_S 20 9044 #define VSI_VSI2F_VSI_NUMBER_M MAKEMASK(0x3FF, 20) 9045 #define VSI_VSI2F_VSI_ENABLE_S 31 9046 #define VSI_VSI2F_VSI_ENABLE_M BIT(31) 9047 #define VSIQF_FD_CNT(_VSI) (0x00464000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */ 9048 #define VSIQF_FD_CNT_MAX_INDEX 767 9049 #define VSIQF_FD_CNT_FD_GCNT_S 0 9050 #define VSIQF_FD_CNT_FD_GCNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_VSIQF_FD_CNT_FD_GCNT_M : E800_VSIQF_FD_CNT_FD_GCNT_M) 9051 #define E800_VSIQF_FD_CNT_FD_GCNT_M MAKEMASK(0x3FFF, 0) 9052 #define E830_VSIQF_FD_CNT_FD_GCNT_M MAKEMASK(0xFFFF, 0) 9053 #define VSIQF_FD_CNT_FD_BCNT_S 16 9054 #define VSIQF_FD_CNT_FD_BCNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_VSIQF_FD_CNT_FD_BCNT_M : E800_VSIQF_FD_CNT_FD_BCNT_M) 9055 #define E800_VSIQF_FD_CNT_FD_BCNT_M MAKEMASK(0x3FFF, 16) 9056 #define E830_VSIQF_FD_CNT_FD_BCNT_M MAKEMASK(0xFFFF, 16) 9057 #define VSIQF_FD_CTL1(_VSI) (0x00411000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 9058 #define VSIQF_FD_CTL1_MAX_INDEX 767 9059 #define VSIQF_FD_CTL1_FLT_ENA_S 0 9060 #define VSIQF_FD_CTL1_FLT_ENA_M BIT(0) 9061 #define VSIQF_FD_CTL1_CFG_ENA_S 1 9062 #define VSIQF_FD_CTL1_CFG_ENA_M BIT(1) 9063 #define VSIQF_FD_CTL1_EVICT_ENA_S 2 9064 #define VSIQF_FD_CTL1_EVICT_ENA_M BIT(2) 9065 #define VSIQF_FD_DFLT(_VSI) (0x00457000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 9066 #define VSIQF_FD_DFLT_MAX_INDEX 767 9067 #define VSIQF_FD_DFLT_DEFLT_QINDX_S 0 9068 #define VSIQF_FD_DFLT_DEFLT_QINDX_M MAKEMASK(0x7FF, 0) 9069 #define VSIQF_FD_DFLT_DEFLT_TOQUEUE_S 12 9070 #define VSIQF_FD_DFLT_DEFLT_TOQUEUE_M MAKEMASK(0x7, 12) 9071 #define VSIQF_FD_DFLT_COMP_QINDX_S 16 9072 #define VSIQF_FD_DFLT_COMP_QINDX_M MAKEMASK(0x7FF, 16) 9073 #define VSIQF_FD_DFLT_DEFLT_QINDX_PRIO_S 28 9074 #define VSIQF_FD_DFLT_DEFLT_QINDX_PRIO_M MAKEMASK(0x7, 28) 9075 #define VSIQF_FD_DFLT_DEFLT_DROP_S 31 9076 #define VSIQF_FD_DFLT_DEFLT_DROP_M BIT(31) 9077 #define VSIQF_FD_SIZE(_VSI) (0x00462000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 9078 #define VSIQF_FD_SIZE_MAX_INDEX 767 9079 #define VSIQF_FD_SIZE_FD_GSIZE_S 0 9080 #define VSIQF_FD_SIZE_FD_GSIZE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_VSIQF_FD_SIZE_FD_GSIZE_M : E800_VSIQF_FD_SIZE_FD_GSIZE_M) 9081 #define E800_VSIQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0x3FFF, 0) 9082 #define E830_VSIQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0xFFFF, 0) 9083 #define VSIQF_FD_SIZE_FD_BSIZE_S 16 9084 #define VSIQF_FD_SIZE_FD_BSIZE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_VSIQF_FD_SIZE_FD_BSIZE_M : E800_VSIQF_FD_SIZE_FD_BSIZE_M) 9085 #define E800_VSIQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0x3FFF, 16) 9086 #define E830_VSIQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0xFFFF, 16) 9087 #define VSIQF_HASH_CTL(_VSI) (0x0040D000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 9088 #define VSIQF_HASH_CTL_MAX_INDEX 767 9089 #define VSIQF_HASH_CTL_HASH_LUT_SEL_S 0 9090 #define VSIQF_HASH_CTL_HASH_LUT_SEL_M MAKEMASK(0x3, 0) 9091 #define VSIQF_HASH_CTL_GLOB_LUT_S 2 9092 #define VSIQF_HASH_CTL_GLOB_LUT_M MAKEMASK(0xF, 2) 9093 #define VSIQF_HASH_CTL_HASH_SCHEME_S 6 9094 #define VSIQF_HASH_CTL_HASH_SCHEME_M MAKEMASK(0x3, 6) 9095 #define VSIQF_HASH_CTL_TC_OVER_SEL_S 8 9096 #define VSIQF_HASH_CTL_TC_OVER_SEL_M MAKEMASK(0x1F, 8) 9097 #define VSIQF_HASH_CTL_TC_OVER_ENA_S 15 9098 #define VSIQF_HASH_CTL_TC_OVER_ENA_M BIT(15) 9099 #define VSIQF_HKEY(_i, _VSI) (0x00400000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...12, _VSI=0...767 */ /* Reset Source: PFR */ 9100 #define VSIQF_HKEY_MAX_INDEX 12 9101 #define VSIQF_HKEY_KEY_0_S 0 9102 #define VSIQF_HKEY_KEY_0_M MAKEMASK(0xFF, 0) 9103 #define VSIQF_HKEY_KEY_1_S 8 9104 #define VSIQF_HKEY_KEY_1_M MAKEMASK(0xFF, 8) 9105 #define VSIQF_HKEY_KEY_2_S 16 9106 #define VSIQF_HKEY_KEY_2_M MAKEMASK(0xFF, 16) 9107 #define VSIQF_HKEY_KEY_3_S 24 9108 #define VSIQF_HKEY_KEY_3_M MAKEMASK(0xFF, 24) 9109 #define VSIQF_HLUT(_i, _VSI) (0x00420000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...15, _VSI=0...767 */ /* Reset Source: PFR */ 9110 #define VSIQF_HLUT_MAX_INDEX 15 9111 #define VSIQF_HLUT_LUT0_S 0 9112 #define VSIQF_HLUT_LUT0_M MAKEMASK(0xF, 0) 9113 #define VSIQF_HLUT_LUT1_S 8 9114 #define VSIQF_HLUT_LUT1_M MAKEMASK(0xF, 8) 9115 #define VSIQF_HLUT_LUT2_S 16 9116 #define VSIQF_HLUT_LUT2_M MAKEMASK(0xF, 16) 9117 #define VSIQF_HLUT_LUT3_S 24 9118 #define VSIQF_HLUT_LUT3_M MAKEMASK(0xF, 24) 9119 #define VSIQF_PE_CTL1(_VSI) (0x00414000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 9120 #define VSIQF_PE_CTL1_MAX_INDEX 767 9121 #define VSIQF_PE_CTL1_PE_FLTENA_S 0 9122 #define VSIQF_PE_CTL1_PE_FLTENA_M BIT(0) 9123 #define VSIQF_TC_REGION(_i, _VSI) (0x00448000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...3, _VSI=0...767 */ /* Reset Source: CORER */ 9124 #define VSIQF_TC_REGION_MAX_INDEX 3 9125 #define VSIQF_TC_REGION_TC_BASE0_S 0 9126 #define VSIQF_TC_REGION_TC_BASE0_M MAKEMASK(0x7FF, 0) 9127 #define VSIQF_TC_REGION_TC_SIZE0_S 11 9128 #define VSIQF_TC_REGION_TC_SIZE0_M MAKEMASK(0xF, 11) 9129 #define VSIQF_TC_REGION_TC_BASE1_S 16 9130 #define VSIQF_TC_REGION_TC_BASE1_M MAKEMASK(0x7FF, 16) 9131 #define VSIQF_TC_REGION_TC_SIZE1_S 27 9132 #define VSIQF_TC_REGION_TC_SIZE1_M MAKEMASK(0xF, 27) 9133 #define GLPM_WUMC 0x0009DEE4 /* Reset Source: POR */ 9134 #define GLPM_WUMC_MNG_WU_PF_S 16 9135 #define GLPM_WUMC_MNG_WU_PF_M MAKEMASK(0xFF, 16) 9136 #define PFPM_APM 0x000B8080 /* Reset Source: POR */ 9137 #define PFPM_APM_APME_S 0 9138 #define PFPM_APM_APME_M BIT(0) 9139 #define PFPM_WUC 0x0009DC80 /* Reset Source: POR */ 9140 #define PFPM_WUC_EN_APM_D0_S 5 9141 #define PFPM_WUC_EN_APM_D0_M BIT(5) 9142 #define PFPM_WUFC 0x0009DC00 /* Reset Source: POR */ 9143 #define PFPM_WUFC_LNKC_S 0 9144 #define PFPM_WUFC_LNKC_M BIT(0) 9145 #define PFPM_WUFC_MAG_S 1 9146 #define PFPM_WUFC_MAG_M BIT(1) 9147 #define PFPM_WUFC_MNG_S 3 9148 #define PFPM_WUFC_MNG_M BIT(3) 9149 #define PFPM_WUFC_FLX0_ACT_S 4 9150 #define PFPM_WUFC_FLX0_ACT_M BIT(4) 9151 #define PFPM_WUFC_FLX1_ACT_S 5 9152 #define PFPM_WUFC_FLX1_ACT_M BIT(5) 9153 #define PFPM_WUFC_FLX2_ACT_S 6 9154 #define PFPM_WUFC_FLX2_ACT_M BIT(6) 9155 #define PFPM_WUFC_FLX3_ACT_S 7 9156 #define PFPM_WUFC_FLX3_ACT_M BIT(7) 9157 #define PFPM_WUFC_FLX4_ACT_S 8 9158 #define PFPM_WUFC_FLX4_ACT_M BIT(8) 9159 #define PFPM_WUFC_FLX5_ACT_S 9 9160 #define PFPM_WUFC_FLX5_ACT_M BIT(9) 9161 #define PFPM_WUFC_FLX6_ACT_S 10 9162 #define PFPM_WUFC_FLX6_ACT_M BIT(10) 9163 #define PFPM_WUFC_FLX7_ACT_S 11 9164 #define PFPM_WUFC_FLX7_ACT_M BIT(11) 9165 #define PFPM_WUFC_FLX0_S 16 9166 #define PFPM_WUFC_FLX0_M BIT(16) 9167 #define PFPM_WUFC_FLX1_S 17 9168 #define PFPM_WUFC_FLX1_M BIT(17) 9169 #define PFPM_WUFC_FLX2_S 18 9170 #define PFPM_WUFC_FLX2_M BIT(18) 9171 #define PFPM_WUFC_FLX3_S 19 9172 #define PFPM_WUFC_FLX3_M BIT(19) 9173 #define PFPM_WUFC_FLX4_S 20 9174 #define PFPM_WUFC_FLX4_M BIT(20) 9175 #define PFPM_WUFC_FLX5_S 21 9176 #define PFPM_WUFC_FLX5_M BIT(21) 9177 #define PFPM_WUFC_FLX6_S 22 9178 #define PFPM_WUFC_FLX6_M BIT(22) 9179 #define PFPM_WUFC_FLX7_S 23 9180 #define PFPM_WUFC_FLX7_M BIT(23) 9181 #define PFPM_WUFC_FW_RST_WK_S 31 9182 #define PFPM_WUFC_FW_RST_WK_M BIT(31) 9183 #define PFPM_WUS 0x0009DB80 /* Reset Source: POR */ 9184 #define PFPM_WUS_LNKC_S 0 9185 #define PFPM_WUS_LNKC_M BIT(0) 9186 #define PFPM_WUS_MAG_S 1 9187 #define PFPM_WUS_MAG_M BIT(1) 9188 #define PFPM_WUS_PME_STATUS_S 2 9189 #define PFPM_WUS_PME_STATUS_M BIT(2) 9190 #define PFPM_WUS_MNG_S 3 9191 #define PFPM_WUS_MNG_M BIT(3) 9192 #define PFPM_WUS_FLX0_S 16 9193 #define PFPM_WUS_FLX0_M BIT(16) 9194 #define PFPM_WUS_FLX1_S 17 9195 #define PFPM_WUS_FLX1_M BIT(17) 9196 #define PFPM_WUS_FLX2_S 18 9197 #define PFPM_WUS_FLX2_M BIT(18) 9198 #define PFPM_WUS_FLX3_S 19 9199 #define PFPM_WUS_FLX3_M BIT(19) 9200 #define PFPM_WUS_FLX4_S 20 9201 #define PFPM_WUS_FLX4_M BIT(20) 9202 #define PFPM_WUS_FLX5_S 21 9203 #define PFPM_WUS_FLX5_M BIT(21) 9204 #define PFPM_WUS_FLX6_S 22 9205 #define PFPM_WUS_FLX6_M BIT(22) 9206 #define PFPM_WUS_FLX7_S 23 9207 #define PFPM_WUS_FLX7_M BIT(23) 9208 #define PFPM_WUS_FW_RST_WK_S 31 9209 #define PFPM_WUS_FW_RST_WK_M BIT(31) 9210 #define PRTPM_SAH_BY_MAC(hw, _i) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTPM_SAH(_i) : E800_PRTPM_SAH(_i)) 9211 #define E800_PRTPM_SAH(_i) (0x001E3BA0 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */ 9212 #define E830_PRTPM_SAH(_i) (0x001E2380 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */ 9213 #define PRTPM_SAH_MAX_INDEX 3 9214 #define PRTPM_SAH_PFPM_SAH_S 0 9215 #define PRTPM_SAH_PFPM_SAH_M MAKEMASK(0xFFFF, 0) 9216 #define PRTPM_SAH_PF_NUM_S 26 9217 #define PRTPM_SAH_PF_NUM_M MAKEMASK(0xF, 26) 9218 #define PRTPM_SAH_MC_MAG_EN_S 30 9219 #define PRTPM_SAH_MC_MAG_EN_M BIT(30) 9220 #define PRTPM_SAH_AV_S 31 9221 #define PRTPM_SAH_AV_M BIT(31) 9222 #define PRTPM_SAL_BY_MAC(hw, _i) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTPM_SAL(_i) : E800_PRTPM_SAL(_i)) 9223 #define E800_PRTPM_SAL(_i) (0x001E3B20 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */ 9224 #define E830_PRTPM_SAL(_i) (0x001E2300 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */ 9225 #define PRTPM_SAL_MAX_INDEX 3 9226 #define PRTPM_SAL_PFPM_SAL_S 0 9227 #define PRTPM_SAL_PFPM_SAL_M MAKEMASK(0xFFFFFFFF, 0) 9228 #define GLPE_CQM_FUNC_INVALIDATE 0x00503300 /* Reset Source: CORER */ 9229 #define GLPE_CQM_FUNC_INVALIDATE_PF_NUM_S 0 9230 #define GLPE_CQM_FUNC_INVALIDATE_PF_NUM_M MAKEMASK(0x7, 0) 9231 #define GLPE_CQM_FUNC_INVALIDATE_VM_VF_NUM_S 3 9232 #define GLPE_CQM_FUNC_INVALIDATE_VM_VF_NUM_M MAKEMASK(0x3FF, 3) 9233 #define GLPE_CQM_FUNC_INVALIDATE_VM_VF_TYPE_S 13 9234 #define GLPE_CQM_FUNC_INVALIDATE_VM_VF_TYPE_M MAKEMASK(0x3, 13) 9235 #define GLPE_CQM_FUNC_INVALIDATE_ENABLE_S 31 9236 #define GLPE_CQM_FUNC_INVALIDATE_ENABLE_M BIT(31) 9237 #define VFPE_MRTEIDXMASK_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_VFPE_MRTEIDXMASK : E800_VFPE_MRTEIDXMASK) 9238 #define E800_VFPE_MRTEIDXMASK 0x00009000 /* Reset Source: PFR */ 9239 #define E830_VFPE_MRTEIDXMASK(_VF) (0x00509800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */ 9240 #define VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_S 0 9241 #define VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_M MAKEMASK(0x1F, 0) 9242 #define GLTSYN_HH_DLAY 0x0008881C /* Reset Source: CORER */ 9243 #define GLTSYN_HH_DLAY_SYNC_DELAY_S 0 9244 #define GLTSYN_HH_DLAY_SYNC_DELAY_M MAKEMASK(0xF, 0) 9245 #define VF_MBX_ARQBAH1 0x00006000 /* Reset Source: CORER */ 9246 #define VF_MBX_ARQBAH1_ARQBAH_S 0 9247 #define VF_MBX_ARQBAH1_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 9248 #define VF_MBX_ARQBAL1 0x00006C00 /* Reset Source: CORER */ 9249 #define VF_MBX_ARQBAL1_ARQBAL_LSB_S 0 9250 #define VF_MBX_ARQBAL1_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 9251 #define VF_MBX_ARQBAL1_ARQBAL_S 6 9252 #define VF_MBX_ARQBAL1_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 9253 #define VF_MBX_ARQH1 0x00007400 /* Reset Source: CORER */ 9254 #define VF_MBX_ARQH1_ARQH_S 0 9255 #define VF_MBX_ARQH1_ARQH_M MAKEMASK(0x3FF, 0) 9256 #define VF_MBX_ARQLEN1 0x00008000 /* Reset Source: PFR */ 9257 #define VF_MBX_ARQLEN1_ARQLEN_S 0 9258 #define VF_MBX_ARQLEN1_ARQLEN_M MAKEMASK(0x3FF, 0) 9259 #define VF_MBX_ARQLEN1_ARQVFE_S 28 9260 #define VF_MBX_ARQLEN1_ARQVFE_M BIT(28) 9261 #define VF_MBX_ARQLEN1_ARQOVFL_S 29 9262 #define VF_MBX_ARQLEN1_ARQOVFL_M BIT(29) 9263 #define VF_MBX_ARQLEN1_ARQCRIT_S 30 9264 #define VF_MBX_ARQLEN1_ARQCRIT_M BIT(30) 9265 #define VF_MBX_ARQLEN1_ARQENABLE_S 31 9266 #define VF_MBX_ARQLEN1_ARQENABLE_M BIT(31) 9267 #define VF_MBX_ARQT1 0x00007000 /* Reset Source: CORER */ 9268 #define VF_MBX_ARQT1_ARQT_S 0 9269 #define VF_MBX_ARQT1_ARQT_M MAKEMASK(0x3FF, 0) 9270 #define VF_MBX_ATQBAH1 0x00007800 /* Reset Source: CORER */ 9271 #define VF_MBX_ATQBAH1_ATQBAH_S 0 9272 #define VF_MBX_ATQBAH1_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 9273 #define VF_MBX_ATQBAL1 0x00007C00 /* Reset Source: CORER */ 9274 #define VF_MBX_ATQBAL1_ATQBAL_S 6 9275 #define VF_MBX_ATQBAL1_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 9276 #define VF_MBX_ATQH1 0x00006400 /* Reset Source: CORER */ 9277 #define VF_MBX_ATQH1_ATQH_S 0 9278 #define VF_MBX_ATQH1_ATQH_M MAKEMASK(0x3FF, 0) 9279 #define VF_MBX_ATQLEN1 0x00006800 /* Reset Source: PFR */ 9280 #define VF_MBX_ATQLEN1_ATQLEN_S 0 9281 #define VF_MBX_ATQLEN1_ATQLEN_M MAKEMASK(0x3FF, 0) 9282 #define VF_MBX_ATQLEN1_ATQVFE_S 28 9283 #define VF_MBX_ATQLEN1_ATQVFE_M BIT(28) 9284 #define VF_MBX_ATQLEN1_ATQOVFL_S 29 9285 #define VF_MBX_ATQLEN1_ATQOVFL_M BIT(29) 9286 #define VF_MBX_ATQLEN1_ATQCRIT_S 30 9287 #define VF_MBX_ATQLEN1_ATQCRIT_M BIT(30) 9288 #define VF_MBX_ATQLEN1_ATQENABLE_S 31 9289 #define VF_MBX_ATQLEN1_ATQENABLE_M BIT(31) 9290 #define VF_MBX_ATQT1 0x00008400 /* Reset Source: CORER */ 9291 #define VF_MBX_ATQT1_ATQT_S 0 9292 #define VF_MBX_ATQT1_ATQT_M MAKEMASK(0x3FF, 0) 9293 #define PFPCI_VF_FLUSH_DONE1 0x0000E400 /* Reset Source: PCIR */ 9294 #define PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_S 0 9295 #define PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_M BIT(0) 9296 #define VFGEN_RSTAT1 0x00008800 /* Reset Source: VFR */ 9297 #define VFGEN_RSTAT1_VFR_STATE_S 0 9298 #define VFGEN_RSTAT1_VFR_STATE_M MAKEMASK(0x3, 0) 9299 #define VFINT_DYN_CTL0 0x00005C00 /* Reset Source: CORER */ 9300 #define VFINT_DYN_CTL0_INTENA_S 0 9301 #define VFINT_DYN_CTL0_INTENA_M BIT(0) 9302 #define VFINT_DYN_CTL0_CLEARPBA_S 1 9303 #define VFINT_DYN_CTL0_CLEARPBA_M BIT(1) 9304 #define VFINT_DYN_CTL0_SWINT_TRIG_S 2 9305 #define VFINT_DYN_CTL0_SWINT_TRIG_M BIT(2) 9306 #define VFINT_DYN_CTL0_ITR_INDX_S 3 9307 #define VFINT_DYN_CTL0_ITR_INDX_M MAKEMASK(0x3, 3) 9308 #define VFINT_DYN_CTL0_INTERVAL_S 5 9309 #define VFINT_DYN_CTL0_INTERVAL_M MAKEMASK(0xFFF, 5) 9310 #define VFINT_DYN_CTL0_SW_ITR_INDX_ENA_S 24 9311 #define VFINT_DYN_CTL0_SW_ITR_INDX_ENA_M BIT(24) 9312 #define VFINT_DYN_CTL0_SW_ITR_INDX_S 25 9313 #define VFINT_DYN_CTL0_SW_ITR_INDX_M MAKEMASK(0x3, 25) 9314 #define VFINT_DYN_CTL0_WB_ON_ITR_S 30 9315 #define VFINT_DYN_CTL0_WB_ON_ITR_M BIT(30) 9316 #define VFINT_DYN_CTL0_INTENA_MSK_S 31 9317 #define VFINT_DYN_CTL0_INTENA_MSK_M BIT(31) 9318 #define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 9319 #define VFINT_DYN_CTLN_MAX_INDEX 63 9320 #define VFINT_DYN_CTLN_INTENA_S 0 9321 #define VFINT_DYN_CTLN_INTENA_M BIT(0) 9322 #define VFINT_DYN_CTLN_CLEARPBA_S 1 9323 #define VFINT_DYN_CTLN_CLEARPBA_M BIT(1) 9324 #define VFINT_DYN_CTLN_SWINT_TRIG_S 2 9325 #define VFINT_DYN_CTLN_SWINT_TRIG_M BIT(2) 9326 #define VFINT_DYN_CTLN_ITR_INDX_S 3 9327 #define VFINT_DYN_CTLN_ITR_INDX_M MAKEMASK(0x3, 3) 9328 #define VFINT_DYN_CTLN_INTERVAL_S 5 9329 #define VFINT_DYN_CTLN_INTERVAL_M MAKEMASK(0xFFF, 5) 9330 #define VFINT_DYN_CTLN_SW_ITR_INDX_ENA_S 24 9331 #define VFINT_DYN_CTLN_SW_ITR_INDX_ENA_M BIT(24) 9332 #define VFINT_DYN_CTLN_SW_ITR_INDX_S 25 9333 #define VFINT_DYN_CTLN_SW_ITR_INDX_M MAKEMASK(0x3, 25) 9334 #define VFINT_DYN_CTLN_WB_ON_ITR_S 30 9335 #define VFINT_DYN_CTLN_WB_ON_ITR_M BIT(30) 9336 #define VFINT_DYN_CTLN_INTENA_MSK_S 31 9337 #define VFINT_DYN_CTLN_INTENA_MSK_M BIT(31) 9338 #define VFINT_ITR0(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */ 9339 #define VFINT_ITR0_MAX_INDEX 2 9340 #define VFINT_ITR0_INTERVAL_S 0 9341 #define VFINT_ITR0_INTERVAL_M MAKEMASK(0xFFF, 0) 9342 #define VFINT_ITRN_BY_MAC(hw, _i, _j) ((hw)->mac_type == ICE_MAC_E830 ? E830_VFINT_ITRN(_i, _j) : E800_VFINT_ITRN(_i, _j)) 9343 #define E800_VFINT_ITRN(_i, _j) (0x00002800 + ((_i) * 4 + (_j) * 12)) /* _i=0...2, _j=0...63 */ /* Reset Source: CORER */ 9344 #define E830_VFINT_ITRN(_i, _j) (0x00002800 + ((_i) * 4 + (_j) * 64)) /* _i=0...15, _j=0...2 */ /* Reset Source: CORER */ 9345 #define VFINT_ITRN_MAX_INDEX_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_VFINT_ITRN_MAX_INDEX : E800_VFINT_ITRN_MAX_INDEX) 9346 #define E800_VFINT_ITRN_MAX_INDEX 2 9347 #define E830_VFINT_ITRN_MAX_INDEX 15 9348 #define VFINT_ITRN_INTERVAL_S 0 9349 #define VFINT_ITRN_INTERVAL_M MAKEMASK(0xFFF, 0) 9350 #define QRX_TAIL1(_QRX) (0x00002000 + ((_QRX) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 9351 #define QRX_TAIL1_MAX_INDEX 255 9352 #define QRX_TAIL1_TAIL_S 0 9353 #define QRX_TAIL1_TAIL_M MAKEMASK(0x1FFF, 0) 9354 #define QTX_TAIL(_DBQM) (0x00000000 + ((_DBQM) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 9355 #define QTX_TAIL_MAX_INDEX 255 9356 #define QTX_TAIL_QTX_COMM_DBELL_S 0 9357 #define QTX_TAIL_QTX_COMM_DBELL_M MAKEMASK(0xFFFFFFFF, 0) 9358 #define VF_MBX_CPM_ARQBAH1 0x0000F060 /* Reset Source: CORER */ 9359 #define VF_MBX_CPM_ARQBAH1_ARQBAH_S 0 9360 #define VF_MBX_CPM_ARQBAH1_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 9361 #define VF_MBX_CPM_ARQBAL1 0x0000F050 /* Reset Source: CORER */ 9362 #define VF_MBX_CPM_ARQBAL1_ARQBAL_LSB_S 0 9363 #define VF_MBX_CPM_ARQBAL1_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 9364 #define VF_MBX_CPM_ARQBAL1_ARQBAL_S 6 9365 #define VF_MBX_CPM_ARQBAL1_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 9366 #define VF_MBX_CPM_ARQH1 0x0000F080 /* Reset Source: CORER */ 9367 #define VF_MBX_CPM_ARQH1_ARQH_S 0 9368 #define VF_MBX_CPM_ARQH1_ARQH_M MAKEMASK(0x3FF, 0) 9369 #define VF_MBX_CPM_ARQLEN1 0x0000F070 /* Reset Source: PFR */ 9370 #define VF_MBX_CPM_ARQLEN1_ARQLEN_S 0 9371 #define VF_MBX_CPM_ARQLEN1_ARQLEN_M MAKEMASK(0x3FF, 0) 9372 #define VF_MBX_CPM_ARQLEN1_ARQVFE_S 28 9373 #define VF_MBX_CPM_ARQLEN1_ARQVFE_M BIT(28) 9374 #define VF_MBX_CPM_ARQLEN1_ARQOVFL_S 29 9375 #define VF_MBX_CPM_ARQLEN1_ARQOVFL_M BIT(29) 9376 #define VF_MBX_CPM_ARQLEN1_ARQCRIT_S 30 9377 #define VF_MBX_CPM_ARQLEN1_ARQCRIT_M BIT(30) 9378 #define VF_MBX_CPM_ARQLEN1_ARQENABLE_S 31 9379 #define VF_MBX_CPM_ARQLEN1_ARQENABLE_M BIT(31) 9380 #define VF_MBX_CPM_ARQT1 0x0000F090 /* Reset Source: CORER */ 9381 #define VF_MBX_CPM_ARQT1_ARQT_S 0 9382 #define VF_MBX_CPM_ARQT1_ARQT_M MAKEMASK(0x3FF, 0) 9383 #define VF_MBX_CPM_ATQBAH1 0x0000F010 /* Reset Source: CORER */ 9384 #define VF_MBX_CPM_ATQBAH1_ATQBAH_S 0 9385 #define VF_MBX_CPM_ATQBAH1_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 9386 #define VF_MBX_CPM_ATQBAL1 0x0000F000 /* Reset Source: CORER */ 9387 #define VF_MBX_CPM_ATQBAL1_ATQBAL_S 6 9388 #define VF_MBX_CPM_ATQBAL1_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 9389 #define VF_MBX_CPM_ATQH1 0x0000F030 /* Reset Source: CORER */ 9390 #define VF_MBX_CPM_ATQH1_ATQH_S 0 9391 #define VF_MBX_CPM_ATQH1_ATQH_M MAKEMASK(0x3FF, 0) 9392 #define VF_MBX_CPM_ATQLEN1 0x0000F020 /* Reset Source: PFR */ 9393 #define VF_MBX_CPM_ATQLEN1_ATQLEN_S 0 9394 #define VF_MBX_CPM_ATQLEN1_ATQLEN_M MAKEMASK(0x3FF, 0) 9395 #define VF_MBX_CPM_ATQLEN1_ATQVFE_S 28 9396 #define VF_MBX_CPM_ATQLEN1_ATQVFE_M BIT(28) 9397 #define VF_MBX_CPM_ATQLEN1_ATQOVFL_S 29 9398 #define VF_MBX_CPM_ATQLEN1_ATQOVFL_M BIT(29) 9399 #define VF_MBX_CPM_ATQLEN1_ATQCRIT_S 30 9400 #define VF_MBX_CPM_ATQLEN1_ATQCRIT_M BIT(30) 9401 #define VF_MBX_CPM_ATQLEN1_ATQENABLE_S 31 9402 #define VF_MBX_CPM_ATQLEN1_ATQENABLE_M BIT(31) 9403 #define VF_MBX_CPM_ATQT1 0x0000F040 /* Reset Source: CORER */ 9404 #define VF_MBX_CPM_ATQT1_ATQT_S 0 9405 #define VF_MBX_CPM_ATQT1_ATQT_M MAKEMASK(0x3FF, 0) 9406 #define VF_MBX_HLP_ARQBAH1 0x00020060 /* Reset Source: CORER */ 9407 #define VF_MBX_HLP_ARQBAH1_ARQBAH_S 0 9408 #define VF_MBX_HLP_ARQBAH1_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 9409 #define VF_MBX_HLP_ARQBAL1 0x00020050 /* Reset Source: CORER */ 9410 #define VF_MBX_HLP_ARQBAL1_ARQBAL_LSB_S 0 9411 #define VF_MBX_HLP_ARQBAL1_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 9412 #define VF_MBX_HLP_ARQBAL1_ARQBAL_S 6 9413 #define VF_MBX_HLP_ARQBAL1_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 9414 #define VF_MBX_HLP_ARQH1 0x00020080 /* Reset Source: CORER */ 9415 #define VF_MBX_HLP_ARQH1_ARQH_S 0 9416 #define VF_MBX_HLP_ARQH1_ARQH_M MAKEMASK(0x3FF, 0) 9417 #define VF_MBX_HLP_ARQLEN1 0x00020070 /* Reset Source: PFR */ 9418 #define VF_MBX_HLP_ARQLEN1_ARQLEN_S 0 9419 #define VF_MBX_HLP_ARQLEN1_ARQLEN_M MAKEMASK(0x3FF, 0) 9420 #define VF_MBX_HLP_ARQLEN1_ARQVFE_S 28 9421 #define VF_MBX_HLP_ARQLEN1_ARQVFE_M BIT(28) 9422 #define VF_MBX_HLP_ARQLEN1_ARQOVFL_S 29 9423 #define VF_MBX_HLP_ARQLEN1_ARQOVFL_M BIT(29) 9424 #define VF_MBX_HLP_ARQLEN1_ARQCRIT_S 30 9425 #define VF_MBX_HLP_ARQLEN1_ARQCRIT_M BIT(30) 9426 #define VF_MBX_HLP_ARQLEN1_ARQENABLE_S 31 9427 #define VF_MBX_HLP_ARQLEN1_ARQENABLE_M BIT(31) 9428 #define VF_MBX_HLP_ARQT1 0x00020090 /* Reset Source: CORER */ 9429 #define VF_MBX_HLP_ARQT1_ARQT_S 0 9430 #define VF_MBX_HLP_ARQT1_ARQT_M MAKEMASK(0x3FF, 0) 9431 #define VF_MBX_HLP_ATQBAH1 0x00020010 /* Reset Source: CORER */ 9432 #define VF_MBX_HLP_ATQBAH1_ATQBAH_S 0 9433 #define VF_MBX_HLP_ATQBAH1_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 9434 #define VF_MBX_HLP_ATQBAL1 0x00020000 /* Reset Source: CORER */ 9435 #define VF_MBX_HLP_ATQBAL1_ATQBAL_S 6 9436 #define VF_MBX_HLP_ATQBAL1_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 9437 #define VF_MBX_HLP_ATQH1 0x00020030 /* Reset Source: CORER */ 9438 #define VF_MBX_HLP_ATQH1_ATQH_S 0 9439 #define VF_MBX_HLP_ATQH1_ATQH_M MAKEMASK(0x3FF, 0) 9440 #define VF_MBX_HLP_ATQLEN1 0x00020020 /* Reset Source: PFR */ 9441 #define VF_MBX_HLP_ATQLEN1_ATQLEN_S 0 9442 #define VF_MBX_HLP_ATQLEN1_ATQLEN_M MAKEMASK(0x3FF, 0) 9443 #define VF_MBX_HLP_ATQLEN1_ATQVFE_S 28 9444 #define VF_MBX_HLP_ATQLEN1_ATQVFE_M BIT(28) 9445 #define VF_MBX_HLP_ATQLEN1_ATQOVFL_S 29 9446 #define VF_MBX_HLP_ATQLEN1_ATQOVFL_M BIT(29) 9447 #define VF_MBX_HLP_ATQLEN1_ATQCRIT_S 30 9448 #define VF_MBX_HLP_ATQLEN1_ATQCRIT_M BIT(30) 9449 #define VF_MBX_HLP_ATQLEN1_ATQENABLE_S 31 9450 #define VF_MBX_HLP_ATQLEN1_ATQENABLE_M BIT(31) 9451 #define VF_MBX_HLP_ATQT1 0x00020040 /* Reset Source: CORER */ 9452 #define VF_MBX_HLP_ATQT1_ATQT_S 0 9453 #define VF_MBX_HLP_ATQT1_ATQT_M MAKEMASK(0x3FF, 0) 9454 #define VF_MBX_PSM_ARQBAH1 0x00021060 /* Reset Source: CORER */ 9455 #define VF_MBX_PSM_ARQBAH1_ARQBAH_S 0 9456 #define VF_MBX_PSM_ARQBAH1_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 9457 #define VF_MBX_PSM_ARQBAL1 0x00021050 /* Reset Source: CORER */ 9458 #define VF_MBX_PSM_ARQBAL1_ARQBAL_LSB_S 0 9459 #define VF_MBX_PSM_ARQBAL1_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 9460 #define VF_MBX_PSM_ARQBAL1_ARQBAL_S 6 9461 #define VF_MBX_PSM_ARQBAL1_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 9462 #define VF_MBX_PSM_ARQH1 0x00021080 /* Reset Source: CORER */ 9463 #define VF_MBX_PSM_ARQH1_ARQH_S 0 9464 #define VF_MBX_PSM_ARQH1_ARQH_M MAKEMASK(0x3FF, 0) 9465 #define VF_MBX_PSM_ARQLEN1 0x00021070 /* Reset Source: PFR */ 9466 #define VF_MBX_PSM_ARQLEN1_ARQLEN_S 0 9467 #define VF_MBX_PSM_ARQLEN1_ARQLEN_M MAKEMASK(0x3FF, 0) 9468 #define VF_MBX_PSM_ARQLEN1_ARQVFE_S 28 9469 #define VF_MBX_PSM_ARQLEN1_ARQVFE_M BIT(28) 9470 #define VF_MBX_PSM_ARQLEN1_ARQOVFL_S 29 9471 #define VF_MBX_PSM_ARQLEN1_ARQOVFL_M BIT(29) 9472 #define VF_MBX_PSM_ARQLEN1_ARQCRIT_S 30 9473 #define VF_MBX_PSM_ARQLEN1_ARQCRIT_M BIT(30) 9474 #define VF_MBX_PSM_ARQLEN1_ARQENABLE_S 31 9475 #define VF_MBX_PSM_ARQLEN1_ARQENABLE_M BIT(31) 9476 #define VF_MBX_PSM_ARQT1 0x00021090 /* Reset Source: CORER */ 9477 #define VF_MBX_PSM_ARQT1_ARQT_S 0 9478 #define VF_MBX_PSM_ARQT1_ARQT_M MAKEMASK(0x3FF, 0) 9479 #define VF_MBX_PSM_ATQBAH1 0x00021010 /* Reset Source: CORER */ 9480 #define VF_MBX_PSM_ATQBAH1_ATQBAH_S 0 9481 #define VF_MBX_PSM_ATQBAH1_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 9482 #define VF_MBX_PSM_ATQBAL1 0x00021000 /* Reset Source: CORER */ 9483 #define VF_MBX_PSM_ATQBAL1_ATQBAL_S 6 9484 #define VF_MBX_PSM_ATQBAL1_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 9485 #define VF_MBX_PSM_ATQH1 0x00021030 /* Reset Source: CORER */ 9486 #define VF_MBX_PSM_ATQH1_ATQH_S 0 9487 #define VF_MBX_PSM_ATQH1_ATQH_M MAKEMASK(0x3FF, 0) 9488 #define VF_MBX_PSM_ATQLEN1 0x00021020 /* Reset Source: PFR */ 9489 #define VF_MBX_PSM_ATQLEN1_ATQLEN_S 0 9490 #define VF_MBX_PSM_ATQLEN1_ATQLEN_M MAKEMASK(0x3FF, 0) 9491 #define VF_MBX_PSM_ATQLEN1_ATQVFE_S 28 9492 #define VF_MBX_PSM_ATQLEN1_ATQVFE_M BIT(28) 9493 #define VF_MBX_PSM_ATQLEN1_ATQOVFL_S 29 9494 #define VF_MBX_PSM_ATQLEN1_ATQOVFL_M BIT(29) 9495 #define VF_MBX_PSM_ATQLEN1_ATQCRIT_S 30 9496 #define VF_MBX_PSM_ATQLEN1_ATQCRIT_M BIT(30) 9497 #define VF_MBX_PSM_ATQLEN1_ATQENABLE_S 31 9498 #define VF_MBX_PSM_ATQLEN1_ATQENABLE_M BIT(31) 9499 #define VF_MBX_PSM_ATQT1 0x00021040 /* Reset Source: CORER */ 9500 #define VF_MBX_PSM_ATQT1_ATQT_S 0 9501 #define VF_MBX_PSM_ATQT1_ATQT_M MAKEMASK(0x3FF, 0) 9502 #define VF_SB_CPM_ARQBAH1 0x0000F160 /* Reset Source: CORER */ 9503 #define VF_SB_CPM_ARQBAH1_ARQBAH_S 0 9504 #define VF_SB_CPM_ARQBAH1_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0) 9505 #define VF_SB_CPM_ARQBAL1 0x0000F150 /* Reset Source: CORER */ 9506 #define VF_SB_CPM_ARQBAL1_ARQBAL_LSB_S 0 9507 #define VF_SB_CPM_ARQBAL1_ARQBAL_LSB_M MAKEMASK(0x3F, 0) 9508 #define VF_SB_CPM_ARQBAL1_ARQBAL_S 6 9509 #define VF_SB_CPM_ARQBAL1_ARQBAL_M MAKEMASK(0x3FFFFFF, 6) 9510 #define VF_SB_CPM_ARQH1 0x0000F180 /* Reset Source: CORER */ 9511 #define VF_SB_CPM_ARQH1_ARQH_S 0 9512 #define VF_SB_CPM_ARQH1_ARQH_M MAKEMASK(0x3FF, 0) 9513 #define VF_SB_CPM_ARQLEN1 0x0000F170 /* Reset Source: PFR */ 9514 #define VF_SB_CPM_ARQLEN1_ARQLEN_S 0 9515 #define VF_SB_CPM_ARQLEN1_ARQLEN_M MAKEMASK(0x3FF, 0) 9516 #define VF_SB_CPM_ARQLEN1_ARQVFE_S 28 9517 #define VF_SB_CPM_ARQLEN1_ARQVFE_M BIT(28) 9518 #define VF_SB_CPM_ARQLEN1_ARQOVFL_S 29 9519 #define VF_SB_CPM_ARQLEN1_ARQOVFL_M BIT(29) 9520 #define VF_SB_CPM_ARQLEN1_ARQCRIT_S 30 9521 #define VF_SB_CPM_ARQLEN1_ARQCRIT_M BIT(30) 9522 #define VF_SB_CPM_ARQLEN1_ARQENABLE_S 31 9523 #define VF_SB_CPM_ARQLEN1_ARQENABLE_M BIT(31) 9524 #define VF_SB_CPM_ARQT1 0x0000F190 /* Reset Source: CORER */ 9525 #define VF_SB_CPM_ARQT1_ARQT_S 0 9526 #define VF_SB_CPM_ARQT1_ARQT_M MAKEMASK(0x3FF, 0) 9527 #define VF_SB_CPM_ATQBAH1 0x0000F110 /* Reset Source: CORER */ 9528 #define VF_SB_CPM_ATQBAH1_ATQBAH_S 0 9529 #define VF_SB_CPM_ATQBAH1_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0) 9530 #define VF_SB_CPM_ATQBAL1 0x0000F100 /* Reset Source: CORER */ 9531 #define VF_SB_CPM_ATQBAL1_ATQBAL_S 6 9532 #define VF_SB_CPM_ATQBAL1_ATQBAL_M MAKEMASK(0x3FFFFFF, 6) 9533 #define VF_SB_CPM_ATQH1 0x0000F130 /* Reset Source: CORER */ 9534 #define VF_SB_CPM_ATQH1_ATQH_S 0 9535 #define VF_SB_CPM_ATQH1_ATQH_M MAKEMASK(0x3FF, 0) 9536 #define VF_SB_CPM_ATQLEN1 0x0000F120 /* Reset Source: PFR */ 9537 #define VF_SB_CPM_ATQLEN1_ATQLEN_S 0 9538 #define VF_SB_CPM_ATQLEN1_ATQLEN_M MAKEMASK(0x3FF, 0) 9539 #define VF_SB_CPM_ATQLEN1_ATQVFE_S 28 9540 #define VF_SB_CPM_ATQLEN1_ATQVFE_M BIT(28) 9541 #define VF_SB_CPM_ATQLEN1_ATQOVFL_S 29 9542 #define VF_SB_CPM_ATQLEN1_ATQOVFL_M BIT(29) 9543 #define VF_SB_CPM_ATQLEN1_ATQCRIT_S 30 9544 #define VF_SB_CPM_ATQLEN1_ATQCRIT_M BIT(30) 9545 #define VF_SB_CPM_ATQLEN1_ATQENABLE_S 31 9546 #define VF_SB_CPM_ATQLEN1_ATQENABLE_M BIT(31) 9547 #define VF_SB_CPM_ATQT1 0x0000F140 /* Reset Source: CORER */ 9548 #define VF_SB_CPM_ATQT1_ATQT_S 0 9549 #define VF_SB_CPM_ATQT1_ATQT_M MAKEMASK(0x3FF, 0) 9550 #define VFINT_DYN_CTL(_i) (0x00023000 + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: CORER */ 9551 #define VFINT_DYN_CTL_MAX_INDEX 7 9552 #define VFINT_DYN_CTL_INTENA_S 0 9553 #define VFINT_DYN_CTL_INTENA_M BIT(0) 9554 #define VFINT_DYN_CTL_CLEARPBA_S 1 9555 #define VFINT_DYN_CTL_CLEARPBA_M BIT(1) 9556 #define VFINT_DYN_CTL_SWINT_TRIG_S 2 9557 #define VFINT_DYN_CTL_SWINT_TRIG_M BIT(2) 9558 #define VFINT_DYN_CTL_ITR_INDX_S 3 9559 #define VFINT_DYN_CTL_ITR_INDX_M MAKEMASK(0x3, 3) 9560 #define VFINT_DYN_CTL_INTERVAL_S 5 9561 #define VFINT_DYN_CTL_INTERVAL_M MAKEMASK(0xFFF, 5) 9562 #define VFINT_DYN_CTL_SW_ITR_INDX_ENA_S 24 9563 #define VFINT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(24) 9564 #define VFINT_DYN_CTL_SW_ITR_INDX_S 25 9565 #define VFINT_DYN_CTL_SW_ITR_INDX_M MAKEMASK(0x3, 25) 9566 #define VFINT_DYN_CTL_WB_ON_ITR_S 30 9567 #define VFINT_DYN_CTL_WB_ON_ITR_M BIT(30) 9568 #define VFINT_DYN_CTL_INTENA_MSK_S 31 9569 #define VFINT_DYN_CTL_INTENA_MSK_M BIT(31) 9570 #define VFINT_ITR_0(_i) (0x00023004 + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: CORER */ 9571 #define VFINT_ITR_0_MAX_INDEX 7 9572 #define VFINT_ITR_0_INTERVAL_S 0 9573 #define VFINT_ITR_0_INTERVAL_M MAKEMASK(0xFFF, 0) 9574 #define VFINT_ITR_1(_i) (0x00023008 + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: CORER */ 9575 #define VFINT_ITR_1_MAX_INDEX 7 9576 #define VFINT_ITR_1_INTERVAL_S 0 9577 #define VFINT_ITR_1_INTERVAL_M MAKEMASK(0xFFF, 0) 9578 #define VFINT_ITR_2(_i) (0x0002300C + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: CORER */ 9579 #define VFINT_ITR_2_MAX_INDEX 7 9580 #define VFINT_ITR_2_INTERVAL_S 0 9581 #define VFINT_ITR_2_INTERVAL_M MAKEMASK(0xFFF, 0) 9582 #define VFQRX_TAIL(_QRX) (0x0002E000 + ((_QRX) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 9583 #define VFQRX_TAIL_MAX_INDEX 255 9584 #define VFQRX_TAIL_TAIL_S 0 9585 #define VFQRX_TAIL_TAIL_M MAKEMASK(0x1FFF, 0) 9586 #define VFQTX_COMM_DBELL(_DBQM) (0x00030000 + ((_DBQM) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 9587 #define VFQTX_COMM_DBELL_MAX_INDEX 255 9588 #define VFQTX_COMM_DBELL_QTX_COMM_DBELL_S 0 9589 #define VFQTX_COMM_DBELL_QTX_COMM_DBELL_M MAKEMASK(0xFFFFFFFF, 0) 9590 #define VFQTX_COMM_DBLQ_DBELL(_DBLQ) (0x00022000 + ((_DBLQ) * 4)) /* _i=0...3 */ /* Reset Source: CORER */ 9591 #define VFQTX_COMM_DBLQ_DBELL_MAX_INDEX 3 9592 #define VFQTX_COMM_DBLQ_DBELL_TAIL_S 0 9593 #define VFQTX_COMM_DBLQ_DBELL_TAIL_M MAKEMASK(0x1FFF, 0) 9594 #define MSIX_TMSG1(_i) (0x00000008 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */ 9595 #define MSIX_TMSG1_MAX_INDEX 64 9596 #define MSIX_TMSG1_MSIXTMSG_S 0 9597 #define MSIX_TMSG1_MSIXTMSG_M MAKEMASK(0xFFFFFFFF, 0) 9598 #define VFPE_AEQALLOC1 0x0000A400 /* Reset Source: VFR */ 9599 #define VFPE_AEQALLOC1_AECOUNT_S 0 9600 #define VFPE_AEQALLOC1_AECOUNT_M MAKEMASK(0xFFFFFFFF, 0) 9601 #define VFPE_CCQPHIGH1 0x00009800 /* Reset Source: VFR */ 9602 #define VFPE_CCQPHIGH1_PECCQPHIGH_S 0 9603 #define VFPE_CCQPHIGH1_PECCQPHIGH_M MAKEMASK(0xFFFFFFFF, 0) 9604 #define VFPE_CCQPLOW1 0x0000AC00 /* Reset Source: VFR */ 9605 #define VFPE_CCQPLOW1_PECCQPLOW_S 0 9606 #define VFPE_CCQPLOW1_PECCQPLOW_M MAKEMASK(0xFFFFFFFF, 0) 9607 #define VFPE_CCQPSTATUS1 0x0000B800 /* Reset Source: VFR */ 9608 #define VFPE_CCQPSTATUS1_CCQP_DONE_S 0 9609 #define VFPE_CCQPSTATUS1_CCQP_DONE_M BIT(0) 9610 #define VFPE_CCQPSTATUS1_HMC_PROFILE_S 4 9611 #define VFPE_CCQPSTATUS1_HMC_PROFILE_M MAKEMASK(0x7, 4) 9612 #define VFPE_CCQPSTATUS1_RDMA_EN_VFS_S 16 9613 #define VFPE_CCQPSTATUS1_RDMA_EN_VFS_M MAKEMASK(0x3F, 16) 9614 #define VFPE_CCQPSTATUS1_CCQP_ERR_S 31 9615 #define VFPE_CCQPSTATUS1_CCQP_ERR_M BIT(31) 9616 #define VFPE_CQACK1 0x0000B000 /* Reset Source: VFR */ 9617 #define VFPE_CQACK1_PECQID_S 0 9618 #define VFPE_CQACK1_PECQID_M MAKEMASK(0x7FFFF, 0) 9619 #define VFPE_CQARM1 0x0000B400 /* Reset Source: VFR */ 9620 #define VFPE_CQARM1_PECQID_S 0 9621 #define VFPE_CQARM1_PECQID_M MAKEMASK(0x7FFFF, 0) 9622 #define VFPE_CQPDB1 0x0000BC00 /* Reset Source: VFR */ 9623 #define VFPE_CQPDB1_WQHEAD_S 0 9624 #define VFPE_CQPDB1_WQHEAD_M MAKEMASK(0x7FF, 0) 9625 #define VFPE_CQPERRCODES1 0x00009C00 /* Reset Source: VFR */ 9626 #define VFPE_CQPERRCODES1_CQP_MINOR_CODE_S 0 9627 #define VFPE_CQPERRCODES1_CQP_MINOR_CODE_M MAKEMASK(0xFFFF, 0) 9628 #define VFPE_CQPERRCODES1_CQP_MAJOR_CODE_S 16 9629 #define VFPE_CQPERRCODES1_CQP_MAJOR_CODE_M MAKEMASK(0xFFFF, 16) 9630 #define VFPE_CQPTAIL1 0x0000A000 /* Reset Source: VFR */ 9631 #define VFPE_CQPTAIL1_WQTAIL_S 0 9632 #define VFPE_CQPTAIL1_WQTAIL_M MAKEMASK(0x7FF, 0) 9633 #define VFPE_CQPTAIL1_CQP_OP_ERR_S 31 9634 #define VFPE_CQPTAIL1_CQP_OP_ERR_M BIT(31) 9635 #define VFPE_IPCONFIG01 0x00008C00 /* Reset Source: VFR */ 9636 #define VFPE_IPCONFIG01_PEIPID_S 0 9637 #define VFPE_IPCONFIG01_PEIPID_M MAKEMASK(0xFFFF, 0) 9638 #define VFPE_IPCONFIG01_USEENTIREIDRANGE_S 16 9639 #define VFPE_IPCONFIG01_USEENTIREIDRANGE_M BIT(16) 9640 #define VFPE_IPCONFIG01_UDP_SRC_PORT_MASK_EN_S 17 9641 #define VFPE_IPCONFIG01_UDP_SRC_PORT_MASK_EN_M BIT(17) 9642 #define E800_VFPE_MRTEIDXMASK1(_VF) (0x00509800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */ 9643 #define E800_VFPE_MRTEIDXMASK1_MAX_INDEX 255 9644 #define E800_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_S 0 9645 #define E800_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_M MAKEMASK(0x1F, 0) 9646 #define E800_VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset Source: VFR */ 9647 #define E800_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_S 0 9648 #define E800_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0) 9649 #define VFPE_TCPNOWTIMER1 0x0000A800 /* Reset Source: VFR */ 9650 #define VFPE_TCPNOWTIMER1_TCP_NOW_S 0 9651 #define VFPE_TCPNOWTIMER1_TCP_NOW_M MAKEMASK(0xFFFFFFFF, 0) 9652 #define VFPE_WQEALLOC1 0x0000C000 /* Reset Source: VFR */ 9653 #define VFPE_WQEALLOC1_PEQPID_S 0 9654 #define VFPE_WQEALLOC1_PEQPID_M MAKEMASK(0x3FFFF, 0) 9655 #define VFPE_WQEALLOC1_WQE_DESC_INDEX_S 20 9656 #define VFPE_WQEALLOC1_WQE_DESC_INDEX_M MAKEMASK(0xFFF, 20) 9657 #define E830_GL_QRX_CONTEXT_CTL 0x00296640 /* Reset Source: CORER */ 9658 #define E830_GL_QRX_CONTEXT_CTL_QUEUE_ID_S 0 9659 #define E830_GL_QRX_CONTEXT_CTL_QUEUE_ID_M MAKEMASK(0xFFF, 0) 9660 #define E830_GL_QRX_CONTEXT_CTL_CMD_S 16 9661 #define E830_GL_QRX_CONTEXT_CTL_CMD_M MAKEMASK(0x7, 16) 9662 #define E830_GL_QRX_CONTEXT_CTL_CMD_EXEC_S 19 9663 #define E830_GL_QRX_CONTEXT_CTL_CMD_EXEC_M BIT(19) 9664 #define E830_GL_QRX_CONTEXT_DATA(_i) (0x00296620 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 9665 #define E830_GL_QRX_CONTEXT_DATA_MAX_INDEX 7 9666 #define E830_GL_QRX_CONTEXT_DATA_DATA_S 0 9667 #define E830_GL_QRX_CONTEXT_DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0) 9668 #define E830_GL_QRX_CONTEXT_STAT 0x00296644 /* Reset Source: CORER */ 9669 #define E830_GL_QRX_CONTEXT_STAT_CMD_IN_PROG_S 0 9670 #define E830_GL_QRX_CONTEXT_STAT_CMD_IN_PROG_M BIT(0) 9671 #define E830_GL_RCB_INTERNAL(_i) (0x00122600 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 9672 #define E830_GL_RCB_INTERNAL_MAX_INDEX 63 9673 #define E830_GL_RCB_INTERNAL_INTERNAL_S 0 9674 #define E830_GL_RCB_INTERNAL_INTERNAL_M MAKEMASK(0xFFFFFFFF, 0) 9675 #define E830_GL_RLAN_INTERNAL(_i) (0x00296700 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 9676 #define E830_GL_RLAN_INTERNAL_MAX_INDEX 63 9677 #define E830_GL_RLAN_INTERNAL_INTERNAL_S 0 9678 #define E830_GL_RLAN_INTERNAL_INTERNAL_M MAKEMASK(0xFFFFFFFF, 0) 9679 #define E830_GLPQMDBL_PQMDBL_IN_WRR_MAX_CREDITS 0x002D30F0 /* Reset Source: CORER */ 9680 #define E830_GLPQMDBL_PQMDBL_IN_WRR_MAX_CREDITS_DBLQ_S 0 9681 #define E830_GLPQMDBL_PQMDBL_IN_WRR_MAX_CREDITS_DBLQ_M MAKEMASK(0xFF, 0) 9682 #define E830_GLPQMDBL_PQMDBL_IN_WRR_MAX_CREDITS_FDBL_S 8 9683 #define E830_GLPQMDBL_PQMDBL_IN_WRR_MAX_CREDITS_FDBL_M MAKEMASK(0xFF, 8) 9684 #define E830_GLPQMDBL_PQMDBL_IN_WRR_MAX_CREDITS_TXT_S 16 9685 #define E830_GLPQMDBL_PQMDBL_IN_WRR_MAX_CREDITS_TXT_M MAKEMASK(0xFF, 16) 9686 #define E830_GLPQMDBL_PQMDBL_IN_WRR_WEIGHTS 0x002D30F4 /* Reset Source: CORER */ 9687 #define E830_GLPQMDBL_PQMDBL_IN_WRR_WEIGHTS_DBLQ_S 0 9688 #define E830_GLPQMDBL_PQMDBL_IN_WRR_WEIGHTS_DBLQ_M MAKEMASK(0x3F, 0) 9689 #define E830_GLPQMDBL_PQMDBL_IN_WRR_WEIGHTS_FDBL_S 6 9690 #define E830_GLPQMDBL_PQMDBL_IN_WRR_WEIGHTS_FDBL_M MAKEMASK(0x3F, 6) 9691 #define E830_GLPQMDBL_PQMDBL_IN_WRR_WEIGHTS_TXT_S 12 9692 #define E830_GLPQMDBL_PQMDBL_IN_WRR_WEIGHTS_TXT_M MAKEMASK(0x3F, 12) 9693 #define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS 0x002D30F8 /* Reset Source: CORER */ 9694 #define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS_DBLQ_FDBL_S 0 9695 #define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS_DBLQ_FDBL_M MAKEMASK(0xFF, 0) 9696 #define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS_TXT_S 8 9697 #define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS_TXT_M MAKEMASK(0xFF, 8) 9698 #define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS 0x002D30FC /* Reset Source: CORER */ 9699 #define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS_DBLQ_FDBL_S 0 9700 #define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS_DBLQ_FDBL_M MAKEMASK(0x3F, 0) 9701 #define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS_TXT_S 6 9702 #define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS_TXT_M MAKEMASK(0x3F, 6) 9703 #define E830_GLQTX_TXTIME_DBELL_LSB(_DBQM) (0x002E0000 + ((_DBQM) * 8)) /* _i=0...16383 */ /* Reset Source: CORER */ 9704 #define E830_GLQTX_TXTIME_DBELL_LSB_MAX_INDEX 16383 9705 #define E830_GLQTX_TXTIME_DBELL_LSB_QTX_TXTIME_DBELL_S 0 9706 #define E830_GLQTX_TXTIME_DBELL_LSB_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0) 9707 #define E830_GLQTX_TXTIME_DBELL_MSB(_DBQM) (0x002E0004 + ((_DBQM) * 8)) /* _i=0...16383 */ /* Reset Source: CORER */ 9708 #define E830_GLQTX_TXTIME_DBELL_MSB_MAX_INDEX 16383 9709 #define E830_GLQTX_TXTIME_DBELL_MSB_QTX_TXTIME_DBELL_S 0 9710 #define E830_GLQTX_TXTIME_DBELL_MSB_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0) 9711 #define E830_GLTCLAN_CQ_CNTX2_SRC_VSI_S 18 9712 #define E830_GLTCLAN_CQ_CNTX2_SRC_VSI_M MAKEMASK(0x3FF, 18) 9713 #define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS 0x002D320C /* Reset Source: CORER */ 9714 #define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS_DBL_S 0 9715 #define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS_DBL_M MAKEMASK(0xFF, 0) 9716 #define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS_COMP_S 8 9717 #define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS_COMP_M MAKEMASK(0xFF, 8) 9718 #define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS 0x002D3210 /* Reset Source: CORER */ 9719 #define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS_DBL_S 0 9720 #define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS_DBL_M MAKEMASK(0x3F, 0) 9721 #define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS_COMP_S 6 9722 #define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS_COMP_M MAKEMASK(0x3F, 6) 9723 #define E830_GLTXTIME_FETCH_PROFILE(_i, _j) (0x002D3500 + ((_i) * 4 + (_j) * 64)) /* _i=0...15, _j=0...15 */ /* Reset Source: CORER */ 9724 #define E830_GLTXTIME_FETCH_PROFILE_MAX_INDEX 15 9725 #define E830_GLTXTIME_FETCH_PROFILE_FETCH_TS_DESC_S 0 9726 #define E830_GLTXTIME_FETCH_PROFILE_FETCH_TS_DESC_M MAKEMASK(0x1FF, 0) 9727 #define E830_GLTXTIME_FETCH_PROFILE_FETCH_FIFO_TRESH_S 9 9728 #define E830_GLTXTIME_FETCH_PROFILE_FETCH_FIFO_TRESH_M MAKEMASK(0x7F, 9) 9729 #define E830_GLTXTIME_OUTST_REQ_CNTL 0x002D3214 /* Reset Source: CORER */ 9730 #define E830_GLTXTIME_OUTST_REQ_CNTL_THRESHOLD_S 0 9731 #define E830_GLTXTIME_OUTST_REQ_CNTL_THRESHOLD_M MAKEMASK(0x3FF, 0) 9732 #define E830_GLTXTIME_OUTST_REQ_CNTL_SNAPSHOT_S 10 9733 #define E830_GLTXTIME_OUTST_REQ_CNTL_SNAPSHOT_M MAKEMASK(0x3FF, 10) 9734 #define E830_GLTXTIME_QTX_CNTX_CTL 0x002D3204 /* Reset Source: CORER */ 9735 #define E830_GLTXTIME_QTX_CNTX_CTL_QUEUE_ID_S 0 9736 #define E830_GLTXTIME_QTX_CNTX_CTL_QUEUE_ID_M MAKEMASK(0x7FF, 0) 9737 #define E830_GLTXTIME_QTX_CNTX_CTL_CMD_S 16 9738 #define E830_GLTXTIME_QTX_CNTX_CTL_CMD_M MAKEMASK(0x7, 16) 9739 #define E830_GLTXTIME_QTX_CNTX_CTL_CMD_EXEC_S 19 9740 #define E830_GLTXTIME_QTX_CNTX_CTL_CMD_EXEC_M BIT(19) 9741 #define E830_GLTXTIME_QTX_CNTX_DATA(_i) (0x002D3104 + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: CORER */ 9742 #define E830_GLTXTIME_QTX_CNTX_DATA_MAX_INDEX 6 9743 #define E830_GLTXTIME_QTX_CNTX_DATA_DATA_S 0 9744 #define E830_GLTXTIME_QTX_CNTX_DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0) 9745 #define E830_GLTXTIME_QTX_CNTX_STAT 0x002D3208 /* Reset Source: CORER */ 9746 #define E830_GLTXTIME_QTX_CNTX_STAT_CMD_IN_PROG_S 0 9747 #define E830_GLTXTIME_QTX_CNTX_STAT_CMD_IN_PROG_M BIT(0) 9748 #define E830_GLTXTIME_TS_CFG 0x002D3100 /* Reset Source: CORER */ 9749 #define E830_GLTXTIME_TS_CFG_TXTIME_ENABLE_S 0 9750 #define E830_GLTXTIME_TS_CFG_TXTIME_ENABLE_M BIT(0) 9751 #define E830_GLTXTIME_TS_CFG_STORAGE_MODE_S 2 9752 #define E830_GLTXTIME_TS_CFG_STORAGE_MODE_M MAKEMASK(0x7, 2) 9753 #define E830_GLTXTIME_TS_CFG_PIPE_LATENCY_STATIC_S 5 9754 #define E830_GLTXTIME_TS_CFG_PIPE_LATENCY_STATIC_M MAKEMASK(0x1FFF, 5) 9755 #define E830_MBX_PF_DEC_ERR 0x00234100 /* Reset Source: CORER */ 9756 #define E830_MBX_PF_DEC_ERR_DEC_ERR_S 0 9757 #define E830_MBX_PF_DEC_ERR_DEC_ERR_M BIT(0) 9758 #define E830_MBX_PF_IN_FLIGHT_VF_MSGS_THRESH 0x00234000 /* Reset Source: CORER */ 9759 #define E830_MBX_PF_IN_FLIGHT_VF_MSGS_THRESH_TRESH_S 0 9760 #define E830_MBX_PF_IN_FLIGHT_VF_MSGS_THRESH_TRESH_M MAKEMASK(0x3FF, 0) 9761 #define E830_MBX_VF_DEC_TRIG(_VF) (0x00233800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 9762 #define E830_MBX_VF_DEC_TRIG_MAX_INDEX 255 9763 #define E830_MBX_VF_DEC_TRIG_DEC_S 0 9764 #define E830_MBX_VF_DEC_TRIG_DEC_M MAKEMASK(0x3FF, 0) 9765 #define E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT(_VF) (0x00233000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 9766 #define E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT_MAX_INDEX 255 9767 #define E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT_MSGS_S 0 9768 #define E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT_MSGS_M MAKEMASK(0x3FF, 0) 9769 #define E830_GLRCB_AG_ARBITER_CONFIG 0x00122500 /* Reset Source: CORER */ 9770 #define E830_GLRCB_AG_ARBITER_CONFIG_CREDIT_MAX_S 0 9771 #define E830_GLRCB_AG_ARBITER_CONFIG_CREDIT_MAX_M MAKEMASK(0xFFFFF, 0) 9772 #define E830_GLRCB_AG_DCB_ARBITER_CONFIG 0x00122518 /* Reset Source: CORER */ 9773 #define E830_GLRCB_AG_DCB_ARBITER_CONFIG_CREDIT_MAX_S 0 9774 #define E830_GLRCB_AG_DCB_ARBITER_CONFIG_CREDIT_MAX_M MAKEMASK(0x7F, 0) 9775 #define E830_GLRCB_AG_DCB_ARBITER_CONFIG_STRICT_WRR_S 7 9776 #define E830_GLRCB_AG_DCB_ARBITER_CONFIG_STRICT_WRR_M BIT(7) 9777 #define E830_GLRCB_AG_DCB_NODE_CONFIG(_i) (0x00122510 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 9778 #define E830_GLRCB_AG_DCB_NODE_CONFIG_MAX_INDEX 1 9779 #define E830_GLRCB_AG_DCB_NODE_CONFIG_BWSHARE_S 0 9780 #define E830_GLRCB_AG_DCB_NODE_CONFIG_BWSHARE_M MAKEMASK(0xF, 0) 9781 #define E830_GLRCB_AG_DCB_NODE_STATE(_i) (0x00122508 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 9782 #define E830_GLRCB_AG_DCB_NODE_STATE_MAX_INDEX 1 9783 #define E830_GLRCB_AG_DCB_NODE_STATE_CREDITS_S 0 9784 #define E830_GLRCB_AG_DCB_NODE_STATE_CREDITS_M MAKEMASK(0xFF, 0) 9785 #define E830_GLRCB_AG_NODE_CONFIG(_i) (0x001224E0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 9786 #define E830_GLRCB_AG_NODE_CONFIG_MAX_INDEX 7 9787 #define E830_GLRCB_AG_NODE_CONFIG_BWSHARE_S 0 9788 #define E830_GLRCB_AG_NODE_CONFIG_BWSHARE_M MAKEMASK(0x7F, 0) 9789 #define E830_GLRCB_AG_NODE_STATE(_i) (0x001224C0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 9790 #define E830_GLRCB_AG_NODE_STATE_MAX_INDEX 7 9791 #define E830_GLRCB_AG_NODE_STATE_CREDITS_S 0 9792 #define E830_GLRCB_AG_NODE_STATE_CREDITS_M MAKEMASK(0xFFFFF, 0) 9793 #define E830_PRT_AG_PORT_FC_MAP 0x00122520 /* Reset Source: CORER */ 9794 #define E830_PRT_AG_PORT_FC_MAP_AG_BITMAP_S 0 9795 #define E830_PRT_AG_PORT_FC_MAP_AG_BITMAP_M MAKEMASK(0xFF, 0) 9796 #define E830_GL_FW_LOGS_CTL 0x000827F8 /* Reset Source: POR */ 9797 #define E830_GL_FW_LOGS_CTL_PAGE_SELECT_S 0 9798 #define E830_GL_FW_LOGS_CTL_PAGE_SELECT_M MAKEMASK(0x3FF, 0) 9799 #define E830_GL_FW_LOGS_STS 0x000827FC /* Reset Source: POR */ 9800 #define E830_GL_FW_LOGS_STS_MAX_PAGE_S 0 9801 #define E830_GL_FW_LOGS_STS_MAX_PAGE_M MAKEMASK(0x3FF, 0) 9802 #define E830_GL_FW_LOGS_STS_FW_LOGS_ENA_S 31 9803 #define E830_GL_FW_LOGS_STS_FW_LOGS_ENA_M BIT(31) 9804 #define E830_GL_RTCTL 0x000827F0 /* Reset Source: POR */ 9805 #define E830_GL_RTCTL_RTCTL_S 0 9806 #define E830_GL_RTCTL_RTCTL_M MAKEMASK(0xFFFFFFFF, 0) 9807 #define E830_GL_RTCTM 0x000827F4 /* Reset Source: POR */ 9808 #define E830_GL_RTCTM_RTCTM_S 0 9809 #define E830_GL_RTCTM_RTCTM_M MAKEMASK(0xFFFF, 0) 9810 #define E830_GLGEN_RTRIG_EMPR_WO_GLOBR_S 3 9811 #define E830_GLGEN_RTRIG_EMPR_WO_GLOBR_M BIT(3) 9812 #define E830_GLPE_TSCD_NUM_PQS 0x0051E2FC /* Reset Source: CORER */ 9813 #define E830_GLPE_TSCD_NUM_PQS_NUM_PQS_S 0 9814 #define E830_GLPE_TSCD_NUM_PQS_NUM_PQS_M MAKEMASK(0xFFFFFFFF, 0) 9815 #define E830_GLTPB_100G_RPB_FC_THRESH2 0x0009972C /* Reset Source: CORER */ 9816 #define E830_GLTPB_100G_RPB_FC_THRESH2_PORT4_FC_THRESH_S 0 9817 #define E830_GLTPB_100G_RPB_FC_THRESH2_PORT4_FC_THRESH_M MAKEMASK(0xFFFF, 0) 9818 #define E830_GLTPB_100G_RPB_FC_THRESH2_PORT5_FC_THRESH_S 16 9819 #define E830_GLTPB_100G_RPB_FC_THRESH2_PORT5_FC_THRESH_M MAKEMASK(0xFFFF, 16) 9820 #define E830_GLTPB_100G_RPB_FC_THRESH3 0x00099730 /* Reset Source: CORER */ 9821 #define E830_GLTPB_100G_RPB_FC_THRESH3_PORT6_FC_THRESH_S 0 9822 #define E830_GLTPB_100G_RPB_FC_THRESH3_PORT6_FC_THRESH_M MAKEMASK(0xFFFF, 0) 9823 #define E830_GLTPB_100G_RPB_FC_THRESH3_PORT7_FC_THRESH_S 16 9824 #define E830_GLTPB_100G_RPB_FC_THRESH3_PORT7_FC_THRESH_M MAKEMASK(0xFFFF, 16) 9825 #define E830_PORT_TIMER_SEL(_i) (0x00088BE0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 9826 #define E830_PORT_TIMER_SEL_MAX_INDEX 7 9827 #define E830_PORT_TIMER_SEL_TIMER_SEL_S 0 9828 #define E830_PORT_TIMER_SEL_TIMER_SEL_M BIT(0) 9829 #define E830_GL_RDPU_CNTRL_CHECKSUM_COMPLETE_INV_S 22 9830 #define E830_GL_RDPU_CNTRL_CHECKSUM_COMPLETE_INV_M BIT(22) 9831 #define E830_PRTMAC_SHORT_PAC_DROP_BYTE_CNT 0x001E2280 /* Reset Source: GLOBR */ 9832 #define E830_PRTMAC_SHORT_PAC_DROP_BYTE_CNT_PRTMAC_SHORT_PAC_DROP_BYTE_CNT_S 0 9833 #define E830_PRTMAC_SHORT_PAC_DROP_BYTE_CNT_PRTMAC_SHORT_PAC_DROP_BYTE_CNT_M MAKEMASK(0xFFFFFFFF, 0) 9834 #define E830_PRTTSYN_TXTIME_H(_i) (0x001E5800 + ((_i) * 32)) /* _i=0...63 */ /* Reset Source: GLOBR */ 9835 #define E830_PRTTSYN_TXTIME_H_MAX_INDEX 63 9836 #define E830_PRTTSYN_TXTIME_H_TX_TIMESTAMP_HIGH_S 0 9837 #define E830_PRTTSYN_TXTIME_H_TX_TIMESTAMP_HIGH_M MAKEMASK(0xFF, 0) 9838 #define E830_PRTTSYN_TXTIME_L(_i) (0x001E5000 + ((_i) * 32)) /* _i=0...63 */ /* Reset Source: GLOBR */ 9839 #define E830_PRTTSYN_TXTIME_L_MAX_INDEX 63 9840 #define E830_PRTTSYN_TXTIME_L_TX_VALID_S 0 9841 #define E830_PRTTSYN_TXTIME_L_TX_VALID_M BIT(0) 9842 #define E830_PRTTSYN_TXTIME_L_TX_TIMESTAMP_LOW_S 1 9843 #define E830_PRTTSYN_TXTIME_L_TX_TIMESTAMP_LOW_M MAKEMASK(0x7FFFFFFF, 1) 9844 #define E830_GL_MDCK_TDAT_TCLAN_TSYN 0x000FD200 /* Reset Source: CORER */ 9845 #define E830_GL_MDCK_TDAT_TCLAN_TSYN_PF_TSYN_PKT_FROM_Q_NOT_ALLOWED_S 0 9846 #define E830_GL_MDCK_TDAT_TCLAN_TSYN_PF_TSYN_PKT_FROM_Q_NOT_ALLOWED_M BIT(0) 9847 #define E830_GL_MDCK_TDAT_TCLAN_TSYN_PF_TSYN_PKT_RANGE_VIOLATION_S 1 9848 #define E830_GL_MDCK_TDAT_TCLAN_TSYN_PF_TSYN_PKT_RANGE_VIOLATION_M BIT(1) 9849 #define E830_GL_MDET_RX_FIFO 0x00296840 /* Reset Source: CORER */ 9850 #define E830_GL_MDET_RX_FIFO_FUNC_NUM_S 0 9851 #define E830_GL_MDET_RX_FIFO_FUNC_NUM_M MAKEMASK(0x3FF, 0) 9852 #define E830_GL_MDET_RX_FIFO_PF_NUM_S 10 9853 #define E830_GL_MDET_RX_FIFO_PF_NUM_M MAKEMASK(0x7, 10) 9854 #define E830_GL_MDET_RX_FIFO_FUNC_TYPE_S 13 9855 #define E830_GL_MDET_RX_FIFO_FUNC_TYPE_M MAKEMASK(0x3, 13) 9856 #define E830_GL_MDET_RX_FIFO_MAL_TYPE_S 15 9857 #define E830_GL_MDET_RX_FIFO_MAL_TYPE_M MAKEMASK(0x1F, 15) 9858 #define E830_GL_MDET_RX_FIFO_FIFO_FULL_S 20 9859 #define E830_GL_MDET_RX_FIFO_FIFO_FULL_M BIT(20) 9860 #define E830_GL_MDET_RX_FIFO_VALID_S 21 9861 #define E830_GL_MDET_RX_FIFO_VALID_M BIT(21) 9862 #define E830_GL_MDET_RX_FIFO_EVENT_CNT_S 24 9863 #define E830_GL_MDET_RX_FIFO_EVENT_CNT_M MAKEMASK(0xFF, 24) 9864 #define E830_GL_MDET_RX_PF_CNT(_i) (0x00296800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 9865 #define E830_GL_MDET_RX_PF_CNT_MAX_INDEX 7 9866 #define E830_GL_MDET_RX_PF_CNT_CNT_S 0 9867 #define E830_GL_MDET_RX_PF_CNT_CNT_M MAKEMASK(0xFFFFFFFF, 0) 9868 #define E830_GL_MDET_RX_VF(_i) (0x00296820 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 9869 #define E830_GL_MDET_RX_VF_MAX_INDEX 7 9870 #define E830_GL_MDET_RX_VF_VF_MAL_EVENT_S 0 9871 #define E830_GL_MDET_RX_VF_VF_MAL_EVENT_M MAKEMASK(0xFFFFFFFF, 0) 9872 #define E830_GL_MDET_TX_PQM_FIFO 0x002D4B00 /* Reset Source: CORER */ 9873 #define E830_GL_MDET_TX_PQM_FIFO_FUNC_NUM_S 0 9874 #define E830_GL_MDET_TX_PQM_FIFO_FUNC_NUM_M MAKEMASK(0x3FF, 0) 9875 #define E830_GL_MDET_TX_PQM_FIFO_PF_NUM_S 10 9876 #define E830_GL_MDET_TX_PQM_FIFO_PF_NUM_M MAKEMASK(0x7, 10) 9877 #define E830_GL_MDET_TX_PQM_FIFO_FUNC_TYPE_S 13 9878 #define E830_GL_MDET_TX_PQM_FIFO_FUNC_TYPE_M MAKEMASK(0x3, 13) 9879 #define E830_GL_MDET_TX_PQM_FIFO_MAL_TYPE_S 15 9880 #define E830_GL_MDET_TX_PQM_FIFO_MAL_TYPE_M MAKEMASK(0x1F, 15) 9881 #define E830_GL_MDET_TX_PQM_FIFO_FIFO_FULL_S 20 9882 #define E830_GL_MDET_TX_PQM_FIFO_FIFO_FULL_M BIT(20) 9883 #define E830_GL_MDET_TX_PQM_FIFO_VALID_S 21 9884 #define E830_GL_MDET_TX_PQM_FIFO_VALID_M BIT(21) 9885 #define E830_GL_MDET_TX_PQM_FIFO_EVENT_CNT_S 24 9886 #define E830_GL_MDET_TX_PQM_FIFO_EVENT_CNT_M MAKEMASK(0xFF, 24) 9887 #define E830_GL_MDET_TX_PQM_PF_CNT(_i) (0x002D4AC0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 9888 #define E830_GL_MDET_TX_PQM_PF_CNT_MAX_INDEX 7 9889 #define E830_GL_MDET_TX_PQM_PF_CNT_CNT_S 0 9890 #define E830_GL_MDET_TX_PQM_PF_CNT_CNT_M MAKEMASK(0xFFFFFFFF, 0) 9891 #define E830_GL_MDET_TX_PQM_VF(_i) (0x002D4AE0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 9892 #define E830_GL_MDET_TX_PQM_VF_MAX_INDEX 7 9893 #define E830_GL_MDET_TX_PQM_VF_VF_MAL_EVENT_S 0 9894 #define E830_GL_MDET_TX_PQM_VF_VF_MAL_EVENT_M MAKEMASK(0xFFFFFFFF, 0) 9895 #define E830_GL_MDET_TX_TCLAN_FIFO 0x000FCFD0 /* Reset Source: CORER */ 9896 #define E830_GL_MDET_TX_TCLAN_FIFO_FUNC_NUM_S 0 9897 #define E830_GL_MDET_TX_TCLAN_FIFO_FUNC_NUM_M MAKEMASK(0x3FF, 0) 9898 #define E830_GL_MDET_TX_TCLAN_FIFO_PF_NUM_S 10 9899 #define E830_GL_MDET_TX_TCLAN_FIFO_PF_NUM_M MAKEMASK(0x7, 10) 9900 #define E830_GL_MDET_TX_TCLAN_FIFO_FUNC_TYPE_S 13 9901 #define E830_GL_MDET_TX_TCLAN_FIFO_FUNC_TYPE_M MAKEMASK(0x3, 13) 9902 #define E830_GL_MDET_TX_TCLAN_FIFO_MAL_TYPE_S 15 9903 #define E830_GL_MDET_TX_TCLAN_FIFO_MAL_TYPE_M MAKEMASK(0x1F, 15) 9904 #define E830_GL_MDET_TX_TCLAN_FIFO_FIFO_FULL_S 20 9905 #define E830_GL_MDET_TX_TCLAN_FIFO_FIFO_FULL_M BIT(20) 9906 #define E830_GL_MDET_TX_TCLAN_FIFO_VALID_S 21 9907 #define E830_GL_MDET_TX_TCLAN_FIFO_VALID_M BIT(21) 9908 #define E830_GL_MDET_TX_TCLAN_FIFO_EVENT_CNT_S 24 9909 #define E830_GL_MDET_TX_TCLAN_FIFO_EVENT_CNT_M MAKEMASK(0xFF, 24) 9910 #define E830_GL_MDET_TX_TCLAN_PF_CNT(_i) (0x000FCF90 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 9911 #define E830_GL_MDET_TX_TCLAN_PF_CNT_MAX_INDEX 7 9912 #define E830_GL_MDET_TX_TCLAN_PF_CNT_CNT_S 0 9913 #define E830_GL_MDET_TX_TCLAN_PF_CNT_CNT_M MAKEMASK(0xFFFFFFFF, 0) 9914 #define E830_GL_MDET_TX_TCLAN_VF(_i) (0x000FCFB0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 9915 #define E830_GL_MDET_TX_TCLAN_VF_MAX_INDEX 7 9916 #define E830_GL_MDET_TX_TCLAN_VF_VF_MAL_EVENT_S 0 9917 #define E830_GL_MDET_TX_TCLAN_VF_VF_MAL_EVENT_M MAKEMASK(0xFFFFFFFF, 0) 9918 #define E830_GL_MDET_TX_TDPU_FIFO 0x00049D80 /* Reset Source: CORER */ 9919 #define E830_GL_MDET_TX_TDPU_FIFO_FUNC_NUM_S 0 9920 #define E830_GL_MDET_TX_TDPU_FIFO_FUNC_NUM_M MAKEMASK(0x3FF, 0) 9921 #define E830_GL_MDET_TX_TDPU_FIFO_PF_NUM_S 10 9922 #define E830_GL_MDET_TX_TDPU_FIFO_PF_NUM_M MAKEMASK(0x7, 10) 9923 #define E830_GL_MDET_TX_TDPU_FIFO_FUNC_TYPE_S 13 9924 #define E830_GL_MDET_TX_TDPU_FIFO_FUNC_TYPE_M MAKEMASK(0x3, 13) 9925 #define E830_GL_MDET_TX_TDPU_FIFO_MAL_TYPE_S 15 9926 #define E830_GL_MDET_TX_TDPU_FIFO_MAL_TYPE_M MAKEMASK(0x1F, 15) 9927 #define E830_GL_MDET_TX_TDPU_FIFO_FIFO_FULL_S 20 9928 #define E830_GL_MDET_TX_TDPU_FIFO_FIFO_FULL_M BIT(20) 9929 #define E830_GL_MDET_TX_TDPU_FIFO_VALID_S 21 9930 #define E830_GL_MDET_TX_TDPU_FIFO_VALID_M BIT(21) 9931 #define E830_GL_MDET_TX_TDPU_FIFO_EVENT_CNT_S 24 9932 #define E830_GL_MDET_TX_TDPU_FIFO_EVENT_CNT_M MAKEMASK(0xFF, 24) 9933 #define E830_GL_MDET_TX_TDPU_PF_CNT(_i) (0x00049D40 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 9934 #define E830_GL_MDET_TX_TDPU_PF_CNT_MAX_INDEX 7 9935 #define E830_GL_MDET_TX_TDPU_PF_CNT_CNT_S 0 9936 #define E830_GL_MDET_TX_TDPU_PF_CNT_CNT_M MAKEMASK(0xFFFFFFFF, 0) 9937 #define E830_GL_MDET_TX_TDPU_VF(_i) (0x00049D60 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 9938 #define E830_GL_MDET_TX_TDPU_VF_MAX_INDEX 7 9939 #define E830_GL_MDET_TX_TDPU_VF_VF_MAL_EVENT_S 0 9940 #define E830_GL_MDET_TX_TDPU_VF_VF_MAL_EVENT_M MAKEMASK(0xFFFFFFFF, 0) 9941 #define E830_GL_MNG_ECDSA_PUBKEY_HIGH(_i) (0x00083400 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: EMPR */ 9942 #define E830_GL_MNG_ECDSA_PUBKEY_HIGH_MAX_INDEX 11 9943 #define E830_GL_MNG_ECDSA_PUBKEY_HIGH_GL_MNG_ECDSA_PUBKEY_S 0 9944 #define E830_GL_MNG_ECDSA_PUBKEY_HIGH_GL_MNG_ECDSA_PUBKEY_M MAKEMASK(0xFFFFFFFF, 0) 9945 #define E830_GL_MNG_ECDSA_PUBKEY_LOW(_i) (0x00083300 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: EMPR */ 9946 #define E830_GL_MNG_ECDSA_PUBKEY_LOW_MAX_INDEX 11 9947 #define E830_GL_MNG_ECDSA_PUBKEY_LOW_GL_MNG_ECDSA_PUBKEY_S 0 9948 #define E830_GL_MNG_ECDSA_PUBKEY_LOW_GL_MNG_ECDSA_PUBKEY_M MAKEMASK(0xFFFFFFFF, 0) 9949 #define E830_GL_PPRS_RX_SIZE_CTRL_0(_i) (0x00084900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 9950 #define E830_GL_PPRS_RX_SIZE_CTRL_0_MAX_INDEX 1 9951 #define E830_GL_PPRS_RX_SIZE_CTRL_0_MAX_HEADER_SIZE_S 16 9952 #define E830_GL_PPRS_RX_SIZE_CTRL_0_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16) 9953 #define E830_GL_PPRS_RX_SIZE_CTRL_1(_i) (0x00085900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 9954 #define E830_GL_PPRS_RX_SIZE_CTRL_1_MAX_INDEX 1 9955 #define E830_GL_PPRS_RX_SIZE_CTRL_1_MAX_HEADER_SIZE_S 16 9956 #define E830_GL_PPRS_RX_SIZE_CTRL_1_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16) 9957 #define E830_GL_PPRS_RX_SIZE_CTRL_2(_i) (0x00086900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 9958 #define E830_GL_PPRS_RX_SIZE_CTRL_2_MAX_INDEX 1 9959 #define E830_GL_PPRS_RX_SIZE_CTRL_2_MAX_HEADER_SIZE_S 16 9960 #define E830_GL_PPRS_RX_SIZE_CTRL_2_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16) 9961 #define E830_GL_PPRS_RX_SIZE_CTRL_3(_i) (0x00087900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 9962 #define E830_GL_PPRS_RX_SIZE_CTRL_3_MAX_INDEX 1 9963 #define E830_GL_PPRS_RX_SIZE_CTRL_3_MAX_HEADER_SIZE_S 16 9964 #define E830_GL_PPRS_RX_SIZE_CTRL_3_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16) 9965 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP 0x00200740 /* Reset Source: CORER */ 9966 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_0_S 0 9967 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_0_M MAKEMASK(0xFF, 0) 9968 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_1_S 8 9969 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_1_M MAKEMASK(0xFF, 8) 9970 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_0_S 16 9971 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_0_M MAKEMASK(0xFF, 16) 9972 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_1_S 24 9973 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_1_M MAKEMASK(0xFF, 24) 9974 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP 0x00200744 /* Reset Source: CORER */ 9975 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_0_S 0 9976 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_0_M MAKEMASK(0xFF, 0) 9977 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_1_S 8 9978 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_1_M MAKEMASK(0xFF, 8) 9979 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_0_S 16 9980 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_0_M MAKEMASK(0xFF, 16) 9981 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_1_S 24 9982 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_1_M MAKEMASK(0xFF, 24) 9983 #define E830_GL_RPRS_PROT_ID_MAP(_i) (0x00200800 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 9984 #define E830_GL_RPRS_PROT_ID_MAP_MAX_INDEX 255 9985 #define E830_GL_RPRS_PROT_ID_MAP_PROT_ID0_S 0 9986 #define E830_GL_RPRS_PROT_ID_MAP_PROT_ID0_M MAKEMASK(0xFF, 0) 9987 #define E830_GL_RPRS_PROT_ID_MAP_PROT_ID1_S 8 9988 #define E830_GL_RPRS_PROT_ID_MAP_PROT_ID1_M MAKEMASK(0xFF, 8) 9989 #define E830_GL_RPRS_PROT_ID_MAP_PROT_ID2_S 16 9990 #define E830_GL_RPRS_PROT_ID_MAP_PROT_ID2_M MAKEMASK(0xFF, 16) 9991 #define E830_GL_RPRS_PROT_ID_MAP_PROT_ID3_S 24 9992 #define E830_GL_RPRS_PROT_ID_MAP_PROT_ID3_M MAKEMASK(0xFF, 24) 9993 #define E830_GL_RPRS_PROT_ID_MAP_PRFL(_i) (0x00201000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 9994 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_MAX_INDEX 63 9995 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_0_S 0 9996 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_0_M MAKEMASK(0x3, 0) 9997 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_1_S 2 9998 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_1_M MAKEMASK(0x3, 2) 9999 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_2_S 4 10000 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_2_M MAKEMASK(0x3, 4) 10001 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_3_S 6 10002 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_3_M MAKEMASK(0x3, 6) 10003 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_4_S 8 10004 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_4_M MAKEMASK(0x3, 8) 10005 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_5_S 10 10006 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_5_M MAKEMASK(0x3, 10) 10007 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_6_S 12 10008 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_6_M MAKEMASK(0x3, 12) 10009 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_7_S 14 10010 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_7_M MAKEMASK(0x3, 14) 10011 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_8_S 16 10012 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_8_M MAKEMASK(0x3, 16) 10013 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_9_S 18 10014 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_9_M MAKEMASK(0x3, 18) 10015 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_10_S 20 10016 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_10_M MAKEMASK(0x3, 20) 10017 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_11_S 22 10018 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_11_M MAKEMASK(0x3, 22) 10019 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_12_S 24 10020 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_12_M MAKEMASK(0x3, 24) 10021 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_13_S 26 10022 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_13_M MAKEMASK(0x3, 26) 10023 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_14_S 28 10024 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_14_M MAKEMASK(0x3, 28) 10025 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_15_S 30 10026 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_15_M MAKEMASK(0x3, 30) 10027 #define E830_GL_RPRS_VALIDATE_CHECKS_CTL 0x00200748 /* Reset Source: CORER */ 10028 #define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_0_EN_S 0 10029 #define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_0_EN_M BIT(0) 10030 #define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_1_EN_S 1 10031 #define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_1_EN_M BIT(1) 10032 #define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_0_S 2 10033 #define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_0_M BIT(2) 10034 #define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_1_S 3 10035 #define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_1_M BIT(3) 10036 #define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_0_S 4 10037 #define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_0_M BIT(4) 10038 #define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_1_S 5 10039 #define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_1_M BIT(5) 10040 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP 0x00203A04 /* Reset Source: CORER */ 10041 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_0_S 0 10042 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_0_M MAKEMASK(0xFF, 0) 10043 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_1_S 8 10044 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_1_M MAKEMASK(0xFF, 8) 10045 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_0_S 16 10046 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_0_M MAKEMASK(0xFF, 16) 10047 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_1_S 24 10048 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_1_M MAKEMASK(0xFF, 24) 10049 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP 0x00203A08 /* Reset Source: CORER */ 10050 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_0_S 0 10051 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_0_M MAKEMASK(0xFF, 0) 10052 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_1_S 8 10053 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_1_M MAKEMASK(0xFF, 8) 10054 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_0_S 16 10055 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_0_M MAKEMASK(0xFF, 16) 10056 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_1_S 24 10057 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_1_M MAKEMASK(0xFF, 24) 10058 #define E830_GL_TPRS_PROT_ID_MAP(_i) (0x00202200 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 10059 #define E830_GL_TPRS_PROT_ID_MAP_MAX_INDEX 255 10060 #define E830_GL_TPRS_PROT_ID_MAP_PROT_ID0_S 0 10061 #define E830_GL_TPRS_PROT_ID_MAP_PROT_ID0_M MAKEMASK(0xFF, 0) 10062 #define E830_GL_TPRS_PROT_ID_MAP_PROT_ID1_S 8 10063 #define E830_GL_TPRS_PROT_ID_MAP_PROT_ID1_M MAKEMASK(0xFF, 8) 10064 #define E830_GL_TPRS_PROT_ID_MAP_PROT_ID2_S 16 10065 #define E830_GL_TPRS_PROT_ID_MAP_PROT_ID2_M MAKEMASK(0xFF, 16) 10066 #define E830_GL_TPRS_PROT_ID_MAP_PROT_ID3_S 24 10067 #define E830_GL_TPRS_PROT_ID_MAP_PROT_ID3_M MAKEMASK(0xFF, 24) 10068 #define E830_GL_TPRS_PROT_ID_MAP_PRFL(_i) (0x00202A00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 10069 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_MAX_INDEX 63 10070 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_0_S 0 10071 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_0_M MAKEMASK(0x3, 0) 10072 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_1_S 2 10073 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_1_M MAKEMASK(0x3, 2) 10074 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_2_S 4 10075 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_2_M MAKEMASK(0x3, 4) 10076 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_3_S 6 10077 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_3_M MAKEMASK(0x3, 6) 10078 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_4_S 8 10079 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_4_M MAKEMASK(0x3, 8) 10080 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_5_S 10 10081 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_5_M MAKEMASK(0x3, 10) 10082 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_6_S 12 10083 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_6_M MAKEMASK(0x3, 12) 10084 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_7_S 14 10085 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_7_M MAKEMASK(0x3, 14) 10086 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_8_S 16 10087 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_8_M MAKEMASK(0x3, 16) 10088 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_9_S 18 10089 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_9_M MAKEMASK(0x3, 18) 10090 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_10_S 20 10091 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_10_M MAKEMASK(0x3, 20) 10092 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_11_S 22 10093 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_11_M MAKEMASK(0x3, 22) 10094 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_12_S 24 10095 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_12_M MAKEMASK(0x3, 24) 10096 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_13_S 26 10097 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_13_M MAKEMASK(0x3, 26) 10098 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_14_S 28 10099 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_14_M MAKEMASK(0x3, 28) 10100 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_15_S 30 10101 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_15_M MAKEMASK(0x3, 30) 10102 #define E830_GL_TPRS_VALIDATE_CHECKS_CTL 0x00203A00 /* Reset Source: CORER */ 10103 #define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_0_EN_S 0 10104 #define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_0_EN_M BIT(0) 10105 #define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_1_EN_S 1 10106 #define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_1_EN_M BIT(1) 10107 #define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_0_S 2 10108 #define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_0_M BIT(2) 10109 #define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_1_S 3 10110 #define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_1_M BIT(3) 10111 #define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_0_S 4 10112 #define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_0_M BIT(4) 10113 #define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_1_S 5 10114 #define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_1_M BIT(5) 10115 #define E830_PRT_TDPU_TX_SIZE_CTRL 0x00049D20 /* Reset Source: CORER */ 10116 #define E830_PRT_TDPU_TX_SIZE_CTRL_MAX_HEADER_SIZE_S 16 10117 #define E830_PRT_TDPU_TX_SIZE_CTRL_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16) 10118 #define E830_PRT_TPB_RX_LB_SIZE_CTRL 0x00099740 /* Reset Source: CORER */ 10119 #define E830_PRT_TPB_RX_LB_SIZE_CTRL_MAX_HEADER_SIZE_S 16 10120 #define E830_PRT_TPB_RX_LB_SIZE_CTRL_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16) 10121 #define E830_GLQTX_TXTIME_DBELL_LSB_PAGE(_DBQM) (0x04000008 + ((_DBQM) * 4096)) /* _i=0...16383 */ /* Reset Source: CORER */ 10122 #define E830_GLQTX_TXTIME_DBELL_LSB_PAGE_MAX_INDEX 16383 10123 #define E830_GLQTX_TXTIME_DBELL_LSB_PAGE_QTX_TXTIME_DBELL_S 0 10124 #define E830_GLQTX_TXTIME_DBELL_LSB_PAGE_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0) 10125 #define E830_GLQTX_TXTIME_DBELL_MSB_PAGE(_DBQM) (0x0400000C + ((_DBQM) * 4096)) /* _i=0...16383 */ /* Reset Source: CORER */ 10126 #define E830_GLQTX_TXTIME_DBELL_MSB_PAGE_MAX_INDEX 16383 10127 #define E830_GLQTX_TXTIME_DBELL_MSB_PAGE_QTX_TXTIME_DBELL_S 0 10128 #define E830_GLQTX_TXTIME_DBELL_MSB_PAGE_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0) 10129 #define E830_PF0INT_OICR_PSM_PAGE_PTM_COMP_S 8 10130 #define E830_PF0INT_OICR_PSM_PAGE_PTM_COMP_M BIT(8) 10131 #define E830_PF0INT_OICR_PSM_PAGE_PQM_DBL_TO_S 9 10132 #define E830_PF0INT_OICR_PSM_PAGE_PQM_DBL_TO_M BIT(9) 10133 #define E830_PF0INT_OICR_PSM_PAGE_RSV5_S 10 10134 #define E830_PF0INT_OICR_PSM_PAGE_RSV5_M BIT(10) 10135 #define E830_GL_HIBA(_i) (0x00081000 + ((_i) * 4)) /* _i=0...1023 */ /* Reset Source: EMPR */ 10136 #define E830_GL_HIBA_MAX_INDEX 1023 10137 #define E830_GL_HIBA_GL_HIBA_S 0 10138 #define E830_GL_HIBA_GL_HIBA_M MAKEMASK(0xFFFFFFFF, 0) 10139 #define E830_GL_HICR 0x00082040 /* Reset Source: EMPR */ 10140 #define E830_GL_HICR_C_S 1 10141 #define E830_GL_HICR_C_M BIT(1) 10142 #define E830_GL_HICR_SV_S 2 10143 #define E830_GL_HICR_SV_M BIT(2) 10144 #define E830_GL_HICR_EV_S 3 10145 #define E830_GL_HICR_EV_M BIT(3) 10146 #define E830_GL_HICR_EN 0x00082044 /* Reset Source: EMPR */ 10147 #define E830_GL_HICR_EN_EN_S 0 10148 #define E830_GL_HICR_EN_EN_M BIT(0) 10149 #define E830_GL_HIDA(_i) (0x00082000 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: EMPR */ 10150 #define E830_GL_HIDA_MAX_INDEX 15 10151 #define E830_GL_HIDA_GL_HIDB_S 0 10152 #define E830_GL_HIDA_GL_HIDB_M MAKEMASK(0xFFFFFFFF, 0) 10153 #define E830_GLFLXP_RXDID_FLX_WRD_0_SPARE_S 18 10154 #define E830_GLFLXP_RXDID_FLX_WRD_0_SPARE_M MAKEMASK(0xF, 18) 10155 #define E830_GLFLXP_RXDID_FLX_WRD_1_SPARE_S 18 10156 #define E830_GLFLXP_RXDID_FLX_WRD_1_SPARE_M MAKEMASK(0xF, 18) 10157 #define E830_GLFLXP_RXDID_FLX_WRD_2_SPARE_S 18 10158 #define E830_GLFLXP_RXDID_FLX_WRD_2_SPARE_M MAKEMASK(0xF, 18) 10159 #define E830_GLFLXP_RXDID_FLX_WRD_3_SPARE_S 18 10160 #define E830_GLFLXP_RXDID_FLX_WRD_3_SPARE_M MAKEMASK(0xF, 18) 10161 #define E830_GLFLXP_RXDID_FLX_WRD_4_SPARE_S 18 10162 #define E830_GLFLXP_RXDID_FLX_WRD_4_SPARE_M MAKEMASK(0xF, 18) 10163 #define E830_GLFLXP_RXDID_FLX_WRD_5_SPARE_S 18 10164 #define E830_GLFLXP_RXDID_FLX_WRD_5_SPARE_M MAKEMASK(0xF, 18) 10165 #define E830_GLFLXP_RXDID_FLX_WRD_6(_i) (0x0045CE00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 10166 #define E830_GLFLXP_RXDID_FLX_WRD_6_MAX_INDEX 63 10167 #define E830_GLFLXP_RXDID_FLX_WRD_6_PROT_MDID_S 0 10168 #define E830_GLFLXP_RXDID_FLX_WRD_6_PROT_MDID_M MAKEMASK(0xFF, 0) 10169 #define E830_GLFLXP_RXDID_FLX_WRD_6_EXTRACTION_OFFSET_S 8 10170 #define E830_GLFLXP_RXDID_FLX_WRD_6_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8) 10171 #define E830_GLFLXP_RXDID_FLX_WRD_6_L2TAG_OVRD_EN_S 18 10172 #define E830_GLFLXP_RXDID_FLX_WRD_6_L2TAG_OVRD_EN_M BIT(18) 10173 #define E830_GLFLXP_RXDID_FLX_WRD_6_SPARE_S 19 10174 #define E830_GLFLXP_RXDID_FLX_WRD_6_SPARE_M MAKEMASK(0x7, 19) 10175 #define E830_GLFLXP_RXDID_FLX_WRD_6_RXDID_OPCODE_S 30 10176 #define E830_GLFLXP_RXDID_FLX_WRD_6_RXDID_OPCODE_M MAKEMASK(0x3, 30) 10177 #define E830_GLFLXP_RXDID_FLX_WRD_7(_i) (0x0045CF00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 10178 #define E830_GLFLXP_RXDID_FLX_WRD_7_MAX_INDEX 63 10179 #define E830_GLFLXP_RXDID_FLX_WRD_7_PROT_MDID_S 0 10180 #define E830_GLFLXP_RXDID_FLX_WRD_7_PROT_MDID_M MAKEMASK(0xFF, 0) 10181 #define E830_GLFLXP_RXDID_FLX_WRD_7_EXTRACTION_OFFSET_S 8 10182 #define E830_GLFLXP_RXDID_FLX_WRD_7_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8) 10183 #define E830_GLFLXP_RXDID_FLX_WRD_7_L2TAG_OVRD_EN_S 18 10184 #define E830_GLFLXP_RXDID_FLX_WRD_7_L2TAG_OVRD_EN_M BIT(18) 10185 #define E830_GLFLXP_RXDID_FLX_WRD_7_SPARE_S 19 10186 #define E830_GLFLXP_RXDID_FLX_WRD_7_SPARE_M MAKEMASK(0x7, 19) 10187 #define E830_GLFLXP_RXDID_FLX_WRD_7_RXDID_OPCODE_S 30 10188 #define E830_GLFLXP_RXDID_FLX_WRD_7_RXDID_OPCODE_M MAKEMASK(0x3, 30) 10189 #define E830_GLFLXP_RXDID_FLX_WRD_8(_i) (0x0045D500 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ 10190 #define E830_GLFLXP_RXDID_FLX_WRD_8_MAX_INDEX 63 10191 #define E830_GLFLXP_RXDID_FLX_WRD_8_PROT_MDID_S 0 10192 #define E830_GLFLXP_RXDID_FLX_WRD_8_PROT_MDID_M MAKEMASK(0xFF, 0) 10193 #define E830_GLFLXP_RXDID_FLX_WRD_8_EXTRACTION_OFFSET_S 8 10194 #define E830_GLFLXP_RXDID_FLX_WRD_8_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8) 10195 #define E830_GLFLXP_RXDID_FLX_WRD_8_L2TAG_OVRD_EN_S 18 10196 #define E830_GLFLXP_RXDID_FLX_WRD_8_L2TAG_OVRD_EN_M BIT(18) 10197 #define E830_GLFLXP_RXDID_FLX_WRD_8_SPARE_S 19 10198 #define E830_GLFLXP_RXDID_FLX_WRD_8_SPARE_M MAKEMASK(0x7, 19) 10199 #define E830_GLFLXP_RXDID_FLX_WRD_8_RXDID_OPCODE_S 30 10200 #define E830_GLFLXP_RXDID_FLX_WRD_8_RXDID_OPCODE_M MAKEMASK(0x3, 30) 10201 #define E830_GL_FW_LOGS(_i) (0x00082800 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: POR */ 10202 #define E830_GL_FW_LOGS_MAX_INDEX 255 10203 #define E830_GL_FW_LOGS_GL_FW_LOGS_S 0 10204 #define E830_GL_FW_LOGS_GL_FW_LOGS_M MAKEMASK(0xFFFFFFFF, 0) 10205 #define E830_GL_FWSTS_FWABS_S 10 10206 #define E830_GL_FWSTS_FWABS_M MAKEMASK(0x3, 10) 10207 #define E830_GL_FWSTS_FW_FAILOVER_TRIG_S 12 10208 #define E830_GL_FWSTS_FW_FAILOVER_TRIG_M BIT(12) 10209 #define E830_GLGEN_RSTAT_EMPR_WO_GLOBR_CNT_S 19 10210 #define E830_GLGEN_RSTAT_EMPR_WO_GLOBR_CNT_M MAKEMASK(0x3, 19) 10211 #define E830_GLGEN_RSTAT_EMPR_TYPE_S 21 10212 #define E830_GLGEN_RSTAT_EMPR_TYPE_M BIT(21) 10213 #define E830_GLPCI_PLATFORM_INFO 0x0009DDC4 /* Reset Source: POR */ 10214 #define E830_GLPCI_PLATFORM_INFO_PLATFORM_TYPE_S 0 10215 #define E830_GLPCI_PLATFORM_INFO_PLATFORM_TYPE_M MAKEMASK(0xFF, 0) 10216 #define E830_GL_MDCK_TDAT_TCLAN_TSYN_PKT_FROM_Q_NOT_ALLOWED_S 21 10217 #define E830_GL_MDCK_TDAT_TCLAN_TSYN_PKT_FROM_Q_NOT_ALLOWED_M BIT(21) 10218 #define E830_GL_MDCK_TDAT_TCLAN_TSYN_PKT_RANGE_VIOLATION_S 22 10219 #define E830_GL_MDCK_TDAT_TCLAN_TSYN_PKT_RANGE_VIOLATION_M BIT(22) 10220 #define E830_GL_MDCK_TDAT_TCLAN_DESC_TYPE_ACL_DTYPE_NOT_ALLOWED_S 23 10221 #define E830_GL_MDCK_TDAT_TCLAN_DESC_TYPE_ACL_DTYPE_NOT_ALLOWED_M BIT(23) 10222 #define E830_GL_TPB_LOCAL_TOPO 0x000996F4 /* Reset Source: CORER */ 10223 #define E830_GL_TPB_LOCAL_TOPO_ALLOW_TOPO_OVERRIDE_S 0 10224 #define E830_GL_TPB_LOCAL_TOPO_ALLOW_TOPO_OVERRIDE_M BIT(0) 10225 #define E830_GL_TPB_LOCAL_TOPO_TOPO_VAL_S 1 10226 #define E830_GL_TPB_LOCAL_TOPO_TOPO_VAL_M MAKEMASK(0x3, 1) 10227 #define E830_GL_TPB_PM_RESET 0x000996F0 /* Reset Source: CORER */ 10228 #define E830_GL_TPB_PM_RESET_MAC_PM_RESET_S 0 10229 #define E830_GL_TPB_PM_RESET_MAC_PM_RESET_M BIT(0) 10230 #define E830_GL_TPB_PM_RESET_RPB_PM_RESET_S 1 10231 #define E830_GL_TPB_PM_RESET_RPB_PM_RESET_M BIT(1) 10232 #define E830_GLTPB_100G_MAC_FC_THRESH1 0x00099724 /* Reset Source: CORER */ 10233 #define E830_GLTPB_100G_MAC_FC_THRESH1_PORT2_FC_THRESH_S 0 10234 #define E830_GLTPB_100G_MAC_FC_THRESH1_PORT2_FC_THRESH_M MAKEMASK(0xFFFF, 0) 10235 #define E830_GLTPB_100G_MAC_FC_THRESH1_PORT3_FC_THRESH_S 16 10236 #define E830_GLTPB_100G_MAC_FC_THRESH1_PORT3_FC_THRESH_M MAKEMASK(0xFFFF, 16) 10237 #define E830_GLTPB_100G_RPB_FC_THRESH0 0x0009963C /* Reset Source: CORER */ 10238 #define E830_GLTPB_100G_RPB_FC_THRESH0_PORT0_FC_THRESH_S 0 10239 #define E830_GLTPB_100G_RPB_FC_THRESH0_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0) 10240 #define E830_GLTPB_100G_RPB_FC_THRESH0_PORT1_FC_THRESH_S 16 10241 #define E830_GLTPB_100G_RPB_FC_THRESH0_PORT1_FC_THRESH_M MAKEMASK(0xFFFF, 16) 10242 #define E830_GLTPB_100G_RPB_FC_THRESH1 0x00099728 /* Reset Source: CORER */ 10243 #define E830_GLTPB_100G_RPB_FC_THRESH1_PORT2_FC_THRESH_S 0 10244 #define E830_GLTPB_100G_RPB_FC_THRESH1_PORT2_FC_THRESH_M MAKEMASK(0xFFFF, 0) 10245 #define E830_GLTPB_100G_RPB_FC_THRESH1_PORT3_FC_THRESH_S 16 10246 #define E830_GLTPB_100G_RPB_FC_THRESH1_PORT3_FC_THRESH_M MAKEMASK(0xFFFF, 16) 10247 #define E830_GL_UFUSE_SOC_MAX_PORT_SPEED_S 12 10248 #define E830_GL_UFUSE_SOC_MAX_PORT_SPEED_M MAKEMASK(0xFFFF, 12) 10249 #define E830_PF0INT_OICR_PSM_PTM_COMP_S 8 10250 #define E830_PF0INT_OICR_PSM_PTM_COMP_M BIT(8) 10251 #define E830_PF0INT_OICR_PSM_PQM_DBL_TO_S 9 10252 #define E830_PF0INT_OICR_PSM_PQM_DBL_TO_M BIT(9) 10253 #define E830_PF0INT_OICR_PSM_RSV5_S 10 10254 #define E830_PF0INT_OICR_PSM_RSV5_M BIT(10) 10255 #define E830_PFINT_OICR_PTM_COMP_S 8 10256 #define E830_PFINT_OICR_PTM_COMP_M BIT(8) 10257 #define E830_PFINT_OICR_PQM_DBL_TO_S 9 10258 #define E830_PFINT_OICR_PQM_DBL_TO_M BIT(9) 10259 #define E830_PFINT_OICR_RSV5_S 10 10260 #define E830_PFINT_OICR_RSV5_M BIT(10) 10261 #define E830_QRX_CTRL_IDE_S 27 10262 #define E830_QRX_CTRL_IDE_M BIT(27) 10263 #define E830_PRTMAC_200G_CL01_PAUSE_QUANTA 0x001E3854 /* Reset Source: GLOBR */ 10264 #define E830_PRTMAC_200G_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_S 0 10265 #define E830_PRTMAC_200G_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0) 10266 #define E830_PRTMAC_200G_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_S 16 10267 #define E830_PRTMAC_200G_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16) 10268 #define E830_PRTMAC_200G_CL01_QUANTA_THRESH 0x001E3864 /* Reset Source: GLOBR */ 10269 #define E830_PRTMAC_200G_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_S 0 10270 #define E830_PRTMAC_200G_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0) 10271 #define E830_PRTMAC_200G_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_S 16 10272 #define E830_PRTMAC_200G_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16) 10273 #define E830_PRTMAC_200G_CL23_PAUSE_QUANTA 0x001E3858 /* Reset Source: GLOBR */ 10274 #define E830_PRTMAC_200G_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_S 0 10275 #define E830_PRTMAC_200G_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0) 10276 #define E830_PRTMAC_200G_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_S 16 10277 #define E830_PRTMAC_200G_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16) 10278 #define E830_PRTMAC_200G_CL23_QUANTA_THRESH 0x001E3868 /* Reset Source: GLOBR */ 10279 #define E830_PRTMAC_200G_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_S 0 10280 #define E830_PRTMAC_200G_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0) 10281 #define E830_PRTMAC_200G_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_S 16 10282 #define E830_PRTMAC_200G_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16) 10283 #define E830_PRTMAC_200G_CL45_PAUSE_QUANTA 0x001E385C /* Reset Source: GLOBR */ 10284 #define E830_PRTMAC_200G_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_S 0 10285 #define E830_PRTMAC_200G_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0) 10286 #define E830_PRTMAC_200G_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_S 16 10287 #define E830_PRTMAC_200G_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16) 10288 #define E830_PRTMAC_200G_CL45_QUANTA_THRESH 0x001E386C /* Reset Source: GLOBR */ 10289 #define E830_PRTMAC_200G_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_S 0 10290 #define E830_PRTMAC_200G_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0) 10291 #define E830_PRTMAC_200G_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_S 16 10292 #define E830_PRTMAC_200G_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16) 10293 #define E830_PRTMAC_200G_CL67_PAUSE_QUANTA 0x001E3860 /* Reset Source: GLOBR */ 10294 #define E830_PRTMAC_200G_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_S 0 10295 #define E830_PRTMAC_200G_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0) 10296 #define E830_PRTMAC_200G_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_S 16 10297 #define E830_PRTMAC_200G_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16) 10298 #define E830_PRTMAC_200G_CL67_QUANTA_THRESH 0x001E3870 /* Reset Source: GLOBR */ 10299 #define E830_PRTMAC_200G_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_S 0 10300 #define E830_PRTMAC_200G_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0) 10301 #define E830_PRTMAC_200G_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_S 16 10302 #define E830_PRTMAC_200G_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16) 10303 #define E830_PRTMAC_200G_COMMAND_CONFIG 0x001E3808 /* Reset Source: GLOBR */ 10304 #define E830_PRTMAC_200G_COMMAND_CONFIG_TX_ENA_S 0 10305 #define E830_PRTMAC_200G_COMMAND_CONFIG_TX_ENA_M BIT(0) 10306 #define E830_PRTMAC_200G_COMMAND_CONFIG_RX_ENA_S 1 10307 #define E830_PRTMAC_200G_COMMAND_CONFIG_RX_ENA_M BIT(1) 10308 #define E830_PRTMAC_200G_COMMAND_CONFIG_PROMIS_EN_S 4 10309 #define E830_PRTMAC_200G_COMMAND_CONFIG_PROMIS_EN_M BIT(4) 10310 #define E830_PRTMAC_200G_COMMAND_CONFIG_PAD_EN_S 5 10311 #define E830_PRTMAC_200G_COMMAND_CONFIG_PAD_EN_M BIT(5) 10312 #define E830_PRTMAC_200G_COMMAND_CONFIG_CRC_FWD_S 6 10313 #define E830_PRTMAC_200G_COMMAND_CONFIG_CRC_FWD_M BIT(6) 10314 #define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_FWD_S 7 10315 #define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_FWD_M BIT(7) 10316 #define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_IGNORE_S 8 10317 #define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_IGNORE_M BIT(8) 10318 #define E830_PRTMAC_200G_COMMAND_CONFIG_TX_ADDR_INS_S 9 10319 #define E830_PRTMAC_200G_COMMAND_CONFIG_TX_ADDR_INS_M BIT(9) 10320 #define E830_PRTMAC_200G_COMMAND_CONFIG_LOOPBACK_EN_S 10 10321 #define E830_PRTMAC_200G_COMMAND_CONFIG_LOOPBACK_EN_M BIT(10) 10322 #define E830_PRTMAC_200G_COMMAND_CONFIG_TX_PAD_EN_S 11 10323 #define E830_PRTMAC_200G_COMMAND_CONFIG_TX_PAD_EN_M BIT(11) 10324 #define E830_PRTMAC_200G_COMMAND_CONFIG_SW_RESET_S 12 10325 #define E830_PRTMAC_200G_COMMAND_CONFIG_SW_RESET_M BIT(12) 10326 #define E830_PRTMAC_200G_COMMAND_CONFIG_CNTL_FRM_ENA_S 13 10327 #define E830_PRTMAC_200G_COMMAND_CONFIG_CNTL_FRM_ENA_M BIT(13) 10328 #define E830_PRTMAC_200G_COMMAND_CONFIG_RX_ERR_DISC_S 14 10329 #define E830_PRTMAC_200G_COMMAND_CONFIG_RX_ERR_DISC_M BIT(14) 10330 #define E830_PRTMAC_200G_COMMAND_CONFIG_PHY_TXENA_S 15 10331 #define E830_PRTMAC_200G_COMMAND_CONFIG_PHY_TXENA_M BIT(15) 10332 #define E830_PRTMAC_200G_COMMAND_CONFIG_SEND_IDLE_S 16 10333 #define E830_PRTMAC_200G_COMMAND_CONFIG_SEND_IDLE_M BIT(16) 10334 #define E830_PRTMAC_200G_COMMAND_CONFIG_NO_LGTH_CHECK_S 17 10335 #define E830_PRTMAC_200G_COMMAND_CONFIG_NO_LGTH_CHECK_M BIT(17) 10336 #define E830_PRTMAC_200G_COMMAND_CONFIG_PFC_MODE_S 19 10337 #define E830_PRTMAC_200G_COMMAND_CONFIG_PFC_MODE_M BIT(19) 10338 #define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_PFC_COMP_S 20 10339 #define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_PFC_COMP_M BIT(20) 10340 #define E830_PRTMAC_200G_COMMAND_CONFIG_RX_SFD_ANY_S 21 10341 #define E830_PRTMAC_200G_COMMAND_CONFIG_RX_SFD_ANY_M BIT(21) 10342 #define E830_PRTMAC_200G_COMMAND_CONFIG_TX_FLUSH_S 22 10343 #define E830_PRTMAC_200G_COMMAND_CONFIG_TX_FLUSH_M BIT(22) 10344 #define E830_PRTMAC_200G_COMMAND_CONFIG_FLT_TX_STOP_S 25 10345 #define E830_PRTMAC_200G_COMMAND_CONFIG_FLT_TX_STOP_M BIT(25) 10346 #define E830_PRTMAC_200G_COMMAND_CONFIG_TX_FIFO_RESET_S 26 10347 #define E830_PRTMAC_200G_COMMAND_CONFIG_TX_FIFO_RESET_M BIT(26) 10348 #define E830_PRTMAC_200G_COMMAND_CONFIG_FLT_HDL_DIS_S 27 10349 #define E830_PRTMAC_200G_COMMAND_CONFIG_FLT_HDL_DIS_M BIT(27) 10350 #define E830_PRTMAC_200G_COMMAND_CONFIG_INV_LOOP_S 31 10351 #define E830_PRTMAC_200G_COMMAND_CONFIG_INV_LOOP_M BIT(31) 10352 #define E830_PRTMAC_200G_CRC_INV_M 0x001E384C /* Reset Source: GLOBR */ 10353 #define E830_PRTMAC_200G_CRC_INV_MASK_CRC_INV_MASK_S 0 10354 #define E830_PRTMAC_200G_CRC_INV_MASK_CRC_INV_MASK_M MAKEMASK(0xFFFFFFFF, 0) 10355 #define E830_PRTMAC_200G_FRM_LENGTH 0x001E3814 /* Reset Source: GLOBR */ 10356 #define E830_PRTMAC_200G_FRM_LENGTH_FRM_LENGTH_S 0 10357 #define E830_PRTMAC_200G_FRM_LENGTH_FRM_LENGTH_M MAKEMASK(0xFFFF, 0) 10358 #define E830_PRTMAC_200G_FRM_LENGTH_TX_MTU_S 16 10359 #define E830_PRTMAC_200G_FRM_LENGTH_TX_MTU_M MAKEMASK(0xFFFF, 16) 10360 #define E830_PRTMAC_200G_HASHTABLE_LOAD 0x001E382C /* Reset Source: GLOBR */ 10361 #define E830_PRTMAC_200G_HASHTABLE_LOAD_HASH_TABLE_ADDR_S 0 10362 #define E830_PRTMAC_200G_HASHTABLE_LOAD_HASH_TABLE_ADDR_M MAKEMASK(0x3F, 0) 10363 #define E830_PRTMAC_200G_HASHTABLE_LOAD_MCAST_EN_S 8 10364 #define E830_PRTMAC_200G_HASHTABLE_LOAD_MCAST_EN_M BIT(8) 10365 #define E830_PRTMAC_200G_MAC_ADDR_0 0x001E380C /* Reset Source: GLOBR */ 10366 #define E830_PRTMAC_200G_MAC_ADDR_0_MAC_ADDR_0_S 0 10367 #define E830_PRTMAC_200G_MAC_ADDR_0_MAC_ADDR_0_M MAKEMASK(0xFFFFFFFF, 0) 10368 #define E830_PRTMAC_200G_MAC_ADDR_1 0x001E3810 /* Reset Source: GLOBR */ 10369 #define E830_PRTMAC_200G_MAC_ADDR_1_MAC_ADDR_1_S 0 10370 #define E830_PRTMAC_200G_MAC_ADDR_1_MAC_ADDR_1_M MAKEMASK(0xFFFF, 0) 10371 #define E830_PRTMAC_200G_MDIO_CFG_STATUS 0x001E3830 /* Reset Source: GLOBR */ 10372 #define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_BUSY_S 0 10373 #define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_BUSY_M BIT(0) 10374 #define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_RD_ERR_S 1 10375 #define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_RD_ERR_M BIT(1) 10376 #define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_HOLD_TIME_S 2 10377 #define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_HOLD_TIME_M MAKEMASK(0x7, 2) 10378 #define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_DIS_PREAMBLE_S 5 10379 #define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_DIS_PREAMBLE_M BIT(5) 10380 #define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_CLS_45_EN_S 6 10381 #define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_CLS_45_EN_M BIT(6) 10382 #define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_CLK_DIVISOR_S 7 10383 #define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_CLK_DIVISOR_M MAKEMASK(0x1FF, 7) 10384 #define E830_PRTMAC_200G_MDIO_COMMAND 0x001E3834 /* Reset Source: GLOBR */ 10385 #define E830_PRTMAC_200G_MDIO_COMMAND_MDIO_COMMAND_S 0 10386 #define E830_PRTMAC_200G_MDIO_COMMAND_MDIO_COMMAND_M MAKEMASK(0xFFFF, 0) 10387 #define E830_PRTMAC_200G_MDIO_COMMAND_RESERVED_2_S 16 10388 #define E830_PRTMAC_200G_MDIO_COMMAND_RESERVED_2_M MAKEMASK(0x7FFF, 16) 10389 #define E830_PRTMAC_200G_MDIO_COMMAND_MDIO_BUSY_S 31 10390 #define E830_PRTMAC_200G_MDIO_COMMAND_MDIO_BUSY_M BIT(31) 10391 #define E830_PRTMAC_200G_MDIO_DATA 0x001E3838 /* Reset Source: GLOBR */ 10392 #define E830_PRTMAC_200G_MDIO_DATA_MDIO_DATA_S 0 10393 #define E830_PRTMAC_200G_MDIO_DATA_MDIO_DATA_M MAKEMASK(0xFFFF, 0) 10394 #define E830_PRTMAC_200G_MDIO_DATA_RESERVED_2_S 16 10395 #define E830_PRTMAC_200G_MDIO_DATA_RESERVED_2_M MAKEMASK(0x7FFF, 16) 10396 #define E830_PRTMAC_200G_MDIO_DATA_MDIO_BUSY_S 31 10397 #define E830_PRTMAC_200G_MDIO_DATA_MDIO_BUSY_M BIT(31) 10398 #define E830_PRTMAC_200G_MDIO_REGADDR 0x001E383C /* Reset Source: GLOBR */ 10399 #define E830_PRTMAC_200G_MDIO_REGADDR_MDIO_REGADDR_S 0 10400 #define E830_PRTMAC_200G_MDIO_REGADDR_MDIO_REGADDR_M MAKEMASK(0xFFFFFFFF, 0) 10401 #define E830_PRTMAC_200G_REVISION 0x001E3800 /* Reset Source: GLOBR */ 10402 #define E830_PRTMAC_200G_REVISION_CORE_REVISION_S 0 10403 #define E830_PRTMAC_200G_REVISION_CORE_REVISION_M MAKEMASK(0xFF, 0) 10404 #define E830_PRTMAC_200G_REVISION_CORE_VERSION_S 8 10405 #define E830_PRTMAC_200G_REVISION_CORE_VERSION_M MAKEMASK(0xFF, 8) 10406 #define E830_PRTMAC_200G_REVISION_CUSTOMER_VERSION_S 16 10407 #define E830_PRTMAC_200G_REVISION_CUSTOMER_VERSION_M MAKEMASK(0xFFFF, 16) 10408 #define E830_PRTMAC_200G_RX_PAUSE_STATUS 0x001E3874 /* Reset Source: GLOBR */ 10409 #define E830_PRTMAC_200G_RX_PAUSE_STATUS_RX_PAUSE_STATUS_S 0 10410 #define E830_PRTMAC_200G_RX_PAUSE_STATUS_RX_PAUSE_STATUS_M MAKEMASK(0xFF, 0) 10411 #define E830_PRTMAC_200G_SCRATCH 0x001E3804 /* Reset Source: GLOBR */ 10412 #define E830_PRTMAC_200G_SCRATCH_SCRATCH_S 0 10413 #define E830_PRTMAC_200G_SCRATCH_SCRATCH_M MAKEMASK(0xFFFFFFFF, 0) 10414 #define E830_PRTMAC_200G_STATUS 0x001E3840 /* Reset Source: GLOBR */ 10415 #define E830_PRTMAC_200G_STATUS_RX_LOC_FAULT_S 0 10416 #define E830_PRTMAC_200G_STATUS_RX_LOC_FAULT_M BIT(0) 10417 #define E830_PRTMAC_200G_STATUS_RX_REM_FAULT_S 1 10418 #define E830_PRTMAC_200G_STATUS_RX_REM_FAULT_M BIT(1) 10419 #define E830_PRTMAC_200G_STATUS_PHY_LOS_S 2 10420 #define E830_PRTMAC_200G_STATUS_PHY_LOS_M BIT(2) 10421 #define E830_PRTMAC_200G_STATUS_TS_AVAIL_S 3 10422 #define E830_PRTMAC_200G_STATUS_TS_AVAIL_M BIT(3) 10423 #define E830_PRTMAC_200G_STATUS_RESERVED_5_S 4 10424 #define E830_PRTMAC_200G_STATUS_RESERVED_5_M BIT(4) 10425 #define E830_PRTMAC_200G_STATUS_TX_EMPTY_S 5 10426 #define E830_PRTMAC_200G_STATUS_TX_EMPTY_M BIT(5) 10427 #define E830_PRTMAC_200G_STATUS_RX_EMPTY_S 6 10428 #define E830_PRTMAC_200G_STATUS_RX_EMPTY_M BIT(6) 10429 #define E830_PRTMAC_200G_STATUS_RESERVED1_S 7 10430 #define E830_PRTMAC_200G_STATUS_RESERVED1_M BIT(7) 10431 #define E830_PRTMAC_200G_STATUS_TX_ISIDLE_S 8 10432 #define E830_PRTMAC_200G_STATUS_TX_ISIDLE_M BIT(8) 10433 #define E830_PRTMAC_200G_STATUS_RESERVED2_S 9 10434 #define E830_PRTMAC_200G_STATUS_RESERVED2_M MAKEMASK(0x7FFFFF, 9) 10435 #define E830_PRTMAC_200G_TS_TIMESTAMP 0x001E387C /* Reset Source: GLOBR */ 10436 #define E830_PRTMAC_200G_TS_TIMESTAMP_TS_TIMESTAMP_S 0 10437 #define E830_PRTMAC_200G_TS_TIMESTAMP_TS_TIMESTAMP_M MAKEMASK(0xFFFFFFFF, 0) 10438 #define E830_PRTMAC_200G_TX_FIFO_SECTIONS 0x001E3820 /* Reset Source: GLOBR */ 10439 #define E830_PRTMAC_200G_TX_FIFO_SECTIONS_TX_SECTION_AVAIL_THRESHOLD_S 0 10440 #define E830_PRTMAC_200G_TX_FIFO_SECTIONS_TX_SECTION_AVAIL_THRESHOLD_M MAKEMASK(0xFFFF, 0) 10441 #define E830_PRTMAC_200G_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_THRESHOLD_S 16 10442 #define E830_PRTMAC_200G_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_THRESHOLD_M MAKEMASK(0xFFFF, 16) 10443 #define E830_PRTMAC_200G_TX_IPG_LENGTH 0x001E3844 /* Reset Source: GLOBR */ 10444 #define E830_PRTMAC_200G_TX_IPG_LENGTH_AVG_IPG_LEN_S 0 10445 #define E830_PRTMAC_200G_TX_IPG_LENGTH_AVG_IPG_LEN_M MAKEMASK(0x7F, 0) 10446 #define E830_PRTMAC_200G_TX_IPG_LENGTH_IPG_COMP_12_0_S 19 10447 #define E830_PRTMAC_200G_TX_IPG_LENGTH_IPG_COMP_12_0_M MAKEMASK(0x1FFF, 19) 10448 #define E830_PRTMAC_200G_XIF_MODE 0x001E3880 /* Reset Source: GLOBR */ 10449 #define E830_PRTMAC_200G_XIF_MODE_RESERVED_1_S 0 10450 #define E830_PRTMAC_200G_XIF_MODE_RESERVED_1_M MAKEMASK(0x1F, 0) 10451 #define E830_PRTMAC_200G_XIF_MODE_ONE_STEP_ENA_S 5 10452 #define E830_PRTMAC_200G_XIF_MODE_ONE_STEP_ENA_M BIT(5) 10453 #define E830_PRTMAC_200G_XIF_MODE_PFC_PULSE_MODE_S 17 10454 #define E830_PRTMAC_200G_XIF_MODE_PFC_PULSE_MODE_M BIT(17) 10455 #define E830_PRTMAC_200G_XIF_MODE_PFC_LP_MODE_S 18 10456 #define E830_PRTMAC_200G_XIF_MODE_PFC_LP_MODE_M BIT(18) 10457 #define E830_PRTMAC_200G_XIF_MODE_PFC_LP_16PRI_S 19 10458 #define E830_PRTMAC_200G_XIF_MODE_PFC_LP_16PRI_M BIT(19) 10459 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_0 0x001E3C00 /* Reset Source: GLOBR */ 10460 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_0_APPROVED_SW_ADDR_MAC_100G_0_S 0 10461 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_0_APPROVED_SW_ADDR_MAC_100G_0_M MAKEMASK(0x3F, 0) 10462 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_1 0x001E3C20 /* Reset Source: GLOBR */ 10463 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_1_APPROVED_SW_ADDR_MAC_100G_1_S 0 10464 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_1_APPROVED_SW_ADDR_MAC_100G_1_M MAKEMASK(0x3F, 0) 10465 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_2 0x001E3C40 /* Reset Source: GLOBR */ 10466 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_2_APPROVED_SW_ADDR_MAC_100G_2_S 0 10467 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_2_APPROVED_SW_ADDR_MAC_100G_2_M MAKEMASK(0x3F, 0) 10468 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_3 0x001E3C60 /* Reset Source: GLOBR */ 10469 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_3_APPROVED_SW_ADDR_MAC_100G_3_S 0 10470 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_3_APPROVED_SW_ADDR_MAC_100G_3_M MAKEMASK(0x3F, 0) 10471 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_0 0x001E3C80 /* Reset Source: GLOBR */ 10472 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_0_APPROVED_SW_ADDR_MAC_200G_0_S 0 10473 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_0_APPROVED_SW_ADDR_MAC_200G_0_M MAKEMASK(0xFF, 0) 10474 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_1 0x001E3CA0 /* Reset Source: GLOBR */ 10475 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_1_APPROVED_SW_ADDR_MAC_200G_1_S 0 10476 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_1_APPROVED_SW_ADDR_MAC_200G_1_M MAKEMASK(0xFF, 0) 10477 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_2 0x001E3CC0 /* Reset Source: GLOBR */ 10478 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_2_APPROVED_SW_ADDR_MAC_200G_2_S 0 10479 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_2_APPROVED_SW_ADDR_MAC_200G_2_M MAKEMASK(0xFF, 0) 10480 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_3 0x001E3CE0 /* Reset Source: GLOBR */ 10481 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_3_APPROVED_SW_ADDR_MAC_200G_3_S 0 10482 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_3_APPROVED_SW_ADDR_MAC_200G_3_M MAKEMASK(0xFF, 0) 10483 #define E830_PRTMAC_CF_GEN_STATUS 0x001E33C0 /* Reset Source: GLOBR */ 10484 #define E830_PRTMAC_CF_GEN_STATUS_CF_GEN_SENT_S 0 10485 #define E830_PRTMAC_CF_GEN_STATUS_CF_GEN_SENT_M BIT(0) 10486 #define E830_PRTMAC_CL01_PAUSE_QUANTA 0x001E32A0 /* Reset Source: GLOBR */ 10487 #define E830_PRTMAC_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_S 0 10488 #define E830_PRTMAC_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0) 10489 #define E830_PRTMAC_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_S 16 10490 #define E830_PRTMAC_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16) 10491 #define E830_PRTMAC_CL01_QUANTA_THRESH 0x001E3320 /* Reset Source: GLOBR */ 10492 #define E830_PRTMAC_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_S 0 10493 #define E830_PRTMAC_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0) 10494 #define E830_PRTMAC_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_S 16 10495 #define E830_PRTMAC_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16) 10496 #define E830_PRTMAC_CL23_PAUSE_QUANTA 0x001E32C0 /* Reset Source: GLOBR */ 10497 #define E830_PRTMAC_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_S 0 10498 #define E830_PRTMAC_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0) 10499 #define E830_PRTMAC_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_S 16 10500 #define E830_PRTMAC_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16) 10501 #define E830_PRTMAC_CL23_QUANTA_THRESH 0x001E3340 /* Reset Source: GLOBR */ 10502 #define E830_PRTMAC_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_S 0 10503 #define E830_PRTMAC_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0) 10504 #define E830_PRTMAC_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_S 16 10505 #define E830_PRTMAC_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16) 10506 #define E830_PRTMAC_CL45_PAUSE_QUANTA 0x001E32E0 /* Reset Source: GLOBR */ 10507 #define E830_PRTMAC_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_S 0 10508 #define E830_PRTMAC_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0) 10509 #define E830_PRTMAC_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_S 16 10510 #define E830_PRTMAC_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16) 10511 #define E830_PRTMAC_CL45_QUANTA_THRESH 0x001E3360 /* Reset Source: GLOBR */ 10512 #define E830_PRTMAC_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_S 0 10513 #define E830_PRTMAC_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0) 10514 #define E830_PRTMAC_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_S 16 10515 #define E830_PRTMAC_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16) 10516 #define E830_PRTMAC_CL67_PAUSE_QUANTA 0x001E3300 /* Reset Source: GLOBR */ 10517 #define E830_PRTMAC_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_S 0 10518 #define E830_PRTMAC_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0) 10519 #define E830_PRTMAC_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_S 16 10520 #define E830_PRTMAC_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16) 10521 #define E830_PRTMAC_CL67_QUANTA_THRESH 0x001E3380 /* Reset Source: GLOBR */ 10522 #define E830_PRTMAC_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_S 0 10523 #define E830_PRTMAC_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0) 10524 #define E830_PRTMAC_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_S 16 10525 #define E830_PRTMAC_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16) 10526 #define E830_PRTMAC_COMMAND_CONFIG 0x001E3040 /* Reset Source: GLOBR */ 10527 #define E830_PRTMAC_COMMAND_CONFIG_TX_ENA_S 0 10528 #define E830_PRTMAC_COMMAND_CONFIG_TX_ENA_M BIT(0) 10529 #define E830_PRTMAC_COMMAND_CONFIG_RX_ENA_S 1 10530 #define E830_PRTMAC_COMMAND_CONFIG_RX_ENA_M BIT(1) 10531 #define E830_PRTMAC_COMMAND_CONFIG_RESERVED1_S 3 10532 #define E830_PRTMAC_COMMAND_CONFIG_RESERVED1_M BIT(3) 10533 #define E830_PRTMAC_COMMAND_CONFIG_PROMIS_EN_S 4 10534 #define E830_PRTMAC_COMMAND_CONFIG_PROMIS_EN_M BIT(4) 10535 #define E830_PRTMAC_COMMAND_CONFIG_RESERVED2_S 5 10536 #define E830_PRTMAC_COMMAND_CONFIG_RESERVED2_M BIT(5) 10537 #define E830_PRTMAC_COMMAND_CONFIG_CRC_FWD_S 6 10538 #define E830_PRTMAC_COMMAND_CONFIG_CRC_FWD_M BIT(6) 10539 #define E830_PRTMAC_COMMAND_CONFIG_PAUSE_FWD_S 7 10540 #define E830_PRTMAC_COMMAND_CONFIG_PAUSE_FWD_M BIT(7) 10541 #define E830_PRTMAC_COMMAND_CONFIG_PAUSE_IGNORE_S 8 10542 #define E830_PRTMAC_COMMAND_CONFIG_PAUSE_IGNORE_M BIT(8) 10543 #define E830_PRTMAC_COMMAND_CONFIG_TX_ADDR_INS_S 9 10544 #define E830_PRTMAC_COMMAND_CONFIG_TX_ADDR_INS_M BIT(9) 10545 #define E830_PRTMAC_COMMAND_CONFIG_LOOP_ENA_S 10 10546 #define E830_PRTMAC_COMMAND_CONFIG_LOOP_ENA_M BIT(10) 10547 #define E830_PRTMAC_COMMAND_CONFIG_TX_PAD_EN_S 11 10548 #define E830_PRTMAC_COMMAND_CONFIG_TX_PAD_EN_M BIT(11) 10549 #define E830_PRTMAC_COMMAND_CONFIG_SW_RESET_S 12 10550 #define E830_PRTMAC_COMMAND_CONFIG_SW_RESET_M BIT(12) 10551 #define E830_PRTMAC_COMMAND_CONFIG_CNTL_FRM_ENA_S 13 10552 #define E830_PRTMAC_COMMAND_CONFIG_CNTL_FRM_ENA_M BIT(13) 10553 #define E830_PRTMAC_COMMAND_CONFIG_RESERVED3_S 14 10554 #define E830_PRTMAC_COMMAND_CONFIG_RESERVED3_M BIT(14) 10555 #define E830_PRTMAC_COMMAND_CONFIG_PHY_TXENA_S 15 10556 #define E830_PRTMAC_COMMAND_CONFIG_PHY_TXENA_M BIT(15) 10557 #define E830_PRTMAC_COMMAND_CONFIG_FORCE_SEND__S 16 10558 #define E830_PRTMAC_COMMAND_CONFIG_FORCE_SEND__M BIT(16) 10559 #define E830_PRTMAC_COMMAND_CONFIG_RESERVED4_S 17 10560 #define E830_PRTMAC_COMMAND_CONFIG_RESERVED4_M BIT(17) 10561 #define E830_PRTMAC_COMMAND_CONFIG_RESERVED5_S 18 10562 #define E830_PRTMAC_COMMAND_CONFIG_RESERVED5_M BIT(18) 10563 #define E830_PRTMAC_COMMAND_CONFIG_PFC_MODE_S 19 10564 #define E830_PRTMAC_COMMAND_CONFIG_PFC_MODE_M BIT(19) 10565 #define E830_PRTMAC_COMMAND_CONFIG_PAUSE_PFC_COMP_S 20 10566 #define E830_PRTMAC_COMMAND_CONFIG_PAUSE_PFC_COMP_M BIT(20) 10567 #define E830_PRTMAC_COMMAND_CONFIG_RX_SFD_ANY_S 21 10568 #define E830_PRTMAC_COMMAND_CONFIG_RX_SFD_ANY_M BIT(21) 10569 #define E830_PRTMAC_COMMAND_CONFIG_TX_FLUSH_S 22 10570 #define E830_PRTMAC_COMMAND_CONFIG_TX_FLUSH_M BIT(22) 10571 #define E830_PRTMAC_COMMAND_CONFIG_TX_LOWP_ENA_S 23 10572 #define E830_PRTMAC_COMMAND_CONFIG_TX_LOWP_ENA_M BIT(23) 10573 #define E830_PRTMAC_COMMAND_CONFIG_REG_LOWP_RXEMPTY_S 24 10574 #define E830_PRTMAC_COMMAND_CONFIG_REG_LOWP_RXEMPTY_M BIT(24) 10575 #define E830_PRTMAC_COMMAND_CONFIG_FLT_TX_STOP_S 25 10576 #define E830_PRTMAC_COMMAND_CONFIG_FLT_TX_STOP_M BIT(25) 10577 #define E830_PRTMAC_COMMAND_CONFIG_TX_FIFO_RESET_S 26 10578 #define E830_PRTMAC_COMMAND_CONFIG_TX_FIFO_RESET_M BIT(26) 10579 #define E830_PRTMAC_COMMAND_CONFIG_FLT_HDL_DIS_S 27 10580 #define E830_PRTMAC_COMMAND_CONFIG_FLT_HDL_DIS_M BIT(27) 10581 #define E830_PRTMAC_COMMAND_CONFIG_TX_PAUSE_DIS_S 28 10582 #define E830_PRTMAC_COMMAND_CONFIG_TX_PAUSE_DIS_M BIT(28) 10583 #define E830_PRTMAC_COMMAND_CONFIG_RX_PAUSE_DIS_S 29 10584 #define E830_PRTMAC_COMMAND_CONFIG_RX_PAUSE_DIS_M BIT(29) 10585 #define E830_PRTMAC_COMMAND_CONFIG_SHORT_PREAM_S 30 10586 #define E830_PRTMAC_COMMAND_CONFIG_SHORT_PREAM_M BIT(30) 10587 #define E830_PRTMAC_COMMAND_CONFIG_NO_PREAM_S 31 10588 #define E830_PRTMAC_COMMAND_CONFIG_NO_PREAM_M BIT(31) 10589 #define E830_PRTMAC_CRC_INV_M 0x001E3260 /* Reset Source: GLOBR */ 10590 #define E830_PRTMAC_CRC_INV_MASK_CRC_INV_MASK_S 0 10591 #define E830_PRTMAC_CRC_INV_MASK_CRC_INV_MASK_M MAKEMASK(0xFFFFFFFF, 0) 10592 #define E830_PRTMAC_CRC_MODE 0x001E3240 /* Reset Source: GLOBR */ 10593 #define E830_PRTMAC_CRC_MODE_DISABLE_RX_CRC_CHECKING_S 16 10594 #define E830_PRTMAC_CRC_MODE_DISABLE_RX_CRC_CHECKING_M BIT(16) 10595 #define E830_PRTMAC_CRC_MODE_ONE_BYTE_CRC_S 18 10596 #define E830_PRTMAC_CRC_MODE_ONE_BYTE_CRC_M BIT(18) 10597 #define E830_PRTMAC_CRC_MODE_TWO_BYTES_CRC_S 19 10598 #define E830_PRTMAC_CRC_MODE_TWO_BYTES_CRC_M BIT(19) 10599 #define E830_PRTMAC_CRC_MODE_ZERO_BYTE_CRC_S 20 10600 #define E830_PRTMAC_CRC_MODE_ZERO_BYTE_CRC_M BIT(20) 10601 #define E830_PRTMAC_CSR_TIMEOUT_CFG 0x001E3D00 /* Reset Source: GLOBR */ 10602 #define E830_PRTMAC_CSR_TIMEOUT_CFG_CSR_TIMEOUT_EN_S 0 10603 #define E830_PRTMAC_CSR_TIMEOUT_CFG_CSR_TIMEOUT_EN_M BIT(0) 10604 #define E830_PRTMAC_CTL_RX_CFG 0x001E2160 /* Reset Source: GLOBR */ 10605 #define E830_PRTMAC_CTL_RX_CFG_SUB_CRC_STAT_S 0 10606 #define E830_PRTMAC_CTL_RX_CFG_SUB_CRC_STAT_M BIT(0) 10607 #define E830_PRTMAC_CTL_RX_CFG_FRM_DROP_FOR_STAT_MODE_S 1 10608 #define E830_PRTMAC_CTL_RX_CFG_FRM_DROP_FOR_STAT_MODE_M MAKEMASK(0x3, 1) 10609 #define E830_PRTMAC_CTL_RX_CFG_MAC_PAC_AFULL_TRSH_S 3 10610 #define E830_PRTMAC_CTL_RX_CFG_MAC_PAC_AFULL_TRSH_M MAKEMASK(0x7, 3) 10611 #define E830_PRTMAC_CTL_RX_PAUSE_ENABLE 0x001E2180 /* Reset Source: GLOBR */ 10612 #define E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_S 0 10613 #define E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0) 10614 #define E830_PRTMAC_CTL_TX_PAUSE_ENABLE 0x001E21A0 /* Reset Source: GLOBR */ 10615 #define E830_PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_S 0 10616 #define E830_PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0) 10617 #define E830_PRTMAC_FRM_LENGTH 0x001E30A0 /* Reset Source: GLOBR */ 10618 #define E830_PRTMAC_FRM_LENGTH_FRM_LENGTH_S 0 10619 #define E830_PRTMAC_FRM_LENGTH_FRM_LENGTH_M MAKEMASK(0xFFFF, 0) 10620 #define E830_PRTMAC_FRM_LENGTH_TX_MTU_S 16 10621 #define E830_PRTMAC_FRM_LENGTH_TX_MTU_M MAKEMASK(0xFFFF, 16) 10622 #define E830_PRTMAC_MAC_ADDR_0 0x001E3060 /* Reset Source: GLOBR */ 10623 #define E830_PRTMAC_MAC_ADDR_0_MAC_ADDR_0_S 0 10624 #define E830_PRTMAC_MAC_ADDR_0_MAC_ADDR_0_M MAKEMASK(0xFFFFFFFF, 0) 10625 #define E830_PRTMAC_MAC_ADDR_1 0x001E3080 /* Reset Source: GLOBR */ 10626 #define E830_PRTMAC_MAC_ADDR_1_MAC_ADDR_1_S 0 10627 #define E830_PRTMAC_MAC_ADDR_1_MAC_ADDR_1_M MAKEMASK(0xFFFF, 0) 10628 #define E830_PRTMAC_MDIO_CFG_STATUS 0x001E3180 /* Reset Source: GLOBR */ 10629 #define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_BUSY_S 0 10630 #define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_BUSY_M BIT(0) 10631 #define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_RD_ERR_S 1 10632 #define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_RD_ERR_M BIT(1) 10633 #define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_HOLD_TIME_S 2 10634 #define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_HOLD_TIME_M MAKEMASK(0x7, 2) 10635 #define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_DIS_PREAMBLE_S 5 10636 #define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_DIS_PREAMBLE_M BIT(5) 10637 #define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_CLS_45_EN_S 6 10638 #define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_CLS_45_EN_M BIT(6) 10639 #define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_CLK_DIVISOR_S 7 10640 #define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_CLK_DIVISOR_M MAKEMASK(0x1FF, 7) 10641 #define E830_PRTMAC_MDIO_COMMAND 0x001E31A0 /* Reset Source: GLOBR */ 10642 #define E830_PRTMAC_MDIO_COMMAND_MDIO_COMMAND_S 0 10643 #define E830_PRTMAC_MDIO_COMMAND_MDIO_COMMAND_M MAKEMASK(0xFFFF, 0) 10644 #define E830_PRTMAC_MDIO_COMMAND_RESERVED_2_S 16 10645 #define E830_PRTMAC_MDIO_COMMAND_RESERVED_2_M MAKEMASK(0x7FFF, 16) 10646 #define E830_PRTMAC_MDIO_COMMAND_MDIO_BUSY_S 31 10647 #define E830_PRTMAC_MDIO_COMMAND_MDIO_BUSY_M BIT(31) 10648 #define E830_PRTMAC_MDIO_DATA 0x001E31C0 /* Reset Source: GLOBR */ 10649 #define E830_PRTMAC_MDIO_DATA_MDIO_DATA_S 0 10650 #define E830_PRTMAC_MDIO_DATA_MDIO_DATA_M MAKEMASK(0xFFFF, 0) 10651 #define E830_PRTMAC_MDIO_DATA_RESERVED_2_S 16 10652 #define E830_PRTMAC_MDIO_DATA_RESERVED_2_M MAKEMASK(0x7FFF, 16) 10653 #define E830_PRTMAC_MDIO_DATA_MDIO_BUSY_S 31 10654 #define E830_PRTMAC_MDIO_DATA_MDIO_BUSY_M BIT(31) 10655 #define E830_PRTMAC_MDIO_REGADDR 0x001E31E0 /* Reset Source: GLOBR */ 10656 #define E830_PRTMAC_MDIO_REGADDR_MDIO_REGADDR_S 0 10657 #define E830_PRTMAC_MDIO_REGADDR_MDIO_REGADDR_M MAKEMASK(0xFFFFFFFF, 0) 10658 #define E830_PRTMAC_REVISION 0x001E3000 /* Reset Source: GLOBR */ 10659 #define E830_PRTMAC_REVISION_CORE_REVISION_S 0 10660 #define E830_PRTMAC_REVISION_CORE_REVISION_M MAKEMASK(0xFF, 0) 10661 #define E830_PRTMAC_REVISION_CORE_VERSION_S 8 10662 #define E830_PRTMAC_REVISION_CORE_VERSION_M MAKEMASK(0xFF, 8) 10663 #define E830_PRTMAC_REVISION_CUSTOMER_VERSION_S 16 10664 #define E830_PRTMAC_REVISION_CUSTOMER_VERSION_M MAKEMASK(0xFFFF, 16) 10665 #define E830_PRTMAC_RX_OFLOW_PKT_DRP_BSOP_CNT 0x001E24C0 /* Reset Source: GLOBR */ 10666 #define E830_PRTMAC_RX_OFLOW_PKT_DRP_BSOP_CNT_RX_OFLOW_PKT_DRP_BSOP_CNT_S 0 10667 #define E830_PRTMAC_RX_OFLOW_PKT_DRP_BSOP_CNT_RX_OFLOW_PKT_DRP_BSOP_CNT_M MAKEMASK(0xFFFF, 0) 10668 #define E830_PRTMAC_RX_PAUSE_STATUS 0x001E33A0 /* Reset Source: GLOBR */ 10669 #define E830_PRTMAC_RX_PAUSE_STATUS_RX_PAUSE_STATUS_S 0 10670 #define E830_PRTMAC_RX_PAUSE_STATUS_RX_PAUSE_STATUS_M MAKEMASK(0xFF, 0) 10671 #define E830_PRTMAC_RX_PKT_DRP_CNT_RX_OFLOW_PKT_DRP_CNT_S 12 10672 #define E830_PRTMAC_RX_PKT_DRP_CNT_RX_OFLOW_PKT_DRP_CNT_M MAKEMASK(0xFFFF, 12) 10673 #define E830_PRTMAC_SCRATCH 0x001E3020 /* Reset Source: GLOBR */ 10674 #define E830_PRTMAC_SCRATCH_SCRATCH_S 0 10675 #define E830_PRTMAC_SCRATCH_SCRATCH_M MAKEMASK(0xFFFFFFFF, 0) 10676 #define E830_PRTMAC_STATUS 0x001E3200 /* Reset Source: GLOBR */ 10677 #define E830_PRTMAC_STATUS_RX_LOC_FAULT_S 0 10678 #define E830_PRTMAC_STATUS_RX_LOC_FAULT_M BIT(0) 10679 #define E830_PRTMAC_STATUS_RX_REM_FAULT_S 1 10680 #define E830_PRTMAC_STATUS_RX_REM_FAULT_M BIT(1) 10681 #define E830_PRTMAC_STATUS_PHY_LOS_S 2 10682 #define E830_PRTMAC_STATUS_PHY_LOS_M BIT(2) 10683 #define E830_PRTMAC_STATUS_TS_AVAIL_S 3 10684 #define E830_PRTMAC_STATUS_TS_AVAIL_M BIT(3) 10685 #define E830_PRTMAC_STATUS_RX_LOWP_S 4 10686 #define E830_PRTMAC_STATUS_RX_LOWP_M BIT(4) 10687 #define E830_PRTMAC_STATUS_TX_EMPTY_S 5 10688 #define E830_PRTMAC_STATUS_TX_EMPTY_M BIT(5) 10689 #define E830_PRTMAC_STATUS_RX_EMPTY_S 6 10690 #define E830_PRTMAC_STATUS_RX_EMPTY_M BIT(6) 10691 #define E830_PRTMAC_STATUS_RX_LINT_FAULT_S 7 10692 #define E830_PRTMAC_STATUS_RX_LINT_FAULT_M BIT(7) 10693 #define E830_PRTMAC_STATUS_TX_ISIDLE_S 8 10694 #define E830_PRTMAC_STATUS_TX_ISIDLE_M BIT(8) 10695 #define E830_PRTMAC_STATUS_RESERVED_10_S 9 10696 #define E830_PRTMAC_STATUS_RESERVED_10_M MAKEMASK(0x7FFFFF, 9) 10697 #define E830_PRTMAC_STATUS_SPARE 0x001E2740 /* Reset Source: GLOBR */ 10698 #define E830_PRTMAC_STATUS_SPARE_DFD_STATUS_SPARE_S 0 10699 #define E830_PRTMAC_STATUS_SPARE_DFD_STATUS_SPARE_M MAKEMASK(0xFFFFFFFF, 0) 10700 #define E830_PRTMAC_TS_RX_PCS_LATENCY 0x001E2220 /* Reset Source: GLOBR */ 10701 #define E830_PRTMAC_TS_RX_PCS_LATENCY_TS_RX_PCS_LATENCY_S 0 10702 #define E830_PRTMAC_TS_RX_PCS_LATENCY_TS_RX_PCS_LATENCY_M MAKEMASK(0xFFFF, 0) 10703 #define E830_PRTMAC_TS_TIMESTAMP 0x001E33E0 /* Reset Source: GLOBR */ 10704 #define E830_PRTMAC_TS_TIMESTAMP_TS_TIMESTAMP_S 0 10705 #define E830_PRTMAC_TS_TIMESTAMP_TS_TIMESTAMP_M MAKEMASK(0xFFFFFFFF, 0) 10706 #define E830_PRTMAC_TS_TX_MEM_VALID_H 0x001E2020 /* Reset Source: GLOBR */ 10707 #define E830_PRTMAC_TS_TX_MEM_VALID_H_TIMESTAMP_TX_VALID_ARR_H_S 0 10708 #define E830_PRTMAC_TS_TX_MEM_VALID_H_TIMESTAMP_TX_VALID_ARR_H_M MAKEMASK(0xFFFFFFFF, 0) 10709 #define E830_PRTMAC_TS_TX_MEM_VALID_L 0x001E2000 /* Reset Source: GLOBR */ 10710 #define E830_PRTMAC_TS_TX_MEM_VALID_L_TIMESTAMP_TX_VALID_ARR_L_S 0 10711 #define E830_PRTMAC_TS_TX_MEM_VALID_L_TIMESTAMP_TX_VALID_ARR_L_M MAKEMASK(0xFFFFFFFF, 0) 10712 #define E830_PRTMAC_TS_TX_PCS_LATENCY 0x001E2200 /* Reset Source: GLOBR */ 10713 #define E830_PRTMAC_TS_TX_PCS_LATENCY_TS_TX_PCS_LATENCY_S 0 10714 #define E830_PRTMAC_TS_TX_PCS_LATENCY_TS_TX_PCS_LATENCY_M MAKEMASK(0xFFFF, 0) 10715 #define E830_PRTMAC_TX_FIFO_SECTIONS 0x001E3100 /* Reset Source: GLOBR */ 10716 #define E830_PRTMAC_TX_FIFO_SECTIONS_TX_SECTION_AVAIL_THRESHOLD_S 0 10717 #define E830_PRTMAC_TX_FIFO_SECTIONS_TX_SECTION_AVAIL_THRESHOLD_M MAKEMASK(0xFFFF, 0) 10718 #define E830_PRTMAC_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_THRESHOLD_S 16 10719 #define E830_PRTMAC_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_THRESHOLD_M MAKEMASK(0xFFFF, 16) 10720 #define E830_PRTMAC_TX_IPG_LENGTH 0x001E3220 /* Reset Source: GLOBR */ 10721 #define E830_PRTMAC_TX_IPG_LENGTH_AVG_IPG_LEN_S 0 10722 #define E830_PRTMAC_TX_IPG_LENGTH_AVG_IPG_LEN_M MAKEMASK(0x3F, 0) 10723 #define E830_PRTMAC_TX_IPG_LENGTH_IPG_COMP_23_16_S 8 10724 #define E830_PRTMAC_TX_IPG_LENGTH_IPG_COMP_23_16_M MAKEMASK(0xFF, 8) 10725 #define E830_PRTMAC_TX_IPG_LENGTH_IPG_COMP_15_0_S 16 10726 #define E830_PRTMAC_TX_IPG_LENGTH_IPG_COMP_15_0_M MAKEMASK(0xFFFF, 16) 10727 #define E830_PRTMAC_USER_TX_PAUSE_CNT 0x001E2760 /* Reset Source: GLOBR */ 10728 #define E830_PRTMAC_USER_TX_PAUSE_CNT_USER_TX_PAUSE_CNT_S 0 10729 #define E830_PRTMAC_USER_TX_PAUSE_CNT_USER_TX_PAUSE_CNT_M MAKEMASK(0xFFFF, 0) 10730 #define E830_PRTMAC_XIF_MODE 0x001E3400 /* Reset Source: GLOBR */ 10731 #define E830_PRTMAC_XIF_MODE_XGMII_ENA_S 0 10732 #define E830_PRTMAC_XIF_MODE_XGMII_ENA_M BIT(0) 10733 #define E830_PRTMAC_XIF_MODE_RESERVED_2_S 1 10734 #define E830_PRTMAC_XIF_MODE_RESERVED_2_M MAKEMASK(0x7, 1) 10735 #define E830_PRTMAC_XIF_MODE_PAUSETIMERX8_S 4 10736 #define E830_PRTMAC_XIF_MODE_PAUSETIMERX8_M BIT(4) 10737 #define E830_PRTMAC_XIF_MODE_ONE_STEP_ENA_S 5 10738 #define E830_PRTMAC_XIF_MODE_ONE_STEP_ENA_M BIT(5) 10739 #define E830_PRTMAC_XIF_MODE_RX_PAUSE_BYPASS_S 6 10740 #define E830_PRTMAC_XIF_MODE_RX_PAUSE_BYPASS_M BIT(6) 10741 #define E830_PRTMAC_XIF_MODE_RESERVED1_S 7 10742 #define E830_PRTMAC_XIF_MODE_RESERVED1_M BIT(7) 10743 #define E830_PRTMAC_XIF_MODE_TX_MAC_RS_ERR_S 8 10744 #define E830_PRTMAC_XIF_MODE_TX_MAC_RS_ERR_M BIT(8) 10745 #define E830_PRTMAC_XIF_MODE_TS_DELTA_MODE_S 9 10746 #define E830_PRTMAC_XIF_MODE_TS_DELTA_MODE_M BIT(9) 10747 #define E830_PRTMAC_XIF_MODE_TS_DELAY_MODE_S 10 10748 #define E830_PRTMAC_XIF_MODE_TS_DELAY_MODE_M BIT(10) 10749 #define E830_PRTMAC_XIF_MODE_TS_BINARY_MODE_S 11 10750 #define E830_PRTMAC_XIF_MODE_TS_BINARY_MODE_M BIT(11) 10751 #define E830_PRTMAC_XIF_MODE_TS_UPD64_MODE_S 12 10752 #define E830_PRTMAC_XIF_MODE_TS_UPD64_MODE_M BIT(12) 10753 #define E830_PRTMAC_XIF_MODE_RESERVED2_S 13 10754 #define E830_PRTMAC_XIF_MODE_RESERVED2_M MAKEMASK(0x7, 13) 10755 #define E830_PRTMAC_XIF_MODE_RX_CNT_MODE_S 16 10756 #define E830_PRTMAC_XIF_MODE_RX_CNT_MODE_M BIT(16) 10757 #define E830_PRTMAC_XIF_MODE_PFC_PULSE_MODE_S 17 10758 #define E830_PRTMAC_XIF_MODE_PFC_PULSE_MODE_M BIT(17) 10759 #define E830_PRTMAC_XIF_MODE_PFC_LP_MODE_S 18 10760 #define E830_PRTMAC_XIF_MODE_PFC_LP_MODE_M BIT(18) 10761 #define E830_PRTMAC_XIF_MODE_PFC_LP_16PRI_S 19 10762 #define E830_PRTMAC_XIF_MODE_PFC_LP_16PRI_M BIT(19) 10763 #define E830_PRTMAC_XIF_MODE_TS_SFD_ENA_S 20 10764 #define E830_PRTMAC_XIF_MODE_TS_SFD_ENA_M BIT(20) 10765 #define E830_PRTMAC_XIF_MODE_RESERVED3_S 21 10766 #define E830_PRTMAC_XIF_MODE_RESERVED3_M MAKEMASK(0x7FF, 21) 10767 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF 0x001E2700 /* Reset Source: GLOBR */ 10768 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF0_S 0 10769 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF0_M MAKEMASK(0xF, 0) 10770 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF1_S 4 10771 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF1_M MAKEMASK(0xF, 4) 10772 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF2_S 8 10773 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF2_M MAKEMASK(0xF, 8) 10774 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF3_S 12 10775 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF3_M MAKEMASK(0xF, 12) 10776 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF4_S 16 10777 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF4_M MAKEMASK(0xF, 16) 10778 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF5_S 20 10779 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF5_M MAKEMASK(0xF, 20) 10780 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF6_S 24 10781 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF6_M MAKEMASK(0xF, 24) 10782 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF7_S 28 10783 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF7_M MAKEMASK(0xF, 28) 10784 #define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_SW_ABOVE_HW_TAIL_S 28 10785 #define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_SW_ABOVE_HW_TAIL_M BIT(28) 10786 #define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_SAME_TAIL_S 29 10787 #define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_SAME_TAIL_M BIT(29) 10788 #define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_TAIL_GE_QLEN_S 30 10789 #define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_TAIL_GE_QLEN_M BIT(30) 10790 #define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_UR_S 31 10791 #define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_UR_M BIT(31) 10792 #define E830_GL_MDET_HIF_UR_FIFO 0x00096844 /* Reset Source: CORER */ 10793 #define E830_GL_MDET_HIF_UR_FIFO_FUNC_NUM_S 0 10794 #define E830_GL_MDET_HIF_UR_FIFO_FUNC_NUM_M MAKEMASK(0x3FF, 0) 10795 #define E830_GL_MDET_HIF_UR_FIFO_PF_NUM_S 10 10796 #define E830_GL_MDET_HIF_UR_FIFO_PF_NUM_M MAKEMASK(0x7, 10) 10797 #define E830_GL_MDET_HIF_UR_FIFO_FUNC_TYPE_S 13 10798 #define E830_GL_MDET_HIF_UR_FIFO_FUNC_TYPE_M MAKEMASK(0x3, 13) 10799 #define E830_GL_MDET_HIF_UR_FIFO_MAL_TYPE_S 15 10800 #define E830_GL_MDET_HIF_UR_FIFO_MAL_TYPE_M MAKEMASK(0x1F, 15) 10801 #define E830_GL_MDET_HIF_UR_FIFO_FIFO_FULL_S 20 10802 #define E830_GL_MDET_HIF_UR_FIFO_FIFO_FULL_M BIT(20) 10803 #define E830_GL_MDET_HIF_UR_FIFO_VALID_S 21 10804 #define E830_GL_MDET_HIF_UR_FIFO_VALID_M BIT(21) 10805 #define E830_GL_MDET_HIF_UR_FIFO_EVENT_CNT_S 24 10806 #define E830_GL_MDET_HIF_UR_FIFO_EVENT_CNT_M MAKEMASK(0xFF, 24) 10807 #define E830_GL_MDET_HIF_UR_PF_CNT(_i) (0x00096804 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 10808 #define E830_GL_MDET_HIF_UR_PF_CNT_MAX_INDEX 7 10809 #define E830_GL_MDET_HIF_UR_PF_CNT_CNT_S 0 10810 #define E830_GL_MDET_HIF_UR_PF_CNT_CNT_M MAKEMASK(0xFFFFFFFF, 0) 10811 #define E830_GL_MDET_HIF_UR_VF(_i) (0x00096824 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 10812 #define E830_GL_MDET_HIF_UR_VF_MAX_INDEX 7 10813 #define E830_GL_MDET_HIF_UR_VF_VF_MAL_EVENT_S 0 10814 #define E830_GL_MDET_HIF_UR_VF_VF_MAL_EVENT_M MAKEMASK(0xFFFFFFFF, 0) 10815 #define E830_PF_MDET_HIF_UR 0x00096880 /* Reset Source: CORER */ 10816 #define E830_PF_MDET_HIF_UR_VALID_S 0 10817 #define E830_PF_MDET_HIF_UR_VALID_M BIT(0) 10818 #define E830_VM_MDET_TX_TCLAN(_i) (0x000FC348 + ((_i) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 10819 #define E830_VM_MDET_TX_TCLAN_MAX_INDEX 767 10820 #define E830_VM_MDET_TX_TCLAN_VALID_S 0 10821 #define E830_VM_MDET_TX_TCLAN_VALID_M BIT(0) 10822 #define E830_VP_MDET_HIF_UR(_VF) (0x00096C00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ 10823 #define E830_VP_MDET_HIF_UR_MAX_INDEX 255 10824 #define E830_VP_MDET_HIF_UR_VALID_S 0 10825 #define E830_VP_MDET_HIF_UR_VALID_M BIT(0) 10826 #define E830_GLNVM_FLA_GLOBAL_LOCKED_S 7 10827 #define E830_GLNVM_FLA_GLOBAL_LOCKED_M BIT(7) 10828 #define E830_DMA_AGENT_AT0 0x000BE268 /* Reset Source: PCIR */ 10829 #define E830_DMA_AGENT_AT0_RLAN_PASID_SELECTED_S 0 10830 #define E830_DMA_AGENT_AT0_RLAN_PASID_SELECTED_M MAKEMASK(0x3, 0) 10831 #define E830_DMA_AGENT_AT0_TCLAN_PASID_SELECTED_S 2 10832 #define E830_DMA_AGENT_AT0_TCLAN_PASID_SELECTED_M MAKEMASK(0x3, 2) 10833 #define E830_DMA_AGENT_AT0_PQM_DBL_PASID_SELECTED_S 4 10834 #define E830_DMA_AGENT_AT0_PQM_DBL_PASID_SELECTED_M MAKEMASK(0x3, 4) 10835 #define E830_DMA_AGENT_AT0_PQM_DESC_PASID_SELECTED_S 6 10836 #define E830_DMA_AGENT_AT0_PQM_DESC_PASID_SELECTED_M MAKEMASK(0x3, 6) 10837 #define E830_DMA_AGENT_AT0_PQM_TS_DESC_PASID_SELECTED_S 8 10838 #define E830_DMA_AGENT_AT0_PQM_TS_DESC_PASID_SELECTED_M MAKEMASK(0x3, 8) 10839 #define E830_DMA_AGENT_AT0_RDPU_PASID_SELECTED_S 10 10840 #define E830_DMA_AGENT_AT0_RDPU_PASID_SELECTED_M MAKEMASK(0x3, 10) 10841 #define E830_DMA_AGENT_AT0_TDPU_PASID_SELECTED_S 12 10842 #define E830_DMA_AGENT_AT0_TDPU_PASID_SELECTED_M MAKEMASK(0x3, 12) 10843 #define E830_DMA_AGENT_AT0_MBX_PASID_SELECTED_S 14 10844 #define E830_DMA_AGENT_AT0_MBX_PASID_SELECTED_M MAKEMASK(0x3, 14) 10845 #define E830_DMA_AGENT_AT0_MNG_PASID_SELECTED_S 16 10846 #define E830_DMA_AGENT_AT0_MNG_PASID_SELECTED_M MAKEMASK(0x3, 16) 10847 #define E830_DMA_AGENT_AT0_TEP_PMAT_PASID_SELECTED_S 18 10848 #define E830_DMA_AGENT_AT0_TEP_PMAT_PASID_SELECTED_M MAKEMASK(0x3, 18) 10849 #define E830_DMA_AGENT_AT0_RX_PE_PASID_SELECTED_S 20 10850 #define E830_DMA_AGENT_AT0_RX_PE_PASID_SELECTED_M MAKEMASK(0x3, 20) 10851 #define E830_DMA_AGENT_AT0_TX_PE_PASID_SELECTED_S 22 10852 #define E830_DMA_AGENT_AT0_TX_PE_PASID_SELECTED_M MAKEMASK(0x3, 22) 10853 #define E830_DMA_AGENT_AT0_PEPMAT_PASID_SELECTED_S 24 10854 #define E830_DMA_AGENT_AT0_PEPMAT_PASID_SELECTED_M MAKEMASK(0x3, 24) 10855 #define E830_DMA_AGENT_AT0_FPMAT_PASID_SELECTED_S 26 10856 #define E830_DMA_AGENT_AT0_FPMAT_PASID_SELECTED_M MAKEMASK(0x3, 26) 10857 #define E830_DMA_AGENT_AT1 0x000BE26C /* Reset Source: PCIR */ 10858 #define E830_DMA_AGENT_AT1_RLAN_PASID_SELECTED_S 0 10859 #define E830_DMA_AGENT_AT1_RLAN_PASID_SELECTED_M MAKEMASK(0x3, 0) 10860 #define E830_DMA_AGENT_AT1_TCLAN_PASID_SELECTED_S 2 10861 #define E830_DMA_AGENT_AT1_TCLAN_PASID_SELECTED_M MAKEMASK(0x3, 2) 10862 #define E830_DMA_AGENT_AT1_PQM_DBL_PASID_SELECTED_S 4 10863 #define E830_DMA_AGENT_AT1_PQM_DBL_PASID_SELECTED_M MAKEMASK(0x3, 4) 10864 #define E830_DMA_AGENT_AT1_PQM_DESC_PASID_SELECTED_S 6 10865 #define E830_DMA_AGENT_AT1_PQM_DESC_PASID_SELECTED_M MAKEMASK(0x3, 6) 10866 #define E830_DMA_AGENT_AT1_PQM_TS_DESC_PASID_SELECTED_S 8 10867 #define E830_DMA_AGENT_AT1_PQM_TS_DESC_PASID_SELECTED_M MAKEMASK(0x3, 8) 10868 #define E830_DMA_AGENT_AT1_RDPU_PASID_SELECTED_S 10 10869 #define E830_DMA_AGENT_AT1_RDPU_PASID_SELECTED_M MAKEMASK(0x3, 10) 10870 #define E830_DMA_AGENT_AT1_TDPU_PASID_SELECTED_S 12 10871 #define E830_DMA_AGENT_AT1_TDPU_PASID_SELECTED_M MAKEMASK(0x3, 12) 10872 #define E830_DMA_AGENT_AT1_MBX_PASID_SELECTED_S 14 10873 #define E830_DMA_AGENT_AT1_MBX_PASID_SELECTED_M MAKEMASK(0x3, 14) 10874 #define E830_DMA_AGENT_AT1_MNG_PASID_SELECTED_S 16 10875 #define E830_DMA_AGENT_AT1_MNG_PASID_SELECTED_M MAKEMASK(0x3, 16) 10876 #define E830_DMA_AGENT_AT1_TEP_PMAT_PASID_SELECTED_S 18 10877 #define E830_DMA_AGENT_AT1_TEP_PMAT_PASID_SELECTED_M MAKEMASK(0x3, 18) 10878 #define E830_DMA_AGENT_AT1_RX_PE_PASID_SELECTED_S 20 10879 #define E830_DMA_AGENT_AT1_RX_PE_PASID_SELECTED_M MAKEMASK(0x3, 20) 10880 #define E830_DMA_AGENT_AT1_TX_PE_PASID_SELECTED_S 22 10881 #define E830_DMA_AGENT_AT1_TX_PE_PASID_SELECTED_M MAKEMASK(0x3, 22) 10882 #define E830_DMA_AGENT_AT1_PEPMAT_PASID_SELECTED_S 24 10883 #define E830_DMA_AGENT_AT1_PEPMAT_PASID_SELECTED_M MAKEMASK(0x3, 24) 10884 #define E830_DMA_AGENT_AT1_FPMAT_PASID_SELECTED_S 26 10885 #define E830_DMA_AGENT_AT1_FPMAT_PASID_SELECTED_M MAKEMASK(0x3, 26) 10886 #define E830_GLPCI_CAPSUP_DOE_EN_S 1 10887 #define E830_GLPCI_CAPSUP_DOE_EN_M BIT(1) 10888 #define E830_GLPCI_CAPSUP_GEN5_EXT_EN_S 12 10889 #define E830_GLPCI_CAPSUP_GEN5_EXT_EN_M BIT(12) 10890 #define E830_GLPCI_CAPSUP_PTM_EN_S 13 10891 #define E830_GLPCI_CAPSUP_PTM_EN_M BIT(13) 10892 #define E830_GLPCI_CAPSUP_SNPS_RAS_EN_S 14 10893 #define E830_GLPCI_CAPSUP_SNPS_RAS_EN_M BIT(14) 10894 #define E830_GLPCI_CAPSUP_SIOV_EN_S 15 10895 #define E830_GLPCI_CAPSUP_SIOV_EN_M BIT(15) 10896 #define E830_GLPCI_CAPSUP_PTM_VSEC_EN_S 22 10897 #define E830_GLPCI_CAPSUP_PTM_VSEC_EN_M BIT(22) 10898 #define E830_GLPCI_CAPSUP_SNPS_RAS_PROT_EN_S 23 10899 #define E830_GLPCI_CAPSUP_SNPS_RAS_PROT_EN_M BIT(23) 10900 #define E830_GLPCI_DOE_BUSY_STATUS 0x0009DF70 /* Reset Source: PCIR */ 10901 #define E830_GLPCI_DOE_BUSY_STATUS_BUSY_REQ_S 0 10902 #define E830_GLPCI_DOE_BUSY_STATUS_BUSY_REQ_M BIT(0) 10903 #define E830_GLPCI_DOE_BUSY_STATUS_BUSY_EMPR_S 1 10904 #define E830_GLPCI_DOE_BUSY_STATUS_BUSY_EMPR_M BIT(1) 10905 #define E830_GLPCI_DOE_BUSY_STATUS_BUSY_PCIER_S 2 10906 #define E830_GLPCI_DOE_BUSY_STATUS_BUSY_PCIER_M BIT(2) 10907 #define E830_GLPCI_DOE_BUSY_STATUS_BUSY_FLR_S 3 10908 #define E830_GLPCI_DOE_BUSY_STATUS_BUSY_FLR_M BIT(3) 10909 #define E830_GLPCI_DOE_BUSY_STATUS_BUSY_CFG_ABORT_S 4 10910 #define E830_GLPCI_DOE_BUSY_STATUS_BUSY_CFG_ABORT_M BIT(4) 10911 #define E830_GLPCI_DOE_BUSY_STATUS_BUSY_FW_S 5 10912 #define E830_GLPCI_DOE_BUSY_STATUS_BUSY_FW_M BIT(5) 10913 #define E830_GLPCI_DOE_CFG 0x0009DF54 /* Reset Source: PCIR */ 10914 #define E830_GLPCI_DOE_CFG_ENABLE_S 0 10915 #define E830_GLPCI_DOE_CFG_ENABLE_M BIT(0) 10916 #define E830_GLPCI_DOE_CFG_ITR_SUPPORT_S 1 10917 #define E830_GLPCI_DOE_CFG_ITR_SUPPORT_M BIT(1) 10918 #define E830_GLPCI_DOE_CFG_POISON_CFGWR_PIOSF_EP_BIT_S 2 10919 #define E830_GLPCI_DOE_CFG_POISON_CFGWR_PIOSF_EP_BIT_M BIT(2) 10920 #define E830_GLPCI_DOE_CFG_POISON_CFGWR_SBIOSF_AER_MSG_S 3 10921 #define E830_GLPCI_DOE_CFG_POISON_CFGWR_SBIOSF_AER_MSG_M BIT(3) 10922 #define E830_GLPCI_DOE_CFG_MSIX_VECTOR_S 8 10923 #define E830_GLPCI_DOE_CFG_MSIX_VECTOR_M MAKEMASK(0x7FF, 8) 10924 #define E830_GLPCI_DOE_CTRL 0x0009DF60 /* Reset Source: PCIR */ 10925 #define E830_GLPCI_DOE_CTRL_BUSY_FW_SET_S 0 10926 #define E830_GLPCI_DOE_CTRL_BUSY_FW_SET_M BIT(0) 10927 #define E830_GLPCI_DOE_CTRL_DOE_CFG_ERR_SET_S 1 10928 #define E830_GLPCI_DOE_CTRL_DOE_CFG_ERR_SET_M BIT(1) 10929 #define E830_GLPCI_DOE_DBG 0x0009DF6C /* Reset Source: PCIR */ 10930 #define E830_GLPCI_DOE_DBG_CFG_BUSY_S 0 10931 #define E830_GLPCI_DOE_DBG_CFG_BUSY_M BIT(0) 10932 #define E830_GLPCI_DOE_DBG_CFG_DATA_OBJECT_READY_S 1 10933 #define E830_GLPCI_DOE_DBG_CFG_DATA_OBJECT_READY_M BIT(1) 10934 #define E830_GLPCI_DOE_DBG_CFG_ERROR_S 2 10935 #define E830_GLPCI_DOE_DBG_CFG_ERROR_M BIT(2) 10936 #define E830_GLPCI_DOE_DBG_CFG_INTERRUPT_ENABLE_S 3 10937 #define E830_GLPCI_DOE_DBG_CFG_INTERRUPT_ENABLE_M BIT(3) 10938 #define E830_GLPCI_DOE_DBG_CFG_INTERRUPT_STATUS_S 4 10939 #define E830_GLPCI_DOE_DBG_CFG_INTERRUPT_STATUS_M BIT(4) 10940 #define E830_GLPCI_DOE_DBG_REQ_BUF_SW_WR_PTR_S 8 10941 #define E830_GLPCI_DOE_DBG_REQ_BUF_SW_WR_PTR_M MAKEMASK(0x1FF, 8) 10942 #define E830_GLPCI_DOE_DBG_RESP_BUF_SW_RD_PTR_S 20 10943 #define E830_GLPCI_DOE_DBG_RESP_BUF_SW_RD_PTR_M MAKEMASK(0x1FF, 20) 10944 #define E830_GLPCI_DOE_ERR_EN 0x0009DF64 /* Reset Source: PCIR */ 10945 #define E830_GLPCI_DOE_ERR_EN_RD_REQ_BUF_ECC_ERR_EN_S 0 10946 #define E830_GLPCI_DOE_ERR_EN_RD_REQ_BUF_ECC_ERR_EN_M BIT(0) 10947 #define E830_GLPCI_DOE_ERR_EN_RD_RESP_BUF_ECC_ERR_EN_S 1 10948 #define E830_GLPCI_DOE_ERR_EN_RD_RESP_BUF_ECC_ERR_EN_M BIT(1) 10949 #define E830_GLPCI_DOE_ERR_EN_SW_WR_CFG_POISONED_EN_S 2 10950 #define E830_GLPCI_DOE_ERR_EN_SW_WR_CFG_POISONED_EN_M BIT(2) 10951 #define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_REQ_EN_S 3 10952 #define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_REQ_EN_M BIT(3) 10953 #define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_REQ_EN_S 4 10954 #define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_REQ_EN_M BIT(4) 10955 #define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_FW_EN_S 5 10956 #define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_FW_EN_M BIT(5) 10957 #define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_FW_EN_S 6 10958 #define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_FW_EN_M BIT(6) 10959 #define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_OVERFLOW_EN_S 7 10960 #define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_OVERFLOW_EN_M BIT(7) 10961 #define E830_GLPCI_DOE_ERR_EN_SW_GO_REQ_BUF_EMPTY_EN_S 8 10962 #define E830_GLPCI_DOE_ERR_EN_SW_GO_REQ_BUF_EMPTY_EN_M BIT(8) 10963 #define E830_GLPCI_DOE_ERR_EN_SW_RD_RESP_BUF_ON_READY_LOW_EN_S 9 10964 #define E830_GLPCI_DOE_ERR_EN_SW_RD_RESP_BUF_ON_READY_LOW_EN_M BIT(9) 10965 #define E830_GLPCI_DOE_ERR_EN_SW_REQ_DURING_MNG_RST_EN_S 10 10966 #define E830_GLPCI_DOE_ERR_EN_SW_REQ_DURING_MNG_RST_EN_M BIT(10) 10967 #define E830_GLPCI_DOE_ERR_EN_FW_SET_ERROR_EN_S 11 10968 #define E830_GLPCI_DOE_ERR_EN_FW_SET_ERROR_EN_M BIT(11) 10969 #define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_ABORT_EN_S 12 10970 #define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_ABORT_EN_M BIT(12) 10971 #define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_ABORT_EN_S 13 10972 #define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_ABORT_EN_M BIT(13) 10973 #define E830_GLPCI_DOE_ERR_EN_SW_RD_RESP_BUF_ON_BUSY_DUE_ABORT_EN_S 14 10974 #define E830_GLPCI_DOE_ERR_EN_SW_RD_RESP_BUF_ON_BUSY_DUE_ABORT_EN_M BIT(14) 10975 #define E830_GLPCI_DOE_ERR_STATUS 0x0009DF68 /* Reset Source: PCIR */ 10976 #define E830_GLPCI_DOE_ERR_STATUS_RD_REQ_BUF_ECC_ERR_S 0 10977 #define E830_GLPCI_DOE_ERR_STATUS_RD_REQ_BUF_ECC_ERR_M BIT(0) 10978 #define E830_GLPCI_DOE_ERR_STATUS_RD_RESP_BUF_ECC_ERR_S 1 10979 #define E830_GLPCI_DOE_ERR_STATUS_RD_RESP_BUF_ECC_ERR_M BIT(1) 10980 #define E830_GLPCI_DOE_ERR_STATUS_SW_WR_CFG_POISONED_S 2 10981 #define E830_GLPCI_DOE_ERR_STATUS_SW_WR_CFG_POISONED_M BIT(2) 10982 #define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_REQ_S 3 10983 #define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_REQ_M BIT(3) 10984 #define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_REQ_S 4 10985 #define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_REQ_M BIT(4) 10986 #define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_FW_S 5 10987 #define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_FW_M BIT(5) 10988 #define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_FW_S 6 10989 #define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_FW_M BIT(6) 10990 #define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_OVERFLOW_S 7 10991 #define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_OVERFLOW_M BIT(7) 10992 #define E830_GLPCI_DOE_ERR_STATUS_SW_GO_REQ_BUF_EMPTY_S 8 10993 #define E830_GLPCI_DOE_ERR_STATUS_SW_GO_REQ_BUF_EMPTY_M BIT(8) 10994 #define E830_GLPCI_DOE_ERR_STATUS_SW_RD_RESP_BUF_ON_READY_LOW_S 9 10995 #define E830_GLPCI_DOE_ERR_STATUS_SW_RD_RESP_BUF_ON_READY_LOW_M BIT(9) 10996 #define E830_GLPCI_DOE_ERR_STATUS_SW_REQ_DURING_MNG_RST_S 10 10997 #define E830_GLPCI_DOE_ERR_STATUS_SW_REQ_DURING_MNG_RST_M BIT(10) 10998 #define E830_GLPCI_DOE_ERR_STATUS_FW_SET_ERROR_S 11 10999 #define E830_GLPCI_DOE_ERR_STATUS_FW_SET_ERROR_M BIT(11) 11000 #define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_ABORT_S 12 11001 #define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_ABORT_M BIT(12) 11002 #define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_ABORT_S 13 11003 #define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_ABORT_M BIT(13) 11004 #define E830_GLPCI_DOE_ERR_STATUS_SW_RD_RESP_BUF_ON_BUSY_DUE_ABORT_S 14 11005 #define E830_GLPCI_DOE_ERR_STATUS_SW_RD_RESP_BUF_ON_BUSY_DUE_ABORT_M BIT(14) 11006 #define E830_GLPCI_DOE_ERR_STATUS_CFG_ERR_IDX_S 24 11007 #define E830_GLPCI_DOE_ERR_STATUS_CFG_ERR_IDX_M MAKEMASK(0x1F, 24) 11008 #define E830_GLPCI_DOE_REQ_MSG_NUM_DWS 0x0009DF58 /* Reset Source: PCIR */ 11009 #define E830_GLPCI_DOE_REQ_MSG_NUM_DWS_GLPCI_DOE_REQ_MSG_NUM_DWS_S 0 11010 #define E830_GLPCI_DOE_REQ_MSG_NUM_DWS_GLPCI_DOE_REQ_MSG_NUM_DWS_M MAKEMASK(0x1FF, 0) 11011 #define E830_GLPCI_DOE_RESP 0x0009DF5C /* Reset Source: PCIR */ 11012 #define E830_GLPCI_DOE_RESP_MSG_NUM_DWS_S 0 11013 #define E830_GLPCI_DOE_RESP_MSG_NUM_DWS_M MAKEMASK(0x1FF, 0) 11014 #define E830_GLPCI_DOE_RESP_READY_SET_S 16 11015 #define E830_GLPCI_DOE_RESP_READY_SET_M BIT(16) 11016 #define E830_GLPCI_ERR_DBG 0x0009DF84 /* Reset Source: PCIR */ 11017 #define E830_GLPCI_ERR_DBG_ERR_MIFO_FULL_DROP_CTR_S 0 11018 #define E830_GLPCI_ERR_DBG_ERR_MIFO_FULL_DROP_CTR_M MAKEMASK(0x3, 0) 11019 #define E830_GLPCI_ERR_DBG_PCIE2SB_AER_MSG_SM_S 2 11020 #define E830_GLPCI_ERR_DBG_PCIE2SB_AER_MSG_SM_M BIT(2) 11021 #define E830_GLPCI_ERR_DBG_PCIE2SB_AER_MSG_FIFO_NUM_ENTRIES_S 3 11022 #define E830_GLPCI_ERR_DBG_PCIE2SB_AER_MSG_FIFO_NUM_ENTRIES_M MAKEMASK(0x7, 3) 11023 #define E830_GLPCI_ERR_DBG_ERR_MIFO_NUM_ENTRIES_S 6 11024 #define E830_GLPCI_ERR_DBG_ERR_MIFO_NUM_ENTRIES_M MAKEMASK(0xF, 6) 11025 #define E830_GLPCI_NPQ_CFG_HIGH_TO_S 20 11026 #define E830_GLPCI_NPQ_CFG_HIGH_TO_M BIT(20) 11027 #define E830_GLPCI_NPQ_CFG_INC_150MS_TO_S 21 11028 #define E830_GLPCI_NPQ_CFG_INC_150MS_TO_M BIT(21) 11029 #define E830_GLPCI_PUSH_PQM_CTRL 0x0009DF74 /* Reset Source: POR */ 11030 #define E830_GLPCI_PUSH_PQM_CTRL_PF_LEGACY_RANGE_EN_S 0 11031 #define E830_GLPCI_PUSH_PQM_CTRL_PF_LEGACY_RANGE_EN_M BIT(0) 11032 #define E830_GLPCI_PUSH_PQM_CTRL_PF_TXTIME_RANGE_EN_S 1 11033 #define E830_GLPCI_PUSH_PQM_CTRL_PF_TXTIME_RANGE_EN_M BIT(1) 11034 #define E830_GLPCI_PUSH_PQM_CTRL_PF_4K_RANGE_EN_S 2 11035 #define E830_GLPCI_PUSH_PQM_CTRL_PF_4K_RANGE_EN_M BIT(2) 11036 #define E830_GLPCI_PUSH_PQM_CTRL_VF_LEGACY_RANGE_EN_S 3 11037 #define E830_GLPCI_PUSH_PQM_CTRL_VF_LEGACY_RANGE_EN_M BIT(3) 11038 #define E830_GLPCI_PUSH_PQM_CTRL_VF_TXTIME_RANGE_EN_S 4 11039 #define E830_GLPCI_PUSH_PQM_CTRL_VF_TXTIME_RANGE_EN_M BIT(4) 11040 #define E830_GLPCI_PUSH_PQM_CTRL_PUSH_PQM_IF_TO_VAL_S 8 11041 #define E830_GLPCI_PUSH_PQM_CTRL_PUSH_PQM_IF_TO_VAL_M MAKEMASK(0xF, 8) 11042 #define E830_GLPCI_PUSH_PQM_CTRL_PUSH_PQM_IF_TO_DIS_S 12 11043 #define E830_GLPCI_PUSH_PQM_CTRL_PUSH_PQM_IF_TO_DIS_M BIT(12) 11044 #define E830_GLPCI_PUSH_PQM_CTRL_RD_COMP_LEN_2DWS_ONE_CHUNK_EN_S 16 11045 #define E830_GLPCI_PUSH_PQM_CTRL_RD_COMP_LEN_2DWS_ONE_CHUNK_EN_M BIT(16) 11046 #define E830_GLPCI_PUSH_PQM_CTRL_RD_COMP_LEN_1DW_ON_XLR_S 17 11047 #define E830_GLPCI_PUSH_PQM_CTRL_RD_COMP_LEN_1DW_ON_XLR_M BIT(17) 11048 #define E830_GLPCI_PUSH_PQM_DBG 0x0009DF7C /* Reset Source: PCIR */ 11049 #define E830_GLPCI_PUSH_PQM_DBG_EVENTS_CTR_S 0 11050 #define E830_GLPCI_PUSH_PQM_DBG_EVENTS_CTR_M MAKEMASK(0xFF, 0) 11051 #define E830_GLPCI_PUSH_PQM_DBG_DROP_CTR_S 8 11052 #define E830_GLPCI_PUSH_PQM_DBG_DROP_CTR_M MAKEMASK(0xFF, 8) 11053 #define E830_GLPCI_PUSH_PQM_DBG_ASYNC_FIFO_USED_SPACE_S 16 11054 #define E830_GLPCI_PUSH_PQM_DBG_ASYNC_FIFO_USED_SPACE_M MAKEMASK(0xF, 16) 11055 #define E830_GLPCI_PUSH_PQM_DBG_CDT_FIFO_USED_SPACE_S 20 11056 #define E830_GLPCI_PUSH_PQM_DBG_CDT_FIFO_USED_SPACE_M MAKEMASK(0x1F, 20) 11057 #define E830_GLPCI_PUSH_PQM_DBG_CDT_FIFO_PUSH_WHEN_FULL_ERR_S 25 11058 #define E830_GLPCI_PUSH_PQM_DBG_CDT_FIFO_PUSH_WHEN_FULL_ERR_M BIT(25) 11059 #define E830_GLPCI_PUSH_PQM_IF_TO_STATUS 0x0009DF78 /* Reset Source: PCIR */ 11060 #define E830_GLPCI_PUSH_PQM_IF_TO_STATUS_GLPCI_PUSH_PQM_IF_TO_STATUS_S 0 11061 #define E830_GLPCI_PUSH_PQM_IF_TO_STATUS_GLPCI_PUSH_PQM_IF_TO_STATUS_M BIT(0) 11062 #define E830_GLPCI_RDPU_CMD_DBG 0x000BE264 /* Reset Source: PCIR */ 11063 #define E830_GLPCI_RDPU_CMD_DBG_RDPU0_CMD_POP_CNT_S 0 11064 #define E830_GLPCI_RDPU_CMD_DBG_RDPU0_CMD_POP_CNT_M MAKEMASK(0xFF, 0) 11065 #define E830_GLPCI_RDPU_CMD_DBG_RDPU1_CMD_POP_CNT_S 8 11066 #define E830_GLPCI_RDPU_CMD_DBG_RDPU1_CMD_POP_CNT_M MAKEMASK(0xFF, 8) 11067 #define E830_GLPCI_RDPU_CMD_DBG_RDPU2_CMD_POP_CNT_S 16 11068 #define E830_GLPCI_RDPU_CMD_DBG_RDPU2_CMD_POP_CNT_M MAKEMASK(0xFF, 16) 11069 #define E830_GLPCI_RDPU_CMD_DBG_RDPU3_CMD_POP_CNT_S 24 11070 #define E830_GLPCI_RDPU_CMD_DBG_RDPU3_CMD_POP_CNT_M MAKEMASK(0xFF, 24) 11071 #define E830_GLPCI_RDPU_CMD_FIFO_DBG0 0x000BE25C /* Reset Source: PCIR */ 11072 #define E830_GLPCI_RDPU_CMD_FIFO_DBG0_RDPU0_CMD_NUM_ENTRIES_S 0 11073 #define E830_GLPCI_RDPU_CMD_FIFO_DBG0_RDPU0_CMD_NUM_ENTRIES_M MAKEMASK(0x1FF, 0) 11074 #define E830_GLPCI_RDPU_CMD_FIFO_DBG0_RDPU1_CMD_NUM_ENTRIES_S 16 11075 #define E830_GLPCI_RDPU_CMD_FIFO_DBG0_RDPU1_CMD_NUM_ENTRIES_M MAKEMASK(0x1FF, 16) 11076 #define E830_GLPCI_RDPU_CMD_FIFO_DBG1 0x000BE260 /* Reset Source: PCIR */ 11077 #define E830_GLPCI_RDPU_CMD_FIFO_DBG1_RDPU2_CMD_NUM_ENTRIES_S 0 11078 #define E830_GLPCI_RDPU_CMD_FIFO_DBG1_RDPU2_CMD_NUM_ENTRIES_M MAKEMASK(0x1FF, 0) 11079 #define E830_GLPCI_RDPU_CMD_FIFO_DBG1_RDPU3_CMD_NUM_ENTRIES_S 16 11080 #define E830_GLPCI_RDPU_CMD_FIFO_DBG1_RDPU3_CMD_NUM_ENTRIES_M MAKEMASK(0x1FF, 16) 11081 #define E830_GLPCI_RDPU_TAG 0x000BE258 /* Reset Source: PCIR */ 11082 #define E830_GLPCI_RDPU_TAG_OVERRIDE_DELAY_S 0 11083 #define E830_GLPCI_RDPU_TAG_OVERRIDE_DELAY_M MAKEMASK(0xFF, 0) 11084 #define E830_GLPCI_RDPU_TAG_EXPECTED_TAG_S 8 11085 #define E830_GLPCI_RDPU_TAG_EXPECTED_TAG_M MAKEMASK(0x3FF, 8) 11086 #define E830_GLPCI_SB_AER_MSG_OUT 0x0009DF80 /* Reset Source: PCIR */ 11087 #define E830_GLPCI_SB_AER_MSG_OUT_EN_S 0 11088 #define E830_GLPCI_SB_AER_MSG_OUT_EN_M BIT(0) 11089 #define E830_GLPCI_SB_AER_MSG_OUT_ANF_SET_EN_S 1 11090 #define E830_GLPCI_SB_AER_MSG_OUT_ANF_SET_EN_M BIT(1) 11091 #define E830_PF_FUNC_RID_HOST_S 16 11092 #define E830_PF_FUNC_RID_HOST_M MAKEMASK(0x3, 16) 11093 #define E830_GLPES_PFRXNPECNMARKEDPKTSHI(_i) (0x00553004 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 11094 #define E830_GLPES_PFRXNPECNMARKEDPKTSHI_MAX_INDEX 127 11095 #define E830_GLPES_PFRXNPECNMARKEDPKTSHI_RXNPECNMARKEDPKTSHI_S 0 11096 #define E830_GLPES_PFRXNPECNMARKEDPKTSHI_RXNPECNMARKEDPKTSHI_M MAKEMASK(0xFFFFFF, 0) 11097 #define E830_GLPES_PFRXNPECNMARKEDPKTSLO(_i) (0x00553000 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ 11098 #define E830_GLPES_PFRXNPECNMARKEDPKTSLO_MAX_INDEX 127 11099 #define E830_GLPES_PFRXNPECNMARKEDPKTSLO_RXNPECNMARKEDPKTSLO_S 0 11100 #define E830_GLPES_PFRXNPECNMARKEDPKTSLO_RXNPECNMARKEDPKTSLO_M MAKEMASK(0xFFFFFFFF, 0) 11101 #define E830_GLPES_PFRXRPCNPHANDLED(_i) (0x00552C00 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 11102 #define E830_GLPES_PFRXRPCNPHANDLED_MAX_INDEX 127 11103 #define E830_GLPES_PFRXRPCNPHANDLED_RXRPCNPHANDLED_S 0 11104 #define E830_GLPES_PFRXRPCNPHANDLED_RXRPCNPHANDLED_M MAKEMASK(0xFFFFFFFF, 0) 11105 #define E830_GLPES_PFRXRPCNPIGNORED(_i) (0x00552800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 11106 #define E830_GLPES_PFRXRPCNPIGNORED_MAX_INDEX 127 11107 #define E830_GLPES_PFRXRPCNPIGNORED_RXRPCNPIGNORED_S 0 11108 #define E830_GLPES_PFRXRPCNPIGNORED_RXRPCNPIGNORED_M MAKEMASK(0xFFFFFF, 0) 11109 #define E830_GLPES_PFTXNPCNPSENT(_i) (0x00553800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ 11110 #define E830_GLPES_PFTXNPCNPSENT_MAX_INDEX 127 11111 #define E830_GLPES_PFTXNPCNPSENT_TXNPCNPSENT_S 0 11112 #define E830_GLPES_PFTXNPCNPSENT_TXNPCNPSENT_M MAKEMASK(0xFFFFFF, 0) 11113 #define E830_GLQF_FLAT_HLUT(_i) (0x004C0000 + ((_i) * 4)) /* _i=0...8191 */ /* Reset Source: CORER */ 11114 #define E830_GLQF_FLAT_HLUT_MAX_INDEX 8191 11115 #define E830_GLQF_FLAT_HLUT_LUT0_S 0 11116 #define E830_GLQF_FLAT_HLUT_LUT0_M MAKEMASK(0xFF, 0) 11117 #define E830_GLQF_FLAT_HLUT_LUT1_S 8 11118 #define E830_GLQF_FLAT_HLUT_LUT1_M MAKEMASK(0xFF, 8) 11119 #define E830_GLQF_FLAT_HLUT_LUT2_S 16 11120 #define E830_GLQF_FLAT_HLUT_LUT2_M MAKEMASK(0xFF, 16) 11121 #define E830_GLQF_FLAT_HLUT_LUT3_S 24 11122 #define E830_GLQF_FLAT_HLUT_LUT3_M MAKEMASK(0xFF, 24) 11123 #define E830_GLQF_QGRP_CNTX(_i) (0x00490000 + ((_i) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */ 11124 #define E830_GLQF_QGRP_CNTX_MAX_INDEX 2047 11125 #define E830_GLQF_QGRP_CNTX_QG_LUT_BASE_S 0 11126 #define E830_GLQF_QGRP_CNTX_QG_LUT_BASE_M MAKEMASK(0x7FFF, 0) 11127 #define E830_GLQF_QGRP_CNTX_QG_LUT_SIZE_S 16 11128 #define E830_GLQF_QGRP_CNTX_QG_LUT_SIZE_M MAKEMASK(0xF, 16) 11129 #define E830_GLQF_QGRP_CNTX_VSI_S 20 11130 #define E830_GLQF_QGRP_CNTX_VSI_M MAKEMASK(0x3FF, 20) 11131 #define E830_GLQF_QGRP_PF_OWNER(_i) (0x00484000 + ((_i) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */ 11132 #define E830_GLQF_QGRP_PF_OWNER_MAX_INDEX 2047 11133 #define E830_GLQF_QGRP_PF_OWNER_OWNER_PF_S 0 11134 #define E830_GLQF_QGRP_PF_OWNER_OWNER_PF_M MAKEMASK(0x7, 0) 11135 #define E830_PFQF_LUT_ALLOC 0x0048E000 /* Reset Source: CORER */ 11136 #define E830_PFQF_LUT_ALLOC_LUT_BASE_S 0 11137 #define E830_PFQF_LUT_ALLOC_LUT_BASE_M MAKEMASK(0x7FFF, 0) 11138 #define E830_PFQF_LUT_ALLOC_LUT_SIZE_S 16 11139 #define E830_PFQF_LUT_ALLOC_LUT_SIZE_M MAKEMASK(0xF, 16) 11140 #define E830_VSIQF_DEF_QGRP(_VSI) (0x00486000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */ 11141 #define E830_VSIQF_DEF_QGRP_MAX_INDEX 767 11142 #define E830_VSIQF_DEF_QGRP_DEF_QGRP_S 0 11143 #define E830_VSIQF_DEF_QGRP_DEF_QGRP_M MAKEMASK(0x7FF, 0) 11144 #define E830_GLPRT_BPRCH_BPRCH_S 0 11145 #define E830_GLPRT_BPRCH_BPRCH_M MAKEMASK(0xFF, 0) 11146 #define E830_GLPRT_BPRCL_BPRCL_S 0 11147 #define E830_GLPRT_BPRCL_BPRCL_M MAKEMASK(0xFFFFFFFF, 0) 11148 #define E830_GLPRT_BPTCH_BPTCH_S 0 11149 #define E830_GLPRT_BPTCH_BPTCH_M MAKEMASK(0xFF, 0) 11150 #define E830_GLPRT_BPTCL_BPTCL_S 0 11151 #define E830_GLPRT_BPTCL_BPTCL_M MAKEMASK(0xFFFFFFFF, 0) 11152 #define E830_GLPRT_UPTCL_UPTCL_S 0 11153 #define E830_GLPRT_UPTCL_UPTCL_M MAKEMASK(0xFFFFFFFF, 0) 11154 #define E830_GLPTM_ART_CTL 0x00088B50 /* Reset Source: POR */ 11155 #define E830_GLPTM_ART_CTL_ACTIVE_S 0 11156 #define E830_GLPTM_ART_CTL_ACTIVE_M BIT(0) 11157 #define E830_GLPTM_ART_CTL_TIME_OUT_S 1 11158 #define E830_GLPTM_ART_CTL_TIME_OUT_M BIT(1) 11159 #define E830_GLPTM_ART_CTL_PTM_READY_S 2 11160 #define E830_GLPTM_ART_CTL_PTM_READY_M BIT(2) 11161 #define E830_GLPTM_ART_CTL_PTM_AUTO_S 3 11162 #define E830_GLPTM_ART_CTL_PTM_AUTO_M BIT(3) 11163 #define E830_GLPTM_ART_CTL_PTM_AUTO_LATCH_S 4 11164 #define E830_GLPTM_ART_CTL_PTM_AUTO_LATCH_M BIT(4) 11165 #define E830_GLPTM_ART_CTL_LATCH_PTP_T1_S 5 11166 #define E830_GLPTM_ART_CTL_LATCH_PTP_T1_M BIT(5) 11167 #define E830_GLPTM_ART_CTL_AUTO_POURSE_S 6 11168 #define E830_GLPTM_ART_CTL_AUTO_POURSE_M BIT(6) 11169 #define E830_GLPTM_ART_TIME_H 0x00088B54 /* Reset Source: POR */ 11170 #define E830_GLPTM_ART_TIME_H_ART_TIME_H_S 0 11171 #define E830_GLPTM_ART_TIME_H_ART_TIME_H_M MAKEMASK(0xFFFFFFFF, 0) 11172 #define E830_GLPTM_ART_TIME_L 0x00088B58 /* Reset Source: POR */ 11173 #define E830_GLPTM_ART_TIME_L_ART_TIME_L_S 0 11174 #define E830_GLPTM_ART_TIME_L_ART_TIME_L_M MAKEMASK(0xFFFFFFFF, 0) 11175 #define E830_GLTSYN_PTMTIME_H(_i) (0x00088B48 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 11176 #define E830_GLTSYN_PTMTIME_H_MAX_INDEX 1 11177 #define E830_GLTSYN_PTMTIME_H_TSYNEVNT_H_S 0 11178 #define E830_GLTSYN_PTMTIME_H_TSYNEVNT_H_M MAKEMASK(0xFFFFFFFF, 0) 11179 #define E830_GLTSYN_PTMTIME_L(_i) (0x00088B40 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ 11180 #define E830_GLTSYN_PTMTIME_L_MAX_INDEX 1 11181 #define E830_GLTSYN_PTMTIME_L_TSYNEVNT_L_S 0 11182 #define E830_GLTSYN_PTMTIME_L_TSYNEVNT_L_M MAKEMASK(0xFFFFFFFF, 0) 11183 #define E830_GLTSYN_TIME_H_0_AL 0x0008A004 /* Reset Source: CORER */ 11184 #define E830_GLTSYN_TIME_H_0_AL_TSYNTIME_L_S 0 11185 #define E830_GLTSYN_TIME_H_0_AL_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0) 11186 #define E830_GLTSYN_TIME_H_1_AL 0x0008B004 /* Reset Source: CORER */ 11187 #define E830_GLTSYN_TIME_H_1_AL_TSYNTIME_L_S 0 11188 #define E830_GLTSYN_TIME_H_1_AL_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0) 11189 #define E830_GLTSYN_TIME_L_0_AL 0x0008A000 /* Reset Source: CORER */ 11190 #define E830_GLTSYN_TIME_L_0_AL_TSYNTIME_L_S 0 11191 #define E830_GLTSYN_TIME_L_0_AL_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0) 11192 #define E830_GLTSYN_TIME_L_1_AL 0x0008B000 /* Reset Source: CORER */ 11193 #define E830_GLTSYN_TIME_L_1_AL_TSYNTIME_L_S 0 11194 #define E830_GLTSYN_TIME_L_1_AL_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0) 11195 #define E830_PFPTM_SEM 0x00088B00 /* Reset Source: PFR */ 11196 #define E830_PFPTM_SEM_BUSY_S 0 11197 #define E830_PFPTM_SEM_BUSY_M BIT(0) 11198 #define E830_PFPTM_SEM_PF_OWNER_S 4 11199 #define E830_PFPTM_SEM_PF_OWNER_M MAKEMASK(0x7, 4) 11200 #define E830_VSI_PASID_1(_VSI) (0x00094000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */ 11201 #define E830_VSI_PASID_1_MAX_INDEX 767 11202 #define E830_VSI_PASID_1_PASID_S 0 11203 #define E830_VSI_PASID_1_PASID_M MAKEMASK(0xFFFFF, 0) 11204 #define E830_VSI_PASID_1_EN_S 31 11205 #define E830_VSI_PASID_1_EN_M BIT(31) 11206 #define E830_VSI_PASID_2(_VSI) (0x00095000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */ 11207 #define E830_VSI_PASID_2_MAX_INDEX 767 11208 #define E830_VSI_PASID_2_PASID_S 0 11209 #define E830_VSI_PASID_2_PASID_M MAKEMASK(0xFFFFF, 0) 11210 #define E830_VSI_PASID_2_EN_S 31 11211 #define E830_VSI_PASID_2_EN_M BIT(31) 11212 #define E830_GLPE_CQM_FUNC_INVALIDATE_PMF_ID_S 15 11213 #define E830_GLPE_CQM_FUNC_INVALIDATE_PMF_ID_M MAKEMASK(0x3F, 15) 11214 #define E830_GLPE_CQM_FUNC_INVALIDATE_INVALIDATE_TYPE_S 29 11215 #define E830_GLPE_CQM_FUNC_INVALIDATE_INVALIDATE_TYPE_M MAKEMASK(0x3, 29) 11216 #define E830_VFPE_MRTEIDXMASK_MAX_INDEX 255 11217 #define E830_VSIQF_QGRP_CFG(_VSI) (0x00492000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ 11218 #define E830_VSIQF_QGRP_CFG_MAX_INDEX 767 11219 #define E830_VSIQF_QGRP_CFG_VSI_QGRP_ENABLE_S 0 11220 #define E830_VSIQF_QGRP_CFG_VSI_QGRP_ENABLE_M BIT(0) 11221 #define E830_VSIQF_QGRP_CFG_VSI_QGRP_GEN_INDEX_S 1 11222 #define E830_VSIQF_QGRP_CFG_VSI_QGRP_GEN_INDEX_M MAKEMASK(0x7, 1) 11223 #define E830_GLDCB_RTC_BLOCKED 0x0012274C /* Reset Source: CORER */ 11224 #define E830_GLDCB_RTC_BLOCKED_BLOCKED_S 0 11225 #define E830_GLDCB_RTC_BLOCKED_BLOCKED_M MAKEMASK(0xFFFFFFFF, 0) 11226 #define E830_GLDCB_RTCID 0x00122900 /* Reset Source: CORER */ 11227 #define E830_GLDCB_RTCID_IMM_DROP_TC_S 0 11228 #define E830_GLDCB_RTCID_IMM_DROP_TC_M MAKEMASK(0xFFFFFFFF, 0) 11229 #define E830_GLDCB_RTCTI_CDS_SET 0x00122748 /* Reset Source: CORER */ 11230 #define E830_GLDCB_RTCTI_CDS_SET_CDS_SET_S 0 11231 #define E830_GLDCB_RTCTI_CDS_SET_CDS_SET_M MAKEMASK(0xFFFFFFFF, 0) 11232 #define E830_GLDCB_RTCTQ_PD(_i) (0x00122700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 11233 #define E830_GLDCB_RTCTQ_PD_MAX_INDEX 7 11234 #define E830_GLDCB_RTCTQ_PD_RXQNUM_S 0 11235 #define E830_GLDCB_RTCTQ_PD_RXQNUM_M MAKEMASK(0x7FF, 0) 11236 #define E830_GLDCB_RTCTQ_PD_IS_PF_Q_S 16 11237 #define E830_GLDCB_RTCTQ_PD_IS_PF_Q_M BIT(16) 11238 #define E830_GLDCB_RTCTQ_SET 0x00122750 /* Reset Source: CORER */ 11239 #define E830_GLDCB_RTCTQ_SET_RTCTQ_VALID_S 0 11240 #define E830_GLDCB_RTCTQ_SET_RTCTQ_VALID_M MAKEMASK(0xFFFFFFFF, 0) 11241 #define E830_GLDCB_RTCTQ_STICKY_EN 0x00122754 /* Reset Source: CORER */ 11242 #define E830_GLDCB_RTCTQ_STICKY_EN_EN_S 0 11243 #define E830_GLDCB_RTCTQ_STICKY_EN_EN_M BIT(0) 11244 #define E830_GLDCB_RTCTS_PD(_i) (0x00122720 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ 11245 #define E830_GLDCB_RTCTS_PD_MAX_INDEX 7 11246 #define E830_GLDCB_RTCTS_PD_PFCTIMER_S 0 11247 #define E830_GLDCB_RTCTS_PD_PFCTIMER_M MAKEMASK(0x3FFF, 0) 11248 #define E830_GLRPB_TC_TOTAL_PC(_i) (0x000ACD00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ 11249 #define E830_GLRPB_TC_TOTAL_PC_MAX_INDEX 31 11250 #define E830_GLRPB_TC_TOTAL_PC_BYTE_CNT_S 0 11251 #define E830_GLRPB_TC_TOTAL_PC_BYTE_CNT_M MAKEMASK(0xFFFFFFFF, 0) 11252 #define E830_VFINT_ITRN_64(_i, _j) (0x00002C00 + ((_i) * 4 + (_j) * 256)) /* _i=0...63, _j=0...2 */ /* Reset Source: CORER */ 11253 #define E830_VFINT_ITRN_64_MAX_INDEX 63 11254 #define E830_VFINT_ITRN_64_INTERVAL_S 0 11255 #define E830_VFINT_ITRN_64_INTERVAL_M MAKEMASK(0xFFF, 0) 11256 #define E830_GLQTX_TXTIME_DBELL_LSB1(_DBQM) (0x0000D000 + ((_DBQM) * 8)) /* _i=0...255 */ /* Reset Source: CORER */ 11257 #define E830_GLQTX_TXTIME_DBELL_LSB1_MAX_INDEX 255 11258 #define E830_GLQTX_TXTIME_DBELL_LSB1_QTX_TXTIME_DBELL_S 0 11259 #define E830_GLQTX_TXTIME_DBELL_LSB1_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0) 11260 #define E830_GLQTX_TXTIME_DBELL_MSB1(_DBQM) (0x0000D004 + ((_DBQM) * 8)) /* _i=0...255 */ /* Reset Source: CORER */ 11261 #define E830_GLQTX_TXTIME_DBELL_MSB1_MAX_INDEX 255 11262 #define E830_GLQTX_TXTIME_DBELL_MSB1_QTX_TXTIME_DBELL_S 0 11263 #define E830_GLQTX_TXTIME_DBELL_MSB1_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0) 11264 #define E830_GLQTX_TXTIME_LARGE_DBELL_LSB(_DBQM) (0x00040000 + ((_DBQM) * 8)) /* _i=0...255 */ /* Reset Source: CORER */ 11265 #define E830_GLQTX_TXTIME_LARGE_DBELL_LSB_MAX_INDEX 255 11266 #define E830_GLQTX_TXTIME_LARGE_DBELL_LSB_QTX_TXTIME_DBELL_S 0 11267 #define E830_GLQTX_TXTIME_LARGE_DBELL_LSB_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0) 11268 #define E830_GLQTX_TXTIME_LARGE_DBELL_MSB(_DBQM) (0x00040004 + ((_DBQM) * 8)) /* _i=0...255 */ /* Reset Source: CORER */ 11269 #define E830_GLQTX_TXTIME_LARGE_DBELL_MSB_MAX_INDEX 255 11270 #define E830_GLQTX_TXTIME_LARGE_DBELL_MSB_QTX_TXTIME_DBELL_S 0 11271 #define E830_GLQTX_TXTIME_LARGE_DBELL_MSB_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0) 11272 #define E830_GLTSYN_TIME_H_0_AL1 0x00003004 /* Reset Source: CORER */ 11273 #define E830_GLTSYN_TIME_H_0_AL1_TSYNTIME_L_S 0 11274 #define E830_GLTSYN_TIME_H_0_AL1_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0) 11275 #define E830_GLTSYN_TIME_H_1_AL1 0x0000300C /* Reset Source: CORER */ 11276 #define E830_GLTSYN_TIME_H_1_AL1_TSYNTIME_L_S 0 11277 #define E830_GLTSYN_TIME_H_1_AL1_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0) 11278 #define E830_GLTSYN_TIME_L_0_AL1 0x00003000 /* Reset Source: CORER */ 11279 #define E830_GLTSYN_TIME_L_0_AL1_TSYNTIME_L_S 0 11280 #define E830_GLTSYN_TIME_L_0_AL1_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0) 11281 #define E830_GLTSYN_TIME_L_1_AL1 0x00003008 /* Reset Source: CORER */ 11282 #define E830_GLTSYN_TIME_L_1_AL1_TSYNTIME_L_S 0 11283 #define E830_GLTSYN_TIME_L_1_AL1_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0) 11284 #define E830_VSI_VSI2F_LEM(_VSI) (0x006100A0 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */ 11285 #define E830_VSI_VSI2F_LEM_MAX_INDEX 767 11286 #define E830_VSI_VSI2F_LEM_VFVMNUMBER_S 0 11287 #define E830_VSI_VSI2F_LEM_VFVMNUMBER_M MAKEMASK(0x3FF, 0) 11288 #define E830_VSI_VSI2F_LEM_FUNCTIONTYPE_S 10 11289 #define E830_VSI_VSI2F_LEM_FUNCTIONTYPE_M MAKEMASK(0x3, 10) 11290 #define E830_VSI_VSI2F_LEM_PFNUMBER_S 12 11291 #define E830_VSI_VSI2F_LEM_PFNUMBER_M MAKEMASK(0x7, 12) 11292 #define E830_VSI_VSI2F_LEM_BUFFERNUMBER_S 16 11293 #define E830_VSI_VSI2F_LEM_BUFFERNUMBER_M MAKEMASK(0x7, 16) 11294 #define E830_VSI_VSI2F_LEM_VSI_NUMBER_S 20 11295 #define E830_VSI_VSI2F_LEM_VSI_NUMBER_M MAKEMASK(0x3FF, 20) 11296 #define E830_VSI_VSI2F_LEM_VSI_ENABLE_S 31 11297 #define E830_VSI_VSI2F_LEM_VSI_ENABLE_M BIT(31) 11298 #endif /* !_ICE_HW_AUTOGEN_H_ */ 11299 11300