1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #ifndef __AMDGPU_SMU_H__ 23 #define __AMDGPU_SMU_H__ 24 25 #include <linux/acpi_amd_wbrf.h> 26 #include <linux/units.h> 27 28 #include "amdgpu.h" 29 #include "kgd_pp_interface.h" 30 #include "dm_pp_interface.h" 31 #include "dm_pp_smu.h" 32 #include "smu_types.h" 33 #include "linux/firmware.h" 34 35 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0 36 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255 37 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000 38 #define SMU_FW_NAME_LEN 0x24 39 40 #define SMU_DPM_USER_PROFILE_RESTORE (1 << 0) 41 #define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1) 42 #define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2) 43 44 // Power Throttlers 45 #define SMU_THROTTLER_PPT0_BIT 0 46 #define SMU_THROTTLER_PPT1_BIT 1 47 #define SMU_THROTTLER_PPT2_BIT 2 48 #define SMU_THROTTLER_PPT3_BIT 3 49 #define SMU_THROTTLER_SPL_BIT 4 50 #define SMU_THROTTLER_FPPT_BIT 5 51 #define SMU_THROTTLER_SPPT_BIT 6 52 #define SMU_THROTTLER_SPPT_APU_BIT 7 53 54 // Current Throttlers 55 #define SMU_THROTTLER_TDC_GFX_BIT 16 56 #define SMU_THROTTLER_TDC_SOC_BIT 17 57 #define SMU_THROTTLER_TDC_MEM_BIT 18 58 #define SMU_THROTTLER_TDC_VDD_BIT 19 59 #define SMU_THROTTLER_TDC_CVIP_BIT 20 60 #define SMU_THROTTLER_EDC_CPU_BIT 21 61 #define SMU_THROTTLER_EDC_GFX_BIT 22 62 #define SMU_THROTTLER_APCC_BIT 23 63 64 // Temperature 65 #define SMU_THROTTLER_TEMP_GPU_BIT 32 66 #define SMU_THROTTLER_TEMP_CORE_BIT 33 67 #define SMU_THROTTLER_TEMP_MEM_BIT 34 68 #define SMU_THROTTLER_TEMP_EDGE_BIT 35 69 #define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36 70 #define SMU_THROTTLER_TEMP_SOC_BIT 37 71 #define SMU_THROTTLER_TEMP_VR_GFX_BIT 38 72 #define SMU_THROTTLER_TEMP_VR_SOC_BIT 39 73 #define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40 74 #define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41 75 #define SMU_THROTTLER_TEMP_LIQUID0_BIT 42 76 #define SMU_THROTTLER_TEMP_LIQUID1_BIT 43 77 #define SMU_THROTTLER_VRHOT0_BIT 44 78 #define SMU_THROTTLER_VRHOT1_BIT 45 79 #define SMU_THROTTLER_PROCHOT_CPU_BIT 46 80 #define SMU_THROTTLER_PROCHOT_GFX_BIT 47 81 82 // Other 83 #define SMU_THROTTLER_PPM_BIT 56 84 #define SMU_THROTTLER_FIT_BIT 57 85 86 struct smu_hw_power_state { 87 unsigned int magic; 88 }; 89 90 struct smu_power_state; 91 92 enum smu_state_ui_label { 93 SMU_STATE_UI_LABEL_NONE, 94 SMU_STATE_UI_LABEL_BATTERY, 95 SMU_STATE_UI_TABEL_MIDDLE_LOW, 96 SMU_STATE_UI_LABEL_BALLANCED, 97 SMU_STATE_UI_LABEL_MIDDLE_HIGHT, 98 SMU_STATE_UI_LABEL_PERFORMANCE, 99 SMU_STATE_UI_LABEL_BACO, 100 }; 101 102 enum smu_state_classification_flag { 103 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001, 104 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002, 105 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004, 106 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008, 107 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010, 108 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020, 109 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040, 110 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080, 111 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100, 112 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200, 113 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400, 114 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800, 115 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000, 116 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000, 117 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000, 118 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000, 119 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000, 120 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000, 121 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000, 122 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000, 123 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000, 124 }; 125 126 struct smu_state_classification_block { 127 enum smu_state_ui_label ui_label; 128 enum smu_state_classification_flag flags; 129 int bios_index; 130 bool temporary_state; 131 bool to_be_deleted; 132 }; 133 134 struct smu_state_pcie_block { 135 unsigned int lanes; 136 }; 137 138 enum smu_refreshrate_source { 139 SMU_REFRESHRATE_SOURCE_EDID, 140 SMU_REFRESHRATE_SOURCE_EXPLICIT 141 }; 142 143 struct smu_state_display_block { 144 bool disable_frame_modulation; 145 bool limit_refreshrate; 146 enum smu_refreshrate_source refreshrate_source; 147 int explicit_refreshrate; 148 int edid_refreshrate_index; 149 bool enable_vari_bright; 150 }; 151 152 struct smu_state_memory_block { 153 bool dll_off; 154 uint8_t m3arb; 155 uint8_t unused[3]; 156 }; 157 158 struct smu_state_software_algorithm_block { 159 bool disable_load_balancing; 160 bool enable_sleep_for_timestamps; 161 }; 162 163 struct smu_temperature_range { 164 int min; 165 int max; 166 int edge_emergency_max; 167 int hotspot_min; 168 int hotspot_crit_max; 169 int hotspot_emergency_max; 170 int mem_min; 171 int mem_crit_max; 172 int mem_emergency_max; 173 int software_shutdown_temp; 174 int software_shutdown_temp_offset; 175 }; 176 177 struct smu_state_validation_block { 178 bool single_display_only; 179 bool disallow_on_dc; 180 uint8_t supported_power_levels; 181 }; 182 183 struct smu_uvd_clocks { 184 uint32_t vclk; 185 uint32_t dclk; 186 }; 187 188 /** 189 * Structure to hold a SMU Power State. 190 */ 191 struct smu_power_state { 192 uint32_t id; 193 struct list_head ordered_list; 194 struct list_head all_states_list; 195 196 struct smu_state_classification_block classification; 197 struct smu_state_validation_block validation; 198 struct smu_state_pcie_block pcie; 199 struct smu_state_display_block display; 200 struct smu_state_memory_block memory; 201 struct smu_state_software_algorithm_block software; 202 struct smu_uvd_clocks uvd_clocks; 203 struct smu_hw_power_state hardware; 204 }; 205 206 enum smu_power_src_type { 207 SMU_POWER_SOURCE_AC, 208 SMU_POWER_SOURCE_DC, 209 SMU_POWER_SOURCE_COUNT, 210 }; 211 212 enum smu_ppt_limit_type { 213 SMU_DEFAULT_PPT_LIMIT = 0, 214 SMU_FAST_PPT_LIMIT, 215 }; 216 217 enum smu_ppt_limit_level { 218 SMU_PPT_LIMIT_MIN = -1, 219 SMU_PPT_LIMIT_CURRENT, 220 SMU_PPT_LIMIT_DEFAULT, 221 SMU_PPT_LIMIT_MAX, 222 }; 223 224 enum smu_memory_pool_size { 225 SMU_MEMORY_POOL_SIZE_ZERO = 0, 226 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000, 227 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000, 228 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000, 229 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000, 230 }; 231 232 struct smu_user_dpm_profile { 233 uint32_t fan_mode; 234 uint32_t power_limit; 235 uint32_t fan_speed_pwm; 236 uint32_t fan_speed_rpm; 237 uint32_t flags; 238 uint32_t user_od; 239 240 /* user clock state information */ 241 uint32_t clk_mask[SMU_CLK_COUNT]; 242 uint32_t clk_dependency; 243 }; 244 245 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \ 246 do { \ 247 tables[table_id].size = s; \ 248 tables[table_id].align = a; \ 249 tables[table_id].domain = d; \ 250 } while (0) 251 252 struct smu_table { 253 uint64_t size; 254 uint32_t align; 255 uint8_t domain; 256 uint64_t mc_address; 257 void *cpu_addr; 258 struct amdgpu_bo *bo; 259 uint32_t version; 260 }; 261 262 enum smu_perf_level_designation { 263 PERF_LEVEL_ACTIVITY, 264 PERF_LEVEL_POWER_CONTAINMENT, 265 }; 266 267 struct smu_performance_level { 268 uint32_t core_clock; 269 uint32_t memory_clock; 270 uint32_t vddc; 271 uint32_t vddci; 272 uint32_t non_local_mem_freq; 273 uint32_t non_local_mem_width; 274 }; 275 276 struct smu_clock_info { 277 uint32_t min_mem_clk; 278 uint32_t max_mem_clk; 279 uint32_t min_eng_clk; 280 uint32_t max_eng_clk; 281 uint32_t min_bus_bandwidth; 282 uint32_t max_bus_bandwidth; 283 }; 284 285 struct smu_bios_boot_up_values { 286 uint32_t revision; 287 uint32_t gfxclk; 288 uint32_t uclk; 289 uint32_t socclk; 290 uint32_t dcefclk; 291 uint32_t eclk; 292 uint32_t vclk; 293 uint32_t dclk; 294 uint16_t vddc; 295 uint16_t vddci; 296 uint16_t mvddc; 297 uint16_t vdd_gfx; 298 uint8_t cooling_id; 299 uint32_t pp_table_id; 300 uint32_t format_revision; 301 uint32_t content_revision; 302 uint32_t fclk; 303 uint32_t lclk; 304 uint32_t firmware_caps; 305 }; 306 307 enum smu_table_id { 308 SMU_TABLE_PPTABLE = 0, 309 SMU_TABLE_WATERMARKS, 310 SMU_TABLE_CUSTOM_DPM, 311 SMU_TABLE_DPMCLOCKS, 312 SMU_TABLE_AVFS, 313 SMU_TABLE_AVFS_PSM_DEBUG, 314 SMU_TABLE_AVFS_FUSE_OVERRIDE, 315 SMU_TABLE_PMSTATUSLOG, 316 SMU_TABLE_SMU_METRICS, 317 SMU_TABLE_DRIVER_SMU_CONFIG, 318 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 319 SMU_TABLE_OVERDRIVE, 320 SMU_TABLE_I2C_COMMANDS, 321 SMU_TABLE_PACE, 322 SMU_TABLE_ECCINFO, 323 SMU_TABLE_COMBO_PPTABLE, 324 SMU_TABLE_WIFIBAND, 325 SMU_TABLE_COUNT, 326 }; 327 328 struct smu_table_context { 329 void *power_play_table; 330 uint32_t power_play_table_size; 331 void *hardcode_pptable; 332 unsigned long metrics_time; 333 void *metrics_table; 334 void *clocks_table; 335 void *watermarks_table; 336 337 void *max_sustainable_clocks; 338 struct smu_bios_boot_up_values boot_values; 339 void *driver_pptable; 340 void *combo_pptable; 341 void *ecc_table; 342 void *driver_smu_config_table; 343 struct smu_table tables[SMU_TABLE_COUNT]; 344 /* 345 * The driver table is just a staging buffer for 346 * uploading/downloading content from the SMU. 347 * 348 * And the table_id for SMU_MSG_TransferTableSmu2Dram/ 349 * SMU_MSG_TransferTableDram2Smu instructs SMU 350 * which content driver is interested. 351 */ 352 struct smu_table driver_table; 353 struct smu_table memory_pool; 354 struct smu_table dummy_read_1_table; 355 uint8_t thermal_controller_type; 356 357 void *overdrive_table; 358 void *boot_overdrive_table; 359 void *user_overdrive_table; 360 361 uint32_t gpu_metrics_table_size; 362 void *gpu_metrics_table; 363 }; 364 365 struct smu_context; 366 struct smu_dpm_policy; 367 368 struct smu_dpm_policy_desc { 369 const char *name; 370 char *(*get_desc)(struct smu_dpm_policy *dpm_policy, int level); 371 }; 372 373 struct smu_dpm_policy { 374 struct smu_dpm_policy_desc *desc; 375 enum pp_pm_policy policy_type; 376 unsigned long level_mask; 377 int current_level; 378 int (*set_policy)(struct smu_context *ctxt, int level); 379 }; 380 381 struct smu_dpm_policy_ctxt { 382 struct smu_dpm_policy policies[PP_PM_POLICY_NUM]; 383 unsigned long policy_mask; 384 }; 385 386 struct smu_dpm_context { 387 uint32_t dpm_context_size; 388 void *dpm_context; 389 void *golden_dpm_context; 390 enum amd_dpm_forced_level dpm_level; 391 enum amd_dpm_forced_level saved_dpm_level; 392 enum amd_dpm_forced_level requested_dpm_level; 393 struct smu_power_state *dpm_request_power_state; 394 struct smu_power_state *dpm_current_power_state; 395 struct mclock_latency_table *mclk_latency_table; 396 struct smu_dpm_policy_ctxt *dpm_policies; 397 }; 398 399 struct smu_power_gate { 400 bool uvd_gated; 401 bool vce_gated; 402 atomic_t vcn_gated[AMDGPU_MAX_VCN_INSTANCES]; 403 atomic_t jpeg_gated; 404 atomic_t vpe_gated; 405 atomic_t isp_gated; 406 atomic_t umsch_mm_gated; 407 }; 408 409 struct smu_power_context { 410 void *power_context; 411 uint32_t power_context_size; 412 struct smu_power_gate power_gate; 413 }; 414 415 #define SMU_FEATURE_MAX (64) 416 struct smu_feature { 417 uint32_t feature_num; 418 DECLARE_BITMAP(supported, SMU_FEATURE_MAX); 419 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX); 420 }; 421 422 struct smu_clocks { 423 uint32_t engine_clock; 424 uint32_t memory_clock; 425 uint32_t bus_bandwidth; 426 uint32_t engine_clock_in_sr; 427 uint32_t dcef_clock; 428 uint32_t dcef_clock_in_sr; 429 }; 430 431 #define MAX_REGULAR_DPM_NUM 16 432 struct mclk_latency_entries { 433 uint32_t frequency; 434 uint32_t latency; 435 }; 436 struct mclock_latency_table { 437 uint32_t count; 438 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM]; 439 }; 440 441 enum smu_reset_mode { 442 SMU_RESET_MODE_0, 443 SMU_RESET_MODE_1, 444 SMU_RESET_MODE_2, 445 SMU_RESET_MODE_3, 446 SMU_RESET_MODE_4, 447 }; 448 449 enum smu_baco_state { 450 SMU_BACO_STATE_ENTER = 0, 451 SMU_BACO_STATE_EXIT, 452 SMU_BACO_STATE_NONE, 453 }; 454 455 struct smu_baco_context { 456 uint32_t state; 457 bool platform_support; 458 bool maco_support; 459 }; 460 461 struct smu_freq_info { 462 uint32_t min; 463 uint32_t max; 464 uint32_t freq_level; 465 }; 466 467 struct pstates_clk_freq { 468 uint32_t min; 469 uint32_t standard; 470 uint32_t peak; 471 struct smu_freq_info custom; 472 struct smu_freq_info curr; 473 }; 474 475 struct smu_umd_pstate_table { 476 struct pstates_clk_freq gfxclk_pstate; 477 struct pstates_clk_freq socclk_pstate; 478 struct pstates_clk_freq uclk_pstate; 479 struct pstates_clk_freq vclk_pstate; 480 struct pstates_clk_freq dclk_pstate; 481 struct pstates_clk_freq fclk_pstate; 482 }; 483 484 struct cmn2asic_msg_mapping { 485 int valid_mapping; 486 int map_to; 487 uint32_t flags; 488 }; 489 490 struct cmn2asic_mapping { 491 int valid_mapping; 492 int map_to; 493 }; 494 495 struct stb_context { 496 uint32_t stb_buf_size; 497 bool enabled; 498 spinlock_t lock; 499 }; 500 501 enum smu_fw_status { 502 SMU_FW_INIT = 0, 503 SMU_FW_RUNTIME, 504 SMU_FW_HANG, 505 }; 506 507 #define WORKLOAD_POLICY_MAX 7 508 509 /* 510 * Configure wbrf event handling pace as there can be only one 511 * event processed every SMU_WBRF_EVENT_HANDLING_PACE ms. 512 */ 513 #define SMU_WBRF_EVENT_HANDLING_PACE 10 514 515 struct smu_context { 516 struct amdgpu_device *adev; 517 struct amdgpu_irq_src irq_source; 518 519 const struct pptable_funcs *ppt_funcs; 520 const struct cmn2asic_msg_mapping *message_map; 521 const struct cmn2asic_mapping *clock_map; 522 const struct cmn2asic_mapping *feature_map; 523 const struct cmn2asic_mapping *table_map; 524 const struct cmn2asic_mapping *pwr_src_map; 525 const struct cmn2asic_mapping *workload_map; 526 struct mutex message_lock; 527 uint64_t pool_size; 528 529 struct smu_table_context smu_table; 530 struct smu_dpm_context smu_dpm; 531 struct smu_power_context smu_power; 532 struct smu_feature smu_feature; 533 struct amd_pp_display_configuration *display_config; 534 struct smu_baco_context smu_baco; 535 struct smu_temperature_range thermal_range; 536 void *od_settings; 537 538 struct smu_umd_pstate_table pstate_table; 539 uint32_t pstate_sclk; 540 uint32_t pstate_mclk; 541 542 bool od_enabled; 543 uint32_t current_power_limit; 544 uint32_t default_power_limit; 545 uint32_t max_power_limit; 546 uint32_t min_power_limit; 547 548 /* soft pptable */ 549 uint32_t ppt_offset_bytes; 550 uint32_t ppt_size_bytes; 551 uint8_t *ppt_start_addr; 552 553 bool support_power_containment; 554 bool disable_watermark; 555 556 #define WATERMARKS_EXIST (1 << 0) 557 #define WATERMARKS_LOADED (1 << 1) 558 uint32_t watermarks_bitmap; 559 uint32_t hard_min_uclk_req_from_dal; 560 bool disable_uclk_switch; 561 562 /* asic agnostic workload mask */ 563 uint32_t workload_mask; 564 bool pause_workload; 565 /* default/user workload preference */ 566 uint32_t power_profile_mode; 567 uint32_t workload_refcount[PP_SMC_POWER_PROFILE_COUNT]; 568 /* backend specific custom workload settings */ 569 long *custom_profile_params; 570 bool pm_enabled; 571 bool is_apu; 572 573 uint32_t smc_driver_if_version; 574 uint32_t smc_fw_if_version; 575 uint32_t smc_fw_version; 576 uint32_t smc_fw_caps; 577 uint8_t smc_fw_state; 578 579 bool uploading_custom_pp_table; 580 bool dc_controlled_by_gpio; 581 582 struct work_struct throttling_logging_work; 583 atomic64_t throttle_int_counter; 584 struct work_struct interrupt_work; 585 586 unsigned fan_max_rpm; 587 unsigned manual_fan_speed_pwm; 588 589 uint32_t gfx_default_hard_min_freq; 590 uint32_t gfx_default_soft_max_freq; 591 uint32_t gfx_actual_hard_min_freq; 592 uint32_t gfx_actual_soft_max_freq; 593 594 /* APU only */ 595 uint32_t cpu_default_soft_min_freq; 596 uint32_t cpu_default_soft_max_freq; 597 uint32_t cpu_actual_soft_min_freq; 598 uint32_t cpu_actual_soft_max_freq; 599 uint32_t cpu_core_id_select; 600 uint16_t cpu_core_num; 601 602 struct smu_user_dpm_profile user_dpm_profile; 603 604 struct stb_context stb_context; 605 606 struct firmware pptable_firmware; 607 608 u32 param_reg; 609 u32 msg_reg; 610 u32 resp_reg; 611 612 u32 debug_param_reg; 613 u32 debug_msg_reg; 614 u32 debug_resp_reg; 615 616 struct delayed_work swctf_delayed_work; 617 618 /* data structures for wbrf feature support */ 619 bool wbrf_supported; 620 struct notifier_block wbrf_notifier; 621 struct delayed_work wbrf_delayed_work; 622 }; 623 624 struct i2c_adapter; 625 626 /** 627 * struct pptable_funcs - Callbacks used to interact with the SMU. 628 */ 629 struct pptable_funcs { 630 /** 631 * @run_btc: Calibrate voltage/frequency curve to fit the system's 632 * power delivery and voltage margins. Required for adaptive 633 * voltage frequency scaling (AVFS). 634 */ 635 int (*run_btc)(struct smu_context *smu); 636 637 /** 638 * @get_allowed_feature_mask: Get allowed feature mask. 639 * &feature_mask: Array to store feature mask. 640 * &num: Elements in &feature_mask. 641 */ 642 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 643 644 /** 645 * @get_current_power_state: Get the current power state. 646 * 647 * Return: Current power state on success, negative errno on failure. 648 */ 649 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu); 650 651 /** 652 * @set_default_dpm_table: Retrieve the default overdrive settings from 653 * the SMU. 654 */ 655 int (*set_default_dpm_table)(struct smu_context *smu); 656 657 int (*set_power_state)(struct smu_context *smu); 658 659 /** 660 * @populate_umd_state_clk: Populate the UMD power state table with 661 * defaults. 662 */ 663 int (*populate_umd_state_clk)(struct smu_context *smu); 664 665 /** 666 * @print_clk_levels: Print DPM clock levels for a clock domain 667 * to buffer. Star current level. 668 * 669 * Used for sysfs interfaces. 670 * Return: Number of characters written to the buffer 671 */ 672 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); 673 674 /** 675 * @emit_clk_levels: Print DPM clock levels for a clock domain 676 * to buffer using sysfs_emit_at. Star current level. 677 * 678 * Used for sysfs interfaces. 679 * &buf: sysfs buffer 680 * &offset: offset within buffer to start printing, which is updated by the 681 * function. 682 * 683 * Return: 0 on Success or Negative to indicate an error occurred. 684 */ 685 int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset); 686 687 /** 688 * @force_clk_levels: Set a range of allowed DPM levels for a clock 689 * domain. 690 * &clk_type: Clock domain. 691 * &mask: Range of allowed DPM levels. 692 */ 693 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); 694 695 /** 696 * @od_edit_dpm_table: Edit the custom overdrive DPM table. 697 * &type: Type of edit. 698 * &input: Edit parameters. 699 * &size: Size of &input. 700 */ 701 int (*od_edit_dpm_table)(struct smu_context *smu, 702 enum PP_OD_DPM_TABLE_COMMAND type, 703 long *input, uint32_t size); 704 705 /** 706 * @restore_user_od_settings: Restore the user customized 707 * OD settings on S3/S4/Runpm resume. 708 */ 709 int (*restore_user_od_settings)(struct smu_context *smu); 710 711 /** 712 * @get_clock_by_type_with_latency: Get the speed and latency of a clock 713 * domain. 714 */ 715 int (*get_clock_by_type_with_latency)(struct smu_context *smu, 716 enum smu_clk_type clk_type, 717 struct 718 pp_clock_levels_with_latency 719 *clocks); 720 /** 721 * @get_clock_by_type_with_voltage: Get the speed and voltage of a clock 722 * domain. 723 */ 724 int (*get_clock_by_type_with_voltage)(struct smu_context *smu, 725 enum amd_pp_clock_type type, 726 struct 727 pp_clock_levels_with_voltage 728 *clocks); 729 730 /** 731 * @get_power_profile_mode: Print all power profile modes to 732 * buffer. Star current mode. 733 */ 734 int (*get_power_profile_mode)(struct smu_context *smu, char *buf); 735 736 /** 737 * @set_power_profile_mode: Set a power profile mode. Also used to 738 * create/set custom power profile modes. 739 * &input: Power profile mode parameters. 740 * &workload_mask: mask of workloads to enable 741 * &custom_params: custom profile parameters 742 * &custom_params_max_idx: max valid idx into custom_params 743 */ 744 int (*set_power_profile_mode)(struct smu_context *smu, u32 workload_mask, 745 long *custom_params, u32 custom_params_max_idx); 746 747 /** 748 * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power 749 * management. 750 */ 751 int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable, int inst); 752 753 /** 754 * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power 755 * management. 756 */ 757 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable); 758 759 /** 760 * @set_gfx_power_up_by_imu: Enable GFX engine with IMU 761 */ 762 int (*set_gfx_power_up_by_imu)(struct smu_context *smu); 763 764 /** 765 * @read_sensor: Read data from a sensor. 766 * &sensor: Sensor to read data from. 767 * &data: Sensor reading. 768 * &size: Size of &data. 769 */ 770 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor, 771 void *data, uint32_t *size); 772 773 /** 774 * @get_apu_thermal_limit: get apu core limit from smu 775 * &limit: current limit temperature in millidegrees Celsius 776 */ 777 int (*get_apu_thermal_limit)(struct smu_context *smu, uint32_t *limit); 778 779 /** 780 * @set_apu_thermal_limit: update all controllers with new limit 781 * &limit: limit temperature to be setted, in millidegrees Celsius 782 */ 783 int (*set_apu_thermal_limit)(struct smu_context *smu, uint32_t limit); 784 785 /** 786 * @pre_display_config_changed: Prepare GPU for a display configuration 787 * change. 788 * 789 * Disable display tracking and pin memory clock speed to maximum. Used 790 * in display component synchronization. 791 */ 792 int (*pre_display_config_changed)(struct smu_context *smu); 793 794 /** 795 * @display_config_changed: Notify the SMU of the current display 796 * configuration. 797 * 798 * Allows SMU to properly track blanking periods for memory clock 799 * adjustment. Used in display component synchronization. 800 */ 801 int (*display_config_changed)(struct smu_context *smu); 802 803 int (*apply_clocks_adjust_rules)(struct smu_context *smu); 804 805 /** 806 * @notify_smc_display_config: Applies display requirements to the 807 * current power state. 808 * 809 * Optimize deep sleep DCEFclk and mclk for the current display 810 * configuration. Used in display component synchronization. 811 */ 812 int (*notify_smc_display_config)(struct smu_context *smu); 813 814 /** 815 * @is_dpm_running: Check if DPM is running. 816 * 817 * Return: True if DPM is running, false otherwise. 818 */ 819 bool (*is_dpm_running)(struct smu_context *smu); 820 821 /** 822 * @get_fan_speed_pwm: Get the current fan speed in PWM. 823 */ 824 int (*get_fan_speed_pwm)(struct smu_context *smu, uint32_t *speed); 825 826 /** 827 * @get_fan_speed_rpm: Get the current fan speed in rpm. 828 */ 829 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed); 830 831 /** 832 * @set_watermarks_table: Configure and upload the watermarks tables to 833 * the SMU. 834 */ 835 int (*set_watermarks_table)(struct smu_context *smu, 836 struct pp_smu_wm_range_sets *clock_ranges); 837 838 /** 839 * @get_thermal_temperature_range: Get safe thermal limits in Celcius. 840 */ 841 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range); 842 843 /** 844 * @get_uclk_dpm_states: Get memory clock DPM levels in kHz. 845 * &clocks_in_khz: Array of DPM levels. 846 * &num_states: Elements in &clocks_in_khz. 847 */ 848 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states); 849 850 /** 851 * @set_default_od_settings: Set the overdrive tables to defaults. 852 */ 853 int (*set_default_od_settings)(struct smu_context *smu); 854 855 /** 856 * @set_performance_level: Set a performance level. 857 */ 858 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level); 859 860 /** 861 * @display_disable_memory_clock_switch: Enable/disable dynamic memory 862 * clock switching. 863 * 864 * Disabling this feature forces memory clock speed to maximum. 865 * Enabling sets the minimum memory clock capable of driving the 866 * current display configuration. 867 */ 868 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch); 869 870 /** 871 * @get_power_limit: Get the device's power limits. 872 */ 873 int (*get_power_limit)(struct smu_context *smu, 874 uint32_t *current_power_limit, 875 uint32_t *default_power_limit, 876 uint32_t *max_power_limit, 877 uint32_t *min_power_limit); 878 879 /** 880 * @get_ppt_limit: Get the device's ppt limits. 881 */ 882 int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit, 883 enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level); 884 885 /** 886 * @set_df_cstate: Set data fabric cstate. 887 */ 888 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state); 889 890 /** 891 * @update_pcie_parameters: Update and upload the system's PCIe 892 * capabilites to the SMU. 893 * &pcie_gen_cap: Maximum allowed PCIe generation. 894 * &pcie_width_cap: Maximum allowed PCIe width. 895 */ 896 int (*update_pcie_parameters)(struct smu_context *smu, uint8_t pcie_gen_cap, uint8_t pcie_width_cap); 897 898 /** 899 * @i2c_init: Initialize i2c. 900 * 901 * The i2c bus is used internally by the SMU voltage regulators and 902 * other devices. The i2c's EEPROM also stores bad page tables on boards 903 * with ECC. 904 */ 905 int (*i2c_init)(struct smu_context *smu); 906 907 /** 908 * @i2c_fini: Tear down i2c. 909 */ 910 void (*i2c_fini)(struct smu_context *smu); 911 912 /** 913 * @get_unique_id: Get the GPU's unique id. Used for asset tracking. 914 */ 915 void (*get_unique_id)(struct smu_context *smu); 916 917 /** 918 * @get_dpm_clock_table: Get a copy of the DPM clock table. 919 * 920 * Used by display component in bandwidth and watermark calculations. 921 */ 922 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table); 923 924 /** 925 * @init_microcode: Request the SMU's firmware from the kernel. 926 */ 927 int (*init_microcode)(struct smu_context *smu); 928 929 /** 930 * @load_microcode: Load firmware onto the SMU. 931 */ 932 int (*load_microcode)(struct smu_context *smu); 933 934 /** 935 * @fini_microcode: Release the SMU's firmware. 936 */ 937 void (*fini_microcode)(struct smu_context *smu); 938 939 /** 940 * @init_smc_tables: Initialize the SMU tables. 941 */ 942 int (*init_smc_tables)(struct smu_context *smu); 943 944 /** 945 * @fini_smc_tables: Release the SMU tables. 946 */ 947 int (*fini_smc_tables)(struct smu_context *smu); 948 949 /** 950 * @init_power: Initialize the power gate table context. 951 */ 952 int (*init_power)(struct smu_context *smu); 953 954 /** 955 * @fini_power: Release the power gate table context. 956 */ 957 int (*fini_power)(struct smu_context *smu); 958 959 /** 960 * @check_fw_status: Check the SMU's firmware status. 961 * 962 * Return: Zero if check passes, negative errno on failure. 963 */ 964 int (*check_fw_status)(struct smu_context *smu); 965 966 /** 967 * @set_mp1_state: put SMU into a correct state for comming 968 * resume from runpm or gpu reset. 969 */ 970 int (*set_mp1_state)(struct smu_context *smu, 971 enum pp_mp1_state mp1_state); 972 973 /** 974 * @setup_pptable: Initialize the power play table and populate it with 975 * default values. 976 */ 977 int (*setup_pptable)(struct smu_context *smu); 978 979 /** 980 * @get_vbios_bootup_values: Get default boot values from the VBIOS. 981 */ 982 int (*get_vbios_bootup_values)(struct smu_context *smu); 983 984 /** 985 * @check_fw_version: Print driver and SMU interface versions to the 986 * system log. 987 * 988 * Interface mismatch is not a critical failure. 989 */ 990 int (*check_fw_version)(struct smu_context *smu); 991 992 /** 993 * @powergate_sdma: Power up/down system direct memory access. 994 */ 995 int (*powergate_sdma)(struct smu_context *smu, bool gate); 996 997 /** 998 * @set_gfx_cgpg: Enable/disable graphics engine course grain power 999 * gating. 1000 */ 1001 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable); 1002 1003 /** 1004 * @write_pptable: Write the power play table to the SMU. 1005 */ 1006 int (*write_pptable)(struct smu_context *smu); 1007 1008 /** 1009 * @set_driver_table_location: Send the location of the driver table to 1010 * the SMU. 1011 */ 1012 int (*set_driver_table_location)(struct smu_context *smu); 1013 1014 /** 1015 * @set_tool_table_location: Send the location of the tool table to the 1016 * SMU. 1017 */ 1018 int (*set_tool_table_location)(struct smu_context *smu); 1019 1020 /** 1021 * @notify_memory_pool_location: Send the location of the memory pool to 1022 * the SMU. 1023 */ 1024 int (*notify_memory_pool_location)(struct smu_context *smu); 1025 1026 /** 1027 * @system_features_control: Enable/disable all SMU features. 1028 */ 1029 int (*system_features_control)(struct smu_context *smu, bool en); 1030 1031 /** 1032 * @send_smc_msg_with_param: Send a message with a parameter to the SMU. 1033 * &msg: Type of message. 1034 * ¶m: Message parameter. 1035 * &read_arg: SMU response (optional). 1036 */ 1037 int (*send_smc_msg_with_param)(struct smu_context *smu, 1038 enum smu_message_type msg, uint32_t param, uint32_t *read_arg); 1039 1040 /** 1041 * @send_smc_msg: Send a message to the SMU. 1042 * &msg: Type of message. 1043 * &read_arg: SMU response (optional). 1044 */ 1045 int (*send_smc_msg)(struct smu_context *smu, 1046 enum smu_message_type msg, 1047 uint32_t *read_arg); 1048 1049 /** 1050 * @init_display_count: Notify the SMU of the number of display 1051 * components in current display configuration. 1052 */ 1053 int (*init_display_count)(struct smu_context *smu, uint32_t count); 1054 1055 /** 1056 * @set_allowed_mask: Notify the SMU of the features currently allowed 1057 * by the driver. 1058 */ 1059 int (*set_allowed_mask)(struct smu_context *smu); 1060 1061 /** 1062 * @get_enabled_mask: Get a mask of features that are currently enabled 1063 * on the SMU. 1064 * &feature_mask: Enabled feature mask. 1065 */ 1066 int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask); 1067 1068 /** 1069 * @feature_is_enabled: Test if a feature is enabled. 1070 * 1071 * Return: One if enabled, zero if disabled. 1072 */ 1073 int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask); 1074 1075 /** 1076 * @disable_all_features_with_exception: Disable all features with 1077 * exception to those in &mask. 1078 */ 1079 int (*disable_all_features_with_exception)(struct smu_context *smu, 1080 enum smu_feature_mask mask); 1081 1082 /** 1083 * @notify_display_change: General interface call to let SMU know about DC change 1084 */ 1085 int (*notify_display_change)(struct smu_context *smu); 1086 1087 /** 1088 * @set_power_limit: Set power limit in watts. 1089 */ 1090 int (*set_power_limit)(struct smu_context *smu, 1091 enum smu_ppt_limit_type limit_type, 1092 uint32_t limit); 1093 1094 /** 1095 * @init_max_sustainable_clocks: Populate max sustainable clock speed 1096 * table with values from the SMU. 1097 */ 1098 int (*init_max_sustainable_clocks)(struct smu_context *smu); 1099 1100 /** 1101 * @enable_thermal_alert: Enable thermal alert interrupts. 1102 */ 1103 int (*enable_thermal_alert)(struct smu_context *smu); 1104 1105 /** 1106 * @disable_thermal_alert: Disable thermal alert interrupts. 1107 */ 1108 int (*disable_thermal_alert)(struct smu_context *smu); 1109 1110 /** 1111 * @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep 1112 * clock speed in MHz. 1113 */ 1114 int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk); 1115 1116 /** 1117 * @display_clock_voltage_request: Set a hard minimum frequency 1118 * for a clock domain. 1119 */ 1120 int (*display_clock_voltage_request)(struct smu_context *smu, struct 1121 pp_display_clock_request 1122 *clock_req); 1123 1124 /** 1125 * @get_fan_control_mode: Get the current fan control mode. 1126 */ 1127 uint32_t (*get_fan_control_mode)(struct smu_context *smu); 1128 1129 /** 1130 * @set_fan_control_mode: Set the fan control mode. 1131 */ 1132 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode); 1133 1134 /** 1135 * @set_fan_speed_pwm: Set a static fan speed in PWM. 1136 */ 1137 int (*set_fan_speed_pwm)(struct smu_context *smu, uint32_t speed); 1138 1139 /** 1140 * @set_fan_speed_rpm: Set a static fan speed in rpm. 1141 */ 1142 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed); 1143 1144 /** 1145 * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate. 1146 * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise. 1147 */ 1148 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate); 1149 1150 /** 1151 * @gfx_off_control: Enable/disable graphics engine poweroff. 1152 */ 1153 int (*gfx_off_control)(struct smu_context *smu, bool enable); 1154 1155 1156 /** 1157 * @get_gfx_off_status: Get graphics engine poweroff status. 1158 * 1159 * Return: 1160 * 0 - GFXOFF(default). 1161 * 1 - Transition out of GFX State. 1162 * 2 - Not in GFXOFF. 1163 * 3 - Transition into GFXOFF. 1164 */ 1165 uint32_t (*get_gfx_off_status)(struct smu_context *smu); 1166 1167 /** 1168 * @gfx_off_entrycount: total GFXOFF entry count at the time of 1169 * query since system power-up 1170 */ 1171 u32 (*get_gfx_off_entrycount)(struct smu_context *smu, uint64_t *entrycount); 1172 1173 /** 1174 * @set_gfx_off_residency: set 1 to start logging, 0 to stop logging 1175 */ 1176 u32 (*set_gfx_off_residency)(struct smu_context *smu, bool start); 1177 1178 /** 1179 * @get_gfx_off_residency: Average GFXOFF residency % during the logging interval 1180 */ 1181 u32 (*get_gfx_off_residency)(struct smu_context *smu, uint32_t *residency); 1182 1183 /** 1184 * @register_irq_handler: Register interupt request handlers. 1185 */ 1186 int (*register_irq_handler)(struct smu_context *smu); 1187 1188 /** 1189 * @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep. 1190 */ 1191 int (*set_azalia_d3_pme)(struct smu_context *smu); 1192 1193 /** 1194 * @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable 1195 * clock speeds table. 1196 * 1197 * Provides a way for the display component (DC) to get the max 1198 * sustainable clocks from the SMU. 1199 */ 1200 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks); 1201 1202 /** 1203 * @get_bamaco_support: Check if GPU supports BACO/MACO 1204 * BACO: Bus Active, Chip Off 1205 * MACO: Memory Active, Chip Off 1206 */ 1207 int (*get_bamaco_support)(struct smu_context *smu); 1208 1209 /** 1210 * @baco_get_state: Get the current BACO state. 1211 * 1212 * Return: Current BACO state. 1213 */ 1214 enum smu_baco_state (*baco_get_state)(struct smu_context *smu); 1215 1216 /** 1217 * @baco_set_state: Enter/exit BACO. 1218 */ 1219 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state); 1220 1221 /** 1222 * @baco_enter: Enter BACO. 1223 */ 1224 int (*baco_enter)(struct smu_context *smu); 1225 1226 /** 1227 * @baco_exit: Exit Baco. 1228 */ 1229 int (*baco_exit)(struct smu_context *smu); 1230 1231 /** 1232 * @mode1_reset_is_support: Check if GPU supports mode1 reset. 1233 */ 1234 bool (*mode1_reset_is_support)(struct smu_context *smu); 1235 1236 /** 1237 * @link_reset_is_support: Check if GPU supports link reset. 1238 */ 1239 bool (*link_reset_is_support)(struct smu_context *smu); 1240 1241 /** 1242 * @mode1_reset: Perform mode1 reset. 1243 * 1244 * Complete GPU reset. 1245 */ 1246 int (*mode1_reset)(struct smu_context *smu); 1247 1248 /** 1249 * @mode2_reset: Perform mode2 reset. 1250 * 1251 * Mode2 reset generally does not reset as many IPs as mode1 reset. The 1252 * IPs reset varies by asic. 1253 */ 1254 int (*mode2_reset)(struct smu_context *smu); 1255 /* for gfx feature enablement after mode2 reset */ 1256 int (*enable_gfx_features)(struct smu_context *smu); 1257 1258 /** 1259 * @link_reset: Perform link reset. 1260 * 1261 * The gfx device driver reset 1262 */ 1263 int (*link_reset)(struct smu_context *smu); 1264 1265 /** 1266 * @get_dpm_ultimate_freq: Get the hard frequency range of a clock 1267 * domain in MHz. 1268 */ 1269 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); 1270 1271 /** 1272 * @set_soft_freq_limited_range: Set the soft frequency range of a clock 1273 * domain in MHz. 1274 */ 1275 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max, 1276 bool automatic); 1277 1278 /** 1279 * @set_power_source: Notify the SMU of the current power source. 1280 */ 1281 int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src); 1282 1283 /** 1284 * @log_thermal_throttling_event: Print a thermal throttling warning to 1285 * the system's log. 1286 */ 1287 void (*log_thermal_throttling_event)(struct smu_context *smu); 1288 1289 /** 1290 * @get_pp_feature_mask: Print a human readable table of enabled 1291 * features to buffer. 1292 */ 1293 size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf); 1294 1295 /** 1296 * @set_pp_feature_mask: Request the SMU enable/disable features to 1297 * match those enabled in &new_mask. 1298 */ 1299 int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask); 1300 1301 /** 1302 * @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU. 1303 * 1304 * Return: Size of &table 1305 */ 1306 ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table); 1307 1308 /** 1309 * @get_pm_metrics: Get one snapshot of power management metrics from 1310 * PMFW. 1311 * 1312 * Return: Size of the metrics sample 1313 */ 1314 ssize_t (*get_pm_metrics)(struct smu_context *smu, void *pm_metrics, 1315 size_t size); 1316 1317 /** 1318 * @enable_mgpu_fan_boost: Enable multi-GPU fan boost. 1319 */ 1320 int (*enable_mgpu_fan_boost)(struct smu_context *smu); 1321 1322 /** 1323 * @gfx_ulv_control: Enable/disable ultra low voltage. 1324 */ 1325 int (*gfx_ulv_control)(struct smu_context *smu, bool enablement); 1326 1327 /** 1328 * @deep_sleep_control: Enable/disable deep sleep. 1329 */ 1330 int (*deep_sleep_control)(struct smu_context *smu, bool enablement); 1331 1332 /** 1333 * @get_fan_parameters: Get fan parameters. 1334 * 1335 * Get maximum fan speed from the power play table. 1336 */ 1337 int (*get_fan_parameters)(struct smu_context *smu); 1338 1339 /** 1340 * @post_init: Helper function for asic specific workarounds. 1341 */ 1342 int (*post_init)(struct smu_context *smu); 1343 1344 /** 1345 * @interrupt_work: Work task scheduled from SMU interrupt handler. 1346 */ 1347 void (*interrupt_work)(struct smu_context *smu); 1348 1349 /** 1350 * @gpo_control: Enable/disable graphics power optimization if supported. 1351 */ 1352 int (*gpo_control)(struct smu_context *smu, bool enablement); 1353 1354 /** 1355 * @gfx_state_change_set: Send the current graphics state to the SMU. 1356 */ 1357 int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state); 1358 1359 /** 1360 * @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock 1361 * parameters to defaults. 1362 */ 1363 int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu); 1364 1365 /** 1366 * @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR. 1367 */ 1368 int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable); 1369 1370 /** 1371 * @wait_for_event: Wait for events from SMU. 1372 */ 1373 int (*wait_for_event)(struct smu_context *smu, 1374 enum smu_event_type event, uint64_t event_arg); 1375 1376 /** 1377 * @sned_hbm_bad_pages_num: message SMU to update bad page number 1378 * of SMUBUS table. 1379 */ 1380 int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size); 1381 1382 /** 1383 * @send_rma_reason: message rma reason event to SMU. 1384 */ 1385 int (*send_rma_reason)(struct smu_context *smu); 1386 1387 /** 1388 * @reset_sdma: message SMU to soft reset sdma instance. 1389 */ 1390 int (*reset_sdma)(struct smu_context *smu, uint32_t inst_mask); 1391 /** 1392 * @reset_sdma_is_supported: Check if support resets the SDMA engine. 1393 */ 1394 bool (*reset_sdma_is_supported)(struct smu_context *smu); 1395 1396 /** 1397 * @reset_vcn: message SMU to soft reset vcn instance. 1398 */ 1399 int (*dpm_reset_vcn)(struct smu_context *smu, uint32_t inst_mask); 1400 1401 /** 1402 * @get_ecc_table: message SMU to get ECC INFO table. 1403 */ 1404 ssize_t (*get_ecc_info)(struct smu_context *smu, void *table); 1405 1406 1407 /** 1408 * @stb_collect_info: Collects Smart Trace Buffers data. 1409 */ 1410 int (*stb_collect_info)(struct smu_context *smu, void *buf, uint32_t size); 1411 1412 /** 1413 * @get_default_config_table_settings: Get the ASIC default DriverSmuConfig table settings. 1414 */ 1415 int (*get_default_config_table_settings)(struct smu_context *smu, struct config_table_setting *table); 1416 1417 /** 1418 * @set_config_table: Apply the input DriverSmuConfig table settings. 1419 */ 1420 int (*set_config_table)(struct smu_context *smu, struct config_table_setting *table); 1421 1422 /** 1423 * @sned_hbm_bad_channel_flag: message SMU to update bad channel info 1424 * of SMUBUS table. 1425 */ 1426 int (*send_hbm_bad_channel_flag)(struct smu_context *smu, uint32_t size); 1427 1428 /** 1429 * @init_pptable_microcode: Prepare the pptable microcode to upload via PSP 1430 */ 1431 int (*init_pptable_microcode)(struct smu_context *smu); 1432 1433 /** 1434 * @dpm_set_vpe_enable: Enable/disable VPE engine dynamic power 1435 * management. 1436 */ 1437 int (*dpm_set_vpe_enable)(struct smu_context *smu, bool enable); 1438 1439 /** 1440 * @dpm_set_isp_enable: Enable/disable ISP engine dynamic power 1441 * management. 1442 */ 1443 int (*dpm_set_isp_enable)(struct smu_context *smu, bool enable); 1444 1445 /** 1446 * @dpm_set_umsch_mm_enable: Enable/disable UMSCH engine dynamic power 1447 * management. 1448 */ 1449 int (*dpm_set_umsch_mm_enable)(struct smu_context *smu, bool enable); 1450 1451 /** 1452 * @set_mall_enable: Init MALL power gating control. 1453 */ 1454 int (*set_mall_enable)(struct smu_context *smu); 1455 1456 /** 1457 * @notify_rlc_state: Notify RLC power state to SMU. 1458 */ 1459 int (*notify_rlc_state)(struct smu_context *smu, bool en); 1460 1461 /** 1462 * @is_asic_wbrf_supported: check whether PMFW supports the wbrf feature 1463 */ 1464 bool (*is_asic_wbrf_supported)(struct smu_context *smu); 1465 1466 /** 1467 * @enable_uclk_shadow: Enable the uclk shadow feature on wbrf supported 1468 */ 1469 int (*enable_uclk_shadow)(struct smu_context *smu, bool enable); 1470 1471 /** 1472 * @set_wbrf_exclusion_ranges: notify SMU the wifi bands occupied 1473 */ 1474 int (*set_wbrf_exclusion_ranges)(struct smu_context *smu, 1475 struct freq_band_range *exclusion_ranges); 1476 /** 1477 * @get_xcp_metrics: Get a copy of the partition metrics table from SMU. 1478 * Return: Size of table 1479 */ 1480 ssize_t (*get_xcp_metrics)(struct smu_context *smu, int xcp_id, 1481 void *table); 1482 }; 1483 1484 typedef enum { 1485 METRICS_CURR_GFXCLK, 1486 METRICS_CURR_SOCCLK, 1487 METRICS_CURR_UCLK, 1488 METRICS_CURR_VCLK, 1489 METRICS_CURR_VCLK1, 1490 METRICS_CURR_DCLK, 1491 METRICS_CURR_DCLK1, 1492 METRICS_CURR_FCLK, 1493 METRICS_CURR_DCEFCLK, 1494 METRICS_AVERAGE_CPUCLK, 1495 METRICS_AVERAGE_GFXCLK, 1496 METRICS_AVERAGE_SOCCLK, 1497 METRICS_AVERAGE_FCLK, 1498 METRICS_AVERAGE_UCLK, 1499 METRICS_AVERAGE_VCLK, 1500 METRICS_AVERAGE_DCLK, 1501 METRICS_AVERAGE_VCLK1, 1502 METRICS_AVERAGE_DCLK1, 1503 METRICS_AVERAGE_GFXACTIVITY, 1504 METRICS_AVERAGE_MEMACTIVITY, 1505 METRICS_AVERAGE_VCNACTIVITY, 1506 METRICS_AVERAGE_SOCKETPOWER, 1507 METRICS_TEMPERATURE_EDGE, 1508 METRICS_TEMPERATURE_HOTSPOT, 1509 METRICS_TEMPERATURE_MEM, 1510 METRICS_TEMPERATURE_VRGFX, 1511 METRICS_TEMPERATURE_VRSOC, 1512 METRICS_TEMPERATURE_VRMEM, 1513 METRICS_THROTTLER_STATUS, 1514 METRICS_CURR_FANSPEED, 1515 METRICS_VOLTAGE_VDDSOC, 1516 METRICS_VOLTAGE_VDDGFX, 1517 METRICS_SS_APU_SHARE, 1518 METRICS_SS_DGPU_SHARE, 1519 METRICS_UNIQUE_ID_UPPER32, 1520 METRICS_UNIQUE_ID_LOWER32, 1521 METRICS_PCIE_RATE, 1522 METRICS_PCIE_WIDTH, 1523 METRICS_CURR_FANPWM, 1524 METRICS_CURR_SOCKETPOWER, 1525 METRICS_AVERAGE_VPECLK, 1526 METRICS_AVERAGE_IPUCLK, 1527 METRICS_AVERAGE_MPIPUCLK, 1528 METRICS_THROTTLER_RESIDENCY_PROCHOT, 1529 METRICS_THROTTLER_RESIDENCY_SPL, 1530 METRICS_THROTTLER_RESIDENCY_FPPT, 1531 METRICS_THROTTLER_RESIDENCY_SPPT, 1532 METRICS_THROTTLER_RESIDENCY_THM_CORE, 1533 METRICS_THROTTLER_RESIDENCY_THM_GFX, 1534 METRICS_THROTTLER_RESIDENCY_THM_SOC, 1535 } MetricsMember_t; 1536 1537 enum smu_cmn2asic_mapping_type { 1538 CMN2ASIC_MAPPING_MSG, 1539 CMN2ASIC_MAPPING_CLK, 1540 CMN2ASIC_MAPPING_FEATURE, 1541 CMN2ASIC_MAPPING_TABLE, 1542 CMN2ASIC_MAPPING_PWR, 1543 CMN2ASIC_MAPPING_WORKLOAD, 1544 }; 1545 1546 enum smu_baco_seq { 1547 BACO_SEQ_BACO = 0, 1548 BACO_SEQ_MSR, 1549 BACO_SEQ_BAMACO, 1550 BACO_SEQ_ULPS, 1551 BACO_SEQ_COUNT, 1552 }; 1553 1554 #define MSG_MAP(msg, index, flags) \ 1555 [SMU_MSG_##msg] = {1, (index), (flags)} 1556 1557 #define CLK_MAP(clk, index) \ 1558 [SMU_##clk] = {1, (index)} 1559 1560 #define FEA_MAP(fea) \ 1561 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT} 1562 1563 #define FEA_MAP_REVERSE(fea) \ 1564 [SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1565 1566 #define FEA_MAP_HALF_REVERSE(fea) \ 1567 [SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1568 1569 #define TAB_MAP(tab) \ 1570 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1571 1572 #define TAB_MAP_VALID(tab) \ 1573 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1574 1575 #define TAB_MAP_INVALID(tab) \ 1576 [SMU_TABLE_##tab] = {0, TABLE_##tab} 1577 1578 #define PWR_MAP(tab) \ 1579 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab} 1580 1581 #define WORKLOAD_MAP(profile, workload) \ 1582 [profile] = {1, (workload)} 1583 1584 /** 1585 * smu_memcpy_trailing - Copy the end of one structure into the middle of another 1586 * 1587 * @dst: Pointer to destination struct 1588 * @first_dst_member: The member name in @dst where the overwrite begins 1589 * @last_dst_member: The member name in @dst where the overwrite ends after 1590 * @src: Pointer to the source struct 1591 * @first_src_member: The member name in @src where the copy begins 1592 * 1593 */ 1594 #define smu_memcpy_trailing(dst, first_dst_member, last_dst_member, \ 1595 src, first_src_member) \ 1596 ({ \ 1597 size_t __src_offset = offsetof(typeof(*(src)), first_src_member); \ 1598 size_t __src_size = sizeof(*(src)) - __src_offset; \ 1599 size_t __dst_offset = offsetof(typeof(*(dst)), first_dst_member); \ 1600 size_t __dst_size = offsetofend(typeof(*(dst)), last_dst_member) - \ 1601 __dst_offset; \ 1602 BUILD_BUG_ON(__src_size != __dst_size); \ 1603 __builtin_memcpy((u8 *)(dst) + __dst_offset, \ 1604 (u8 *)(src) + __src_offset, \ 1605 __dst_size); \ 1606 }) 1607 1608 typedef struct { 1609 uint16_t LowFreq; 1610 uint16_t HighFreq; 1611 } WifiOneBand_t; 1612 1613 typedef struct { 1614 uint32_t WifiBandEntryNum; 1615 WifiOneBand_t WifiBandEntry[11]; 1616 uint32_t MmHubPadding[8]; 1617 } WifiBandEntryTable_t; 1618 1619 #define STR_SOC_PSTATE_POLICY "soc_pstate" 1620 #define STR_XGMI_PLPD_POLICY "xgmi_plpd" 1621 1622 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 1623 enum pp_pm_policy p_type); 1624 1625 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4) 1626 int smu_get_power_limit(void *handle, 1627 uint32_t *limit, 1628 enum pp_power_limit_level pp_limit_level, 1629 enum pp_power_type pp_power_type); 1630 1631 bool smu_mode1_reset_is_support(struct smu_context *smu); 1632 bool smu_link_reset_is_support(struct smu_context *smu); 1633 int smu_mode1_reset(struct smu_context *smu); 1634 int smu_link_reset(struct smu_context *smu); 1635 1636 extern const struct amd_ip_funcs smu_ip_funcs; 1637 1638 bool is_support_sw_smu(struct amdgpu_device *adev); 1639 bool is_support_cclk_dpm(struct amdgpu_device *adev); 1640 int smu_write_watermarks_table(struct smu_context *smu); 1641 1642 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1643 uint32_t *min, uint32_t *max); 1644 1645 int smu_set_soft_freq_range(struct smu_context *smu, enum pp_clock_type clk_type, 1646 uint32_t min, uint32_t max); 1647 1648 int smu_set_gfx_power_up_by_imu(struct smu_context *smu); 1649 1650 int smu_set_ac_dc(struct smu_context *smu); 1651 1652 int smu_set_xgmi_plpd_mode(struct smu_context *smu, 1653 enum pp_xgmi_plpd_mode mode); 1654 1655 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value); 1656 1657 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value); 1658 1659 int smu_set_residency_gfxoff(struct smu_context *smu, bool value); 1660 1661 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value); 1662 1663 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable); 1664 1665 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 1666 uint64_t event_arg); 1667 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc); 1668 int smu_stb_collect_info(struct smu_context *smu, void *buff, uint32_t size); 1669 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev); 1670 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size); 1671 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size); 1672 int smu_send_rma_reason(struct smu_context *smu); 1673 int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask); 1674 bool smu_reset_sdma_is_supported(struct smu_context *smu); 1675 int smu_reset_vcn(struct smu_context *smu, uint32_t inst_mask); 1676 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 1677 int level); 1678 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 1679 enum pp_pm_policy p_type, char *sysbuf); 1680 1681 #endif 1682 #endif 1683