1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* Copyright 2015 QLogic Corporation */ 23 24 /* 25 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 26 */ 27 28 #ifndef _QL_MBX_H 29 #define _QL_MBX_H 30 31 /* 32 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file. 33 * 34 * *********************************************************************** 35 * * ** 36 * * NOTICE ** 37 * * COPYRIGHT (C) 1996-2015 QLOGIC CORPORATION ** 38 * * ALL RIGHTS RESERVED ** 39 * * ** 40 * *********************************************************************** 41 * 42 */ 43 44 #ifdef __cplusplus 45 extern "C" { 46 #endif 47 48 /* 49 * ISP mailbox Self-Test status codes 50 */ 51 #define MBS_ROM_IDLE 0 /* Firmware Alive. */ 52 #define MBS_ROM_CHKSUM_ERR 1 /* Checksum Error. */ 53 #define MBS_ROM_BUSY 4 /* Busy. */ 54 #define MBS_ROM_CONFIG_ERR 0xF /* Board Config Error. */ 55 #define MBS_ROM_STATUS_MASK 0xF 56 57 #define MBS_ROM_FW_RUNNING 0x8400 /* firmware running. */ 58 #define MBS_ROM_FW_CONFIG_ERR 0x8401 /* firmware config error */ 59 60 /* 61 * ISP mailbox command complete status codes 62 */ 63 #define MBS_COMMAND_COMPLETE 0x4000 64 #define MBS_INVALID_COMMAND 0x4001 65 #define MBS_HOST_INTERFACE_ERROR 0x4002 66 #define MBS_TEST_FAILED 0x4003 67 #define MBS_POST_ERROR 0x4004 68 #define MBS_COMMAND_ERROR 0x4005 69 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 70 #define MBS_PORT_ID_USED 0x4007 71 #define MBS_LOOP_ID_USED 0x4008 72 #define MBS_ALL_IDS_IN_USE 0x4009 73 #define MBS_NOT_LOGGED_IN 0x400A 74 #define MBS_LOOP_DOWN 0x400B 75 #define MBS_LOOP_BACK_ERROR 0x400C 76 #define MBS_CHECKSUM_ERROR 0x4010 77 78 /* 79 * Sub-error Codes for Mailbox Command Completion Status Code 4005h 80 */ 81 #define MBSS_NO_LINK 0x0001 82 #define MBSS_IOCB_ALLOC_ERR 0x0002 83 #define MBSS_ECB_ALLOC_ERR 0x0003 84 #define MBSS_CMD_FAILURE 0x0004 85 #define MBSS_NO_FABRIC 0x0005 86 #define MBSS_FIRMWARE_NOT_RDY 0x0007 87 #define MBSS_INITIATOR_DISABLED 0x0008 88 #define MBSS_NOT_LOGGED_IN 0x0009 89 #define MBSS_PARTIAL_DATA_XFER 0x000A 90 #define MBSS_TOPOLOGY_ERR 0x0016 91 #define MBSS_CHIP_RESET_NEEDED 0x0017 92 #define MBSS_MULTIPLE_OPEN_EXCH 0x0018 93 #define MBSS_IOCB_COUNT_ERR 0x0019 94 #define MBSS_CMD_AFTER_FW_INIT_ERR 0x001A 95 #define MBSS_NO_VIRTUAL_PORT_ID 0x001B 96 #define MBSS_INVALID_FCF_INDEX 0x0022 97 #define MBSS_MPI_PROCESSOR_ERR 0x0023 98 #define MBSS_SEMAPHORE_ERR 0x0024 99 #define MBSS_RANGE_ERR 0x0025 100 #define MBSS_TRANSFER_SIZE_TO_LARGE 0x0026 101 #define MBSS_CHECKSUM_ERR 0x0027 102 #define MBSS_CONFIGURATION_ERR 0x0028 103 104 /* 105 * ISP mailbox asynchronous event status codes 106 */ 107 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 108 #define MBA_RESET 0x8001 /* Reset Detected. */ 109 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 110 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 111 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 112 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 113 #define MBA_MENLO_ALERT 0x800f /* Menlo Alert Notification. */ 114 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 115 /* occurred. */ 116 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 117 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 118 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 119 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 120 #define MBA_RSCN_UPDATE 0x8015 /* State Change Registration. */ 121 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 122 #define MBA_LIP_ERROR 0x8017 /* Loop initialization errors. */ 123 #define MBA_LOGIN_REJECT 0x8018 /* Login Reject Reason. */ 124 #define MBA_SECURITY_UPDATE 0x801B /* FC-SP security update. */ 125 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 126 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 127 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 128 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 129 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 130 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 131 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 132 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 133 /* used. */ 134 #define MBA_ERROR_LOGGING_DISABLED 0x8029 /* Error Logging Disabled. */ 135 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 136 #define MBA_DCBX_COMPLETED 0x8030 /* DCBX completed. */ 137 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 138 #define MBA_FCF_CONFIG_ERROR 0x8031 /* FCF configuration error. */ 139 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 140 #define MBA_DCBX_PARAM_CHANGED 0x8032 /* DCBX parameters changed. */ 141 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 142 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 143 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 144 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 145 #define MBA_ZIO_UPDATE 0x8040 /* ZIO response queue update. */ 146 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 147 #define MBA_PORT_BYPASS_CHANGED 0x8043 /* Crystal+ port#0 bypass transition */ 148 #define MBA_RECEIVE_ERROR 0x8048 /* Receive Error */ 149 #define MBA_LS_RJT_SENT 0x8049 /* LS_RJT response sent */ 150 #define MBA_QUEUE_FULL 0x8049 /* Queue full */ 151 #define MBA_CLASS_2_RJT 0x804F /* Class 2 RJT sent */ 152 #define MBA_VDC_MESSAGE 0x805F /* VDC message event */ 153 #define MBA_FW_RESTART_COMP 0x8060 /* Firmware Restart Complete. */ 154 #define MBA_TEMPERATURE_EVENT 0x8070 /* Temperature event. */ 155 #define MBA_D_PORT_DIAGS 0x8080 /* D_Port Diagnostics. */ 156 #define MBA_IDC_COMPLETE 0x8100 /* Inter-driver communication */ 157 /* complete. */ 158 #define MBA_IDC_NOTIFICATION 0x8101 /* Inter-driver communication */ 159 /* notification. */ 160 #define MBA_IDC_TIME_EXTENDED 0x8102 /* Inter-driver communication */ 161 /* time extended. */ 162 #define MBA_SFP_INSERTION 0x8130 /* Transceiver insertion */ 163 #define MBA_SFP_REMOVAL 0x8131 /* Transceiver removal */ 164 #define MBA_NIC_STATE_CHANGE 0x8200 /* NIC Firmware State Change */ 165 #define MBA_AUTO_FW_INIT_COMP 0x8400 /* Autoload fw init complete. */ 166 #define MBA_AUTO_FW_INIT_ERR 0x8401 /* Autoload fw init failure. */ 167 168 /* Driver defined. */ 169 #define MBA_CMPLT_1_32BIT 0x9000 /* Completion 1 32bit IOSB. */ 170 /* 171 * Mailbox 23 event codes 172 */ 173 #define MBX23_MBX_OR_ASYNC_EVENT 0x0 174 #define MBX23_RESPONSE_QUEUE_UPDATE 0x1 175 #define MBX23_SCSI_COMPLETION 0x2 176 177 /* 178 * System Error event (0x8002) defines 179 */ 180 #define SE_NIC_HEARTHBEAT BIT_3 181 #define SE_MPI_RISC BIT_2 182 #define SE_NIC_1 BIT_1 183 #define SE_NIC_2 BIT_0 184 185 /* 186 * Port Database Update event (0x8014) defines 187 */ 188 #define PDU_GLOBAL_EVENT 0xffff 189 /* 190 * Port Database Update event (0x8014) login states 191 */ 192 #define PDU_PLOGI_COMPLETE 0x4 193 #define PDU_PRLI_COMPLETE 0x6 194 #define PDU_PORT_LOGOUT 0x7 195 /* 196 * Port Database Update event (0x8014) reason codes 197 */ 198 #define PDU_LINK_INITIALIZED 0x0 199 #define PDU_ADISC_ACC_CONFLICT 0x1 200 #define PDU_ADISC_REJECT 0x2 201 #define PDU_ADISC_REQ_CONFLICT 0x3 202 #define PDU_PLOGI_RECEIVED 0x4 203 #define PDU_PLOGI_REJECT 0x5 204 #define PDU_PRLI_RECEIVED 0x6 205 #define PDU_PRLI_REJECT 0x7 206 #define PDU_GLOBAL_TPRLO 0x8 207 #define PDU_SELECTIVE_TPRLO 0x9 208 #define PDU_PRLO_RECEIVED 0xa 209 #define PDU_LOGO_RECEIVED 0xb 210 #define PDU_TOPOLOGY_CHANGE 0xc 211 #define PDU_N_PORT_ID_CHANGE 0xd 212 #define PDU_FLOGI_REJECT 0xe 213 #define PDU_BAD_FAN 0xf 214 #define PDU_FLOGI_TIMEOUT 0x10 215 #define PDU_ABTS_LOGO_FAILED 0x11 216 #define PDU_PLOGI_COMPLETED 0x12 217 #define PDU_PRLI_COMPLETED 0x13 218 #define PDU_OWN_OPN_FRAME_PATH 0x14 219 #define PDU_OWN_OPN_DATA_PATH 0x15 220 #define PDU_TRANSMIT_ERROR 0x16 221 #define PDU_EXPLICIT_LOGO_REQ 0x17 222 #define PDU_ADISC_REQ_TIMEOUT 0x18 223 #define PDU_EVFP_RECEIVED 0x19 224 #define PDU_SW_LOGO_RECEIVED 0x1a 225 #define PDU_FCF_LIST_CHANGED 0x1b 226 #define PDU_FCF_CONFIG_CHANGED 0x1c 227 #define PDU_FIP_RECEIVED 0x1d 228 #define PDU_FCF_TIMEOUT 0x1e 229 230 /* 231 * Registered State Change Notification (0x8015) defines 232 */ 233 #define RSCN_AF_PORT 0x0 234 #define RSCN_AF_AREA 0x1 235 #define RSCN_AF_DOMAIN 0x2 236 #define RSCN_AF_FABRIC 0x3 237 #define RSCN_AF_MASK (BIT_1 | BIT_0) 238 239 /* 240 * Temperature alert event (0x8070) defines 241 */ 242 #define TCA_INVALID_CONFIGURATION 0x10 243 #define TCA_INVALID_NUMBER_OF_SENSORS 0x11 244 #define TCA_SHUTDOWN_INITIATED 0x12 245 #define TCA_SENSOR_NOT_FUNCTIONAL 0x13 246 247 /* 248 * Thermal temperature defines 249 */ 250 #define READ_ASIC_TEMP 0xC 251 #define TEMP_SUPPORT_I2C BIT_0 252 #define TEMP_SUPPORT_ISP BIT_1 253 254 /* 255 * D_Port Diagnostic event (0x8080) defines 256 */ 257 #define DPA_START 0 258 #define DPA_DONE 1 259 #define DPA_ERROR 2 260 #define DPA_MASK 0xF 261 262 /* 263 * Menlo alert event defines 264 */ 265 #define MLA_PANIC_RECOVERY 0x1 266 #define MLA_LOGIN_OPERATIONAL_FW 0x2 267 #define MLA_LOGIN_DIAGNOSTIC_FW 0x3 268 #define MLA_LOGIN_GOLDEN_FW 0x4 269 #define MLA_REJECT_RESPONSE 0x5 270 271 /* 272 * ISP mailbox commands 273 */ 274 #define MBC_LOAD_RAM 1 /* Load RAM. */ 275 #define MBC_WRITE_REMOTE_REG 1 /* Write remote register. */ 276 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 277 #define MBC_DUMP_RAM 3 /* Dump RAM. */ 278 #define MBC_LOAD_FLASH_IMAGE 3 /* Load flash image. */ 279 #define MBC_WRITE_SERDES_REG 3 /* Write FC serdes register */ 280 #define MBC_READ_SERDES_REG 4 /* Read FC serdes registers */ 281 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */ 282 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 283 #define MBC_MPI_RAM 5 /* Load/dump MPI RAM. */ 284 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 285 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 286 #define MBC_ABOUT_FIRMWARE 8 /* About Firmware. */ 287 #define MBC_LOAD_RISC_RAM 9 /* Load RSIC RAM. */ 288 #define MBC_READ_REMOTE_REG 9 /* Read remote register. */ 289 #define MBC_DUMP_RISC_RAM 0xa /* Dump RISC RAM command. */ 290 #define MBC_LOAD_RAM_EXTENDED 0xb /* Load RAM extended. */ 291 #define MBC_DUMP_RAM_EXTENDED 0xc /* Dump RAM extended. */ 292 #define MBC_WRITE_RAM_EXTENDED 0xd /* Write RAM word. */ 293 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 294 #define MBC_SERDES_TRANSMIT_PARAMETERS 0x10 /* Serdes Xmit Parameters */ 295 #define MBC_TOGGLE_INTERRUPT 0x10 /* 82XX enable/disable intr */ 296 #define MBC_2300_EXECUTE_IOCB 0x12 /* ISP2300 Execute IOCB cmd */ 297 #define MBC_GET_IO_STATUS 0x12 /* ISP2422 Get I/O Status */ 298 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware */ 299 #define MBC_ABORT_COMMAND_IOCB 0x15 /* Abort IOCB command. */ 300 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 301 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 302 #define MBC_RESET 0x18 /* Target reset. */ 303 #define MBC_XMIT_PARM 0x19 /* Change default xmit parms */ 304 #define MBC_PORT_PARAM 0x1a /* Get/set port speed parms */ 305 #define MBC_INIT_MULTIPLE_QUEUE 0x1f /* Initialize Multiple Queue */ 306 #define MBC_GET_ID 0x20 /* Get loop id of ISP2200. */ 307 #define MBC_GET_TIMEOUT_PARAMETERS 0x22 /* Get Timeout Parameters. */ 308 #define MBC_TRACE_CONTROL 0x27 /* Trace control. */ 309 #define MBC_GET_FIRMWARE_OPTIONS 0x28 /* Get firmware options */ 310 #define MBC_READ_SFP 0x31 /* Read SFP. */ 311 #define MBC_SET_FIRMWARE_OPTIONS 0x38 /* set firmware options */ 312 #define MBC_RESET_MENLO 0x3a /* Reset Menlo. */ 313 #define MBC_FC_LED_CONFIG 0x3b /* Set/Get FC LED Config */ 314 #define MBC_RESTART_MPI 0x3d /* Restart MPI. */ 315 #define MBC_FLASH_ACCESS 0x3e /* Flash Access Control */ 316 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 317 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 318 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 319 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 320 #define MBC_ECHO 0x44 /* ELS ECHO */ 321 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 322 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 323 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get Port Database + login */ 324 #define MBC_INITIALIZE_MULTI_ID_FW 0x48 /* Initialize multi-id fw */ 325 #define MBC_GET_FCF_LIST 0x50 /* Get FCF List */ 326 #define MBC_GET_DCBX_PARAMS 0x51 /* Get DCBX parameters */ 327 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 328 #define MBC_EXECUTE_IOCB 0x54 /* 64 Bit Execute IOCB cmd. */ 329 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 330 #define MBC_SET_PARAMETERS 0x59 /* Set RNID parameters */ 331 #define MBC_GET_PARAMETERS 0x5a /* Get RNID parameters */ 332 #define MBC_DATA_RATE 0x5d /* Data Rate */ 333 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 334 #define MBC_INITIATE_LIP 0x62 /* Initiate LIP */ 335 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 336 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 337 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 338 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 339 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 340 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 341 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 342 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 343 #define MBC_GET_LINK_STATUS 0x6b /* Get Link Status. */ 344 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 345 #define MBC_GET_STATUS_COUNTS 0x6d /* Get Link Statistics and */ 346 /* Private Data Counts */ 347 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 348 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 349 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 350 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 351 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 352 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 353 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list */ 354 #define MBC_INITIALIZE_IP 0x77 /* Initialize IP */ 355 #define MBC_SEND_FARP_REQ_COMMAND 0x78 /* FARP request. */ 356 #define MBC_UNLOAD_IP 0x79 /* Unload IP */ 357 #define MBC_GET_XGMAC_STATS 0x7a /* Get XGMAC Statistics. */ 358 #define MBC_GET_ID_LIST 0x7c /* Get port ID list. */ 359 #define MBC_SEND_LFA_COMMAND 0x7d /* Send Loop Fabric Address */ 360 #define MBC_LUN_RESET 0x7e /* Send Task mgmt LUN reset */ 361 #define MBC_IDC_REQUEST 0x100 /* IDC request */ 362 #define MBC_IDC_ACK 0x101 /* IDC acknowledge */ 363 #define MBC_IDC_TIME_EXTEND 0x102 /* IDC extend time */ 364 #define MBC_PORT_RESET 0x120 /* Port Reset */ 365 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 366 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 367 #define MBC_SET_LED_CONFIG 0x125 /* Beaconing set led config */ 368 #define MBC_GET_LED_CONFIG 0x126 /* Get led config */ 369 #define MBC_GET_MD_TEMPLATE 0x129 /* Get mini dump template */ 370 371 /* 372 * Mbc 0x100 (IDC request) 373 */ 374 /* Timeout Value */ 375 #define IDC_TIMEOUT_POS 8 376 #define IDC_TIMEOUT_MASK (BIT_11 | BIT_10 | BIT_9 | BIT_8) 377 378 /* Function Destination Selector */ 379 #define IDC_FUNC_DST_MASK (BIT_5 | BIT_4) 380 #define IDC_FUNC_DST_MBX3 0 381 #define IDC_FUNC_DST_SP 0x10 382 383 /* Function Source */ 384 #define IDC_FUNC_SRC_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0) 385 386 /* Information opcode */ 387 #define IDC_OPC_DRV_START 0x100 388 #define IDC_OPC_FLASH_ACC 0x101 389 #define IDC_OPC_RESTART_MPI 0x102 390 #define IDC_OPC_PORT_RESET_MBC 0x120 391 #define IDC_OPC_SET_PORT_CONFIG_MBC 0x122 392 393 /* Function Destination Mask */ 394 #define IDC_FUNC_3 BIT_3 395 #define IDC_FUNC_2 BIT_2 396 #define IDC_FUNC_1 BIT_1 397 #define IDC_FUNC_0 BIT_0 398 #define IDC_FC_FUNC (BIT_3 | BIT_2) 399 #define IDC_NIC_FUNC (BIT_1 | BIT_0) 400 #define IDC_ALL_FUNC (IDC_FC_FUNC | IDC_NIC_FUNC) 401 402 /* Requestor Id Function Type */ 403 #define IDC_RIT_MASK (BIT_6 | BIT_5 | BIT_4) 404 #define IDC_RIT_NIC 0 405 #define IDC_RIT_FC 0x10 406 407 /* Requestor Id Originator */ 408 #define IDC_RIO_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0) 409 #define IDC_RIO_DRV 0 410 #define IDC_RIO_FW 1 411 #define IDC_RIO_MPI 2 412 #define IDC_RIO_DRV_APP 3 413 #define IDC_RIO_QL_APP 4 414 #define IDC_RIO_QL_MFG 5 415 #define IDC_RIO_OTH_APP 6 416 417 /* Region Code */ 418 #define IDC_RC_POS 8 419 #define IDC_RC_MASK 0xFF00 420 421 /* Region Size in 64k blocks */ 422 #define IDC_RS_POS 0 423 #define IDC_RS_MASK 0xFF 424 425 /* Message Source */ 426 #define IDC_MSG_QLGC BIT_15 427 428 /* Message Subcode */ 429 #define IDC_MS_MASK (BIT_7 | BIT_6 | BIT_5 | BIT_4) 430 #define IDC_MS_NONE 0x00 431 #define IDC_MS_READ 0x10 432 #define IDC_MS_WRITE 0x20 433 #define IDC_MS_ERASE 0x30 434 435 /* Marker */ 436 #define IDC_MM_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0) 437 #define IDC_MM_NONE 0x0 438 #define IDC_MM_BEG 0x1 439 #define IDC_MM_END 0x2 440 #define IDC_MM_WIP 0x3 441 #define IDC_MM_ABORT 0x4 442 443 /* 444 * Mbc 0x3e (Flash Access Control) 445 */ 446 #define FAC_FORCE_SEMA_LOCK BIT_15 447 #define FAC_APPL_ID BIT_14 448 #define FAC_WRT_PROTECT 0 449 #define FAC_WRT_ENABLE 1 450 #define FAC_ERASE_SECTOR 2 451 #define FAC_SEMA_LOCK 3 452 #define FAC_SEMA_UNLOCK 4 453 #define FAC_GET_SECTOR_SIZE 5 454 #define FAC_ADDR_MASK 0x3fff 455 456 /* 457 * MBC_DIAGNOSTIC_LOOP_BACK 458 */ 459 #define MBC_LOOPBACK_POINT_MASK 0x07 460 #define MBC_LOOPBACK_POINT_10BIT 0x00 /* 2425xx */ 461 #define MBC_LOOPBACK_POINT_1BIT 0x01 /* 2425xx */ 462 #define MBC_LOOPBACK_POINT_INTERNAL 0x01 /* 81xx */ 463 #define MBC_LOOPBACK_POINT_EXTERNAL 0x02 /* 242581xx */ 464 #define MBC_LOOPBACK_64BIT BIT_6 /* 2200 0r 2300 */ 465 466 /* 467 * MBC_ECHO 468 */ 469 #define MBC_ECHO_ELS BIT_15 /* echo ELS */ 470 #define MBC_ECHO_64BIT BIT_6 /* 64bit DMA address used */ 471 472 /* 473 * 81xx, 83xx 474 * MBC_SET_PORT_CONFIG 475 * MBC_GET_PORT_CONFIG 476 */ 477 #define LOOPBACK_MODE_FIELD_MASK 0xE 478 #define LOOPBACK_MODE_NONE 0x00 479 #define LOOPBACK_MODE_INTERNAL 0x04 480 #define LOOPBACK_MODE_EXTERNAL 0x08 /* 8031 */ 481 482 /* 483 * Mbc 20h (Get ID) returns the switch capabilities in mailbox7. 484 * The extra bits were added with 4.00.28 MID firmware. 485 */ 486 #define GID_TOP_NL_PORT 0 487 #define GID_TOP_FL_PORT 1 488 #define GID_TOP_N_PORT 2 489 #define GID_TOP_F_PORT 3 490 #define GID_TOP_N_PORT_NO_TGT 4 491 492 #define GID_FP_IN_ORDER BIT_8 493 #define GID_FP_MAC_ADDR BIT_9 494 #define GID_FP_NPIV_SUPPORT BIT_10 /* implies FDISC support */ 495 #define GID_FP_VF_SUPPORT BIT_12 496 #define GID_FP_SP_SUPPORT BIT_13 497 #define GID_FP_FA_WWPN BIT_14 498 499 /* 500 * Mbc 20h (Get ID) returns the Buffer to Buffer Credits in mailbox15. 501 */ 502 #define BBCR_INITIAL_MASK 0xf 503 #define BBCR_RUNTIME_MASK 0xf 504 #define BBCR_RUNTIME_REJECT BIT_4 505 506 /* 507 * Driver Mailbox command definitions. 508 */ 509 #define MAILBOX_TOV 30 /* Default Timeout value. */ 510 511 /* Mailbox command parameter structure definition. */ 512 typedef struct mbx_cmd { 513 uint32_t out_mb; /* Outgoing from driver */ 514 uint32_t in_mb; /* Incomming from RISC */ 515 uint16_t mb[MAX_MBOX_COUNT]; 516 clock_t timeout; /* Timeout in seconds. */ 517 } mbx_cmd_t; 518 519 /* Mailbox bit definitions for out_mb and in_mb */ 520 #define MBX_29 BIT_29 521 #define MBX_28 BIT_28 522 #define MBX_27 BIT_27 523 #define MBX_26 BIT_26 524 #define MBX_25 BIT_25 525 #define MBX_24 BIT_24 526 #define MBX_23 BIT_23 527 #define MBX_22 BIT_22 528 #define MBX_21 BIT_21 529 #define MBX_20 BIT_20 530 #define MBX_19 BIT_19 531 #define MBX_18 BIT_18 532 #define MBX_17 BIT_17 533 #define MBX_16 BIT_16 534 #define MBX_15 BIT_15 535 #define MBX_14 BIT_14 536 #define MBX_13 BIT_13 537 #define MBX_12 BIT_12 538 #define MBX_11 BIT_11 539 #define MBX_10 BIT_10 540 #define MBX_9 BIT_9 541 #define MBX_8 BIT_8 542 #define MBX_7 BIT_7 543 #define MBX_6 BIT_6 544 #define MBX_5 BIT_5 545 #define MBX_4 BIT_4 546 #define MBX_3 BIT_3 547 #define MBX_2 BIT_2 548 #define MBX_1 BIT_1 549 #define MBX_0 BIT_0 550 551 #define MBX_0_THRU_1 MBX_0|MBX_1 552 #define MBX_0_THRU_2 MBX_0_THRU_1 | MBX_2 553 #define MBX_0_THRU_3 MBX_0_THRU_2 | MBX_3 554 #define MBX_0_THRU_4 MBX_0_THRU_3 | MBX_4 555 #define MBX_0_THRU_5 MBX_0_THRU_4 | MBX_5 556 #define MBX_0_THRU_6 MBX_0_THRU_5 | MBX_6 557 #define MBX_0_THRU_7 MBX_0_THRU_6 | MBX_7 558 #define MBX_0_THRU_8 MBX_0_THRU_7 | MBX_8 559 #define MBX_0_THRU_9 MBX_0_THRU_8 | MBX_9 560 #define MBX_0_THRU_10 MBX_0_THRU_9 | MBX_10 561 #define MBX_0_THRU_11 MBX_0_THRU_10 | MBX_11 562 #define MBX_0_THRU_12 MBX_0_THRU_11 | MBX_12 563 #define MBX_0_THRU_13 MBX_0_THRU_12 | MBX_13 564 #define MBX_0_THRU_14 MBX_0_THRU_13 | MBX_14 565 #define MBX_0_THRU_15 MBX_0_THRU_14 | MBX_15 566 #define MBX_0_THRU_16 MBX_0_THRU_15 | MBX_16 567 #define MBX_0_THRU_17 MBX_0_THRU_16 | MBX_17 568 #define MBX_0_THRU_18 MBX_0_THRU_17 | MBX_18 569 #define MBX_0_THRU_19 MBX_0_THRU_18 | MBX_19 570 #define MBX_0_THRU_20 MBX_0_THRU_19 | MBX_20 571 #define MBX_0_THRU_21 MBX_0_THRU_20 | MBX_21 572 #define MBX_0_THRU_22 MBX_0_THRU_21 | MBX_22 573 #define MBX_0_THRU_23 MBX_0_THRU_22 | MBX_23 574 #define MBX_0_THRU_24 MBX_0_THRU_23 | MBX_24 /* not supported by 2200 */ 575 #define MBX_0_THRU_25 MBX_0_THRU_24 | MBX_25 /* not supported by 2200 */ 576 577 /* 578 * Firmware state codes from get firmware state mailbox command 579 */ 580 #define FSTATE_CONFIG_WAIT 0 581 #define FSTATE_WAIT_AL_PA 1 582 #define FSTATE_WAIT_LOGIN 2 583 #define FSTATE_READY 3 584 #define FSTATE_LOSS_SYNC 4 585 #define FSTATE_ERROR 5 586 #define FSTATE_NON_PART 7 587 #define FSTATE_MPI_NIC_ERROR 0x10 588 589 /* 590 * Firmware options 1, 2, 3. 591 */ 592 #define FO1_AE_ON_LIPF8 BIT_0 593 #define FO1_AE_ALL_LIP_RESET BIT_1 594 #define FO1_CTIO_RETRY BIT_3 595 #define FO1_DISABLE_LIP_F7_SW BIT_4 596 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 597 #define FO1_DISABLE_GPIO BIT_6 598 #define FO1_DISABLE_LEDS BIT_6 599 #define FO1_AE_AUTO_BYPASS BIT_9 600 #define FO1_ENABLE_PURE_IOCB BIT_10 601 #define FO1_AE_PLOGI_RJT BIT_11 602 #define FO1_AE_IMMEDIATE_NOTIFY_IOCB BIT_11 603 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 604 #define FO1_AE_QUEUE_FULL BIT_13 605 #define FO1_POST_NOTIFY_ACK_IOCB_2_ATIO BIT_13 606 #define FO1_POST_NOTIFY_ACK_IOCB BIT_14 607 608 #define FO2_ENABLE_FIBRE_LITE BIT_13 609 #define FO2_FCOE_512_MAX_MEM_WR_BURST BIT_9 610 #define FO2_ENABLE_SELECTIVE_CLASS_2 BIT_5 611 #define FO2_REV_LOOPBACK BIT_1 612 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 613 614 #define FO3_NO_ABORT_IO_ON_LINK_DOWN BIT_14 615 #define FO3_HOLD_STS_FOR_ABTS_RSP BIT_12 616 #define FO3_STARTUP_OPTS_VALID BIT_5 617 #define FO3_SEND_N2N_PRLI BIT_4 618 #define FO3_AE_RND_ERROR BIT_1 619 #define FO3_ENABLE_EMERG_IOCB BIT_0 620 621 #define FO13_LESB_NO_RESET BIT_0 622 623 /* 624 * f/w trace opcodes - mailbox 1(bits 7-0) 625 */ 626 #define FTO_INSERT_TIME_STAMP 1 627 #define FTO_RESERVED_2 2 628 #define FTO_RESERVED_3 3 629 #define FTO_EXT_TRACE_ENABLE 4 630 #define FTO_EXT_TRACE_DISABLE 5 631 #define FTO_FCE_TRACE_ENABLE 8 632 #define FTO_FCE_TRACE_DISABLE 9 633 #define FTO_FCEMAXTRACEBUF 0x840 /* max frame size */ 634 635 /* 636 * fw version 1 attributes defines from firmware version mailbox command 637 */ 638 #define FWATTRIB_EF 0x7 639 #define FWATTRIB_TP 0x17 640 #define FWATTRIB_IP 0x37 641 #define FWATTRIB_TPX 0x117 642 #define FWATTRIB_IPX 0x137 643 #define FWATTRIB_FL 0x217 644 #define FWATTRIB_FPX 0x317 645 646 /* 647 * fw version 2 attributes defines 648 */ 649 #define FWATTRIB2_CLASS2 BIT_0 650 #define FWATTRIB2_IP BIT_1 651 #define FWATTRIB2_MID BIT_2 652 #define FWATTRIB2_SB2 BIT_3 653 #define FWATTRIB2_T10_CRC BIT_4 654 #define FWATTRIB2_VI BIT_5 655 #define FWATTRIB2_MQUE BIT_6 656 #define FWATTRIB2_FCOE BIT_11 657 #define FWATTRIB2_EX_REL BIT_13 658 659 /* 660 * Initialize Multiple Queue mailbox command options. 661 * qlc_init_req_q() options 662 */ 663 #define IMO_QUEUE_POINTER_SHADOWING BIT_13 664 #define IMO_ATIO_QUEUE_SERVICE BIT_12 665 #define IMO_MOVE_QUEUE_BASE_ADDRESS BIT_11 666 #define IMO_FORCE_DELETE BIT_9 667 #define IMO_QOS_BANDWIDTH_MODE BIT_8 668 #define IMO_QUEUE_NOT_ASSOCIATED BIT_7 669 #define IMO_INTERRUPT_HANDSHAKE BIT_6 670 #define IMO_DEVICE_FUNCTION_NUMBER BIT_5 671 #define IMO_BUS_NUMBER BIT_4 672 #define IMO_QOS_UPDATE BIT_3 673 #define IMO_REQ_RSP_Q_ADDR_TLA BIT_2 674 #define IMO_RESPONSE_Q_SERVICE BIT_1 675 #define IMO_DELETE_Q BIT_0 676 #define IMO_NONE 0 677 678 /* 679 * Diagnostic ELS ECHO parameter structure definition. 680 */ 681 typedef struct echo { 682 uint16_t options; 683 uint32_t transfer_count; 684 ddi_dma_cookie_t transfer_data_address; 685 ddi_dma_cookie_t receive_data_address; 686 } echo_t; 687 688 /* 689 * LFA command structure. 690 */ 691 #define LFA_PAYLOAD_SIZE 38 692 typedef struct lfa_cmd { 693 uint8_t resp_buffer_length[2]; /* length in 16bit words. */ 694 uint8_t reserved[2]; 695 uint8_t resp_buffer_address[8]; 696 uint8_t subcommand_length[2]; /* length in 16bit words. */ 697 uint8_t reserved_1[2]; 698 uint8_t addr[4]; 699 uint8_t subcommand[2]; 700 uint8_t payload[LFA_PAYLOAD_SIZE]; 701 } lfa_cmd_t; 702 703 /* Define size of Loop Position Map. */ 704 #define LOOP_POSITION_MAP_SIZE 128 /* bytes */ 705 706 /* 707 * Port Database structure definition 708 * Little endian except where noted. 709 */ 710 #define PORT_DATABASE_SIZE 128 /* bytes */ 711 typedef struct port_database_23 { 712 uint8_t options; 713 uint8_t control; 714 uint8_t master_state; 715 uint8_t slave_state; 716 uint8_t hard_address[3]; 717 uint8_t rsvd; 718 uint32_t port_id; 719 uint8_t node_name[8]; /* Big endian. */ 720 uint8_t port_name[8]; /* Big endian. */ 721 uint16_t execution_throttle; 722 uint16_t execution_count; 723 uint8_t reset_count; 724 uint8_t reserved_2; 725 uint16_t resource_allocation; 726 uint16_t current_allocation; 727 uint16_t queue_head; 728 uint16_t queue_tail; 729 uint16_t transmit_execution_list_next; 730 uint16_t transmit_execution_list_previous; 731 uint16_t common_features; 732 uint16_t total_concurrent_sequences; 733 uint16_t RO_by_information_category; 734 uint8_t recipient; 735 uint8_t initiator; 736 uint16_t receive_data_size; 737 uint16_t concurrent_sequences; 738 uint16_t open_sequences_per_exchange; 739 uint16_t lun_abort_flags; 740 uint16_t lun_stop_flags; 741 uint16_t stop_queue_head; 742 uint16_t stop_queue_tail; 743 uint16_t port_retry_timer; 744 uint16_t next_sequence_id; 745 uint16_t frame_count; 746 uint16_t PRLI_payload_length; 747 uint16_t PRLI_service_parameter_word_0; /* Big endian */ 748 /* Bits 15-0 of word 0 */ 749 uint16_t PRLI_service_parameter_word_3; /* Big endian */ 750 /* Bits 15-0 of word 3 */ 751 uint16_t loop_id; 752 uint16_t extended_lun_info_list_pointer; 753 uint16_t extended_lun_stop_list_pointer; 754 } port_database_23_t; 755 756 typedef struct port_database_24 { 757 uint16_t flags; 758 uint8_t current_login_state; 759 uint8_t last_stable_login_state; 760 uint8_t hard_address[3]; 761 uint8_t rsvd; 762 uint8_t port_id[3]; 763 uint8_t sequence_id; 764 uint16_t port_retry_timer; 765 uint16_t n_port_handle; 766 uint16_t receive_data_size; 767 uint8_t reserved_1[2]; 768 uint16_t PRLI_service_parameter_word_0; /* Big endian */ 769 /* Bits 15-0 of word 0 */ 770 uint16_t PRLI_service_parameter_word_3; /* Big endian */ 771 /* Bits 15-0 of word 3 */ 772 uint8_t port_name[8]; /* Big endian. */ 773 uint8_t node_name[8]; /* Big endian. */ 774 uint8_t reserved_2[24]; 775 } port_database_24_t; 776 777 /* 778 * Port database slave/master/current_login/ast_stable_login states 779 */ 780 #define PD_STATE_DISCOVERY 0 781 #define PD_STATE_WAIT_DISCOVERY_ACK 1 782 #define PD_STATE_PORT_LOGIN 2 783 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 784 #define PD_STATE_PLOGI_PENDING 3 785 #define PD_STATE_PROCESS_LOGIN 4 786 #define PD_STATE_PLOGI_COMPLETED 4 787 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 788 #define PD_STATE_PRLI_PENDING 5 789 #define PD_STATE_PORT_LOGGED_IN 6 790 #define PD_STATE_PLOGI_PRLI_COMPLETED 6 791 #define PD_STATE_PORT_UNAVAILABLE 7 792 #define PD_STATE_PROCESS_LOGOUT 8 793 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 794 #define PD_STATE_PORT_LOGOUT 10 795 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 796 797 #define PD_PORT_LOGIN(tq) \ 798 (tq->master_state == PD_STATE_PROCESS_LOGIN || \ 799 tq->master_state == PD_STATE_PORT_LOGGED_IN || \ 800 tq->slave_state == PD_STATE_PROCESS_LOGIN || \ 801 tq->slave_state == PD_STATE_PORT_LOGGED_IN) 802 803 /* 804 * ql_login_lport() options 805 */ 806 #define LLF_NONE 0 807 #define LLF_PLOGI BIT_0 /* unconditional PLOGI */ 808 809 /* 810 * ql_login_fport() options 811 */ 812 #define LFF_NONE 0 813 #define LFF_NO_PLOGI BIT_0 814 #define LFF_NO_PRLI BIT_1 815 816 /* 817 * ql_get_port_database() options 818 */ 819 #define PDF_NONE 0 820 #define PDF_PLOGI BIT_0 821 #define PDF_ADISC BIT_1 822 823 /* 824 * Set/Get Port Configuration MBC 825 */ 826 #define LINK_CONFIG_PAUSE_MASK (BIT_6 | BIT_5) 827 #define LINK_CONFIG_PAUSE_DISABLE 0x00 828 #define LINK_CONFIG_PAUSE_STD_ETH 0x01 829 #define LINK_CONFIG_PAUSE_PER_PRIO 0x02 830 831 #define LINK_CONFIG_DCBX_ENA BIT_4 832 833 #define LINK_CONFIG_LB_MODE_MASK (BIT_3 | BIT_2 | BIT_1) 834 #define LINK_CONFIG_LB_NONE 0x00 835 #define LINK_CONFIG_LB_INTERNAL 0x02 836 837 #define LINK_CONFIG2_BP_TRAIN_ENA BIT_15 838 #define LINK_CONFIG2_BP_AUTO_NEGO_ENA BIT_14 839 #define LINK_CONFIG2_JUMBO_FRM_ENA BIT_0 840 841 /* 842 * 843 */ 844 #define FCF_LIST_RETURN_ALL BIT_0 845 #define FCF_LIST_RETURN_ONE BIT_1 846 847 typedef struct fcf_desc { 848 uint16_t options; 849 uint16_t fcf_index; 850 uint32_t buffer_size; 851 } ql_fcf_list_desc_t; 852 853 /* 854 * Global Data in ql_mbx.c source file. 855 */ 856 857 /* 858 * Global Function Prototypes in ql_mbx.c source file. 859 */ 860 int ql_initialize_ip(ql_adapter_state_t *); 861 int ql_shutdown_ip(ql_adapter_state_t *); 862 int ql_online_selftest(ql_adapter_state_t *); 863 int ql_loop_back(ql_adapter_state_t *, uint16_t, lbp_t *, uint32_t, uint32_t); 864 int ql_echo(ql_adapter_state_t *, uint16_t, echo_t *); 865 int ql_send_change_request(ql_adapter_state_t *, uint16_t); 866 int ql_send_lfa(ql_adapter_state_t *, lfa_cmd_t *); 867 int ql_clear_aca(ql_adapter_state_t *, ql_tgt_t *, ql_lun_t *); 868 int ql_target_reset(ql_adapter_state_t *, ql_tgt_t *, uint16_t); 869 int ql_abort_target(ql_adapter_state_t *, ql_tgt_t *, uint16_t); 870 int ql_lun_reset(ql_adapter_state_t *, ql_tgt_t *, ql_lun_t *); 871 int ql_clear_task_set(ql_adapter_state_t *, ql_tgt_t *, ql_lun_t *); 872 int ql_abort_task_set(ql_adapter_state_t *, ql_tgt_t *, ql_lun_t *); 873 int ql_loop_port_bypass(ql_adapter_state_t *, ql_tgt_t *); 874 int ql_loop_port_enable(ql_adapter_state_t *, ql_tgt_t *); 875 int ql_login_lport(ql_adapter_state_t *, ql_tgt_t *, uint16_t, uint16_t); 876 int ql_login_fport(ql_adapter_state_t *, ql_tgt_t *, uint16_t, uint16_t, 877 ql_mbx_data_t *); 878 int ql_logout_fabric_port(ql_adapter_state_t *, ql_tgt_t *); 879 int ql_log_iocb(ql_adapter_state_t *, ql_tgt_t *, uint16_t, uint16_t, 880 ql_mbx_data_t *); 881 int ql_get_port_database(ql_adapter_state_t *, ql_tgt_t *, uint8_t); 882 int ql_get_loop_position_map(ql_adapter_state_t *, size_t, caddr_t); 883 int ql_set_rnid_params(ql_adapter_state_t *, size_t, caddr_t); 884 int ql_send_rnid_els(ql_adapter_state_t *, uint16_t, uint8_t, size_t, caddr_t); 885 int ql_get_rnid_params(ql_adapter_state_t *, size_t, caddr_t); 886 int ql_get_link_status(ql_adapter_state_t *, uint16_t, size_t, caddr_t, 887 uint8_t); 888 int ql_get_status_counts(ql_adapter_state_t *, uint16_t, size_t, caddr_t, 889 uint8_t); 890 int ql_reset_link_status(ql_adapter_state_t *); 891 int ql_loop_reset(ql_adapter_state_t *); 892 int ql_initiate_lip(ql_adapter_state_t *); 893 int ql_full_login_lip(ql_adapter_state_t *); 894 int ql_lip_reset(ql_adapter_state_t *, uint16_t); 895 int ql_abort_command(ql_adapter_state_t *, ql_srb_t *); 896 int ql_verify_checksum(ql_adapter_state_t *); 897 int ql_get_id_list(ql_adapter_state_t *, caddr_t, uint32_t, ql_mbx_data_t *); 898 int ql_wrt_risc_ram(ql_adapter_state_t *, uint32_t, uint64_t, uint32_t); 899 int ql_rd_risc_ram(ql_adapter_state_t *, uint32_t, uint64_t, uint32_t); 900 int ql_wrt_risc_ram_word(ql_adapter_state_t *, uint32_t, uint32_t); 901 int ql_rd_risc_ram_word(ql_adapter_state_t *, uint32_t, uint32_t *); 902 int ql_issue_mbx_iocb(ql_adapter_state_t *, caddr_t, uint32_t); 903 int ql_mbx_wrap_test(ql_adapter_state_t *, ql_mbx_data_t *); 904 int ql_execute_fw(ql_adapter_state_t *); 905 int ql_get_firmware_option(ql_adapter_state_t *, ql_mbx_data_t *); 906 int ql_set_firmware_option(ql_adapter_state_t *, ql_mbx_data_t *); 907 int ql_init_firmware(ql_adapter_state_t *); 908 int ql_get_firmware_state(ql_adapter_state_t *, ql_mbx_data_t *); 909 int ql_get_adapter_id(ql_adapter_state_t *, ql_mbx_data_t *); 910 int ql_get_fw_version(ql_adapter_state_t *, ql_mbx_data_t *, uint16_t); 911 int ql_data_rate(ql_adapter_state_t *, ql_mbx_data_t *); 912 int ql_diag_loopback(ql_adapter_state_t *, caddr_t, uint32_t, uint16_t, 913 uint32_t, ql_mbx_data_t *); 914 int ql_diag_echo(ql_adapter_state_t *, caddr_t, uint32_t, uint16_t, 915 ql_mbx_data_t *); 916 int ql_diag_beacon(ql_adapter_state_t *, int, ql_mbx_data_t *); 917 int ql_serdes_param(ql_adapter_state_t *, ql_mbx_data_t *); 918 int ql_get_timeout_parameters(ql_adapter_state_t *, uint16_t *); 919 int ql_stop_firmware(ql_adapter_state_t *); 920 int ql_read_sfp(ql_adapter_state_t *, dma_mem_t *, uint16_t, uint16_t); 921 int ql_iidma_rate(ql_adapter_state_t *, uint16_t, uint32_t *, uint32_t); 922 int ql_fw_etrace(ql_adapter_state_t *, dma_mem_t *, uint16_t, ql_mbx_data_t *); 923 int ql_reset_menlo(ql_adapter_state_t *, ql_mbx_data_t *, uint16_t); 924 int ql_restart_mpi(ql_adapter_state_t *); 925 int ql_idc_request(ql_adapter_state_t *, ql_mbx_data_t *); 926 int ql_idc_ack(ql_adapter_state_t *); 927 int ql_idc_time_extend(ql_adapter_state_t *); 928 int ql_port_reset(ql_adapter_state_t *); 929 int ql_set_port_config(ql_adapter_state_t *, ql_mbx_data_t *); 930 int ql_get_port_config(ql_adapter_state_t *, ql_mbx_data_t *); 931 int ql_flash_access(ql_adapter_state_t *, uint16_t, uint32_t, uint32_t, 932 uint32_t *); 933 int ql_get_xgmac_stats(ql_adapter_state_t *, size_t, caddr_t); 934 int ql_get_dcbx_params(ql_adapter_state_t *, uint32_t, caddr_t); 935 int ql_get_fcf_list_mbx(ql_adapter_state_t *, ql_fcf_list_desc_t *, caddr_t); 936 int ql_get_resource_cnts(ql_adapter_state_t *, ql_mbx_data_t *); 937 int ql_toggle_interrupt(ql_adapter_state_t *, uint16_t); 938 int ql_get_md_template(ql_adapter_state_t *, dma_mem_t *, ql_mbx_data_t *, 939 uint32_t, uint16_t); 940 int ql_load_flash_image(ql_adapter_state_t *); 941 int ql_set_led_config(ql_adapter_state_t *, ql_mbx_data_t *); 942 int ql_get_led_config(ql_adapter_state_t *, ql_mbx_data_t *); 943 int ql_led_config(ql_adapter_state_t *, ql_mbx_data_t *); 944 int ql_write_remote_reg(ql_adapter_state_t *, uint32_t, uint32_t); 945 int ql_read_remote_reg(ql_adapter_state_t *, uint32_t, uint32_t *); 946 int ql_get_temp(ql_adapter_state_t *, ql_mbx_data_t *mr); 947 int ql_write_serdes(ql_adapter_state_t *, ql_mbx_data_t *); 948 int ql_read_serdes(ql_adapter_state_t *, ql_mbx_data_t *); 949 950 /* 951 * Mailbox command table initializer 952 */ 953 #define MBOX_CMD_TABLE() \ 954 { \ 955 {MBC_LOAD_RAM, "MBC_LOAD_RAM or MBC_WRITE_REMOTE_REG"}, \ 956 {MBC_EXECUTE_FIRMWARE, "MBC_EXECUTE_FIRMWARE"}, \ 957 {MBC_DUMP_RAM, \ 958 "MBC_DUMP_RAM, MBC_LOAD_FLASH_IMAGE or MBC_WRITE_SERDES_REG"}, \ 959 {MBC_WRITE_RAM_WORD, "MBC_WRITE_RAM_WORD or MBC_READ_SERDES_REG"},\ 960 {MBC_READ_RAM_WORD, "MBC_READ_RAM_WORD or MBC_MPI_RAM"}, \ 961 {MBC_MAILBOX_REGISTER_TEST, "MBC_MAILBOX_REGISTER_TEST"}, \ 962 {MBC_VERIFY_CHECKSUM, "MBC_VERIFY_CHECKSUM"}, \ 963 {MBC_ABOUT_FIRMWARE, "MBC_ABOUT_FIRMWARE"}, \ 964 {MBC_LOAD_RISC_RAM, "MBC_LOAD_RISC_RAM or MBC_READ_REMOTE_REG"},\ 965 {MBC_DUMP_RISC_RAM, "MBC_DUMP_RISC_RAM"}, \ 966 {MBC_LOAD_RAM_EXTENDED, "MBC_LOAD_RAM_EXTENDED"}, \ 967 {MBC_DUMP_RAM_EXTENDED, "MBC_DUMP_RAM_EXTENDED"}, \ 968 {MBC_WRITE_RAM_EXTENDED, "MBC_WRITE_RAM_EXTENDED"}, \ 969 {MBC_READ_RAM_EXTENDED, "MBC_READ_RAM_EXTENDED"}, \ 970 {MBC_SERDES_TRANSMIT_PARAMETERS, \ 971 "MBC_SERDES_TRANSMIT_PARAMETERS or MBC_TOGGLE_INTERRUPT"},\ 972 {MBC_2300_EXECUTE_IOCB, "MBC_2300_EXECUTE_IOCB"}, \ 973 {MBC_GET_IO_STATUS, "MBC_GET_IO_STATUS"}, \ 974 {MBC_STOP_FIRMWARE, "MBC_STOP_FIRMWARE"}, \ 975 {MBC_ABORT_COMMAND_IOCB, "MBC_ABORT_COMMAND_IOCB"}, \ 976 {MBC_ABORT_DEVICE, "MBC_ABORT_DEVICE"}, \ 977 {MBC_ABORT_TARGET, "MBC_ABORT_TARGET"}, \ 978 {MBC_RESET, "MBC_RESET"}, \ 979 {MBC_XMIT_PARM, "MBC_XMIT_PARM"}, \ 980 {MBC_PORT_PARAM, "MBC_PORT_PARAM"}, \ 981 {MBC_INIT_MULTIPLE_QUEUE, "MBC_INIT_MULTIPLE_QUEUE"}, \ 982 {MBC_GET_ID, "MBC_GET_ID"}, \ 983 {MBC_GET_TIMEOUT_PARAMETERS, "MBC_GET_TIMEOUT_PARAMETERS"}, \ 984 {MBC_TRACE_CONTROL, "MBC_TRACE_CONTROL"}, \ 985 {MBC_GET_FIRMWARE_OPTIONS, "MBC_GET_FIRMWARE_OPTIONS"}, \ 986 {MBC_READ_SFP, "MBC_READ_SFP"}, \ 987 {MBC_SET_FIRMWARE_OPTIONS, "MBC_SET_FIRMWARE_OPTIONS"}, \ 988 {MBC_RESET_MENLO, "MBC_RESET_MENLO"}, \ 989 {MBC_FC_LED_CONFIG, "MBC_FC_LED_CONFIG"}, \ 990 {MBC_RESTART_MPI, "MBC_RESTART_MPI"}, \ 991 {MBC_FLASH_ACCESS, "MBC_FLASH_ACCESS"}, \ 992 {MBC_LOOP_PORT_BYPASS, "MBC_LOOP_PORT_BYPASS"}, \ 993 {MBC_LOOP_PORT_ENABLE, "MBC_LOOP_PORT_ENABLE"}, \ 994 {MBC_GET_RESOURCE_COUNTS, "MBC_GET_RESOURCE_COUNTS"}, \ 995 {MBC_NON_PARTICIPATE, "MBC_NON_PARTICIPATE"}, \ 996 {MBC_ECHO, "MBC_ECHO"}, \ 997 {MBC_DIAGNOSTIC_LOOP_BACK, "MBC_DIAGNOSTIC_LOOP_BACK"}, \ 998 {MBC_ONLINE_SELF_TEST, "MBC_ONLINE_SELF_TEST"}, \ 999 {MBC_ENHANCED_GET_PORT_DATABASE, "MBC_ENHANCED_GET_PORT_DATABASE"},\ 1000 {MBC_INITIALIZE_MULTI_ID_FW, "MBC_INITIALIZE_MULTI_ID_FW"}, \ 1001 {MBC_GET_FCF_LIST, "MBC_GET_FCF_LIST"}, \ 1002 {MBC_GET_DCBX_PARAMS, "MBC_GET_DCBX_PARAMS"}, \ 1003 {MBC_RESET_LINK_STATUS, "MBC_RESET_LINK_STATUS"}, \ 1004 {MBC_EXECUTE_IOCB, "MBC_EXECUTE_IOCB"}, \ 1005 {MBC_SEND_RNID_ELS, "MBC_SEND_RNID_ELS"}, \ 1006 {MBC_SET_PARAMETERS, "MBC_SET_PARAMETERS"}, \ 1007 {MBC_GET_PARAMETERS, "MBC_GET_PARAMETERS"}, \ 1008 {MBC_DATA_RATE, "MBC_DATA_RATE"}, \ 1009 {MBC_INITIALIZE_FIRMWARE, "MBC_INITIALIZE_FIRMWARE"}, \ 1010 {MBC_INITIATE_LIP, "MBC_INITIATE_LIP"}, \ 1011 {MBC_GET_FC_AL_POSITION_MAP, "MBC_GET_FC_AL_POSITION_MAP"}, \ 1012 {MBC_GET_PORT_DATABASE, "MBC_GET_PORT_DATABASE"}, \ 1013 {MBC_CLEAR_ACA, "MBC_CLEAR_ACA"}, \ 1014 {MBC_TARGET_RESET, "MBC_TARGET_RESET"}, \ 1015 {MBC_CLEAR_TASK_SET, "MBC_CLEAR_TASK_SET"}, \ 1016 {MBC_ABORT_TASK_SET, "MBC_ABORT_TASK_SET"}, \ 1017 {MBC_GET_FIRMWARE_STATE, "MBC_GET_FIRMWARE_STATE"}, \ 1018 {MBC_GET_PORT_NAME, "MBC_GET_PORT_NAME"}, \ 1019 {MBC_GET_LINK_STATUS, "MBC_GET_LINK_STATUS"}, \ 1020 {MBC_LIP_RESET, "MBC_LIP_RESET"}, \ 1021 {MBC_GET_STATUS_COUNTS, "MBC_GET_STATUS_COUNTS"}, \ 1022 {MBC_SEND_SNS_COMMAND, "MBC_SEND_SNS_COMMAND"}, \ 1023 {MBC_LOGIN_FABRIC_PORT, "MBC_LOGIN_FABRIC_PORT"}, \ 1024 {MBC_SEND_CHANGE_REQUEST, "MBC_SEND_CHANGE_REQUEST"}, \ 1025 {MBC_LOGOUT_FABRIC_PORT, "MBC_LOGOUT_FABRIC_PORT"}, \ 1026 {MBC_LIP_FULL_LOGIN, "MBC_LIP_FULL_LOGIN"}, \ 1027 {MBC_LOGIN_LOOP_PORT, "MBC_LOGIN_LOOP_PORT"}, \ 1028 {MBC_PORT_NODE_NAME_LIST, "MBC_PORT_NODE_NAME_LIST"}, \ 1029 {MBC_INITIALIZE_IP, "MBC_INITIALIZE_IP"}, \ 1030 {MBC_SEND_FARP_REQ_COMMAND, "MBC_SEND_FARP_REQ_COMMAND"}, \ 1031 {MBC_UNLOAD_IP, "MBC_UNLOAD_IP"}, \ 1032 {MBC_GET_XGMAC_STATS, "MBC_GET_XGMAC_STATS"}, \ 1033 {MBC_GET_ID_LIST, "MBC_GET_ID_LIST"}, \ 1034 {MBC_SEND_LFA_COMMAND, "MBC_SEND_LFA_COMMAND"}, \ 1035 {MBC_LUN_RESET, "MBC_LUN_RESET"}, \ 1036 {MBC_IDC_REQUEST, "MBC_IDC_REQUEST"}, \ 1037 {MBC_IDC_ACK, "MBC_IDC_ACK"}, \ 1038 {MBC_IDC_TIME_EXTEND, "MBC_IDC_TIME_EXTEND"}, \ 1039 {MBC_PORT_RESET, "MBC_PORT_RESET"}, \ 1040 {MBC_SET_PORT_CONFIG, "MBC_SET_PORT_CONFIG"}, \ 1041 {MBC_GET_PORT_CONFIG, "MBC_GET_PORT_CONFIG"}, \ 1042 {MBC_SET_LED_CONFIG, "MBC_SET_LED_CONFIG"}, \ 1043 {MBC_GET_LED_CONFIG, "MBC_GET_LED_CONFIG"}, \ 1044 {MBC_GET_MD_TEMPLATE, "MBC_GET_MD_TEMPLATE"}, \ 1045 {0, "Unsupported"} \ 1046 } 1047 1048 #ifdef __cplusplus 1049 } 1050 #endif 1051 1052 #endif /* _QL_MBX_H */ 1053